Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/hptnr/him.h
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1 /* $Id: him.h,v 1.57 2011/02/21 06:03:21 zsf Exp $ */ 2 /*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (C) 2004-2005 HighPoint Technologies, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 #include <dev/hptnr/hptnr_config.h> 32 #ifndef _HPT_HIM_H_ 33 #define _HPT_HIM_H_ 34 35 #define VERMAGIC_HIM 55 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #include <dev/hptnr/list.h> 42 43 #define SECTOR_TO_BYTE_SHIFT 9 44 #define SECTOR_TO_BYTE(x) ((HPT_U32)(x) << SECTOR_TO_BYTE_SHIFT) 45 #define BYTE_TO_SECTOR(x) ((x)>>SECTOR_TO_BYTE_SHIFT) 46 47 typedef struct _PCI_ID 48 { 49 HPT_U16 vid; 50 HPT_U16 did; 51 HPT_U32 subsys; 52 HPT_U8 rev; 53 HPT_U8 nbase; 54 HPT_U16 reserve; 55 } 56 PCI_ID; 57 58 typedef struct _PCI_ADDRESS 59 { 60 HPT_U8 tree; 61 HPT_U8 bus; 62 HPT_U8 device; 63 HPT_U8 function; 64 } 65 PCI_ADDRESS; 66 67 typedef struct _HIM_ADAPTER_CONFIG 68 { 69 PCI_ADDRESS pci_addr; 70 PCI_ID pci_id; 71 72 HPT_U8 max_devices; 73 74 HPT_U8 bProbeInInitializing:1; 75 76 HPT_U8 bSpinupOneDevEachTime:1; 77 78 HPT_U8 bGlobalNcq:1; 79 HPT_U8 bSGPIOPartSupport:1; 80 81 HPT_U8 bNeedSASIdleTimer:1; 82 HPT_U8 reserved:3; 83 84 HPT_U8 bDevsPerBus; 85 HPT_U8 first_on_slot; 86 87 HPT_U8 bChipType; 88 HPT_U8 bChipIntrNum; 89 HPT_U8 bChipFlags; 90 HPT_U8 bNumBuses; 91 92 HPT_U8 szVendorID[36]; 93 HPT_U8 szProductID[36]; 94 HPT_U32 nvramSize; 95 HPT_U64 nvramAddress; 96 HPT_U8 slot_index; 97 HPT_U8 maxWidth; 98 HPT_U8 currentWidth; 99 HPT_U8 maxSpeed; 100 HPT_U8 currentSpeed; 101 HPT_U8 reserved2[7]; 102 } 103 HIM_ADAPTER_CONFIG, *PHIM_ADAPTER_CONFIG; 104 105 typedef struct _HIM_CHANNEL_CONFIG 106 { 107 HPT_U32 io_port; 108 HPT_U32 ctl_port; 109 } HIM_CHANNEL_CONFIG, *PHIM_CHANNEL_CONFIG; 110 111 typedef struct _HIM_DEVICE_FLAGS 112 { 113 HPT_UINT df_atapi :1; 114 HPT_UINT df_removable_drive :1; 115 HPT_UINT df_on_line :1; 116 HPT_UINT df_reduce_mode :1; 117 HPT_UINT df_sata :1; 118 HPT_UINT df_on_pm_port :1; 119 HPT_UINT df_support_read_ahead :1; 120 HPT_UINT df_read_ahead_enabled :1; 121 HPT_UINT df_support_write_cache :1; 122 HPT_UINT df_write_cache_enabled :1; 123 HPT_UINT df_cdrom_device :1; 124 HPT_UINT df_tape_device :1; 125 HPT_UINT df_support_tcq :1; 126 HPT_UINT df_tcq_enabled :1; 127 HPT_UINT df_support_ncq :1; 128 HPT_UINT df_ncq_enabled :1; 129 HPT_UINT df_sas :1; 130 HPT_UINT df_in_enclosure :1; 131 HPT_UINT df_ssd :1; 132 } DEVICE_FLAGS, *PDEVICE_FLAGS; 133 134 #pragma pack(1) 135 typedef struct _IDENTIFY_DATA { 136 HPT_U16 GeneralConfiguration; 137 HPT_U16 NumberOfCylinders; 138 HPT_U16 Reserved1; 139 HPT_U16 NumberOfHeads; 140 HPT_U16 UnformattedBytesPerTrack; 141 HPT_U16 UnformattedBytesPerSector; 142 HPT_U8 SasAddress[8]; 143 HPT_U16 SerialNumber[10]; 144 HPT_U16 BufferType; 145 HPT_U16 BufferSectorSize; 146 HPT_U16 NumberOfEccBytes; 147 HPT_U16 FirmwareRevision[4]; 148 HPT_U16 ModelNumber[20]; 149 HPT_U8 MaximumBlockTransfer; 150 HPT_U8 VendorUnique2; 151 HPT_U16 DoubleWordIo; 152 HPT_U16 Capabilities; 153 HPT_U16 Reserved2; 154 HPT_U8 VendorUnique3; 155 HPT_U8 PioCycleTimingMode; 156 HPT_U8 VendorUnique4; 157 HPT_U8 DmaCycleTimingMode; 158 HPT_U16 TranslationFieldsValid; 159 HPT_U16 NumberOfCurrentCylinders; 160 HPT_U16 NumberOfCurrentHeads; 161 HPT_U16 CurrentSectorsPerTrack; 162 HPT_U32 CurrentSectorCapacity; 163 HPT_U16 CurrentMultiSectorSetting; 164 HPT_U32 UserAddressableSectors; 165 HPT_U8 SingleWordDMASupport; 166 HPT_U8 SingleWordDMAActive; 167 HPT_U8 MultiWordDMASupport; 168 HPT_U8 MultiWordDMAActive; 169 HPT_U8 AdvancedPIOModes; 170 HPT_U8 Reserved4; 171 HPT_U16 MinimumMWXferCycleTime; 172 HPT_U16 RecommendedMWXferCycleTime; 173 HPT_U16 MinimumPIOCycleTime; 174 HPT_U16 MinimumPIOCycleTimeIORDY; 175 HPT_U16 Reserved5[2]; 176 HPT_U16 ReleaseTimeOverlapped; 177 HPT_U16 ReleaseTimeServiceCommand; 178 HPT_U16 MajorRevision; 179 HPT_U16 MinorRevision; 180 HPT_U16 MaxQueueDepth; 181 HPT_U16 SataCapability; 182 HPT_U16 Reserved6[9]; 183 HPT_U16 CommandSupport; 184 HPT_U16 CommandEnable; 185 HPT_U16 UtralDmaMode; 186 HPT_U16 Reserved7[11]; 187 HPT_U32 Lba48BitLow; 188 HPT_U32 Lba48BitHigh; 189 HPT_U16 Reserved8[23]; 190 HPT_U16 SpecialFunctionsEnabled; 191 HPT_U16 Reserved9[128]; 192 } 193 #ifdef __GNUC__ 194 __attribute__((packed)) 195 #endif 196 IDENTIFY_DATA, *PIDENTIFY_DATA; 197 #pragma pack() 198 199 typedef struct _HIM_DEVICE_CONFIG 200 { 201 HPT_U64 capacity; 202 HPT_U32 logical_sector_size; 203 HPT_U8 logicalsectors_per_physicalsector; 204 HPT_U16 lowest_aligned; 205 206 DEVICE_FLAGS flags; 207 208 HPT_U8 path_id; 209 HPT_U8 target_id; 210 HPT_U8 max_queue_depth; 211 HPT_U8 spin_up_mode; 212 213 HPT_U8 reserved; 214 HPT_U8 transfer_mode; 215 HPT_U8 bMaxShowMode; 216 HPT_U8 bDeUsable_Mode; 217 218 HPT_U16 max_sectors_per_cmd; 219 220 PIDENTIFY_DATA pIdentifyData; 221 222 223 HPT_U8 fixed_path_id; /*equals to phy id */ 224 } 225 HIM_DEVICE_CONFIG, *PHIM_DEVICE_CONFIG; 226 227 228 #define _DIT_MODE 0 229 #define _DIT_601 1 230 #define _DIT_READ_AHEAD 2 231 #define _DIT_WRITE_CACHE 3 232 #define _DIT_TCQ 4 233 #define _DIT_NCQ 5 234 #define _DIT_BEEP_OFF 6 235 #define _DIT_SPIN_UP_MODE 7 236 #define _DIT_IDLE_STANDBY 8 237 #define _DIT_IDENTIFY 9 238 239 #define SPIN_UP_MODE_NOSUPPORT 0 240 #define SPIN_UP_MODE_FULL 1 241 #define SPIN_UP_MODE_STANDBY 2 242 243 struct tcq_control { 244 HPT_U8 enable; 245 HPT_U8 depth; 246 }; 247 248 struct ncq_control { 249 HPT_U8 enable; 250 HPT_U8 depth; 251 }; 252 253 typedef struct _HIM_ALTERABLE_DEV_INFO{ 254 HPT_U8 type; 255 union { 256 HPT_U8 mode; 257 HPT_U8 enable_read_ahead; 258 HPT_U8 enable_read_cache; 259 HPT_U8 enable_write_cache; 260 struct tcq_control tcq; 261 struct ncq_control ncq; 262 void * adapter; 263 HPT_U8 spin_up_mode; 264 HPT_U8 idle_standby_timeout; 265 HPT_U8 identify_indicator; 266 }u; 267 } HIM_ALTERABLE_DEV_INFO, *PHIM_ALTERABLE_DEV_INFO; 268 269 struct _COMMAND; 270 struct _IOCTL_ARG; 271 272 typedef void (*PROBE_CALLBACK)(void *arg, void *dev, int index); 273 274 typedef struct _HIM { 275 char *name; 276 struct _HIM *next; 277 HPT_UINT max_sg_descriptors; 278 #define _HIM_INTERFACE(_type, _fn, _args) _type (* _fn) _args; 279 #include <dev/hptnr/himfuncs.h> 280 } 281 HIM, *PHIM; 282 283 284 #pragma pack(1) 285 #ifdef SG_FLAG_EOT 286 #error "don't use SG_FLAG_EOT with _SG.eot. clean the code!" 287 #endif 288 289 typedef struct _SG { 290 HPT_U32 size; 291 HPT_UINT eot; 292 union { 293 HPT_U8 FAR * _logical; 294 BUS_ADDRESS bus; 295 } 296 addr; 297 } 298 SG, *PSG; 299 #pragma pack() 300 301 typedef struct _AtaCommand 302 { 303 HPT_U64 Lba; 304 HPT_U16 nSectors; 305 HPT_U16 pad; 306 } AtaComm, *PAtaComm; 307 308 #define ATA_CMD_NOP 0x0 309 310 #define ATA_CMD_SET_FEATURES 0xef 311 #define ATA_CMD_FLUSH 0xE7 312 #define ATA_CMD_VERIFY 0x40 313 #define ATA_CMD_STANDBY 0xe2 314 #define ATA_CMD_READ_MULTI 0xC4 315 #define ATA_CMD_READ_MULTI_EXT 0x29 316 #define ATA_CMD_WRITE_MULTI 0xC5 317 #define ATA_CMD_WRITE_MULTI_EXT 0x39 318 #define ATA_CMD_WRITE_MULTI_FUA_EXT 0xCE 319 320 #define ATA_CMD_READ_DMA 0xc8 /* IDE DMA read command */ 321 #define ATA_CMD_WRITE_DMA 0xca /* IDE DMA write command */ 322 #define ATA_CMD_READ_DMA_EXT 0x25 323 #define ATA_CMD_READ_QUEUE_EXT 0x26 324 #define ATA_CMD_READ_MAX_ADDR 0x27 325 #define ATA_CMD_READ_EXT 0x24 326 #define ATA_CMD_VERIFY_EXT 0x42 327 #define ATA_CMD_WRITE_DMA_EXT 0x35 328 #define ATA_CMD_WRITE_QUEUE_EXT 0x36 329 #define ATA_CMD_WRITE_EXT 0x34 330 331 #define ATA_SET_FEATURES_XFER 0x3 332 #define ATA_SECTOR_SIZE 512 333 334 typedef struct _PassthroughCmd { 335 HPT_U16 bFeaturesReg; 336 HPT_U16 bSectorCountReg; 337 HPT_U16 bLbaLowReg; 338 HPT_U16 bLbaMidReg; 339 HPT_U16 bLbaHighReg; 340 HPT_U8 bDriveHeadReg; 341 HPT_U8 bCommandReg; 342 HPT_U16 nSectors; 343 HPT_U8 *pDataBuffer; 344 } 345 PassthroughCmd; 346 347 typedef struct _ScsiComm { 348 HPT_U8 cdbLength; 349 HPT_U8 senseLength; 350 HPT_U8 scsiStatus; 351 HPT_U8 reserve1; 352 HPT_U32 dataLength; 353 HPT_U8 cdb[16]; 354 HPT_U8 *senseBuffer; 355 } 356 ScsiComm; 357 358 359 #define CTRL_CMD_REBUILD 1 360 #define CTRL_CMD_VERIFY 2 361 #define CTRL_CMD_INIT 3 362 363 364 typedef struct _R5ControlCmd { 365 HPT_U64 StripeLine; 366 HPT_U16 Offset; 367 HPT_U8 Command; 368 HPT_U8 CmdTarget; 369 } 370 R5ControlCmd, *PR5ControlCmd; 371 372 typedef struct _HPT_ADDRESS 373 { 374 HPT_U8 * logical; 375 BUS_ADDRESS bus; 376 } 377 HPT_ADDRESS; 378 379 380 typedef struct ctl_pages { 381 HPT_ADDRESS *pages; 382 HPT_UINT page_size; 383 HPT_UINT npages; 384 HPT_UINT min_sg_descriptors; 385 } CONTROL_PAGES, *PCONTROL_PAGES; 386 387 typedef struct _R1ControlCmd { 388 HPT_U64 Lba; 389 HPT_U16 nSectors; 390 HPT_U8 Command; 391 HPT_U8 CmdTarget; 392 PCONTROL_PAGES ctl_pages; 393 } 394 R1ControlCmd, *PR1ControlCmd; 395 396 typedef void (*TQ_PROC)(void *arg); 397 398 struct tq_item { 399 TQ_PROC proc; 400 void *arg; 401 struct tq_item *next; 402 }; 403 404 #define INIT_TQ_ITEM(t, p, a) \ 405 do { (t)->proc = p; (t)->arg = a; (t)->next = 0; } while (0) 406 407 typedef struct _COMMAND 408 { 409 410 struct _VBUS * vbus; 411 412 struct freelist *grplist; 413 HPT_UINT grpcnt; 414 415 416 struct list_head q_link; 417 struct tq_item done_dpc; 418 419 HPT_UINT extsize; 420 void *ext; 421 422 423 424 void *target; 425 void *priv; 426 HPT_UPTR priv2; 427 428 int priority; 429 struct lock_request *owned_lock; 430 struct lock_request *lock_req; 431 void (*dtor)(struct _COMMAND *, void *); 432 void *dtor_arg; 433 434 union{ 435 AtaComm Ide; 436 PassthroughCmd Passthrough; 437 ScsiComm Scsi; 438 R5ControlCmd R5Control; 439 R1ControlCmd R1Control; 440 } uCmd; 441 442 HPT_U8 type; /* CMD_TYPE_* */ 443 444 struct { 445 HPT_U8 physical_sg: 1; 446 HPT_U8 data_in: 1; 447 HPT_U8 data_out: 1; 448 HPT_U8 transform : 1; 449 HPT_U8 hard_flush: 2; 450 HPT_U8 from_cc: 1; 451 HPT_U8 force_cc: 1; 452 } flags; 453 454 /* return status */ 455 HPT_U8 Result; 456 /* retry count */ 457 HPT_U8 RetryCount; 458 459 460 PSG psg; 461 462 463 int (*buildsgl)(struct _COMMAND *cmd, PSG psg, int logical); 464 void (*done)(struct _COMMAND *cmd); 465 } 466 COMMAND, *PCOMMAND; 467 468 /* command types */ 469 #define CMD_TYPE_IO 0 470 #define CMD_TYPE_CONTROL 1 471 #define CMD_TYPE_ATAPI 2 472 #define CMD_TYPE_SCSI CMD_TYPE_ATAPI 473 #define CMD_TYPE_PASSTHROUGH 3 474 #define CMD_TYPE_FLUSH 4 475 #define CMD_TYPE_IO_INDIRECT 0x80 476 477 /* flush command flags */ 478 #define CF_HARD_FLUSH_CACHE 1 479 #define CF_HARD_FLUSH_STANDBY 2 480 481 /* command return values */ 482 #define RETURN_PENDING 0 483 #define RETURN_SUCCESS 1 484 #define RETURN_BAD_DEVICE 2 485 #define RETURN_BAD_PARAMETER 3 486 #define RETURN_WRITE_NO_DRQ 4 487 #define RETURN_DEVICE_BUSY 5 488 #define RETURN_INVALID_REQUEST 6 489 #define RETURN_SELECTION_TIMEOUT 7 490 #define RETURN_IDE_ERROR 8 491 #define RETURN_NEED_LOGICAL_SG 9 492 #define RETURN_NEED_PHYSICAL_SG 10 493 #define RETURN_RETRY 11 494 #define RETURN_DATA_ERROR 12 495 #define RETURN_BUS_RESET 13 496 #define RETURN_BAD_TRANSFER_LENGTH 14 497 #define RETURN_INSUFFICIENT_MEMORY 15 498 #define RETURN_SECTOR_ERROR 16 499 #define RETURN_NEED_SPINUP 17 500 501 #if defined(__cplusplus) 502 } 503 #endif 504 #endif
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