hwpmc_core.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2008 Joseph Koshy
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD$
   29  */
   30 
   31 #ifndef _DEV_HWPMC_CORE_H_
   32 #define _DEV_HWPMC_CORE_H_ 1
   33 
   34 #define IA32_PERF_CAPABILITIES          0x345
   35 #define PERFCAP_LBR_FORMAT              0x003f
   36 #define PERFCAP_PEBS_TRAP               0x0040
   37 #define PERFCAP_PEBS_SAVEARCH           0x0080
   38 #define PERFCAP_PEBS_RECFORMAT          0x0f00
   39 #define PERFCAP_SMM_FREEZE              0x1000
   40 #define PERFCAP_FW_WRITE                0x2000  /* full width write aliases */
   41 
   42 #define IAF_OS          0x1
   43 #define IAF_USR         0x2
   44 #define IAF_ANY         0x4
   45 #define IAF_PMI         0x8
   46 
   47 /*
   48  * Programmable PMCs.
   49  */
   50 struct pmc_md_iap_op_pmcallocate {
   51         uint64_t        pm_iap_config;
   52         uint64_t        pm_iap_rsp;
   53 };
   54 
   55 #define IAP_EVSEL(C)    ((C) & 0xFF)
   56 #define IAP_UMASK(C)    (((C) & 0xFF) << 8)
   57 #define IAP_USR         (1 << 16)
   58 #define IAP_OS          (1 << 17)
   59 #define IAP_EDGE        (1 << 18)
   60 #define IAP_INT         (1 << 20)
   61 #define IAP_ANY         (1 << 21)
   62 #define IAP_EN          (1 << 22)
   63 #define IAP_INV         (1 << 23)
   64 #define IAP_CMASK(C)    (((C) & 0xFF) << 24)
   65 
   66 #define IAP_EVSEL_GET(C)        ((C) & 0xFF)
   67 #define IAP_UMASK_GET(C)        (((C) & 0xFF00) >> 8)
   68 
   69 #define IA_OFFCORE_RSP_MASK_I7WM        0x000000F7FF
   70 #define IA_OFFCORE_RSP_MASK_SBIB        0x3F807F8FFF
   71 
   72 #ifdef  _KERNEL
   73 
   74 /*
   75  * Fixed-function counters.
   76  */
   77 
   78 #define IAF_MASK                                0x000000010000000f
   79 
   80 #define IAF_CTR0                                0x309
   81 #define IAF_CTR1                                0x30A
   82 #define IAF_CTR2                                0x30B
   83 
   84 /*
   85  * The IAF_CTRL MSR is laid out in the following way.
   86  *
   87  * Bit Position    Use
   88  * 63 - 45         Reserved (do not touch)
   89  * 44              Ctr 3 Adaptive Record (v5)
   90  * 43 - 41         Reserved (do not touch)
   91  * 40              Ctr 2 Adaptive Record (v5)
   92  * 39 - 37         Reserved (do not touch)
   93  * 36              Ctr 1 Adaptive Record (v5)
   94  * 35 - 33         Reserved (do not touch)
   95  * 32              Ctr 0 Adaptive Record (v5)
   96  * 15              Ctr 3 PMI
   97  * 14              Ctr 3 Any Thread (v3)
   98  * 13-12           Ctr 3 Enable
   99  * 11              Ctr 2 PMI
  100  * 10              Ctr 2 Any Thread (v3)
  101  * 9-8             Ctr 2 Enable
  102  * 7               Ctr 1 PMI
  103  * 6               Ctr 1 Any Thread (v3)
  104  * 5-4             Ctr 1 Enable
  105  * 3               Ctr 0 PMI
  106  * 2               Ctr 0 Any Thread (v3)
  107  * 1-0             Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable)
  108  */
  109 
  110 #define IAF_OFFSET                              32
  111 #define IAF_CTRL                                0x38D
  112 
  113 /*
  114  * Programmable counters.
  115  */
  116 
  117 #define IAP_PMC0                                0x0C1
  118 #define IAP_A_PMC0                              0x4C1
  119 
  120 /*
  121  * IAP_EVSEL(n) is laid out in the following way.
  122  *
  123  * Bit Position    Use
  124  * 63-35           Reserved (do not touch)
  125  * 34              Adaptive Record (v5)
  126  * 33              IN_TX (v3)
  127  * 32              IN_TXCP (v3)
  128  * 31-24           Counter Mask
  129  * 23              Invert
  130  * 22              Enable
  131  * 21              Any Thread (v3)
  132  * 20              APIC Interrupt Enable
  133  * 19              Pin Control
  134  * 18              Edge Detect
  135  * 17              OS
  136  * 16              User
  137  * 15-8            Unit Mask
  138  * 7-0             Event Select
  139  */
  140 
  141 #define IAP_EVSEL0                              0x186
  142 
  143 /*
  144  * Simplified programming interface in Intel Performance Architecture
  145  * v2 and later.
  146  */
  147 
  148 #define IA_GLOBAL_STATUS                        0x38E
  149 #define IA_GLOBAL_CTRL                          0x38F
  150 
  151 /*
  152  * IA_GLOBAL_CTRL is laid out in the following way.
  153  * 
  154  * Bit Position    Use
  155  * 63-49           Reserved (do not touch)
  156  * 48              Perf Metrics Enable (v5)
  157  * 47-36           Reserved (do not touch)
  158  * 35              IAF Counter 3 Enable
  159  * 34              IAF Counter 2 Enable
  160  * 33              IAF Counter 1 Enable
  161  * 32              IAF Counter 0 Enable
  162  * 31-0            Depends on programmable counters
  163  */
  164 
  165 #define IA_GLOBAL_OVF_CTRL                      0x390
  166 #define IA_GLOBAL_STATUS_RESET                  0x390
  167 #define IA_GLOBAL_STATUS_SET                    0x391           /* v4 */
  168 
  169 #define IA_GLOBAL_STATUS_FLAG_CONDCHG           (1ULL << 63)
  170 #define IA_GLOBAL_STATUS_FLAG_OVFBUF            (1ULL << 62)
  171 #define IA_GLOBAL_STATUS_FLAG_OVFUNCORE         (1ULL << 61)    /* v3 */
  172 #define IA_GLOBAL_STATUS_FLAG_ASCI              (1ULL << 60)    /* v4 */
  173 #define IA_GLOBAL_STATUS_FLAG_CTR_FRZ           (1ULL << 59)    /* v4 */
  174 #define IA_GLOBAL_STATUS_FLAG_LBP_FRZ           (1ULL << 58)    /* v4 */
  175 #define IA_GLOBAL_STATUS_FLAG_TRACETOPAPMI      (1ULL << 55)    /* v4 */
  176 
  177 #define IA_GLOBAL_INUSE                         0x392           /* v4 */
  178 
  179 /*
  180  * Offcore response configuration.
  181  */
  182 #define IA_OFFCORE_RSP0                         0x1A6
  183 #define IA_OFFCORE_RSP1                         0x1A7
  184 
  185 struct pmc_md_iaf_pmc {
  186         uint64_t        pm_iaf_ctrl;
  187 };
  188 
  189 struct pmc_md_iap_pmc {
  190         uint64_t        pm_iap_evsel;
  191         uint64_t        pm_iap_rsp;
  192 };
  193 
  194 /*
  195  * Prototypes.
  196  */
  197 
  198 int     pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu,
  199             int _version_override);
  200 void    pmc_core_finalize(struct pmc_mdep *_md);
  201 
  202 int     pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width);
  203 void    pmc_iaf_finalize(struct pmc_mdep *_md);
  204 
  205 int     pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width,
  206             int _flags);
  207 void    pmc_iap_finalize(struct pmc_mdep *_md);
  208 
  209 #endif  /* _KERNEL */
  210 #endif  /* _DEV_HWPMC_CORE_H */

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FreeBSD/Linux Kernel Cross Reference sys/dev/hwpmc/hwpmc_core.h

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sys/dev/hwpmc/hwpmc_core.h