The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/hwpmc/pmu_dmc620_reg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause
    3  *
    4  * Copyright (c) 2021 Ampere Computing LLC
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD$
   28  */
   29 
   30 #ifndef _DEV_HWPMC_PMU_DMC620_REG_H_
   31 #define _DEV_HWPMC_PMU_DMC620_REG_H_
   32 
   33 #define DMC620_UNIT_PER_SOCKET  8
   34 #define DMC620_MAX_SOCKET       2
   35 #define DMC620_UNIT_MAX         (DMC620_UNIT_PER_SOCKET * DMC620_MAX_SOCKET)
   36 
   37 #define DMC620_SNAPSHOT_REQ             0x000 /* WO */
   38 #define DMC620_SNAPSHOT_ACK             0x004 /* RO */
   39 #define DMC620_OVERFLOW_STATUS_CLKDIV2  0x008 /* RW */
   40 #define DMC620_OVERFLOW_STATUS_CLK      0x00C /* RW */
   41 
   42 #define DMC620_COUNTER_MASK_LO          0x000 /* RW */
   43 #define DMC620_COUNTER_MASK_HI          0x004 /* RW */
   44 #define DMC620_COUNTER_MATCH_LO         0x008 /* RW */
   45 #define DMC620_COUNTER_MATCH_HI         0x00C /* RW */
   46 #define DMC620_COUNTER_CONTROL          0x010 /* RW */
   47 #define         DMC620_COUNTER_CONTROL_ENABLE           (1 << 0)
   48 #define         DMC620_COUNTER_CONTROL_INVERT           (1 << 1)
   49 #define         DMC620_COUNTER_CONTROL_EVENT_SHIFT      2
   50 #define         DMC620_COUNTER_CONTROL_EVENT_MASK       (0x1f << 2)
   51 #define         DMC620_COUNTER_CONTROL_INCR_SHIFT       7
   52 #define         DMC620_COUNTER_CONTROL_INCR_MASK        (0x3 << 7)
   53 #define DMC620_COUNTER_SNAPSHOT_VALUE_LO 0x018 /* RO */
   54 #define DMC620_COUNTER_VALUE_LO         0x020 /* RW */
   55 
   56 #define DMC620_CLKDIV2_COUNTERS_BASE    0x010
   57 #define DMC620_CLKDIV2_COUNTERS_OFF     0x28
   58 #define DMC620_CLKDIV2_COUNTERS_N       8
   59 #define DMC620_CLKDIV2_REG(u, r)        (DMC620_CLKDIV2_COUNTERS_BASE + \
   60     (DMC620_CLKDIV2_COUNTERS_OFF * (u)) + (r))
   61 
   62 #define DMC620_CLK_COUNTERS_BASE        0x150
   63 #define DMC620_CLK_COUNTERS_OFF         0x28
   64 #define DMC620_CLK_COUNTERS_N           2
   65 #define DMC620_CLK_REG(u, r)            (DMC620_CLK_COUNTERS_BASE +     \
   66     (DMC620_CLK_COUNTERS_OFF * (u)) + (r))
   67 
   68 /* CLK counters continue registers set. */
   69 #define DMC620_REG(u, r)                (DMC620_CLKDIV2_COUNTERS_BASE + \
   70     (DMC620_CLKDIV2_COUNTERS_OFF * (u)) + (r))
   71 
   72 #define DMC620_PMU_DEFAULT_UNITS_N      8
   73 
   74 #define DMC620_COUNTERS_N       (DMC620_CLKDIV2_COUNTERS_N + \
   75     DMC620_CLK_COUNTERS_N)
   76 
   77 /* IO from HWPMC module to driver. */
   78 uint32_t pmu_dmc620_rd4(void *arg, u_int cntr, off_t reg);
   79 void pmu_dmc620_wr4(void *arg, u_int cntr, off_t reg, uint32_t val);
   80 
   81 /* Driver's interrupt notification to HWPMC module. */
   82 int dmc620_intr(struct trapframe *tf, int c, int unit, int ri);
   83 
   84 /* Registration of counters pool. */
   85 void dmc620_pmc_register(int unit, void *argi, int domain);
   86 void dmc620_pmc_unregister(int unit);
   87 
   88 #endif /*_DEV_HWPMC_PMU_DMC620_REG_H_ */

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