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sys/dev/iavf/iavf_type.h
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1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _IAVF_TYPE_H_ 34 #define _IAVF_TYPE_H_ 35 36 #include "iavf_status.h" 37 #include "iavf_osdep.h" 38 #include "iavf_register.h" 39 #include "iavf_adminq.h" 40 #include "iavf_devids.h" 41 42 #define IAVF_RXQ_CTX_DBUFF_SHIFT 7 43 44 #define BIT(a) (1UL << (a)) 45 #define BIT_ULL(a) (1ULL << (a)) 46 47 #ifndef IAVF_MASK 48 /* IAVF_MASK is a macro used on 32 bit registers */ 49 #define IAVF_MASK(mask, shift) (mask << shift) 50 #endif 51 52 #define IAVF_MAX_PF 16 53 #define IAVF_MAX_PF_VSI 64 54 #define IAVF_MAX_PF_QP 128 55 #define IAVF_MAX_VSI_QP 16 56 #define IAVF_MAX_VF_VSI 4 57 #define IAVF_MAX_CHAINED_RX_BUFFERS 5 58 59 /* something less than 1 minute */ 60 #define IAVF_HEARTBEAT_TIMEOUT (HZ * 50) 61 62 /* Check whether address is multicast. */ 63 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01)) 64 65 /* Check whether an address is broadcast. */ 66 #define IAVF_IS_BROADCAST(address) \ 67 ((((u8 *)(address))[0] == ((u8)0xff)) && \ 68 (((u8 *)(address))[1] == ((u8)0xff))) 69 70 /* forward declaration */ 71 struct iavf_hw; 72 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *); 73 74 #define ETH_ALEN 6 75 /* Data type manipulation macros. */ 76 #define IAVF_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF)) 77 #define IAVF_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF)) 78 79 #define IAVF_HI_WORD(x) ((u16)(((x) >> 16) & 0xFFFF)) 80 #define IAVF_LO_WORD(x) ((u16)((x) & 0xFFFF)) 81 82 #define IAVF_HI_BYTE(x) ((u8)(((x) >> 8) & 0xFF)) 83 #define IAVF_LO_BYTE(x) ((u8)((x) & 0xFF)) 84 85 /* Number of Transmit Descriptors must be a multiple of 8. */ 86 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8 87 /* Number of Receive Descriptors must be a multiple of 32 if 88 * the number of descriptors is greater than 32. 89 */ 90 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32 91 92 #define IAVF_DESC_UNUSED(R) \ 93 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 94 (R)->next_to_clean - (R)->next_to_use - 1) 95 96 /* bitfields for Tx queue mapping in QTX_CTL */ 97 #define IAVF_QTX_CTL_VF_QUEUE 0x0 98 #define IAVF_QTX_CTL_VM_QUEUE 0x1 99 #define IAVF_QTX_CTL_PF_QUEUE 0x2 100 101 /* debug masks - set these bits in hw->debug_mask to control output */ 102 enum iavf_debug_mask { 103 IAVF_DEBUG_INIT = 0x00000001, 104 IAVF_DEBUG_RELEASE = 0x00000002, 105 106 IAVF_DEBUG_LINK = 0x00000010, 107 IAVF_DEBUG_PHY = 0x00000020, 108 IAVF_DEBUG_HMC = 0x00000040, 109 IAVF_DEBUG_NVM = 0x00000080, 110 IAVF_DEBUG_LAN = 0x00000100, 111 IAVF_DEBUG_FLOW = 0x00000200, 112 IAVF_DEBUG_DCB = 0x00000400, 113 IAVF_DEBUG_DIAG = 0x00000800, 114 IAVF_DEBUG_FD = 0x00001000, 115 IAVF_DEBUG_PACKAGE = 0x00002000, 116 117 IAVF_DEBUG_IWARP = 0x00F00000, 118 119 IAVF_DEBUG_AQ_MESSAGE = 0x01000000, 120 IAVF_DEBUG_AQ_DESCRIPTOR = 0x02000000, 121 IAVF_DEBUG_AQ_DESC_BUFFER = 0x04000000, 122 IAVF_DEBUG_AQ_COMMAND = 0x06000000, 123 IAVF_DEBUG_AQ = 0x0F000000, 124 125 IAVF_DEBUG_USER = 0xF0000000, 126 127 IAVF_DEBUG_ALL = 0xFFFFFFFF 128 }; 129 130 /* PCI Bus Info */ 131 #define IAVF_PCI_LINK_STATUS 0xB2 132 #define IAVF_PCI_LINK_WIDTH 0x3F0 133 #define IAVF_PCI_LINK_WIDTH_1 0x10 134 #define IAVF_PCI_LINK_WIDTH_2 0x20 135 #define IAVF_PCI_LINK_WIDTH_4 0x40 136 #define IAVF_PCI_LINK_WIDTH_8 0x80 137 #define IAVF_PCI_LINK_SPEED 0xF 138 #define IAVF_PCI_LINK_SPEED_2500 0x1 139 #define IAVF_PCI_LINK_SPEED_5000 0x2 140 #define IAVF_PCI_LINK_SPEED_8000 0x3 141 142 #define IAVF_MDIO_CLAUSE22_STCODE_MASK IAVF_MASK(1, \ 143 IAVF_GLGEN_MSCA_STCODE_SHIFT) 144 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK IAVF_MASK(1, \ 145 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 146 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK IAVF_MASK(2, \ 147 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 148 149 #define IAVF_MDIO_CLAUSE45_STCODE_MASK IAVF_MASK(0, \ 150 IAVF_GLGEN_MSCA_STCODE_SHIFT) 151 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK IAVF_MASK(0, \ 152 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 153 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK IAVF_MASK(1, \ 154 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 155 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK IAVF_MASK(2, \ 156 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 157 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK IAVF_MASK(3, \ 158 IAVF_GLGEN_MSCA_OPCODE_SHIFT) 159 160 #define IAVF_PHY_COM_REG_PAGE 0x1E 161 #define IAVF_PHY_LED_LINK_MODE_MASK 0xF0 162 #define IAVF_PHY_LED_MANUAL_ON 0x100 163 #define IAVF_PHY_LED_PROV_REG_1 0xC430 164 #define IAVF_PHY_LED_MODE_MASK 0xFFFF 165 #define IAVF_PHY_LED_MODE_ORIG 0x80000000 166 167 /* Memory types */ 168 enum iavf_memset_type { 169 IAVF_NONDMA_MEM = 0, 170 IAVF_DMA_MEM 171 }; 172 173 /* Memcpy types */ 174 enum iavf_memcpy_type { 175 IAVF_NONDMA_TO_NONDMA = 0, 176 IAVF_NONDMA_TO_DMA, 177 IAVF_DMA_TO_DMA, 178 IAVF_DMA_TO_NONDMA 179 }; 180 181 /* These are structs for managing the hardware information and the operations. 182 * The structures of function pointers are filled out at init time when we 183 * know for sure exactly which hardware we're working with. This gives us the 184 * flexibility of using the same main driver code but adapting to slightly 185 * different hardware needs as new parts are developed. For this architecture, 186 * the Firmware and AdminQ are intended to insulate the driver from most of the 187 * future changes, but these structures will also do part of the job. 188 */ 189 enum iavf_mac_type { 190 IAVF_MAC_UNKNOWN = 0, 191 IAVF_MAC_XL710, 192 IAVF_MAC_VF, 193 IAVF_MAC_X722, 194 IAVF_MAC_X722_VF, 195 IAVF_MAC_GENERIC, 196 }; 197 198 enum iavf_vsi_type { 199 IAVF_VSI_MAIN = 0, 200 IAVF_VSI_VMDQ1 = 1, 201 IAVF_VSI_VMDQ2 = 2, 202 IAVF_VSI_CTRL = 3, 203 IAVF_VSI_FCOE = 4, 204 IAVF_VSI_MIRROR = 5, 205 IAVF_VSI_SRIOV = 6, 206 IAVF_VSI_FDIR = 7, 207 IAVF_VSI_IWARP = 8, 208 IAVF_VSI_TYPE_UNKNOWN 209 }; 210 211 enum iavf_queue_type { 212 IAVF_QUEUE_TYPE_RX = 0, 213 IAVF_QUEUE_TYPE_TX, 214 IAVF_QUEUE_TYPE_PE_CEQ, 215 IAVF_QUEUE_TYPE_UNKNOWN 216 }; 217 218 #define IAVF_HW_CAP_MAX_GPIO 30 219 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO 0 220 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C 1 221 222 enum iavf_acpi_programming_method { 223 IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0, 224 IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1 225 }; 226 227 #define IAVF_WOL_SUPPORT_MASK 0x1 228 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK 0x2 229 #define IAVF_PROXY_SUPPORT_MASK 0x4 230 231 /* Capabilities of a PF or a VF or the whole device */ 232 struct iavf_hw_capabilities { 233 /* Cloud filter modes: 234 * Mode1: Filter on L4 port only 235 * Mode2: Filter for non-tunneled traffic 236 * Mode3: Filter for tunnel traffic 237 */ 238 #define IAVF_CLOUD_FILTER_MODE1 0x6 239 #define IAVF_CLOUD_FILTER_MODE2 0x7 240 #define IAVF_CLOUD_FILTER_MODE3 0x8 241 #define IAVF_SWITCH_MODE_MASK 0xF 242 243 bool dcb; 244 bool fcoe; 245 bool iwarp; 246 u32 num_vsis; 247 u32 num_rx_qp; 248 u32 num_tx_qp; 249 u32 base_queue; 250 u32 num_msix_vectors_vf; 251 bool apm_wol_support; 252 enum iavf_acpi_programming_method acpi_prog_method; 253 bool proxy_support; 254 }; 255 256 struct iavf_mac_info { 257 enum iavf_mac_type type; 258 u8 addr[ETH_ALEN]; 259 u8 perm_addr[ETH_ALEN]; 260 u8 san_addr[ETH_ALEN]; 261 u8 port_addr[ETH_ALEN]; 262 u16 max_fcoeq; 263 }; 264 265 #define IAVF_NVM_EXEC_GET_AQ_RESULT 0x0 266 #define IAVF_NVM_EXEC_FEATURES 0xe 267 #define IAVF_NVM_EXEC_STATUS 0xf 268 269 /* NVMUpdate features API */ 270 #define IAVF_NVMUPD_FEATURES_API_VER_MAJOR 0 271 #define IAVF_NVMUPD_FEATURES_API_VER_MINOR 14 272 #define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12 273 274 #define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0) 275 276 struct iavf_nvmupd_features { 277 u8 major; 278 u8 minor; 279 u16 size; 280 u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN]; 281 }; 282 283 #define IAVF_MODULE_SFF_DIAG_CAPAB 0x40 284 /* PCI bus types */ 285 enum iavf_bus_type { 286 iavf_bus_type_unknown = 0, 287 iavf_bus_type_pci, 288 iavf_bus_type_pcix, 289 iavf_bus_type_pci_express, 290 iavf_bus_type_reserved 291 }; 292 293 /* PCI bus speeds */ 294 enum iavf_bus_speed { 295 iavf_bus_speed_unknown = 0, 296 iavf_bus_speed_33 = 33, 297 iavf_bus_speed_66 = 66, 298 iavf_bus_speed_100 = 100, 299 iavf_bus_speed_120 = 120, 300 iavf_bus_speed_133 = 133, 301 iavf_bus_speed_2500 = 2500, 302 iavf_bus_speed_5000 = 5000, 303 iavf_bus_speed_8000 = 8000, 304 iavf_bus_speed_reserved 305 }; 306 307 /* PCI bus widths */ 308 enum iavf_bus_width { 309 iavf_bus_width_unknown = 0, 310 iavf_bus_width_pcie_x1 = 1, 311 iavf_bus_width_pcie_x2 = 2, 312 iavf_bus_width_pcie_x4 = 4, 313 iavf_bus_width_pcie_x8 = 8, 314 iavf_bus_width_32 = 32, 315 iavf_bus_width_64 = 64, 316 iavf_bus_width_reserved 317 }; 318 319 /* Bus parameters */ 320 struct iavf_bus_info { 321 enum iavf_bus_speed speed; 322 enum iavf_bus_width width; 323 enum iavf_bus_type type; 324 325 u16 func; 326 u16 device; 327 u16 lan_id; 328 u16 bus_id; 329 }; 330 331 #define IAVF_MAX_USER_PRIORITY 8 332 #define IAVF_TLV_STATUS_OPER 0x1 333 #define IAVF_TLV_STATUS_SYNC 0x2 334 #define IAVF_TLV_STATUS_ERR 0x4 335 #define IAVF_CEE_OPER_MAX_APPS 3 336 #define IAVF_APP_PROTOID_FCOE 0x8906 337 #define IAVF_APP_PROTOID_ISCSI 0x0cbc 338 #define IAVF_APP_PROTOID_FIP 0x8914 339 #define IAVF_APP_SEL_ETHTYPE 0x1 340 #define IAVF_APP_SEL_TCPIP 0x2 341 #define IAVF_CEE_APP_SEL_ETHTYPE 0x0 342 #define IAVF_CEE_APP_SEL_TCPIP 0x1 343 344 /* Port hardware description */ 345 struct iavf_hw { 346 u8 *hw_addr; 347 void *back; 348 349 /* subsystem structs */ 350 struct iavf_mac_info mac; 351 struct iavf_bus_info bus; 352 353 /* pci info */ 354 u16 device_id; 355 u16 vendor_id; 356 u16 subsystem_device_id; 357 u16 subsystem_vendor_id; 358 u8 revision_id; 359 360 /* capabilities for entire device and PCI func */ 361 struct iavf_hw_capabilities dev_caps; 362 363 /* Admin Queue info */ 364 struct iavf_adminq_info aq; 365 366 /* WoL and proxy support */ 367 u16 num_wol_proxy_filters; 368 u16 wol_proxy_vsi_seid; 369 370 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0) 371 #define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1) 372 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2) 373 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3) 374 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4) 375 u64 flags; 376 377 /* NVMUpdate features */ 378 struct iavf_nvmupd_features nvmupd_features; 379 380 /* debug mask */ 381 u32 debug_mask; 382 char err_str[16]; 383 }; 384 385 struct iavf_driver_version { 386 u8 major_version; 387 u8 minor_version; 388 u8 build_version; 389 u8 subbuild_version; 390 u8 driver_string[32]; 391 }; 392 393 /* RX Descriptors */ 394 union iavf_16byte_rx_desc { 395 struct { 396 __le64 pkt_addr; /* Packet buffer address */ 397 __le64 hdr_addr; /* Header buffer address */ 398 } read; 399 struct { 400 struct { 401 struct { 402 union { 403 __le16 mirroring_status; 404 __le16 fcoe_ctx_id; 405 } mirr_fcoe; 406 __le16 l2tag1; 407 } lo_dword; 408 union { 409 __le32 rss; /* RSS Hash */ 410 __le32 fd_id; /* Flow director filter id */ 411 __le32 fcoe_param; /* FCoE DDP Context id */ 412 } hi_dword; 413 } qword0; 414 struct { 415 /* ext status/error/pktype/length */ 416 __le64 status_error_len; 417 } qword1; 418 } wb; /* writeback */ 419 }; 420 421 union iavf_32byte_rx_desc { 422 struct { 423 __le64 pkt_addr; /* Packet buffer address */ 424 __le64 hdr_addr; /* Header buffer address */ 425 /* bit 0 of hdr_buffer_addr is DD bit */ 426 __le64 rsvd1; 427 __le64 rsvd2; 428 } read; 429 struct { 430 struct { 431 struct { 432 union { 433 __le16 mirroring_status; 434 __le16 fcoe_ctx_id; 435 } mirr_fcoe; 436 __le16 l2tag1; 437 } lo_dword; 438 union { 439 __le32 rss; /* RSS Hash */ 440 __le32 fcoe_param; /* FCoE DDP Context id */ 441 /* Flow director filter id in case of 442 * Programming status desc WB 443 */ 444 __le32 fd_id; 445 } hi_dword; 446 } qword0; 447 struct { 448 /* status/error/pktype/length */ 449 __le64 status_error_len; 450 } qword1; 451 struct { 452 __le16 ext_status; /* extended status */ 453 __le16 rsvd; 454 __le16 l2tag2_1; 455 __le16 l2tag2_2; 456 } qword2; 457 struct { 458 union { 459 __le32 flex_bytes_lo; 460 __le32 pe_status; 461 } lo_dword; 462 union { 463 __le32 flex_bytes_hi; 464 __le32 fd_id; 465 } hi_dword; 466 } qword3; 467 } wb; /* writeback */ 468 }; 469 470 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT 8 471 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \ 472 IAVF_RXD_QW0_MIRROR_STATUS_SHIFT) 473 #define IAVF_RXD_QW0_FCOEINDX_SHIFT 0 474 #define IAVF_RXD_QW0_FCOEINDX_MASK (0xFFFUL << \ 475 IAVF_RXD_QW0_FCOEINDX_SHIFT) 476 477 enum iavf_rx_desc_status_bits { 478 /* Note: These are predefined bit offsets */ 479 IAVF_RX_DESC_STATUS_DD_SHIFT = 0, 480 IAVF_RX_DESC_STATUS_EOF_SHIFT = 1, 481 IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT = 2, 482 IAVF_RX_DESC_STATUS_L3L4P_SHIFT = 3, 483 IAVF_RX_DESC_STATUS_CRCP_SHIFT = 4, 484 IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */ 485 IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT = 7, 486 IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8, 487 488 IAVF_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */ 489 IAVF_RX_DESC_STATUS_FLM_SHIFT = 11, 490 IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */ 491 IAVF_RX_DESC_STATUS_LPBK_SHIFT = 14, 492 IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15, 493 IAVF_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */ 494 IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18, 495 IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */ 496 }; 497 498 #define IAVF_RXD_QW1_STATUS_SHIFT 0 499 #define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \ 500 << IAVF_RXD_QW1_STATUS_SHIFT) 501 502 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT 503 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \ 504 IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT) 505 506 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT 507 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT) 508 509 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT IAVF_RX_DESC_STATUS_UMBCAST 510 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK (0x3UL << \ 511 IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT) 512 513 enum iavf_rx_desc_fltstat_values { 514 IAVF_RX_DESC_FLTSTAT_NO_DATA = 0, 515 IAVF_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */ 516 IAVF_RX_DESC_FLTSTAT_RSV = 2, 517 IAVF_RX_DESC_FLTSTAT_RSS_HASH = 3, 518 }; 519 520 #define IAVF_RXD_PACKET_TYPE_UNICAST 0 521 #define IAVF_RXD_PACKET_TYPE_MULTICAST 1 522 #define IAVF_RXD_PACKET_TYPE_BROADCAST 2 523 #define IAVF_RXD_PACKET_TYPE_MIRRORED 3 524 525 #define IAVF_RXD_QW1_ERROR_SHIFT 19 526 #define IAVF_RXD_QW1_ERROR_MASK (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT) 527 528 enum iavf_rx_desc_error_bits { 529 /* Note: These are predefined bit offsets */ 530 IAVF_RX_DESC_ERROR_RXE_SHIFT = 0, 531 IAVF_RX_DESC_ERROR_RECIPE_SHIFT = 1, 532 IAVF_RX_DESC_ERROR_HBO_SHIFT = 2, 533 IAVF_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */ 534 IAVF_RX_DESC_ERROR_IPE_SHIFT = 3, 535 IAVF_RX_DESC_ERROR_L4E_SHIFT = 4, 536 IAVF_RX_DESC_ERROR_EIPE_SHIFT = 5, 537 IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT = 6, 538 IAVF_RX_DESC_ERROR_PPRS_SHIFT = 7 539 }; 540 541 enum iavf_rx_desc_error_l3l4e_fcoe_masks { 542 IAVF_RX_DESC_ERROR_L3L4E_NONE = 0, 543 IAVF_RX_DESC_ERROR_L3L4E_PROT = 1, 544 IAVF_RX_DESC_ERROR_L3L4E_FC = 2, 545 IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3, 546 IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4 547 }; 548 549 #define IAVF_RXD_QW1_PTYPE_SHIFT 30 550 #define IAVF_RXD_QW1_PTYPE_MASK (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT) 551 552 /* Packet type non-ip values */ 553 enum iavf_rx_l2_ptype { 554 IAVF_RX_PTYPE_L2_RESERVED = 0, 555 IAVF_RX_PTYPE_L2_MAC_PAY2 = 1, 556 IAVF_RX_PTYPE_L2_TIMESYNC_PAY2 = 2, 557 IAVF_RX_PTYPE_L2_FIP_PAY2 = 3, 558 IAVF_RX_PTYPE_L2_OUI_PAY2 = 4, 559 IAVF_RX_PTYPE_L2_MACCNTRL_PAY2 = 5, 560 IAVF_RX_PTYPE_L2_LLDP_PAY2 = 6, 561 IAVF_RX_PTYPE_L2_ECP_PAY2 = 7, 562 IAVF_RX_PTYPE_L2_EVB_PAY2 = 8, 563 IAVF_RX_PTYPE_L2_QCN_PAY2 = 9, 564 IAVF_RX_PTYPE_L2_EAPOL_PAY2 = 10, 565 IAVF_RX_PTYPE_L2_ARP = 11, 566 IAVF_RX_PTYPE_L2_FCOE_PAY3 = 12, 567 IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13, 568 IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14, 569 IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15, 570 IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16, 571 IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17, 572 IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18, 573 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19, 574 IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20, 575 IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21, 576 IAVF_RX_PTYPE_GRENAT4_MAC_PAY3 = 58, 577 IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87, 578 IAVF_RX_PTYPE_GRENAT6_MAC_PAY3 = 124, 579 IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153, 580 IAVF_RX_PTYPE_PARSER_ABORTED = 255 581 }; 582 583 struct iavf_rx_ptype_decoded { 584 u32 ptype:8; 585 u32 known:1; 586 u32 outer_ip:1; 587 u32 outer_ip_ver:1; 588 u32 outer_frag:1; 589 u32 tunnel_type:3; 590 u32 tunnel_end_prot:2; 591 u32 tunnel_end_frag:1; 592 u32 inner_prot:4; 593 u32 payload_layer:3; 594 }; 595 596 enum iavf_rx_ptype_outer_ip { 597 IAVF_RX_PTYPE_OUTER_L2 = 0, 598 IAVF_RX_PTYPE_OUTER_IP = 1 599 }; 600 601 enum iavf_rx_ptype_outer_ip_ver { 602 IAVF_RX_PTYPE_OUTER_NONE = 0, 603 IAVF_RX_PTYPE_OUTER_IPV4 = 0, 604 IAVF_RX_PTYPE_OUTER_IPV6 = 1 605 }; 606 607 enum iavf_rx_ptype_outer_fragmented { 608 IAVF_RX_PTYPE_NOT_FRAG = 0, 609 IAVF_RX_PTYPE_FRAG = 1 610 }; 611 612 enum iavf_rx_ptype_tunnel_type { 613 IAVF_RX_PTYPE_TUNNEL_NONE = 0, 614 IAVF_RX_PTYPE_TUNNEL_IP_IP = 1, 615 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT = 2, 616 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3, 617 IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4, 618 }; 619 620 enum iavf_rx_ptype_tunnel_end_prot { 621 IAVF_RX_PTYPE_TUNNEL_END_NONE = 0, 622 IAVF_RX_PTYPE_TUNNEL_END_IPV4 = 1, 623 IAVF_RX_PTYPE_TUNNEL_END_IPV6 = 2, 624 }; 625 626 enum iavf_rx_ptype_inner_prot { 627 IAVF_RX_PTYPE_INNER_PROT_NONE = 0, 628 IAVF_RX_PTYPE_INNER_PROT_UDP = 1, 629 IAVF_RX_PTYPE_INNER_PROT_TCP = 2, 630 IAVF_RX_PTYPE_INNER_PROT_SCTP = 3, 631 IAVF_RX_PTYPE_INNER_PROT_ICMP = 4, 632 IAVF_RX_PTYPE_INNER_PROT_TIMESYNC = 5 633 }; 634 635 enum iavf_rx_ptype_payload_layer { 636 IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE = 0, 637 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1, 638 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2, 639 IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3, 640 }; 641 642 #define IAVF_RX_PTYPE_BIT_MASK 0x0FFFFFFF 643 #define IAVF_RX_PTYPE_SHIFT 56 644 645 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT 38 646 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \ 647 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) 648 649 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT 52 650 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \ 651 IAVF_RXD_QW1_LENGTH_HBUF_SHIFT) 652 653 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT 63 654 #define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT) 655 656 #define IAVF_RXD_QW1_NEXTP_SHIFT 38 657 #define IAVF_RXD_QW1_NEXTP_MASK (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT) 658 659 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT 0 660 #define IAVF_RXD_QW2_EXT_STATUS_MASK (0xFFFFFUL << \ 661 IAVF_RXD_QW2_EXT_STATUS_SHIFT) 662 663 enum iavf_rx_desc_ext_status_bits { 664 /* Note: These are predefined bit offsets */ 665 IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0, 666 IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1, 667 IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */ 668 IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */ 669 IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9, 670 IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10, 671 IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11, 672 }; 673 674 #define IAVF_RXD_QW2_L2TAG2_SHIFT 0 675 #define IAVF_RXD_QW2_L2TAG2_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT) 676 677 #define IAVF_RXD_QW2_L2TAG3_SHIFT 16 678 #define IAVF_RXD_QW2_L2TAG3_MASK (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT) 679 680 enum iavf_rx_desc_pe_status_bits { 681 /* Note: These are predefined bit offsets */ 682 IAVF_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */ 683 IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */ 684 IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */ 685 IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24, 686 IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25, 687 IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT = 26, 688 IAVF_RX_DESC_PE_STATUS_URG_SHIFT = 27, 689 IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28, 690 IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29 691 }; 692 693 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38 694 #define IAVF_RX_PROG_STATUS_DESC_LENGTH 0x2000000 695 696 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2 697 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \ 698 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT) 699 700 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT 0 701 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK (0x7FFFUL << \ 702 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT) 703 704 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19 705 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \ 706 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT) 707 708 enum iavf_rx_prog_status_desc_status_bits { 709 /* Note: These are predefined bit offsets */ 710 IAVF_RX_PROG_STATUS_DESC_DD_SHIFT = 0, 711 IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */ 712 }; 713 714 enum iavf_rx_prog_status_desc_prog_id_masks { 715 IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1, 716 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2, 717 IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4, 718 }; 719 720 enum iavf_rx_prog_status_desc_error_bits { 721 /* Note: These are predefined bit offsets */ 722 IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0, 723 IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1, 724 IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2, 725 IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3 726 }; 727 728 #define IAVF_TWO_BIT_MASK 0x3 729 #define IAVF_THREE_BIT_MASK 0x7 730 #define IAVF_FOUR_BIT_MASK 0xF 731 #define IAVF_EIGHTEEN_BIT_MASK 0x3FFFF 732 733 /* TX Descriptor */ 734 struct iavf_tx_desc { 735 __le64 buffer_addr; /* Address of descriptor's data buf */ 736 __le64 cmd_type_offset_bsz; 737 }; 738 739 #define IAVF_TXD_QW1_DTYPE_SHIFT 0 740 #define IAVF_TXD_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT) 741 742 enum iavf_tx_desc_dtype_value { 743 IAVF_TX_DESC_DTYPE_DATA = 0x0, 744 IAVF_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */ 745 IAVF_TX_DESC_DTYPE_CONTEXT = 0x1, 746 IAVF_TX_DESC_DTYPE_FCOE_CTX = 0x2, 747 IAVF_TX_DESC_DTYPE_FILTER_PROG = 0x8, 748 IAVF_TX_DESC_DTYPE_DDP_CTX = 0x9, 749 IAVF_TX_DESC_DTYPE_FLEX_DATA = 0xB, 750 IAVF_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC, 751 IAVF_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD, 752 IAVF_TX_DESC_DTYPE_DESC_DONE = 0xF 753 }; 754 755 #define IAVF_TXD_QW1_CMD_SHIFT 4 756 #define IAVF_TXD_QW1_CMD_MASK (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT) 757 758 enum iavf_tx_desc_cmd_bits { 759 IAVF_TX_DESC_CMD_EOP = 0x0001, 760 IAVF_TX_DESC_CMD_RS = 0x0002, 761 IAVF_TX_DESC_CMD_ICRC = 0x0004, 762 IAVF_TX_DESC_CMD_IL2TAG1 = 0x0008, 763 IAVF_TX_DESC_CMD_DUMMY = 0x0010, 764 IAVF_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */ 765 IAVF_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */ 766 IAVF_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */ 767 IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */ 768 IAVF_TX_DESC_CMD_FCOET = 0x0080, 769 IAVF_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */ 770 IAVF_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */ 771 IAVF_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */ 772 IAVF_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */ 773 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */ 774 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */ 775 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */ 776 IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */ 777 }; 778 779 #define IAVF_TXD_QW1_OFFSET_SHIFT 16 780 #define IAVF_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \ 781 IAVF_TXD_QW1_OFFSET_SHIFT) 782 783 enum iavf_tx_desc_length_fields { 784 /* Note: These are predefined bit offsets */ 785 IAVF_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */ 786 IAVF_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */ 787 IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */ 788 }; 789 790 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT) 791 #define IAVF_TXD_QW1_IPLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT) 792 #define IAVF_TXD_QW1_L4LEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 793 #define IAVF_TXD_QW1_FCLEN_MASK (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT) 794 795 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT 34 796 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \ 797 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) 798 799 #define IAVF_TXD_QW1_L2TAG1_SHIFT 48 800 #define IAVF_TXD_QW1_L2TAG1_MASK (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT) 801 802 /* Context descriptors */ 803 struct iavf_tx_context_desc { 804 __le32 tunneling_params; 805 __le16 l2tag2; 806 __le16 rsvd; 807 __le64 type_cmd_tso_mss; 808 }; 809 810 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT 0 811 #define IAVF_TXD_CTX_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT) 812 813 #define IAVF_TXD_CTX_QW1_CMD_SHIFT 4 814 #define IAVF_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT) 815 816 enum iavf_tx_ctx_desc_cmd_bits { 817 IAVF_TX_CTX_DESC_TSO = 0x01, 818 IAVF_TX_CTX_DESC_TSYN = 0x02, 819 IAVF_TX_CTX_DESC_IL2TAG2 = 0x04, 820 IAVF_TX_CTX_DESC_IL2TAG2_IL2H = 0x08, 821 IAVF_TX_CTX_DESC_SWTCH_NOTAG = 0x00, 822 IAVF_TX_CTX_DESC_SWTCH_UPLINK = 0x10, 823 IAVF_TX_CTX_DESC_SWTCH_LOCAL = 0x20, 824 IAVF_TX_CTX_DESC_SWTCH_VSI = 0x30, 825 IAVF_TX_CTX_DESC_SWPE = 0x40 826 }; 827 828 struct iavf_nop_desc { 829 __le64 rsvd; 830 __le64 dtype_cmd; 831 }; 832 833 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT 0 834 #define IAVF_TXD_NOP_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT) 835 836 #define IAVF_TXD_NOP_QW1_CMD_SHIFT 4 837 #define IAVF_TXD_NOP_QW1_CMD_MASK (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT) 838 839 enum iavf_tx_nop_desc_cmd_bits { 840 /* Note: These are predefined bit offsets */ 841 IAVF_TX_NOP_DESC_EOP_SHIFT = 0, 842 IAVF_TX_NOP_DESC_RS_SHIFT = 1, 843 IAVF_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */ 844 }; 845 846 /* Packet Classifier Types for filters */ 847 enum iavf_filter_pctype { 848 /* Note: Values 0-28 are reserved for future use. 849 * Value 29, 30, 32 are not supported on XL710 and X710. 850 */ 851 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29, 852 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30, 853 IAVF_FILTER_PCTYPE_NONF_IPV4_UDP = 31, 854 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32, 855 IAVF_FILTER_PCTYPE_NONF_IPV4_TCP = 33, 856 IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP = 34, 857 IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER = 35, 858 IAVF_FILTER_PCTYPE_FRAG_IPV4 = 36, 859 /* Note: Values 37-38 are reserved for future use. 860 * Value 39, 40, 42 are not supported on XL710 and X710. 861 */ 862 IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39, 863 IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40, 864 IAVF_FILTER_PCTYPE_NONF_IPV6_UDP = 41, 865 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42, 866 IAVF_FILTER_PCTYPE_NONF_IPV6_TCP = 43, 867 IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP = 44, 868 IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER = 45, 869 IAVF_FILTER_PCTYPE_FRAG_IPV6 = 46, 870 /* Note: Value 47 is reserved for future use */ 871 IAVF_FILTER_PCTYPE_FCOE_OX = 48, 872 IAVF_FILTER_PCTYPE_FCOE_RX = 49, 873 IAVF_FILTER_PCTYPE_FCOE_OTHER = 50, 874 /* Note: Values 51-62 are reserved for future use */ 875 IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63, 876 }; 877 878 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT 0 879 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT) 880 881 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \ 882 IAVF_TXD_FLTR_QW1_CMD_SHIFT) 883 #define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT) 884 885 886 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30 887 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \ 888 IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) 889 890 #define IAVF_TXD_CTX_QW1_MSS_SHIFT 50 891 #define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \ 892 IAVF_TXD_CTX_QW1_MSS_SHIFT) 893 894 #define IAVF_TXD_CTX_QW1_VSI_SHIFT 50 895 #define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT) 896 897 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0 898 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \ 899 IAVF_TXD_CTX_QW0_EXT_IP_SHIFT) 900 901 enum iavf_tx_ctx_desc_eipt_offload { 902 IAVF_TX_CTX_EXT_IP_NONE = 0x0, 903 IAVF_TX_CTX_EXT_IP_IPV6 = 0x1, 904 IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2, 905 IAVF_TX_CTX_EXT_IP_IPV4 = 0x3 906 }; 907 908 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2 909 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \ 910 IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT) 911 912 #define IAVF_TXD_CTX_QW0_NATT_SHIFT 9 913 #define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 914 915 #define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT) 916 #define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT) 917 918 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11 919 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \ 920 BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT) 921 922 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK 923 924 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12 925 #define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \ 926 IAVF_TXD_CTX_QW0_NATLEN_SHIFT) 927 928 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19 929 #define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \ 930 IAVF_TXD_CTX_QW0_DECTTL_SHIFT) 931 932 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23 933 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT) 934 935 /* Statistics collected by each port, VSI, VEB, and S-channel */ 936 struct iavf_eth_stats { 937 u64 rx_bytes; /* gorc */ 938 u64 rx_unicast; /* uprc */ 939 u64 rx_multicast; /* mprc */ 940 u64 rx_broadcast; /* bprc */ 941 u64 rx_discards; /* rdpc */ 942 u64 rx_unknown_protocol; /* rupp */ 943 u64 tx_bytes; /* gotc */ 944 u64 tx_unicast; /* uptc */ 945 u64 tx_multicast; /* mptc */ 946 u64 tx_broadcast; /* bptc */ 947 u64 tx_discards; /* tdpc */ 948 u64 tx_errors; /* tepc */ 949 }; 950 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR 0x03 951 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR 0x04 952 #define IAVF_SR_OPTION_ROM_PTR 0x05 953 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR 0x06 954 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR 0x07 955 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR 0x08 956 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR 0x09 957 #define IAVF_SR_RO_PCIE_LCB_PTR 0x0A 958 #define IAVF_SR_EMP_IMAGE_PTR 0x0B 959 #define IAVF_SR_PE_IMAGE_PTR 0x0C 960 #define IAVF_SR_CSR_PROTECTED_LIST_PTR 0x0D 961 #define IAVF_SR_MNG_CONFIG_PTR 0x0E 962 #define IAVF_SR_PBA_FLAGS 0x15 963 #define IAVF_SR_PBA_BLOCK_PTR 0x16 964 #define IAVF_SR_BOOT_CONFIG_PTR 0x17 965 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28 966 #define IAVF_SR_NVM_MAP_VERSION 0x29 967 #define IAVF_SR_NVM_IMAGE_VERSION 0x2A 968 #define IAVF_SR_NVM_STRUCTURE_VERSION 0x2B 969 #define IAVF_SR_PXE_SETUP_PTR 0x30 970 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31 971 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO 0x34 972 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI 0x35 973 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR 0x37 974 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR 0x38 975 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR 0x3A 976 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B 977 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C 978 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR 0x3D 979 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR 0x40 980 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR 0x42 981 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR 0x44 982 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR 0x46 983 #define IAVF_SR_EMP_SR_SETTINGS_PTR 0x48 984 #define IAVF_SR_FEATURE_CONFIGURATION_PTR 0x49 985 #define IAVF_SR_CONFIGURATION_METADATA_PTR 0x4D 986 #define IAVF_SR_IMMEDIATE_VALUES_PTR 0x4E 987 #define IAVF_SR_OCP_CFG_WORD0 0x2B 988 #define IAVF_SR_OCP_ENABLED BIT(15) 989 #define IAVF_SR_BUF_ALIGNMENT 4096 990 991 struct iavf_lldp_variables { 992 u16 length; 993 u16 adminstatus; 994 u16 msgfasttx; 995 u16 msgtxinterval; 996 u16 txparams; 997 u16 timers; 998 u16 crc8; 999 }; 1000 1001 /* Offsets into Alternate Ram */ 1002 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET 0 /* in dwords */ 1003 #define IAVF_ALT_STRUCT_DWORDS_PER_PF 64 /* in dwords */ 1004 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD /* in dwords */ 1005 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC /* in dwords */ 1006 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET 0xE /* in dwords */ 1007 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET 0xF /* in dwords */ 1008 1009 /* Alternate Ram Bandwidth Masks */ 1010 #define IAVF_ALT_BW_VALUE_MASK 0xFF 1011 #define IAVF_ALT_BW_RELATIVE_MASK 0x40000000 1012 #define IAVF_ALT_BW_VALID_MASK 0x80000000 1013 1014 #define IAVF_DDP_TRACKID_RDONLY 0 1015 #define IAVF_DDP_TRACKID_INVALID 0xFFFFFFFF 1016 #define SECTION_TYPE_RB_MMIO 0x00001800 1017 #define SECTION_TYPE_RB_AQ 0x00001801 1018 #define SECTION_TYPE_PROTO 0x80000002 1019 #define SECTION_TYPE_PCTYPE 0x80000003 1020 #define SECTION_TYPE_PTYPE 0x80000004 1021 struct iavf_profile_tlv_section_record { 1022 u8 rtype; 1023 u8 type; 1024 u16 len; 1025 u8 data[12]; 1026 }; 1027 1028 /* Generic AQ section in proflie */ 1029 struct iavf_profile_aq_section { 1030 u16 opcode; 1031 u16 flags; 1032 u8 param[16]; 1033 u16 datalen; 1034 u8 data[1]; 1035 }; 1036 1037 #endif /* _IAVF_TYPE_H_ */
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