FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/adwlib.c
1 /* $NetBSD: adwlib.c,v 1.33 2005/02/27 00:27:00 perry Exp $ */
2
3 /*
4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips
5 *
6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * Author: Baldassare Dante Profeta <dante@mclink.it>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39 /*
40 * Ported from:
41 */
42 /*
43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
44 *
45 * Copyright (c) 1995-2000 Advanced System Products, Inc.
46 * All Rights Reserved.
47 *
48 * Redistribution and use in source and binary forms, with or without
49 * modification, are permitted provided that redistributions of source
50 * code retain the above copyright notice and this comment without
51 * modification.
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.33 2005/02/27 00:27:00 perry Exp $");
56
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/queue.h>
62 #include <sys/device.h>
63
64 #include <machine/bus.h>
65 #include <machine/intr.h>
66
67 #include <dev/scsipi/scsi_all.h>
68 #include <dev/scsipi/scsipi_all.h>
69 #include <dev/scsipi/scsiconf.h>
70
71 #include <dev/pci/pcidevs.h>
72
73 #include <uvm/uvm_extern.h>
74
75 #include <dev/ic/adwlib.h>
76 #include <dev/ic/adwmcode.h>
77 #include <dev/ic/adw.h>
78
79
80 /* Static Functions */
81
82 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t);
83 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, u_int8_t);
84 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *);
85 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *);
86 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *);
87
88 static u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t,
89 ADW_EEPROM *);
90 static void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t,
91 ADW_EEPROM *);
92 static u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int);
93 static void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t);
94
95 static void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
96
97 static void AdwSleepMilliSecond(u_int32_t);
98 static void AdwDelayMicroSecond(u_int32_t);
99
100
101 /*
102 * EEPROM Configuration.
103 *
104 * All drivers should use this structure to set the default EEPROM
105 * configuration. The BIOS now uses this structure when it is built.
106 * Additional structure information can be found in adwlib.h where
107 * the structure is defined.
108 */
109 const static ADW_EEPROM adw_3550_Default_EEPROM = {
110 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
111 0x0000, /* 01 cfg_msw */
112 0xFFFF, /* 02 disc_enable */
113 0xFFFF, /* 03 wdtr_able */
114 { 0xFFFF }, /* 04 sdtr_able */
115 0xFFFF, /* 05 start_motor */
116 0xFFFF, /* 06 tagqng_able */
117 0xFFFF, /* 07 bios_scan */
118 0, /* 08 scam_tolerant */
119 7, /* 09 adapter_scsi_id */
120 0, /* bios_boot_delay */
121 3, /* 10 scsi_reset_delay */
122 0, /* bios_id_lun */
123 0, /* 11 termination */
124 0, /* reserved1 */
125 0xFFE7, /* 12 bios_ctrl */
126 { 0xFFFF }, /* 13 ultra_able */
127 { 0 }, /* 14 reserved2 */
128 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
129 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
130 0, /* 16 dvc_cntl */
131 { 0 }, /* 17 bug_fix */
132 { 0,0,0 }, /* 18-20 serial_number[3] */
133 0, /* 21 check_sum */
134 { /* 22-29 oem_name[16] */
135 0,0,0,0,0,0,0,0,
136 0,0,0,0,0,0,0,0
137 },
138 0, /* 30 dvc_err_code */
139 0, /* 31 adv_err_code */
140 0, /* 32 adv_err_addr */
141 0, /* 33 saved_dvc_err_code */
142 0, /* 34 saved_adv_err_code */
143 0 /* 35 saved_adv_err_addr */
144 };
145
146 const static ADW_EEPROM adw_38C0800_Default_EEPROM = {
147 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
148 0x0000, /* 01 cfg_msw */
149 0xFFFF, /* 02 disc_enable */
150 0xFFFF, /* 03 wdtr_able */
151 { 0x4444 }, /* 04 sdtr_speed1 */
152 0xFFFF, /* 05 start_motor */
153 0xFFFF, /* 06 tagqng_able */
154 0xFFFF, /* 07 bios_scan */
155 0, /* 08 scam_tolerant */
156 7, /* 09 adapter_scsi_id */
157 0, /* bios_boot_delay */
158 3, /* 10 scsi_reset_delay */
159 0, /* bios_id_lun */
160 0, /* 11 termination_se */
161 0, /* termination_lvd */
162 0xFFE7, /* 12 bios_ctrl */
163 { 0x4444 }, /* 13 sdtr_speed2 */
164 { 0x4444 }, /* 14 sdtr_speed3 */
165 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
166 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
167 0, /* 16 dvc_cntl */
168 { 0x4444 }, /* 17 sdtr_speed4 */
169 { 0,0,0 }, /* 18-20 serial_number[3] */
170 0, /* 21 check_sum */
171 { /* 22-29 oem_name[16] */
172 0,0,0,0,0,0,0,0,
173 0,0,0,0,0,0,0,0
174 },
175 0, /* 30 dvc_err_code */
176 0, /* 31 adv_err_code */
177 0, /* 32 adv_err_addr */
178 0, /* 33 saved_dvc_err_code */
179 0, /* 34 saved_adv_err_code */
180 0, /* 35 saved_adv_err_addr */
181 { /* 36-55 reserved1[16] */
182 0,0,0,0,0,0,0,0,0,0,
183 0,0,0,0,0,0,0,0,0,0
184 },
185 0, /* 56 cisptr_lsw */
186 0, /* 57 cisprt_msw */
187 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
188 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */
189 { 0,0,0,0 } /* 60-63 reserved2[4] */
190 };
191
192 const static ADW_EEPROM adw_38C1600_Default_EEPROM = {
193 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
194 0x0000, /* 01 cfg_msw */
195 0xFFFF, /* 02 disc_enable */
196 0xFFFF, /* 03 wdtr_able */
197 { 0x5555 }, /* 04 sdtr_speed1 */
198 0xFFFF, /* 05 start_motor */
199 0xFFFF, /* 06 tagqng_able */
200 0xFFFF, /* 07 bios_scan */
201 0, /* 08 scam_tolerant */
202 7, /* 09 adapter_scsi_id */
203 0, /* bios_boot_delay */
204 3, /* 10 scsi_reset_delay */
205 0, /* bios_id_lun */
206 0, /* 11 termination_se */
207 0, /* termination_lvd */
208 0xFFE7, /* 12 bios_ctrl */
209 { 0x5555 }, /* 13 sdtr_speed2 */
210 { 0x5555 }, /* 14 sdtr_speed3 */
211 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
212 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
213 0, /* 16 dvc_cntl */
214 { 0x5555 }, /* 17 sdtr_speed4 */
215 { 0,0,0 }, /* 18-20 serial_number[3] */
216 0, /* 21 check_sum */
217 { /* 22-29 oem_name[16] */
218 0,0,0,0,0,0,0,0,
219 0,0,0,0,0,0,0,0
220 },
221 0, /* 30 dvc_err_code */
222 0, /* 31 adv_err_code */
223 0, /* 32 adv_err_addr */
224 0, /* 33 saved_dvc_err_code */
225 0, /* 34 saved_adv_err_code */
226 0, /* 35 saved_adv_err_addr */
227 { /* 36-55 reserved1[16] */
228 0,0,0,0,0,0,0,0,0,0,
229 0,0,0,0,0,0,0,0,0,0
230 },
231 0, /* 56 cisptr_lsw */
232 0, /* 57 cisprt_msw */
233 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
234 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */
235 { 0,0,0,0 } /* 60-63 reserved2[4] */
236 };
237
238
239 /*
240 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and
241 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while
242 * all of this is done.
243 *
244 * For a non-fatal error return a warning code. If there are no warnings
245 * then 0 is returned.
246 *
247 * Note: Chip is stopped on entry.
248 */
249 int
250 AdwInitFromEEPROM(sc)
251 ADW_SOFTC *sc;
252 {
253 bus_space_tag_t iot = sc->sc_iot;
254 bus_space_handle_t ioh = sc->sc_ioh;
255 ADW_EEPROM eep_config;
256 u_int16_t warn_code;
257 u_int16_t sdtr_speed = 0;
258 u_int8_t tid, termination;
259 int i, j;
260
261
262 warn_code = 0;
263
264 /*
265 * Read the board's EEPROM configuration.
266 *
267 * Set default values if a bad checksum is found.
268 *
269 * XXX - Don't handle big-endian access to EEPROM yet.
270 */
271 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) {
272 warn_code |= ADW_WARN_EEPROM_CHKSUM;
273
274 /*
275 * Set EEPROM default values.
276 */
277 switch(sc->chip_type) {
278 case ADW_CHIP_ASC3550:
279 eep_config = adw_3550_Default_EEPROM;
280 break;
281 case ADW_CHIP_ASC38C0800:
282 eep_config = adw_38C0800_Default_EEPROM;
283 break;
284 case ADW_CHIP_ASC38C1600:
285 eep_config = adw_38C1600_Default_EEPROM;
286
287 #if 0
288 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) {
289 #endif
290 if (sc->cfg.pci_slot_info != 0) {
291 u_int8_t lsw_msb;
292
293 lsw_msb = eep_config.cfg_lsw >> 8;
294 /*
295 * Set Function 1 EEPROM Word 0 MSB
296 *
297 * Clear the BIOS_ENABLE (bit 14) and
298 * INTAB (bit 11) EEPROM bits.
299 *
300 * Disable Bit 14 (BIOS_ENABLE) to fix
301 * SPARC Ultra 60 and old Mac system booting
302 * problem. The Expansion ROM must
303 * be disabled in Function 1 for these systems.
304 */
305 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE |
306 ADW_EEPROM_INTAB) >> 8) & 0xFF);
307 /*
308 * Set the INTAB (bit 11) if the GPIO 0 input
309 * indicates the Function 1 interrupt line is
310 * wired to INTA.
311 *
312 * Set/Clear Bit 11 (INTAB) from
313 * the GPIO bit 0 input:
314 * 1 - Function 1 intr line wired to INT A.
315 * 0 - Function 1 intr line wired to INT B.
316 *
317 * Note: Adapter boards always have Function 0
318 * wired to INTA.
319 * Put all 5 GPIO bits in input mode and then
320 * read their input values.
321 */
322 ADW_WRITE_BYTE_REGISTER(iot, ioh,
323 IOPB_GPIO_CNTL, 0);
324 if (ADW_READ_BYTE_REGISTER(iot, ioh,
325 IOPB_GPIO_DATA) & 0x01) {
326 /*
327 * Function 1 interrupt wired to INTA;
328 * Set EEPROM bit.
329 */
330 lsw_msb |= (ADW_EEPROM_INTAB >> 8)
331 & 0xFF;
332 }
333 eep_config.cfg_lsw &= 0x00FF;
334 eep_config.cfg_lsw |= lsw_msb << 8;
335 }
336 break;
337 }
338
339 /*
340 * Assume the 6 byte board serial number that was read
341 * from EEPROM is correct even if the EEPROM checksum
342 * failed.
343 */
344 for (i=2, j=1; i>=0; i--, j++) {
345 eep_config.serial_number[i] =
346 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j);
347 }
348
349 AdwSetEEPROMConfig(iot, ioh, &eep_config);
350 }
351 /*
352 * Set sc and sc->cfg variables from the EEPROM configuration
353 * that was read.
354 *
355 * This is the mapping of EEPROM fields to Adw Library fields.
356 */
357 sc->wdtr_able = eep_config.wdtr_able;
358 if (sc->chip_type == ADW_CHIP_ASC3550) {
359 sc->sdtr_able = eep_config.sdtr1.sdtr_able;
360 sc->ultra_able = eep_config.sdtr2.ultra_able;
361 } else {
362 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1;
363 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2;
364 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3;
365 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4;
366 }
367 sc->ppr_able = 0;
368 sc->tagqng_able = eep_config.tagqng_able;
369 sc->cfg.disc_enable = eep_config.disc_enable;
370 sc->max_host_qng = eep_config.max_host_qng;
371 sc->max_dvc_qng = eep_config.max_dvc_qng;
372 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
373 sc->start_motor = eep_config.start_motor;
374 sc->scsi_reset_wait = eep_config.scsi_reset_delay;
375 sc->bios_ctrl = eep_config.bios_ctrl;
376 sc->no_scam = eep_config.scam_tolerant;
377 sc->cfg.serial1 = eep_config.serial_number[0];
378 sc->cfg.serial2 = eep_config.serial_number[1];
379 sc->cfg.serial3 = eep_config.serial_number[2];
380
381 if (sc->chip_type == ADW_CHIP_ASC38C0800 ||
382 sc->chip_type == ADW_CHIP_ASC38C1600) {
383 sc->sdtr_able = 0;
384 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
385 if (tid == 0) {
386 sdtr_speed = sc->sdtr_speed1;
387 } else if (tid == 4) {
388 sdtr_speed = sc->sdtr_speed2;
389 } else if (tid == 8) {
390 sdtr_speed = sc->sdtr_speed3;
391 } else if (tid == 12) {
392 sdtr_speed = sc->sdtr_speed4;
393 }
394 if (sdtr_speed & ADW_MAX_TID) {
395 sc->sdtr_able |= (1 << tid);
396 }
397 sdtr_speed >>= 4;
398 }
399 }
400
401 /*
402 * Set the host maximum queuing (max. 253, min. 16) and the per device
403 * maximum queuing (max. 63, min. 4).
404 */
405 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) {
406 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
407 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG)
408 {
409 /* If the value is zero, assume it is uninitialized. */
410 if (eep_config.max_host_qng == 0) {
411 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
412 } else {
413 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG;
414 }
415 }
416
417 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) {
418 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
419 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) {
420 /* If the value is zero, assume it is uninitialized. */
421 if (eep_config.max_dvc_qng == 0) {
422 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
423 } else {
424 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG;
425 }
426 }
427
428 /*
429 * If 'max_dvc_qng' is greater than 'max_host_qng', then
430 * set 'max_dvc_qng' to 'max_host_qng'.
431 */
432 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
433 eep_config.max_dvc_qng = eep_config.max_host_qng;
434 }
435
436 /*
437 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
438 * values based on possibly adjusted EEPROM values.
439 */
440 sc->max_host_qng = eep_config.max_host_qng;
441 sc->max_dvc_qng = eep_config.max_dvc_qng;
442
443
444 /*
445 * If the EEPROM 'termination' field is set to automatic (0), then set
446 * the ADV_DVC_CFG 'termination' field to automatic also.
447 *
448 * If the termination is specified with a non-zero 'termination'
449 * value check that a legal value is set and set the ADV_DVC_CFG
450 * 'termination' field appropriately.
451 */
452
453 switch(sc->chip_type) {
454 case ADW_CHIP_ASC3550:
455 sc->cfg.termination = 0; /* auto termination */
456 switch(eep_config.termination_se) {
457 case 3:
458 /* Enable manual control with low on / high on. */
459 sc->cfg.termination |= ADW_TERM_CTL_L;
460 case 2:
461 /* Enable manual control with low off / high on. */
462 sc->cfg.termination |= ADW_TERM_CTL_H;
463 case 1:
464 /* Enable manual control with low off / high off. */
465 sc->cfg.termination |= ADW_TERM_CTL_SEL;
466 case 0:
467 break;
468 default:
469 warn_code |= ADW_WARN_EEPROM_TERMINATION;
470 }
471 break;
472
473 case ADW_CHIP_ASC38C0800:
474 case ADW_CHIP_ASC38C1600:
475 switch(eep_config.termination_se) {
476 case 0:
477 /* auto termination for SE */
478 termination = 0;
479 break;
480 case 1:
481 /* Enable manual control with low off / high off. */
482 termination = 0;
483 break;
484 case 2:
485 /* Enable manual control with low off / high on. */
486 termination = ADW_TERM_SE_HI;
487 break;
488 case 3:
489 /* Enable manual control with low on / high on. */
490 termination = ADW_TERM_SE;
491 break;
492 default:
493 /*
494 * The EEPROM 'termination_se' field contains a
495 * bad value. Use automatic termination instead.
496 */
497 termination = 0;
498 warn_code |= ADW_WARN_EEPROM_TERMINATION;
499 }
500
501 switch(eep_config.termination_lvd) {
502 case 0:
503 /* auto termination for LVD */
504 sc->cfg.termination = termination;
505 break;
506 case 1:
507 /* Enable manual control with low off / high off. */
508 sc->cfg.termination = termination;
509 break;
510 case 2:
511 /* Enable manual control with low off / high on. */
512 sc->cfg.termination = termination | ADW_TERM_LVD_HI;
513 break;
514 case 3:
515 /* Enable manual control with low on / high on. */
516 sc->cfg.termination = termination | ADW_TERM_LVD;
517 break;
518 default:
519 /*
520 * The EEPROM 'termination_lvd' field contains a
521 * bad value. Use automatic termination instead.
522 */
523 sc->cfg.termination = termination;
524 warn_code |= ADW_WARN_EEPROM_TERMINATION;
525 }
526 break;
527 }
528
529 return warn_code;
530 }
531
532
533 /*
534 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600.
535 *
536 * On failure return the error code.
537 */
538 int
539 AdwInitDriver(sc)
540 ADW_SOFTC *sc;
541 {
542 bus_space_tag_t iot = sc->sc_iot;
543 bus_space_handle_t ioh = sc->sc_ioh;
544 u_int16_t error_code;
545 int word;
546 int i;
547 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory
548 0x40-0x8F. */
549 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able;
550 u_int8_t max_cmd[ADW_MAX_TID + 1];
551 u_int8_t tid;
552
553
554 error_code = 0;
555
556 /*
557 * Save the RISC memory BIOS region before writing the microcode.
558 * The BIOS may already be loaded and using its RISC LRAM region
559 * so its region must be saved and restored.
560 *
561 * Note: This code makes the assumption, which is currently true,
562 * that a chip reset does not clear RISC LRAM.
563 */
564 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
565 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]);
566 }
567
568 /*
569 * Save current per TID negotiated values.
570 */
571 switch (sc->chip_type) {
572 case ADW_CHIP_ASC3550:
573 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){
574
575 u_int16_t bios_version, major, minor;
576
577 bios_version = bios_mem[(ADW_MC_BIOS_VERSION -
578 ADW_MC_BIOSMEM) / 2];
579 major = (bios_version >> 12) & 0xF;
580 minor = (bios_version >> 8) & 0xF;
581 if (major < 3 || (major == 3 && minor == 1)) {
582 /*
583 * BIOS 3.1 and earlier location of
584 * 'wdtr_able' variable.
585 */
586 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able);
587 } else {
588 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
589 wdtr_able);
590 }
591 }
592 break;
593
594 case ADW_CHIP_ASC38C1600:
595 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
596 /* FALLTHROUGH */
597 case ADW_CHIP_ASC38C0800:
598 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
599 break;
600 }
601 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
602 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
603 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
604 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
605 max_cmd[tid]);
606 }
607
608 /*
609 * Perform a RAM Built-In Self Test
610 */
611 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) {
612 return error_code;
613 }
614
615 /*
616 * Load the Microcode
617 */
618 ;
619 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) {
620 return error_code;
621 }
622
623 /*
624 * Read microcode version and date.
625 */
626 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date);
627 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version);
628
629 /*
630 * If the PCI Configuration Command Register "Parity Error Response
631 * Control" Bit was clear (0), then set the microcode variable
632 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
633 * to ignore DMA parity errors.
634 */
635 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) {
636 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
637 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
638 word | CONTROL_FLAG_IGNORE_PERR);
639 }
640
641 switch (sc->chip_type) {
642 case ADW_CHIP_ASC3550:
643 /*
644 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a
645 * FIFO threshold of 128 bytes.
646 * This register is only accessible to the host.
647 */
648 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
649 START_CTL_EMFU | READ_CMD_MRM);
650 break;
651
652 case ADW_CHIP_ASC38C0800:
653 /*
654 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
655 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
656 * cable detection and then we are able to read C_DET[3:0].
657 *
658 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
659 * Microcode Default Value' section below.
660 */
661 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
662 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
663 | ADW_DIS_TERM_DRV);
664
665 /*
666 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
667 * START_CTL_TH [3:2] bits for the default FIFO threshold.
668 *
669 * Note: ASC-38C0800 FIFO threshold has been changed to
670 * 256 bytes.
671 *
672 * For DMA Errata #4 set the BC_THRESH_ENB bit.
673 */
674 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
675 BC_THRESH_ENB | FIFO_THRESH_80B
676 | START_CTL_TH | READ_CMD_MRM);
677 break;
678
679 case ADW_CHIP_ASC38C1600:
680 /*
681 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
682 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
683 * cable detection and then we are able to read C_DET[3:0].
684 *
685 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
686 * Microcode Default Value' section below.
687 */
688 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
689 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
690 | ADW_DIS_TERM_DRV);
691
692 /*
693 * If the BIOS control flag AIPP (Asynchronous Information
694 * Phase Protection) disable bit is not set, then set the
695 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to
696 * enable AIPP checking and encoding.
697 */
698 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
699 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
700 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
701 word | CONTROL_FLAG_ENABLE_AIPP);
702 }
703
704 /*
705 * For ASC-38C1600 use DMA_CFG0 default values:
706 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2].
707 */
708 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
709 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
710 break;
711 }
712
713 /*
714 * Microcode operating variables for WDTR, SDTR, and command tag
715 * queuing will be set in AdvInquiryHandling() based on what a
716 * device reports it is capable of in Inquiry byte 7.
717 *
718 * If SCSI Bus Resets have been disabled, then directly set
719 * SDTR and WDTR from the EEPROM configuration. This will allow
720 * the BIOS and warm boot to work without a SCSI bus hang on
721 * the Inquiry caused by host and target mismatched DTR values.
722 * Without the SCSI Bus Reset, before an Inquiry a device can't
723 * be assumed to be in Asynchronous, Narrow mode.
724 */
725 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
726 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able);
727 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able);
728 }
729
730 /*
731 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
732 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
733 * bitmask. These values determine the maximum SDTR speed negotiated
734 * with a device.
735 *
736 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
737 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
738 * without determining here whether the device supports SDTR.
739 */
740 switch (sc->chip_type) {
741 case ADW_CHIP_ASC3550:
742 word = 0;
743 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
744 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) {
745 /* Set Ultra speed for TID 'tid'. */
746 word |= (0x3 << (4 * (tid % 4)));
747 } else {
748 /* Set Fast speed for TID 'tid'. */
749 word |= (0x2 << (4 * (tid % 4)));
750 }
751 /* Check if done with sdtr_speed1. */
752 if (tid == 3) {
753 ADW_WRITE_WORD_LRAM(iot, ioh,
754 ADW_MC_SDTR_SPEED1, word);
755 word = 0;
756 /* Check if done with sdtr_speed2. */
757 } else if (tid == 7) {
758 ADW_WRITE_WORD_LRAM(iot, ioh,
759 ADW_MC_SDTR_SPEED2, word);
760 word = 0;
761 /* Check if done with sdtr_speed3. */
762 } else if (tid == 11) {
763 ADW_WRITE_WORD_LRAM(iot, ioh,
764 ADW_MC_SDTR_SPEED3, word);
765 word = 0;
766 /* Check if done with sdtr_speed4. */
767 } else if (tid == 15) {
768 ADW_WRITE_WORD_LRAM(iot, ioh,
769 ADW_MC_SDTR_SPEED4, word);
770 /* End of loop. */
771 }
772 }
773
774 /*
775 * Set microcode operating variable for the
776 * disconnect per TID bitmask.
777 */
778 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
779 sc->cfg.disc_enable);
780 break;
781
782 case ADW_CHIP_ASC38C0800:
783 /* FALLTHROUGH */
784 case ADW_CHIP_ASC38C1600:
785 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
786 sc->cfg.disc_enable);
787 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1,
788 sc->sdtr_speed1);
789 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2,
790 sc->sdtr_speed2);
791 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3,
792 sc->sdtr_speed3);
793 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4,
794 sc->sdtr_speed4);
795 break;
796 }
797
798
799 /*
800 * Set SCSI_CFG0 Microcode Default Value.
801 *
802 * The microcode will set the SCSI_CFG0 register using this value
803 * after it is started below.
804 */
805 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0,
806 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG |
807 ADW_OUR_ID_EN | sc->chip_scsi_id);
808
809
810 switch(sc->chip_type) {
811 case ADW_CHIP_ASC3550:
812 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg);
813 break;
814
815 case ADW_CHIP_ASC38C0800:
816 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg);
817 break;
818
819 case ADW_CHIP_ASC38C1600:
820 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg);
821 break;
822 }
823 if(error_code) {
824 return error_code;
825 }
826
827 /*
828 * Set SEL_MASK Microcode Default Value
829 *
830 * The microcode will set the SEL_MASK register using this value
831 * after it is started below.
832 */
833 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK,
834 ADW_TID_TO_TIDMASK(sc->chip_scsi_id));
835
836 /*
837 * Create and Initialize Host->RISC Carrier lists
838 */
839 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier,
840 sc->sc_control->carriers);
841
842 /*
843 * Set-up the Host->RISC Initiator Command Queue (ICQ).
844 */
845
846 if ((sc->icq_sp = sc->carr_freelist) == NULL) {
847 return ADW_IERR_NO_CARRIER;
848 }
849 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
850 ASC_GET_CARRP(sc->icq_sp->next_ba));
851
852 /*
853 * The first command issued will be placed in the stopper carrier.
854 */
855 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER);
856
857 /*
858 * Set RISC ICQ physical address start value.
859 */
860 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba));
861
862 /*
863 * Initialize the COMMA register to the same value otherwise
864 * the RISC will prematurely detect a command is available.
865 */
866 if(sc->chip_type == ADW_CHIP_ASC38C1600) {
867 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
868 le32toh(sc->icq_sp->carr_ba));
869 }
870
871 /*
872 * Set-up the RISC->Host Initiator Response Queue (IRQ).
873 */
874 if ((sc->irq_sp = sc->carr_freelist) == NULL) {
875 return ADW_IERR_NO_CARRIER;
876 }
877 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
878 ASC_GET_CARRP(sc->irq_sp->next_ba));
879
880 /*
881 * The first command completed by the RISC will be placed in
882 * the stopper.
883 *
884 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is
885 * completed the RISC will set the ASC_RQ_DONE bit.
886 */
887 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER);
888
889 /*
890 * Set RISC IRQ physical address start value.
891 */
892 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba));
893 sc->carr_pending_cnt = 0;
894
895 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES,
896 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR));
897 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word);
898 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word);
899
900 /* finally, finally, gentlemen, start your engine */
901 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN);
902
903 /*
904 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
905 * Resets should be performed. The RISC has to be running
906 * to issue a SCSI Bus Reset.
907 */
908 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
909 {
910 /*
911 * If the BIOS Signature is present in memory, restore the
912 * BIOS Handshake Configuration Table and do not perform
913 * a SCSI Bus Reset.
914 */
915 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] ==
916 0x55AA) {
917 /*
918 * Restore per TID negotiated values.
919 */
920 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
921 wdtr_able);
922 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
923 sdtr_able);
924 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
925 tagqng_able);
926 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
927 ADW_WRITE_BYTE_LRAM(iot, ioh,
928 ADW_MC_NUMBER_OF_MAX_CMD + tid,
929 max_cmd[tid]);
930 }
931 } else {
932 if (AdwResetCCB(sc) != ADW_TRUE) {
933 error_code = ADW_WARN_BUSRESET_ERROR;
934 }
935 }
936 }
937
938 return error_code;
939 }
940
941
942 int
943 AdwRamSelfTest(iot, ioh, chip_type)
944 bus_space_tag_t iot;
945 bus_space_handle_t ioh;
946 u_int8_t chip_type;
947 {
948 int i;
949 u_int8_t byte;
950
951
952 if ((chip_type == ADW_CHIP_ASC38C0800) ||
953 (chip_type == ADW_CHIP_ASC38C1600)) {
954 /*
955 * RAM BIST (RAM Built-In Self Test)
956 *
957 * Address : I/O base + offset 0x38h register (byte).
958 * Function: Bit 7-6(RW) : RAM mode
959 * Normal Mode : 0x00
960 * Pre-test Mode : 0x40
961 * RAM Test Mode : 0x80
962 * Bit 5 : unused
963 * Bit 4(RO) : Done bit
964 * Bit 3-0(RO) : Status
965 * Host Error : 0x08
966 * Int_RAM Error : 0x04
967 * RISC Error : 0x02
968 * SCSI Error : 0x01
969 * No Error : 0x00
970 *
971 * Note: RAM BIST code should be put right here, before loading
972 * the microcode and after saving the RISC memory BIOS region.
973 */
974
975 /*
976 * LRAM Pre-test
977 *
978 * Write PRE_TEST_MODE (0x40) to register and wait for
979 * 10 milliseconds.
980 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05),
981 * return an error. Reset to NORMAL_MODE (0x00) and do again.
982 * If cannot reset to NORMAL_MODE, return an error too.
983 */
984 for (i = 0; i < 2; i++) {
985 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
986 PRE_TEST_MODE);
987 /* Wait for 10ms before reading back. */
988 AdwSleepMilliSecond(10);
989 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
990 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) !=
991 PRE_TEST_VALUE) {
992 return ADW_IERR_BIST_PRE_TEST;
993 }
994
995 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
996 NORMAL_MODE);
997 /* Wait for 10ms before reading back. */
998 AdwSleepMilliSecond(10);
999 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST)
1000 != NORMAL_VALUE) {
1001 return ADW_IERR_BIST_PRE_TEST;
1002 }
1003 }
1004
1005 /*
1006 * LRAM Test - It takes about 1.5 ms to run through the test.
1007 *
1008 * Write RAM_TEST_MODE (0x80) to register and wait for
1009 * 10 milliseconds.
1010 * If Done bit not set or Status not 0, save register byte,
1011 * set the err_code, and return an error.
1012 */
1013 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE);
1014 /* Wait for 10ms before checking status. */
1015 AdwSleepMilliSecond(10);
1016
1017 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
1018 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) {
1019 /* Get here if Done bit not set or Status not 0. */
1020 return ADW_IERR_BIST_RAM_TEST;
1021 }
1022
1023 /* We need to reset back to normal mode after LRAM test passes*/
1024 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE);
1025 }
1026
1027 return 0;
1028 }
1029
1030
1031 int
1032 AdwLoadMCode(iot, ioh, bios_mem, chip_type)
1033 bus_space_tag_t iot;
1034 bus_space_handle_t ioh;
1035 u_int16_t *bios_mem;
1036 u_int8_t chip_type;
1037 {
1038 u_int8_t *mcode_data;
1039 u_int32_t mcode_chksum;
1040 u_int16_t mcode_size;
1041 u_int32_t sum;
1042 u_int16_t code_sum;
1043 int begin_addr;
1044 int end_addr;
1045 int word;
1046 int adw_memsize;
1047 int adw_mcode_expanded_size;
1048 int i, j;
1049
1050
1051 switch(chip_type) {
1052 case ADW_CHIP_ASC3550:
1053 mcode_data = (u_int8_t *)adw_asc3550_mcode_data.mcode_data;
1054 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum;
1055 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size;
1056 adw_memsize = ADW_3550_MEMSIZE;
1057 break;
1058
1059 case ADW_CHIP_ASC38C0800:
1060 mcode_data = (u_int8_t *)adw_asc38C0800_mcode_data.mcode_data;
1061 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum;
1062 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size;
1063 adw_memsize = ADW_38C0800_MEMSIZE;
1064 break;
1065
1066 case ADW_CHIP_ASC38C1600:
1067 mcode_data = (u_int8_t *)adw_asc38C1600_mcode_data.mcode_data;
1068 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum;
1069 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size;
1070 adw_memsize = ADW_38C1600_MEMSIZE;
1071 break;
1072
1073 default:
1074 return (EINVAL);
1075 }
1076
1077 /*
1078 * Write the microcode image to RISC memory starting at address 0.
1079 */
1080 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1081
1082 /* Assume the following compressed format of the microcode buffer:
1083 *
1084 * 254 word (508 byte) table indexed by byte code followed
1085 * by the following byte codes:
1086 *
1087 * 1-Byte Code:
1088 * 00: Emit word 0 in table.
1089 * 01: Emit word 1 in table.
1090 * .
1091 * FD: Emit word 253 in table.
1092 *
1093 * Multi-Byte Code:
1094 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
1095 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
1096 */
1097 word = 0;
1098 for (i = 253 * 2; i < mcode_size; i++) {
1099 if (mcode_data[i] == 0xff) {
1100 for (j = 0; j < mcode_data[i + 1]; j++) {
1101 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1102 (((u_int16_t)mcode_data[i + 3] << 8) |
1103 mcode_data[i + 2]));
1104 word++;
1105 }
1106 i += 3;
1107 } else if (mcode_data[i] == 0xfe) {
1108 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1109 (((u_int16_t)mcode_data[i + 2] << 8) |
1110 mcode_data[i + 1]));
1111 i += 2;
1112 word++;
1113 } else {
1114 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t)
1115 mcode_data[(mcode_data[i] * 2) + 1] <<8) |
1116 mcode_data[mcode_data[i] * 2]));
1117 word++;
1118 }
1119 }
1120
1121 /*
1122 * Set 'word' for later use to clear the rest of memory and save
1123 * the expanded mcode size.
1124 */
1125 word *= 2;
1126 adw_mcode_expanded_size = word;
1127
1128 /*
1129 * Clear the rest of the Internal RAM.
1130 */
1131 for (; word < adw_memsize; word += 2) {
1132 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0);
1133 }
1134
1135 /*
1136 * Verify the microcode checksum.
1137 */
1138 sum = 0;
1139 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1140
1141 for (word = 0; word < adw_mcode_expanded_size; word += 2) {
1142 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1143 }
1144
1145 if (sum != mcode_chksum) {
1146 return ADW_IERR_MCODE_CHKSUM;
1147 }
1148
1149 /*
1150 * Restore the RISC memory BIOS region.
1151 */
1152 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
1153 if(chip_type == ADW_CHIP_ASC3550) {
1154 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1155 bios_mem[i]);
1156 } else {
1157 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1158 bios_mem[i]);
1159 }
1160 }
1161
1162 /*
1163 * Calculate and write the microcode code checksum to the microcode
1164 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C).
1165 */
1166 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr);
1167 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr);
1168 code_sum = 0;
1169 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr);
1170 for (word = begin_addr; word < end_addr; word += 2) {
1171 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1172 }
1173 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum);
1174
1175 /*
1176 * Set the chip type.
1177 */
1178 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type);
1179
1180 return 0;
1181 }
1182
1183
1184 int
1185 AdwASC3550Cabling(iot, ioh, cfg)
1186 bus_space_tag_t iot;
1187 bus_space_handle_t ioh;
1188 ADW_DVC_CFG *cfg;
1189 {
1190 u_int16_t scsi_cfg1;
1191
1192
1193 /*
1194 * Determine SCSI_CFG1 Microcode Default Value.
1195 *
1196 * The microcode will set the SCSI_CFG1 register using this value
1197 * after it is started below.
1198 */
1199
1200 /* Read current SCSI_CFG1 Register value. */
1201 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1202
1203 /*
1204 * If all three connectors are in use in ASC3550, return an error.
1205 */
1206 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
1207 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
1208 return ADW_IERR_ILLEGAL_CONNECTION;
1209 }
1210
1211 /*
1212 * If the cable is reversed all of the SCSI_CTRL register signals
1213 * will be set. Check for and return an error if this condition is
1214 * found.
1215 */
1216 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1217 return ADW_IERR_REVERSED_CABLE;
1218 }
1219
1220 /*
1221 * If this is a differential board and a single-ended device
1222 * is attached to one of the connectors, return an error.
1223 */
1224 if ((scsi_cfg1 & ADW_DIFF_MODE) &&
1225 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) {
1226 return ADW_IERR_SINGLE_END_DEVICE;
1227 }
1228
1229 /*
1230 * If automatic termination control is enabled, then set the
1231 * termination value based on a table listed in a_condor.h.
1232 *
1233 * If manual termination was specified with an EEPROM setting
1234 * then 'termination' was set-up in AdwInitFromEEPROM() and
1235 * is ready to be 'ored' into SCSI_CFG1.
1236 */
1237 if (cfg->termination == 0) {
1238 /*
1239 * The software always controls termination by setting
1240 * TERM_CTL_SEL.
1241 * If TERM_CTL_SEL were set to 0, the hardware would set
1242 * termination.
1243 */
1244 cfg->termination |= ADW_TERM_CTL_SEL;
1245
1246 switch(scsi_cfg1 & ADW_CABLE_DETECT) {
1247 /* TERM_CTL_H: on, TERM_CTL_L: on */
1248 case 0x3: case 0x7: case 0xB:
1249 case 0xD: case 0xE: case 0xF:
1250 cfg->termination |=
1251 (ADW_TERM_CTL_H | ADW_TERM_CTL_L);
1252 break;
1253
1254 /* TERM_CTL_H: on, TERM_CTL_L: off */
1255 case 0x1: case 0x5: case 0x9:
1256 case 0xA: case 0xC:
1257 cfg->termination |= ADW_TERM_CTL_H;
1258 break;
1259
1260 /* TERM_CTL_H: off, TERM_CTL_L: off */
1261 case 0x2: case 0x6:
1262 break;
1263 }
1264 }
1265
1266 /*
1267 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
1268 */
1269 scsi_cfg1 &= ~ADW_TERM_CTL;
1270
1271 /*
1272 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
1273 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
1274 * referenced, because the hardware internally inverts
1275 * the Termination High and Low bits if TERM_POL is set.
1276 */
1277 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL));
1278
1279 /*
1280 * Set SCSI_CFG1 Microcode Default Value
1281 *
1282 * Set filter value and possibly modified termination control
1283 * bits in the Microcode SCSI_CFG1 Register Value.
1284 *
1285 * The microcode will set the SCSI_CFG1 register using this value
1286 * after it is started below.
1287 */
1288 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1,
1289 ADW_FLTR_DISABLE | scsi_cfg1);
1290
1291 /*
1292 * Set MEM_CFG Microcode Default Value
1293 *
1294 * The microcode will set the MEM_CFG register using this value
1295 * after it is started below.
1296 *
1297 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1298 * are defined.
1299 *
1300 * ASC-3550 has 8KB internal memory.
1301 */
1302 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1303 ADW_BIOS_EN | ADW_RAM_SZ_8KB);
1304
1305 return 0;
1306 }
1307
1308
1309 int
1310 AdwASC38C0800Cabling(iot, ioh, cfg)
1311 bus_space_tag_t iot;
1312 bus_space_handle_t ioh;
1313 ADW_DVC_CFG *cfg;
1314 {
1315 u_int16_t scsi_cfg1;
1316
1317
1318 /*
1319 * Determine SCSI_CFG1 Microcode Default Value.
1320 *
1321 * The microcode will set the SCSI_CFG1 register using this value
1322 * after it is started below.
1323 */
1324
1325 /* Read current SCSI_CFG1 Register value. */
1326 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1327
1328 /*
1329 * If the cable is reversed all of the SCSI_CTRL register signals
1330 * will be set. Check for and return an error if this condition is
1331 * found.
1332 */
1333 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1334 return ADW_IERR_REVERSED_CABLE;
1335 }
1336
1337 /*
1338 * All kind of combinations of devices attached to one of four
1339 * connectors are acceptable except HVD device attached.
1340 * For example, LVD device can be attached to SE connector while
1341 * SE device attached to LVD connector.
1342 * If LVD device attached to SE connector, it only runs up to
1343 * Ultra speed.
1344 *
1345 * If an HVD device is attached to one of LVD connectors, return
1346 * an error.
1347 * However, there is no way to detect HVD device attached to
1348 * SE connectors.
1349 */
1350 if (scsi_cfg1 & ADW_HVD) {
1351 return ADW_IERR_HVD_DEVICE;
1352 }
1353
1354 /*
1355 * If either SE or LVD automatic termination control is enabled, then
1356 * set the termination value based on a table listed in a_condor.h.
1357 *
1358 * If manual termination was specified with an EEPROM setting then
1359 * 'termination' was set-up in AdwInitFromEEPROM() and is ready
1360 * to be 'ored' into SCSI_CFG1.
1361 */
1362 if ((cfg->termination & ADW_TERM_SE) == 0) {
1363 /* SE automatic termination control is enabled. */
1364 switch(scsi_cfg1 & ADW_C_DET_SE) {
1365 /* TERM_SE_HI: on, TERM_SE_LO: on */
1366 case 0x1: case 0x2: case 0x3:
1367 cfg->termination |= ADW_TERM_SE;
1368 break;
1369
1370 /* TERM_SE_HI: on, TERM_SE_LO: off */
1371 case 0x0:
1372 cfg->termination |= ADW_TERM_SE_HI;
1373 break;
1374 }
1375 }
1376
1377 if ((cfg->termination & ADW_TERM_LVD) == 0) {
1378 /* LVD automatic termination control is enabled. */
1379 switch(scsi_cfg1 & ADW_C_DET_LVD) {
1380 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
1381 case 0x4: case 0x8: case 0xC:
1382 cfg->termination |= ADW_TERM_LVD;
1383 break;
1384
1385 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
1386 case 0x0:
1387 break;
1388 }
1389 }
1390
1391 /*
1392 * Clear any set TERM_SE and TERM_LVD bits.
1393 */
1394 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD);
1395
1396 /*
1397 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
1398 */
1399 scsi_cfg1 |= (~cfg->termination & 0xF0);
1400
1401 /*
1402 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and
1403 * HVD/LVD/SE bits and set possibly modified termination control bits
1404 * in the Microcode SCSI_CFG1 Register Value.
1405 */
1406 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV &
1407 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE);
1408
1409 /*
1410 * Set SCSI_CFG1 Microcode Default Value
1411 *
1412 * Set possibly modified termination control and reset DIS_TERM_DRV
1413 * bits in the Microcode SCSI_CFG1 Register Value.
1414 *
1415 * The microcode will set the SCSI_CFG1 register using this value
1416 * after it is started below.
1417 */
1418 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1419
1420 /*
1421 * Set MEM_CFG Microcode Default Value
1422 *
1423 * The microcode will set the MEM_CFG register using this value
1424 * after it is started below.
1425 *
1426 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1427 * are defined.
1428 *
1429 * ASC-38C0800 has 16KB internal memory.
1430 */
1431 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1432 ADW_BIOS_EN | ADW_RAM_SZ_16KB);
1433
1434 return 0;
1435 }
1436
1437
1438 int
1439 AdwASC38C1600Cabling(iot, ioh, cfg)
1440 bus_space_tag_t iot;
1441 bus_space_handle_t ioh;
1442 ADW_DVC_CFG *cfg;
1443 {
1444 u_int16_t scsi_cfg1;
1445
1446
1447 /*
1448 * Determine SCSI_CFG1 Microcode Default Value.
1449 *
1450 * The microcode will set the SCSI_CFG1 register using this value
1451 * after it is started below.
1452 * Each ASC-38C1600 function has only two cable detect bits.
1453 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
1454 */
1455
1456 /* Read current SCSI_CFG1 Register value. */
1457 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1458
1459 /*
1460 * If the cable is reversed all of the SCSI_CTRL register signals
1461 * will be set. Check for and return an error if this condition is
1462 * found.
1463 */
1464 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1465 return ADW_IERR_REVERSED_CABLE;
1466 }
1467
1468 /*
1469 * Each ASC-38C1600 function has two connectors. Only an HVD device
1470 * cannot be connected to either connector. An LVD device or SE device
1471 * may be connected to either connector. If an SE device is connected,
1472 * then at most Ultra speed (20 MHz) can be used on both connectors.
1473 *
1474 * If an HVD device is attached, return an error.
1475 */
1476 if (scsi_cfg1 & ADW_HVD) {
1477 return ADW_IERR_HVD_DEVICE;
1478 }
1479
1480 /*
1481 * Each function in the ASC-38C1600 uses only the SE cable detect and
1482 * termination because there are two connectors for each function.
1483 * Each function may use either LVD or SE mode.
1484 * Corresponding the SE automatic termination control EEPROM bits are
1485 * used for each function.
1486 * Each function has its own EEPROM. If SE automatic control is enabled
1487 * for the function, then set the termination value based on a table
1488 * listed in adwlib.h.
1489 *
1490 * If manual termination is specified in the EEPROM for the function,
1491 * then 'termination' was set-up in AdwInitFromEEPROM() and is
1492 * ready to be 'ored' into SCSI_CFG1.
1493 */
1494 if ((cfg->termination & ADW_TERM_SE) == 0) {
1495 /* SE automatic termination control is enabled. */
1496 switch(scsi_cfg1 & ADW_C_DET_SE) {
1497 /* TERM_SE_HI: on, TERM_SE_LO: on */
1498 case 0x1: case 0x2: case 0x3:
1499 cfg->termination |= ADW_TERM_SE;
1500 break;
1501
1502 case 0x0:
1503 #if 0
1504 /* !!!!TODO!!!! */
1505 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) {
1506 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
1507 }
1508 else
1509 #endif
1510 {
1511 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
1512 cfg->termination |= ADW_TERM_SE_HI;
1513 }
1514 break;
1515 }
1516 }
1517
1518 /*
1519 * Clear any set TERM_SE bits.
1520 */
1521 scsi_cfg1 &= ~ADW_TERM_SE;
1522
1523 /*
1524 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
1525 */
1526 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE);
1527
1528 /*
1529 * Clear Big Endian and Terminator Polarity bits and set possibly
1530 * modified termination control bits in the Microcode SCSI_CFG1
1531 * Register Value.
1532 */
1533 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL);
1534
1535 /*
1536 * Set SCSI_CFG1 Microcode Default Value
1537 *
1538 * Set possibly modified termination control bits in the Microcode
1539 * SCSI_CFG1 Register Value.
1540 *
1541 * The microcode will set the SCSI_CFG1 register using this value
1542 * after it is started below.
1543 */
1544 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1545
1546 /*
1547 * Set MEM_CFG Microcode Default Value
1548 *
1549 * The microcode will set the MEM_CFG register using this value
1550 * after it is started below.
1551 *
1552 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1553 * are defined.
1554 *
1555 * ASC-38C1600 has 32KB internal memory.
1556 */
1557 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1558 ADW_BIOS_EN | ADW_RAM_SZ_32KB);
1559
1560 return 0;
1561 }
1562
1563
1564 /*
1565 * Read EEPROM configuration into the specified buffer.
1566 *
1567 * Return a checksum based on the EEPROM configuration read.
1568 */
1569 static u_int16_t
1570 AdwGetEEPROMConfig(iot, ioh, cfg_buf)
1571 bus_space_tag_t iot;
1572 bus_space_handle_t ioh;
1573 ADW_EEPROM *cfg_buf;
1574 {
1575 u_int16_t wval, chksum;
1576 u_int16_t *wbuf;
1577 int eep_addr;
1578
1579
1580 wbuf = (u_int16_t *) cfg_buf;
1581 chksum = 0;
1582
1583 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN;
1584 eep_addr < ASC_EEP_DVC_CFG_END;
1585 eep_addr++, wbuf++) {
1586 wval = AdwReadEEPWord(iot, ioh, eep_addr);
1587 chksum += wval;
1588 *wbuf = wval;
1589 }
1590
1591 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1592 wbuf++;
1593 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN;
1594 eep_addr < ASC_EEP_MAX_WORD_ADDR;
1595 eep_addr++, wbuf++) {
1596 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1597 }
1598
1599 return chksum;
1600 }
1601
1602
1603 /*
1604 * Read the EEPROM from specified location
1605 */
1606 static u_int16_t
1607 AdwReadEEPWord(iot, ioh, eep_word_addr)
1608 bus_space_tag_t iot;
1609 bus_space_handle_t ioh;
1610 int eep_word_addr;
1611 {
1612 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1613 ASC_EEP_CMD_READ | eep_word_addr);
1614 AdwWaitEEPCmd(iot, ioh);
1615
1616 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA);
1617 }
1618
1619
1620 /*
1621 * Wait for EEPROM command to complete
1622 */
1623 static void
1624 AdwWaitEEPCmd(iot, ioh)
1625 bus_space_tag_t iot;
1626 bus_space_handle_t ioh;
1627 {
1628 int eep_delay_ms;
1629
1630
1631 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){
1632 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) &
1633 ASC_EEP_CMD_DONE) {
1634 break;
1635 }
1636 AdwSleepMilliSecond(1);
1637 }
1638
1639 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD);
1640 }
1641
1642
1643 /*
1644 * Write the EEPROM from 'cfg_buf'.
1645 */
1646 static void
1647 AdwSetEEPROMConfig(iot, ioh, cfg_buf)
1648 bus_space_tag_t iot;
1649 bus_space_handle_t ioh;
1650 ADW_EEPROM *cfg_buf;
1651 {
1652 u_int16_t *wbuf;
1653 u_int16_t addr, chksum;
1654
1655
1656 wbuf = (u_int16_t *) cfg_buf;
1657 chksum = 0;
1658
1659 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
1660 AdwWaitEEPCmd(iot, ioh);
1661
1662 /*
1663 * Write EEPROM from word 0 to word 20
1664 */
1665 for (addr = ASC_EEP_DVC_CFG_BEGIN;
1666 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) {
1667 chksum += *wbuf;
1668 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1669 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1670 ASC_EEP_CMD_WRITE | addr);
1671 AdwWaitEEPCmd(iot, ioh);
1672 AdwSleepMilliSecond(ASC_EEP_DELAY_MS);
1673 }
1674
1675 /*
1676 * Write EEPROM checksum at word 21
1677 */
1678 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum);
1679 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1680 ASC_EEP_CMD_WRITE | addr);
1681 AdwWaitEEPCmd(iot, ioh);
1682 wbuf++; /* skip over check_sum */
1683
1684 /*
1685 * Write EEPROM OEM name at words 22 to 29
1686 */
1687 for (addr = ASC_EEP_DVC_CTL_BEGIN;
1688 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
1689 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1690 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1691 ASC_EEP_CMD_WRITE | addr);
1692 AdwWaitEEPCmd(iot, ioh);
1693 }
1694
1695 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1696 ASC_EEP_CMD_WRITE_DISABLE);
1697 AdwWaitEEPCmd(iot, ioh);
1698
1699 return;
1700 }
1701
1702
1703 /*
1704 * AdwExeScsiQueue() - Send a request to the RISC microcode program.
1705 *
1706 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q,
1707 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
1708 * RISC to notify it a new command is ready to be executed.
1709 *
1710 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
1711 * set to SCSI_MAX_RETRY.
1712 *
1713 * Return:
1714 * ADW_SUCCESS(1) - The request was successfully queued.
1715 * ADW_BUSY(0) - Resource unavailable; Retry again after pending
1716 * request completes.
1717 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure
1718 * host IC error.
1719 */
1720 int
1721 AdwExeScsiQueue(sc, scsiq)
1722 ADW_SOFTC *sc;
1723 ADW_SCSI_REQ_Q *scsiq;
1724 {
1725 bus_space_tag_t iot = sc->sc_iot;
1726 bus_space_handle_t ioh = sc->sc_ioh;
1727 ADW_CCB *ccb;
1728 u_int32_t req_paddr;
1729 ADW_CARRIER *new_carrp;
1730
1731 /*
1732 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID.
1733 */
1734 if (scsiq->target_id > ADW_MAX_TID) {
1735 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
1736 scsiq->done_status = QD_WITH_ERROR;
1737 return ADW_ERROR;
1738 }
1739
1740 /*
1741 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair
1742 */
1743
1744 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
1745
1746 /*
1747 * Allocate a carrier and initialize fields.
1748 */
1749 if ((new_carrp = sc->carr_freelist) == NULL) {
1750 return ADW_BUSY;
1751 }
1752 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
1753 ASC_GET_CARRP(new_carrp->next_ba));
1754 sc->carr_pending_cnt++;
1755
1756 /*
1757 * Set the carrier to be a stopper by setting 'next_ba'
1758 * to the stopper value. The current stopper will be changed
1759 * below to point to the new stopper.
1760 */
1761 new_carrp->next_ba = htole32(ASC_CQ_STOPPER);
1762
1763 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
1764 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq);
1765
1766 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */
1767 scsiq->scsiq_rptr = htole32(req_paddr);
1768
1769 /*
1770 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian
1771 * order during initialization.
1772 */
1773 scsiq->carr_ba = sc->icq_sp->carr_ba;
1774 scsiq->carr_va = sc->icq_sp->carr_ba;
1775
1776 /*
1777 * Use the current stopper to send the ADW_SCSI_REQ_Q command to
1778 * the microcode. The newly allocated stopper will become the new
1779 * stopper.
1780 */
1781 sc->icq_sp->areq_ba = htole32(req_paddr);
1782
1783 /*
1784 * Set the 'next_ba' pointer for the old stopper to be the
1785 * physical address of the new stopper. The RISC can only
1786 * follow physical addresses.
1787 */
1788 sc->icq_sp->next_ba = new_carrp->carr_ba;
1789
1790 #if ADW_DEBUG
1791 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n",
1792 sc->icq_sp->carr_id,
1793 sc->icq_sp->carr_ba,
1794 sc->icq_sp->areq_ba,
1795 sc->icq_sp->next_ba);
1796 #endif
1797 /*
1798 * Set the host adapter stopper pointer to point to the new carrier.
1799 */
1800 sc->icq_sp = new_carrp;
1801
1802 if (sc->chip_type == ADW_CHIP_ASC3550 ||
1803 sc->chip_type == ADW_CHIP_ASC38C0800) {
1804 /*
1805 * Tickle the RISC to tell it to read its Command Queue Head
1806 * pointer.
1807 */
1808 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A);
1809 if (sc->chip_type == ADW_CHIP_ASC3550) {
1810 /*
1811 * Clear the tickle value. In the ASC-3550 the RISC flag
1812 * command 'clr_tickle_a' does not work unless the host
1813 * value is cleared.
1814 */
1815 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE,
1816 ADW_TICKLE_NOP);
1817 }
1818 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1819 /*
1820 * Notify the RISC a carrier is ready by writing the physical
1821 * address of the new carrier stopper to the COMMA register.
1822 */
1823 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
1824 le32toh(new_carrp->carr_ba));
1825 }
1826
1827 /*
1828 * End of CRITICAL SECTION: Must be protected within splbio/splx pair
1829 */
1830
1831 return ADW_SUCCESS;
1832 }
1833
1834
1835 void
1836 AdwResetChip(iot, ioh)
1837 bus_space_tag_t iot;
1838 bus_space_handle_t ioh;
1839 {
1840
1841 /*
1842 * Reset Chip.
1843 */
1844 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1845 ADW_CTRL_REG_CMD_RESET);
1846 AdwSleepMilliSecond(100);
1847 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1848 ADW_CTRL_REG_CMD_WR_IO_REG);
1849 }
1850
1851
1852 /*
1853 * Reset SCSI Bus and purge all outstanding requests.
1854 *
1855 * Return Value:
1856 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset.
1857 * ADW_FALSE(0) - Microcode command failed.
1858 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC
1859 * may be hung which requires driver recovery.
1860 */
1861 int
1862 AdwResetCCB(sc)
1863 ADW_SOFTC *sc;
1864 {
1865 int status;
1866
1867 /*
1868 * Send the SCSI Bus Reset idle start idle command which asserts
1869 * the SCSI Bus Reset signal.
1870 */
1871 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L);
1872 if (status != ADW_TRUE) {
1873 return status;
1874 }
1875
1876 /*
1877 * Delay for the specified SCSI Bus Reset hold time.
1878 *
1879 * The hold time delay is done on the host because the RISC has no
1880 * microsecond accurate timer.
1881 */
1882 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US);
1883
1884 /*
1885 * Send the SCSI Bus Reset end idle command which de-asserts
1886 * the SCSI Bus Reset signal and purges any pending requests.
1887 */
1888 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L);
1889 if (status != ADW_TRUE) {
1890 return status;
1891 }
1892
1893 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000);
1894
1895 return status;
1896 }
1897
1898
1899 /*
1900 * Reset chip and SCSI Bus.
1901 *
1902 * Return Value:
1903 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
1904 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
1905 */
1906 int
1907 AdwResetSCSIBus(sc)
1908 ADW_SOFTC *sc;
1909 {
1910 bus_space_tag_t iot = sc->sc_iot;
1911 bus_space_handle_t ioh = sc->sc_ioh;
1912 int status;
1913 u_int16_t wdtr_able, sdtr_able, tagqng_able;
1914 u_int16_t ppr_able = 0; /* XXX: gcc */
1915 u_int8_t tid, max_cmd[ADW_MAX_TID + 1];
1916 u_int16_t bios_sig;
1917
1918
1919 /*
1920 * Save current per TID negotiated values.
1921 */
1922 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1923 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1924 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1925 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1926 }
1927 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1928 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1929 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1930 max_cmd[tid]);
1931 }
1932
1933 /*
1934 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset
1935 * by clearing the BIOS signature word.
1936 * The initialization functions assumes a SCSI Bus Reset is not
1937 * needed if the BIOS signature word is present.
1938 */
1939 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1940 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0);
1941
1942 /*
1943 * Stop chip and reset it.
1944 */
1945 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP);
1946 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1947 ADW_CTRL_REG_CMD_RESET);
1948 AdwSleepMilliSecond(100);
1949 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1950 ADW_CTRL_REG_CMD_WR_IO_REG);
1951
1952 /*
1953 * Reset Adv Library error code, if any, and try
1954 * re-initializing the chip.
1955 * Then translate initialization return value to status value.
1956 */
1957 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE;
1958
1959 /*
1960 * Restore the BIOS signature word.
1961 */
1962 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1963
1964 /*
1965 * Restore per TID negotiated values.
1966 */
1967 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1968 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1969 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1970 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1971 }
1972 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1973 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1974 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1975 max_cmd[tid]);
1976 }
1977
1978 return status;
1979 }
1980
1981
1982 /*
1983 * Adv Library Interrupt Service Routine
1984 *
1985 * This function is called by a driver's interrupt service routine.
1986 * The function disables and re-enables interrupts.
1987 *
1988 * When a microcode idle command is completed, the ADV_DVC_VAR
1989 * 'idle_cmd_done' field is set to ADW_TRUE.
1990 *
1991 * Note: AdwISR() can be called when interrupts are disabled or even
1992 * when there is no hardware interrupt condition present. It will
1993 * always check for completed idle commands and microcode requests.
1994 * This is an important feature that shouldn't be changed because it
1995 * allows commands to be completed from polling mode loops.
1996 *
1997 * Return:
1998 * ADW_TRUE(1) - interrupt was pending
1999 * ADW_FALSE(0) - no interrupt was pending
2000 */
2001 int
2002 AdwISR(sc)
2003 ADW_SOFTC *sc;
2004 {
2005 bus_space_tag_t iot = sc->sc_iot;
2006 bus_space_handle_t ioh = sc->sc_ioh;
2007 u_int8_t int_stat;
2008 ADW_CARRIER *free_carrp/*, *ccb_carr*/;
2009 u_int32_t irq_next_pa;
2010 ADW_SCSI_REQ_Q *scsiq;
2011 ADW_CCB *ccb;
2012 int s;
2013
2014
2015 s = splbio();
2016
2017 /* Reading the register clears the interrupt. */
2018 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG);
2019
2020 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB |
2021 ADW_INTR_STATUS_INTRC)) == 0) {
2022 splx(s);
2023 return ADW_FALSE;
2024 }
2025
2026 /*
2027 * Notify the driver of an asynchronous microcode condition by
2028 * calling the ADV_DVC_VAR.async_callback function. The function
2029 * is passed the microcode ADW_MC_INTRB_CODE byte value.
2030 */
2031 if (int_stat & ADW_INTR_STATUS_INTRB) {
2032 u_int8_t intrb_code;
2033
2034 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code);
2035
2036 if (sc->chip_type == ADW_CHIP_ASC3550 ||
2037 sc->chip_type == ADW_CHIP_ASC38C0800) {
2038 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
2039 sc->carr_pending_cnt != 0) {
2040 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2041 IOPB_TICKLE, ADW_TICKLE_A);
2042 if (sc->chip_type == ADW_CHIP_ASC3550) {
2043 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2044 IOPB_TICKLE, ADW_TICKLE_NOP);
2045 }
2046 }
2047 }
2048
2049 if (sc->async_callback != 0) {
2050 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code);
2051 }
2052 }
2053
2054 /*
2055 * Check if the IRQ stopper carrier contains a completed request.
2056 */
2057 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0)
2058 {
2059 #if ADW_DEBUG
2060 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n",
2061 sc->irq_sp->carr_id,
2062 sc->irq_sp->carr_ba,
2063 sc->irq_sp->areq_ba,
2064 sc->irq_sp->next_ba);
2065 #endif
2066 /*
2067 * Get a pointer to the newly completed ADW_SCSI_REQ_Q
2068 * structure.
2069 * The RISC will have set 'areq_ba' to a virtual address.
2070 *
2071 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr
2072 * field to the carrier ADV_CARR_T.areq_ba field.
2073 * The conversion below complements the conversion of
2074 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue().
2075 */
2076 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba);
2077 scsiq = &ccb->scsiq;
2078 scsiq->ccb_ptr = sc->irq_sp->areq_ba;
2079
2080 /*
2081 * Request finished with good status and the queue was not
2082 * DMAed to host memory by the firmware. Set all status fields
2083 * to indicate good status.
2084 */
2085 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) {
2086 scsiq->done_status = QD_NO_ERROR;
2087 scsiq->host_status = scsiq->scsi_status = 0;
2088 scsiq->data_cnt = 0L;
2089 }
2090
2091 /*
2092 * Advance the stopper pointer to the next carrier
2093 * ignoring the lower four bits. Free the previous
2094 * stopper carrier.
2095 */
2096 free_carrp = sc->irq_sp;
2097 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa));
2098
2099 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0
2100 : sc->carr_freelist->carr_ba;
2101 sc->carr_freelist = free_carrp;
2102 sc->carr_pending_cnt--;
2103
2104 /*
2105 * Clear request microcode control flag.
2106 */
2107 scsiq->cntl = 0;
2108
2109 /*
2110 * Check Condition handling
2111 */
2112 /*
2113 * If the command that completed was a SCSI INQUIRY and
2114 * LUN 0 was sent the command, then process the INQUIRY
2115 * command information for the device.
2116 */
2117 if (scsiq->done_status == QD_NO_ERROR &&
2118 scsiq->cdb[0] == INQUIRY &&
2119 scsiq->target_lun == 0) {
2120 AdwInquiryHandling(sc, scsiq);
2121 }
2122
2123 /*
2124 * Notify the driver of the completed request by passing
2125 * the ADW_SCSI_REQ_Q pointer to its callback function.
2126 */
2127 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq);
2128 /*
2129 * Note: After the driver callback function is called, 'scsiq'
2130 * can no longer be referenced.
2131 *
2132 * Fall through and continue processing other completed
2133 * requests...
2134 */
2135 }
2136
2137 splx(s);
2138
2139 return ADW_TRUE;
2140 }
2141
2142
2143 /*
2144 * Send an idle command to the chip and wait for completion.
2145 *
2146 * Command completion is polled for once per microsecond.
2147 *
2148 * The function can be called from anywhere including an interrupt handler.
2149 * But the function is not re-entrant, so it uses the splbio/splx()
2150 * functions to prevent reentrancy.
2151 *
2152 * Return Values:
2153 * ADW_TRUE - command completed successfully
2154 * ADW_FALSE - command failed
2155 * ADW_ERROR - command timed out
2156 */
2157 int
2158 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter)
2159 ADW_SOFTC *sc;
2160 u_int16_t idle_cmd;
2161 u_int32_t idle_cmd_parameter;
2162 {
2163 bus_space_tag_t iot = sc->sc_iot;
2164 bus_space_handle_t ioh = sc->sc_ioh;
2165 u_int16_t result;
2166 u_int32_t i, j, s;
2167
2168 s = splbio();
2169
2170 /*
2171 * Clear the idle command status which is set by the microcode
2172 * to a non-zero value to indicate when the command is completed.
2173 */
2174 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0);
2175
2176 /*
2177 * Write the idle command value after the idle command parameter
2178 * has been written to avoid a race condition. If the order is not
2179 * followed, the microcode may process the idle command before the
2180 * parameters have been written to LRAM.
2181 */
2182 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER,
2183 idle_cmd_parameter);
2184 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd);
2185
2186 /*
2187 * Tickle the RISC to tell it to process the idle command.
2188 */
2189 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B);
2190 if (sc->chip_type == ADW_CHIP_ASC3550) {
2191 /*
2192 * Clear the tickle value. In the ASC-3550 the RISC flag
2193 * command 'clr_tickle_b' does not work unless the host
2194 * value is cleared.
2195 */
2196 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP);
2197 }
2198
2199 /* Wait for up to 100 millisecond for the idle command to timeout. */
2200 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
2201 /* Poll once each microsecond for command completion. */
2202 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
2203 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS,
2204 result);
2205 if (result != 0) {
2206 splx(s);
2207 return result;
2208 }
2209 AdwDelayMicroSecond(1);
2210 }
2211 }
2212
2213 splx(s);
2214 return ADW_ERROR;
2215 }
2216
2217
2218 /*
2219 * Inquiry Information Byte 7 Handling
2220 *
2221 * Handle SCSI Inquiry Command information for a device by setting
2222 * microcode operating variables that affect WDTR, SDTR, and Tag
2223 * Queuing.
2224 */
2225 static void
2226 AdwInquiryHandling(sc, scsiq)
2227 ADW_SOFTC *sc;
2228 ADW_SCSI_REQ_Q *scsiq;
2229 {
2230 #ifndef FAILSAFE
2231 bus_space_tag_t iot = sc->sc_iot;
2232 bus_space_handle_t ioh = sc->sc_ioh;
2233 u_int8_t tid;
2234 struct scsipi_inquiry_data *inq;
2235 u_int16_t tidmask;
2236 u_int16_t cfg_word;
2237
2238
2239 /*
2240 * AdwInquiryHandling() requires up to INQUIRY information Byte 7
2241 * to be available.
2242 *
2243 * If less than 8 bytes of INQUIRY information were requested or less
2244 * than 8 bytes were transferred, then return. cdb[4] is the request
2245 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the
2246 * microcode to the transfer residual count.
2247 */
2248
2249 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) {
2250 return;
2251 }
2252
2253 tid = scsiq->target_id;
2254
2255 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr;
2256
2257 /*
2258 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
2259 */
2260 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ &&
2261 ((inq->version & SID_ANSII) < 2)) {
2262 return;
2263 } else {
2264 /*
2265 * INQUIRY Byte 7 Handling
2266 *
2267 * Use a device's INQUIRY byte 7 to determine whether it
2268 * supports WDTR, SDTR, and Tag Queuing. If the feature
2269 * is enabled in the EEPROM and the device supports the
2270 * feature, then enable it in the microcode.
2271 */
2272
2273 tidmask = ADW_TID_TO_TIDMASK(tid);
2274
2275 /*
2276 * Wide Transfers
2277 *
2278 * If the EEPROM enabled WDTR for the device and the device
2279 * supports wide bus (16 bit) transfers, then turn on the
2280 * device's 'wdtr_able' bit and write the new value to the
2281 * microcode.
2282 */
2283 #ifdef SCSI_ADW_WDTR_DISABLE
2284 if(!(tidmask & SCSI_ADW_WDTR_DISABLE))
2285 #endif /* SCSI_ADW_WDTR_DISABLE */
2286 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) {
2287 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2288 cfg_word);
2289 if ((cfg_word & tidmask) == 0) {
2290 cfg_word |= tidmask;
2291 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2292 cfg_word);
2293
2294 /*
2295 * Clear the microcode "SDTR negotiation" and
2296 * "WDTR negotiation" done indicators for the
2297 * target to cause it to negotiate with the new
2298 * setting set above.
2299 * WDTR when accepted causes the target to enter
2300 * asynchronous mode, so SDTR must be negotiated
2301 */
2302 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2303 cfg_word);
2304 cfg_word &= ~tidmask;
2305 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2306 cfg_word);
2307 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2308 cfg_word);
2309 cfg_word &= ~tidmask;
2310 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2311 cfg_word);
2312 }
2313 }
2314
2315 /*
2316 * Synchronous Transfers
2317 *
2318 * If the EEPROM enabled SDTR for the device and the device
2319 * supports synchronous transfers, then turn on the device's
2320 * 'sdtr_able' bit. Write the new value to the microcode.
2321 */
2322 #ifdef SCSI_ADW_SDTR_DISABLE
2323 if(!(tidmask & SCSI_ADW_SDTR_DISABLE))
2324 #endif /* SCSI_ADW_SDTR_DISABLE */
2325 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) {
2326 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word);
2327 if ((cfg_word & tidmask) == 0) {
2328 cfg_word |= tidmask;
2329 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
2330 cfg_word);
2331
2332 /*
2333 * Clear the microcode "SDTR negotiation"
2334 * done indicator for the target to cause it
2335 * to negotiate with the new setting set above.
2336 */
2337 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2338 cfg_word);
2339 cfg_word &= ~tidmask;
2340 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2341 cfg_word);
2342 }
2343 }
2344 /*
2345 * If the Inquiry data included enough space for the SPI-3
2346 * Clocking field, then check if DT mode is supported.
2347 */
2348 if (sc->chip_type == ADW_CHIP_ASC38C1600 &&
2349 (scsiq->cdb[4] >= 57 ||
2350 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) {
2351 /*
2352 * PPR (Parallel Protocol Request) Capable
2353 *
2354 * If the device supports DT mode, then it must be
2355 * PPR capable.
2356 * The PPR message will be used in place of the SDTR
2357 * and WDTR messages to negotiate synchronous speed
2358 * and offset, transfer width, and protocol options.
2359 */
2360 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){
2361 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2362 sc->ppr_able);
2363 sc->ppr_able |= tidmask;
2364 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2365 sc->ppr_able);
2366 }
2367 }
2368
2369 /*
2370 * If the EEPROM enabled Tag Queuing for the device and the
2371 * device supports Tag Queueing, then turn on the device's
2372 * 'tagqng_enable' bit in the microcode and set the microcode
2373 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
2374 * value.
2375 *
2376 * Tag Queuing is disabled for the BIOS which runs in polled
2377 * mode and would see no benefit from Tag Queuing. Also by
2378 * disabling Tag Queuing in the BIOS devices with Tag Queuing
2379 * bugs will at least work with the BIOS.
2380 */
2381 #ifdef SCSI_ADW_TAGQ_DISABLE
2382 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE))
2383 #endif /* SCSI_ADW_TAGQ_DISABLE */
2384 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) {
2385 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2386 cfg_word);
2387 cfg_word |= tidmask;
2388 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2389 cfg_word);
2390
2391 ADW_WRITE_BYTE_LRAM(iot, ioh,
2392 ADW_MC_NUMBER_OF_MAX_CMD + tid,
2393 sc->max_dvc_qng);
2394 }
2395 }
2396 #endif /* FAILSAFE */
2397 }
2398
2399
2400 static void
2401 AdwSleepMilliSecond(n)
2402 u_int32_t n;
2403 {
2404
2405 DELAY(n * 1000);
2406 }
2407
2408
2409 static void
2410 AdwDelayMicroSecond(n)
2411 u_int32_t n;
2412 {
2413
2414 DELAY(n);
2415 }
2416
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