FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/adwlib.c
1 /* $NetBSD: adwlib.c,v 1.37 2006/08/27 23:19:03 christos Exp $ */
2
3 /*
4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips
5 *
6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
7 * All rights reserved.
8 *
9 * Author: Baldassare Dante Profeta <dante@mclink.it>
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39 /*
40 * Ported from:
41 */
42 /*
43 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
44 *
45 * Copyright (c) 1995-2000 Advanced System Products, Inc.
46 * All Rights Reserved.
47 *
48 * Redistribution and use in source and binary forms, with or without
49 * modification, are permitted provided that redistributions of source
50 * code retain the above copyright notice and this comment without
51 * modification.
52 */
53
54 #include <sys/cdefs.h>
55 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.37 2006/08/27 23:19:03 christos Exp $");
56
57 #include <sys/param.h>
58 #include <sys/systm.h>
59 #include <sys/malloc.h>
60 #include <sys/kernel.h>
61 #include <sys/queue.h>
62 #include <sys/device.h>
63
64 #include <machine/bus.h>
65 #include <machine/intr.h>
66
67 #include <dev/scsipi/scsi_all.h>
68 #include <dev/scsipi/scsipi_all.h>
69 #include <dev/scsipi/scsiconf.h>
70
71 #include <dev/pci/pcidevs.h>
72
73 #include <uvm/uvm_extern.h>
74
75 #include <dev/ic/adwlib.h>
76 #include <dev/ic/adwmcode.h>
77 #include <dev/ic/adw.h>
78
79
80 /* Static Functions */
81
82 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t);
83 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, u_int8_t);
84 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *);
85 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *);
86 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *);
87
88 static u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t,
89 ADW_EEPROM *);
90 static void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t,
91 ADW_EEPROM *);
92 static u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int);
93 static void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t);
94
95 static void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
96
97 static void AdwSleepMilliSecond(u_int32_t);
98 static void AdwDelayMicroSecond(u_int32_t);
99
100
101 /*
102 * EEPROM Configuration.
103 *
104 * All drivers should use this structure to set the default EEPROM
105 * configuration. The BIOS now uses this structure when it is built.
106 * Additional structure information can be found in adwlib.h where
107 * the structure is defined.
108 */
109 static const ADW_EEPROM adw_3550_Default_EEPROM = {
110 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
111 0x0000, /* 01 cfg_msw */
112 0xFFFF, /* 02 disc_enable */
113 0xFFFF, /* 03 wdtr_able */
114 { 0xFFFF }, /* 04 sdtr_able */
115 0xFFFF, /* 05 start_motor */
116 0xFFFF, /* 06 tagqng_able */
117 0xFFFF, /* 07 bios_scan */
118 0, /* 08 scam_tolerant */
119 7, /* 09 adapter_scsi_id */
120 0, /* bios_boot_delay */
121 3, /* 10 scsi_reset_delay */
122 0, /* bios_id_lun */
123 0, /* 11 termination */
124 0, /* reserved1 */
125 0xFFE7, /* 12 bios_ctrl */
126 { 0xFFFF }, /* 13 ultra_able */
127 { 0 }, /* 14 reserved2 */
128 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
129 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
130 0, /* 16 dvc_cntl */
131 { 0 }, /* 17 bug_fix */
132 { 0,0,0 }, /* 18-20 serial_number[3] */
133 0, /* 21 check_sum */
134 { /* 22-29 oem_name[16] */
135 0,0,0,0,0,0,0,0,
136 0,0,0,0,0,0,0,0
137 },
138 0, /* 30 dvc_err_code */
139 0, /* 31 adv_err_code */
140 0, /* 32 adv_err_addr */
141 0, /* 33 saved_dvc_err_code */
142 0, /* 34 saved_adv_err_code */
143 0, /* 35 saved_adv_err_addr */
144 { /* 36-55 reserved1[16] */
145 0,0,0,0,0,0,0,0,0,0,
146 0,0,0,0,0,0,0,0,0,0
147 },
148 0, /* 56 cisptr_lsw */
149 0, /* 57 cisprt_msw */
150 0, /* 58 subsysvid */
151 0, /* 59 subsysid */
152 { 0,0,0,0 } /* 60-63 reserved2[4] */
153 };
154
155 static const ADW_EEPROM adw_38C0800_Default_EEPROM = {
156 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
157 0x0000, /* 01 cfg_msw */
158 0xFFFF, /* 02 disc_enable */
159 0xFFFF, /* 03 wdtr_able */
160 { 0x4444 }, /* 04 sdtr_speed1 */
161 0xFFFF, /* 05 start_motor */
162 0xFFFF, /* 06 tagqng_able */
163 0xFFFF, /* 07 bios_scan */
164 0, /* 08 scam_tolerant */
165 7, /* 09 adapter_scsi_id */
166 0, /* bios_boot_delay */
167 3, /* 10 scsi_reset_delay */
168 0, /* bios_id_lun */
169 0, /* 11 termination_se */
170 0, /* termination_lvd */
171 0xFFE7, /* 12 bios_ctrl */
172 { 0x4444 }, /* 13 sdtr_speed2 */
173 { 0x4444 }, /* 14 sdtr_speed3 */
174 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
175 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
176 0, /* 16 dvc_cntl */
177 { 0x4444 }, /* 17 sdtr_speed4 */
178 { 0,0,0 }, /* 18-20 serial_number[3] */
179 0, /* 21 check_sum */
180 { /* 22-29 oem_name[16] */
181 0,0,0,0,0,0,0,0,
182 0,0,0,0,0,0,0,0
183 },
184 0, /* 30 dvc_err_code */
185 0, /* 31 adv_err_code */
186 0, /* 32 adv_err_addr */
187 0, /* 33 saved_dvc_err_code */
188 0, /* 34 saved_adv_err_code */
189 0, /* 35 saved_adv_err_addr */
190 { /* 36-55 reserved1[16] */
191 0,0,0,0,0,0,0,0,0,0,
192 0,0,0,0,0,0,0,0,0,0
193 },
194 0, /* 56 cisptr_lsw */
195 0, /* 57 cisprt_msw */
196 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
197 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */
198 { 0,0,0,0 } /* 60-63 reserved2[4] */
199 };
200
201 static const ADW_EEPROM adw_38C1600_Default_EEPROM = {
202 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
203 0x0000, /* 01 cfg_msw */
204 0xFFFF, /* 02 disc_enable */
205 0xFFFF, /* 03 wdtr_able */
206 { 0x5555 }, /* 04 sdtr_speed1 */
207 0xFFFF, /* 05 start_motor */
208 0xFFFF, /* 06 tagqng_able */
209 0xFFFF, /* 07 bios_scan */
210 0, /* 08 scam_tolerant */
211 7, /* 09 adapter_scsi_id */
212 0, /* bios_boot_delay */
213 3, /* 10 scsi_reset_delay */
214 0, /* bios_id_lun */
215 0, /* 11 termination_se */
216 0, /* termination_lvd */
217 0xFFE7, /* 12 bios_ctrl */
218 { 0x5555 }, /* 13 sdtr_speed2 */
219 { 0x5555 }, /* 14 sdtr_speed3 */
220 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
221 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
222 0, /* 16 dvc_cntl */
223 { 0x5555 }, /* 17 sdtr_speed4 */
224 { 0,0,0 }, /* 18-20 serial_number[3] */
225 0, /* 21 check_sum */
226 { /* 22-29 oem_name[16] */
227 0,0,0,0,0,0,0,0,
228 0,0,0,0,0,0,0,0
229 },
230 0, /* 30 dvc_err_code */
231 0, /* 31 adv_err_code */
232 0, /* 32 adv_err_addr */
233 0, /* 33 saved_dvc_err_code */
234 0, /* 34 saved_adv_err_code */
235 0, /* 35 saved_adv_err_addr */
236 { /* 36-55 reserved1[16] */
237 0,0,0,0,0,0,0,0,0,0,
238 0,0,0,0,0,0,0,0,0,0
239 },
240 0, /* 56 cisptr_lsw */
241 0, /* 57 cisprt_msw */
242 PCI_VENDOR_ADVSYS, /* 58 subsysvid */
243 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */
244 { 0,0,0,0 } /* 60-63 reserved2[4] */
245 };
246
247
248 /*
249 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and
250 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while
251 * all of this is done.
252 *
253 * For a non-fatal error return a warning code. If there are no warnings
254 * then 0 is returned.
255 *
256 * Note: Chip is stopped on entry.
257 */
258 int
259 AdwInitFromEEPROM(sc)
260 ADW_SOFTC *sc;
261 {
262 bus_space_tag_t iot = sc->sc_iot;
263 bus_space_handle_t ioh = sc->sc_ioh;
264 ADW_EEPROM eep_config;
265 u_int16_t warn_code;
266 u_int16_t sdtr_speed = 0;
267 u_int8_t tid, termination;
268 int i, j;
269
270
271 warn_code = 0;
272
273 /*
274 * Read the board's EEPROM configuration.
275 *
276 * Set default values if a bad checksum is found.
277 *
278 * XXX - Don't handle big-endian access to EEPROM yet.
279 */
280 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) {
281 warn_code |= ADW_WARN_EEPROM_CHKSUM;
282
283 /*
284 * Set EEPROM default values.
285 */
286 switch(sc->chip_type) {
287 case ADW_CHIP_ASC3550:
288 eep_config = adw_3550_Default_EEPROM;
289 break;
290 case ADW_CHIP_ASC38C0800:
291 eep_config = adw_38C0800_Default_EEPROM;
292 break;
293 case ADW_CHIP_ASC38C1600:
294 eep_config = adw_38C1600_Default_EEPROM;
295
296 #if 0
297 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) {
298 #endif
299 if (sc->cfg.pci_slot_info != 0) {
300 u_int8_t lsw_msb;
301
302 lsw_msb = eep_config.cfg_lsw >> 8;
303 /*
304 * Set Function 1 EEPROM Word 0 MSB
305 *
306 * Clear the BIOS_ENABLE (bit 14) and
307 * INTAB (bit 11) EEPROM bits.
308 *
309 * Disable Bit 14 (BIOS_ENABLE) to fix
310 * SPARC Ultra 60 and old Mac system booting
311 * problem. The Expansion ROM must
312 * be disabled in Function 1 for these systems.
313 */
314 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE |
315 ADW_EEPROM_INTAB) >> 8) & 0xFF);
316 /*
317 * Set the INTAB (bit 11) if the GPIO 0 input
318 * indicates the Function 1 interrupt line is
319 * wired to INTA.
320 *
321 * Set/Clear Bit 11 (INTAB) from
322 * the GPIO bit 0 input:
323 * 1 - Function 1 intr line wired to INT A.
324 * 0 - Function 1 intr line wired to INT B.
325 *
326 * Note: Adapter boards always have Function 0
327 * wired to INTA.
328 * Put all 5 GPIO bits in input mode and then
329 * read their input values.
330 */
331 ADW_WRITE_BYTE_REGISTER(iot, ioh,
332 IOPB_GPIO_CNTL, 0);
333 if (ADW_READ_BYTE_REGISTER(iot, ioh,
334 IOPB_GPIO_DATA) & 0x01) {
335 /*
336 * Function 1 interrupt wired to INTA;
337 * Set EEPROM bit.
338 */
339 lsw_msb |= (ADW_EEPROM_INTAB >> 8)
340 & 0xFF;
341 }
342 eep_config.cfg_lsw &= 0x00FF;
343 eep_config.cfg_lsw |= lsw_msb << 8;
344 }
345 break;
346 }
347
348 /*
349 * Assume the 6 byte board serial number that was read
350 * from EEPROM is correct even if the EEPROM checksum
351 * failed.
352 */
353 for (i=2, j=1; i>=0; i--, j++) {
354 eep_config.serial_number[i] =
355 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j);
356 }
357
358 AdwSetEEPROMConfig(iot, ioh, &eep_config);
359 }
360 /*
361 * Set sc and sc->cfg variables from the EEPROM configuration
362 * that was read.
363 *
364 * This is the mapping of EEPROM fields to Adw Library fields.
365 */
366 sc->wdtr_able = eep_config.wdtr_able;
367 if (sc->chip_type == ADW_CHIP_ASC3550) {
368 sc->sdtr_able = eep_config.sdtr1.sdtr_able;
369 sc->ultra_able = eep_config.sdtr2.ultra_able;
370 } else {
371 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1;
372 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2;
373 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3;
374 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4;
375 }
376 sc->ppr_able = 0;
377 sc->tagqng_able = eep_config.tagqng_able;
378 sc->cfg.disc_enable = eep_config.disc_enable;
379 sc->max_host_qng = eep_config.max_host_qng;
380 sc->max_dvc_qng = eep_config.max_dvc_qng;
381 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID);
382 sc->start_motor = eep_config.start_motor;
383 sc->scsi_reset_wait = eep_config.scsi_reset_delay;
384 sc->bios_ctrl = eep_config.bios_ctrl;
385 sc->no_scam = eep_config.scam_tolerant;
386 sc->cfg.serial1 = eep_config.serial_number[0];
387 sc->cfg.serial2 = eep_config.serial_number[1];
388 sc->cfg.serial3 = eep_config.serial_number[2];
389
390 if (sc->chip_type == ADW_CHIP_ASC38C0800 ||
391 sc->chip_type == ADW_CHIP_ASC38C1600) {
392 sc->sdtr_able = 0;
393 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
394 if (tid == 0) {
395 sdtr_speed = sc->sdtr_speed1;
396 } else if (tid == 4) {
397 sdtr_speed = sc->sdtr_speed2;
398 } else if (tid == 8) {
399 sdtr_speed = sc->sdtr_speed3;
400 } else if (tid == 12) {
401 sdtr_speed = sc->sdtr_speed4;
402 }
403 if (sdtr_speed & ADW_MAX_TID) {
404 sc->sdtr_able |= (1 << tid);
405 }
406 sdtr_speed >>= 4;
407 }
408 }
409
410 /*
411 * Set the host maximum queuing (max. 253, min. 16) and the per device
412 * maximum queuing (max. 63, min. 4).
413 */
414 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) {
415 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
416 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG)
417 {
418 /* If the value is zero, assume it is uninitialized. */
419 if (eep_config.max_host_qng == 0) {
420 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG;
421 } else {
422 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG;
423 }
424 }
425
426 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) {
427 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
428 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) {
429 /* If the value is zero, assume it is uninitialized. */
430 if (eep_config.max_dvc_qng == 0) {
431 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG;
432 } else {
433 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG;
434 }
435 }
436
437 /*
438 * If 'max_dvc_qng' is greater than 'max_host_qng', then
439 * set 'max_dvc_qng' to 'max_host_qng'.
440 */
441 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
442 eep_config.max_dvc_qng = eep_config.max_host_qng;
443 }
444
445 /*
446 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
447 * values based on possibly adjusted EEPROM values.
448 */
449 sc->max_host_qng = eep_config.max_host_qng;
450 sc->max_dvc_qng = eep_config.max_dvc_qng;
451
452
453 /*
454 * If the EEPROM 'termination' field is set to automatic (0), then set
455 * the ADV_DVC_CFG 'termination' field to automatic also.
456 *
457 * If the termination is specified with a non-zero 'termination'
458 * value check that a legal value is set and set the ADV_DVC_CFG
459 * 'termination' field appropriately.
460 */
461
462 switch(sc->chip_type) {
463 case ADW_CHIP_ASC3550:
464 sc->cfg.termination = 0; /* auto termination */
465 switch(eep_config.termination_se) {
466 case 3:
467 /* Enable manual control with low on / high on. */
468 sc->cfg.termination |= ADW_TERM_CTL_L;
469 case 2:
470 /* Enable manual control with low off / high on. */
471 sc->cfg.termination |= ADW_TERM_CTL_H;
472 case 1:
473 /* Enable manual control with low off / high off. */
474 sc->cfg.termination |= ADW_TERM_CTL_SEL;
475 case 0:
476 break;
477 default:
478 warn_code |= ADW_WARN_EEPROM_TERMINATION;
479 }
480 break;
481
482 case ADW_CHIP_ASC38C0800:
483 case ADW_CHIP_ASC38C1600:
484 switch(eep_config.termination_se) {
485 case 0:
486 /* auto termination for SE */
487 termination = 0;
488 break;
489 case 1:
490 /* Enable manual control with low off / high off. */
491 termination = 0;
492 break;
493 case 2:
494 /* Enable manual control with low off / high on. */
495 termination = ADW_TERM_SE_HI;
496 break;
497 case 3:
498 /* Enable manual control with low on / high on. */
499 termination = ADW_TERM_SE;
500 break;
501 default:
502 /*
503 * The EEPROM 'termination_se' field contains a
504 * bad value. Use automatic termination instead.
505 */
506 termination = 0;
507 warn_code |= ADW_WARN_EEPROM_TERMINATION;
508 }
509
510 switch(eep_config.termination_lvd) {
511 case 0:
512 /* auto termination for LVD */
513 sc->cfg.termination = termination;
514 break;
515 case 1:
516 /* Enable manual control with low off / high off. */
517 sc->cfg.termination = termination;
518 break;
519 case 2:
520 /* Enable manual control with low off / high on. */
521 sc->cfg.termination = termination | ADW_TERM_LVD_HI;
522 break;
523 case 3:
524 /* Enable manual control with low on / high on. */
525 sc->cfg.termination = termination | ADW_TERM_LVD;
526 break;
527 default:
528 /*
529 * The EEPROM 'termination_lvd' field contains a
530 * bad value. Use automatic termination instead.
531 */
532 sc->cfg.termination = termination;
533 warn_code |= ADW_WARN_EEPROM_TERMINATION;
534 }
535 break;
536 }
537
538 return warn_code;
539 }
540
541
542 /*
543 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600.
544 *
545 * On failure return the error code.
546 */
547 int
548 AdwInitDriver(sc)
549 ADW_SOFTC *sc;
550 {
551 bus_space_tag_t iot = sc->sc_iot;
552 bus_space_handle_t ioh = sc->sc_ioh;
553 u_int16_t error_code;
554 int word;
555 int i;
556 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory
557 0x40-0x8F. */
558 u_int16_t wdtr_able = 0, sdtr_able, ppr_able, tagqng_able;
559 u_int8_t max_cmd[ADW_MAX_TID + 1];
560 u_int8_t tid;
561
562
563 error_code = 0;
564
565 /*
566 * Save the RISC memory BIOS region before writing the microcode.
567 * The BIOS may already be loaded and using its RISC LRAM region
568 * so its region must be saved and restored.
569 *
570 * Note: This code makes the assumption, which is currently true,
571 * that a chip reset does not clear RISC LRAM.
572 */
573 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
574 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]);
575 }
576
577 /*
578 * Save current per TID negotiated values.
579 */
580 switch (sc->chip_type) {
581 case ADW_CHIP_ASC3550:
582 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){
583
584 u_int16_t bios_version, major, minor;
585
586 bios_version = bios_mem[(ADW_MC_BIOS_VERSION -
587 ADW_MC_BIOSMEM) / 2];
588 major = (bios_version >> 12) & 0xF;
589 minor = (bios_version >> 8) & 0xF;
590 if (major < 3 || (major == 3 && minor == 1)) {
591 /*
592 * BIOS 3.1 and earlier location of
593 * 'wdtr_able' variable.
594 */
595 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able);
596 } else {
597 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
598 wdtr_able);
599 }
600 }
601 break;
602
603 case ADW_CHIP_ASC38C1600:
604 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
605 /* FALLTHROUGH */
606 case ADW_CHIP_ASC38C0800:
607 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
608 break;
609 }
610 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
611 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
612 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
613 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
614 max_cmd[tid]);
615 }
616
617 /*
618 * Perform a RAM Built-In Self Test
619 */
620 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) {
621 return error_code;
622 }
623
624 /*
625 * Load the Microcode
626 */
627 ;
628 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) {
629 return error_code;
630 }
631
632 /*
633 * Read microcode version and date.
634 */
635 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date);
636 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version);
637
638 /*
639 * If the PCI Configuration Command Register "Parity Error Response
640 * Control" Bit was clear (0), then set the microcode variable
641 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
642 * to ignore DMA parity errors.
643 */
644 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) {
645 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
646 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
647 word | CONTROL_FLAG_IGNORE_PERR);
648 }
649
650 switch (sc->chip_type) {
651 case ADW_CHIP_ASC3550:
652 /*
653 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a
654 * FIFO threshold of 128 bytes.
655 * This register is only accessible to the host.
656 */
657 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
658 START_CTL_EMFU | READ_CMD_MRM);
659 break;
660
661 case ADW_CHIP_ASC38C0800:
662 /*
663 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
664 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
665 * cable detection and then we are able to read C_DET[3:0].
666 *
667 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
668 * Microcode Default Value' section below.
669 */
670 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
671 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
672 | ADW_DIS_TERM_DRV);
673
674 /*
675 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
676 * START_CTL_TH [3:2] bits for the default FIFO threshold.
677 *
678 * Note: ASC-38C0800 FIFO threshold has been changed to
679 * 256 bytes.
680 *
681 * For DMA Errata #4 set the BC_THRESH_ENB bit.
682 */
683 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
684 BC_THRESH_ENB | FIFO_THRESH_80B
685 | START_CTL_TH | READ_CMD_MRM);
686 break;
687
688 case ADW_CHIP_ASC38C1600:
689 /*
690 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
691 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
692 * cable detection and then we are able to read C_DET[3:0].
693 *
694 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
695 * Microcode Default Value' section below.
696 */
697 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1,
698 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1)
699 | ADW_DIS_TERM_DRV);
700
701 /*
702 * If the BIOS control flag AIPP (Asynchronous Information
703 * Phase Protection) disable bit is not set, then set the
704 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to
705 * enable AIPP checking and encoding.
706 */
707 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
708 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word);
709 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG,
710 word | CONTROL_FLAG_ENABLE_AIPP);
711 }
712
713 /*
714 * For ASC-38C1600 use DMA_CFG0 default values:
715 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2].
716 */
717 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0,
718 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
719 break;
720 }
721
722 /*
723 * Microcode operating variables for WDTR, SDTR, and command tag
724 * queuing will be set in AdvInquiryHandling() based on what a
725 * device reports it is capable of in Inquiry byte 7.
726 *
727 * If SCSI Bus Resets have been disabled, then directly set
728 * SDTR and WDTR from the EEPROM configuration. This will allow
729 * the BIOS and warm boot to work without a SCSI bus hang on
730 * the Inquiry caused by host and target mismatched DTR values.
731 * Without the SCSI Bus Reset, before an Inquiry a device can't
732 * be assumed to be in Asynchronous, Narrow mode.
733 */
734 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
735 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able);
736 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able);
737 }
738
739 /*
740 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
741 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
742 * bitmask. These values determine the maximum SDTR speed negotiated
743 * with a device.
744 *
745 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
746 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
747 * without determining here whether the device supports SDTR.
748 */
749 switch (sc->chip_type) {
750 case ADW_CHIP_ASC3550:
751 word = 0;
752 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
753 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) {
754 /* Set Ultra speed for TID 'tid'. */
755 word |= (0x3 << (4 * (tid % 4)));
756 } else {
757 /* Set Fast speed for TID 'tid'. */
758 word |= (0x2 << (4 * (tid % 4)));
759 }
760 /* Check if done with sdtr_speed1. */
761 if (tid == 3) {
762 ADW_WRITE_WORD_LRAM(iot, ioh,
763 ADW_MC_SDTR_SPEED1, word);
764 word = 0;
765 /* Check if done with sdtr_speed2. */
766 } else if (tid == 7) {
767 ADW_WRITE_WORD_LRAM(iot, ioh,
768 ADW_MC_SDTR_SPEED2, word);
769 word = 0;
770 /* Check if done with sdtr_speed3. */
771 } else if (tid == 11) {
772 ADW_WRITE_WORD_LRAM(iot, ioh,
773 ADW_MC_SDTR_SPEED3, word);
774 word = 0;
775 /* Check if done with sdtr_speed4. */
776 } else if (tid == 15) {
777 ADW_WRITE_WORD_LRAM(iot, ioh,
778 ADW_MC_SDTR_SPEED4, word);
779 /* End of loop. */
780 }
781 }
782
783 /*
784 * Set microcode operating variable for the
785 * disconnect per TID bitmask.
786 */
787 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
788 sc->cfg.disc_enable);
789 break;
790
791 case ADW_CHIP_ASC38C0800:
792 /* FALLTHROUGH */
793 case ADW_CHIP_ASC38C1600:
794 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE,
795 sc->cfg.disc_enable);
796 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1,
797 sc->sdtr_speed1);
798 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2,
799 sc->sdtr_speed2);
800 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3,
801 sc->sdtr_speed3);
802 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4,
803 sc->sdtr_speed4);
804 break;
805 }
806
807
808 /*
809 * Set SCSI_CFG0 Microcode Default Value.
810 *
811 * The microcode will set the SCSI_CFG0 register using this value
812 * after it is started below.
813 */
814 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0,
815 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG |
816 ADW_OUR_ID_EN | sc->chip_scsi_id);
817
818
819 switch(sc->chip_type) {
820 case ADW_CHIP_ASC3550:
821 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg);
822 break;
823
824 case ADW_CHIP_ASC38C0800:
825 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg);
826 break;
827
828 case ADW_CHIP_ASC38C1600:
829 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg);
830 break;
831 }
832 if(error_code) {
833 return error_code;
834 }
835
836 /*
837 * Set SEL_MASK Microcode Default Value
838 *
839 * The microcode will set the SEL_MASK register using this value
840 * after it is started below.
841 */
842 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK,
843 ADW_TID_TO_TIDMASK(sc->chip_scsi_id));
844
845 /*
846 * Create and Initialize Host->RISC Carrier lists
847 */
848 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier,
849 sc->sc_control->carriers);
850
851 /*
852 * Set-up the Host->RISC Initiator Command Queue (ICQ).
853 */
854
855 if ((sc->icq_sp = sc->carr_freelist) == NULL) {
856 return ADW_IERR_NO_CARRIER;
857 }
858 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
859 ASC_GET_CARRP(sc->icq_sp->next_ba));
860
861 /*
862 * The first command issued will be placed in the stopper carrier.
863 */
864 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER);
865
866 /*
867 * Set RISC ICQ physical address start value.
868 */
869 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba));
870
871 /*
872 * Initialize the COMMA register to the same value otherwise
873 * the RISC will prematurely detect a command is available.
874 */
875 if(sc->chip_type == ADW_CHIP_ASC38C1600) {
876 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
877 le32toh(sc->icq_sp->carr_ba));
878 }
879
880 /*
881 * Set-up the RISC->Host Initiator Response Queue (IRQ).
882 */
883 if ((sc->irq_sp = sc->carr_freelist) == NULL) {
884 return ADW_IERR_NO_CARRIER;
885 }
886 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
887 ASC_GET_CARRP(sc->irq_sp->next_ba));
888
889 /*
890 * The first command completed by the RISC will be placed in
891 * the stopper.
892 *
893 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is
894 * completed the RISC will set the ASC_RQ_DONE bit.
895 */
896 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER);
897
898 /*
899 * Set RISC IRQ physical address start value.
900 */
901 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba));
902 sc->carr_pending_cnt = 0;
903
904 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES,
905 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR));
906 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word);
907 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word);
908
909 /* finally, finally, gentlemen, start your engine */
910 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN);
911
912 /*
913 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
914 * Resets should be performed. The RISC has to be running
915 * to issue a SCSI Bus Reset.
916 */
917 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
918 {
919 /*
920 * If the BIOS Signature is present in memory, restore the
921 * BIOS Handshake Configuration Table and do not perform
922 * a SCSI Bus Reset.
923 */
924 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] ==
925 0x55AA) {
926 /*
927 * Restore per TID negotiated values.
928 */
929 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
930 wdtr_able);
931 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
932 sdtr_able);
933 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
934 tagqng_able);
935 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
936 ADW_WRITE_BYTE_LRAM(iot, ioh,
937 ADW_MC_NUMBER_OF_MAX_CMD + tid,
938 max_cmd[tid]);
939 }
940 } else {
941 if (AdwResetCCB(sc) != ADW_TRUE) {
942 error_code = ADW_WARN_BUSRESET_ERROR;
943 }
944 }
945 }
946
947 return error_code;
948 }
949
950
951 int
952 AdwRamSelfTest(iot, ioh, chip_type)
953 bus_space_tag_t iot;
954 bus_space_handle_t ioh;
955 u_int8_t chip_type;
956 {
957 int i;
958 u_int8_t byte;
959
960
961 if ((chip_type == ADW_CHIP_ASC38C0800) ||
962 (chip_type == ADW_CHIP_ASC38C1600)) {
963 /*
964 * RAM BIST (RAM Built-In Self Test)
965 *
966 * Address : I/O base + offset 0x38h register (byte).
967 * Function: Bit 7-6(RW) : RAM mode
968 * Normal Mode : 0x00
969 * Pre-test Mode : 0x40
970 * RAM Test Mode : 0x80
971 * Bit 5 : unused
972 * Bit 4(RO) : Done bit
973 * Bit 3-0(RO) : Status
974 * Host Error : 0x08
975 * Int_RAM Error : 0x04
976 * RISC Error : 0x02
977 * SCSI Error : 0x01
978 * No Error : 0x00
979 *
980 * Note: RAM BIST code should be put right here, before loading
981 * the microcode and after saving the RISC memory BIOS region.
982 */
983
984 /*
985 * LRAM Pre-test
986 *
987 * Write PRE_TEST_MODE (0x40) to register and wait for
988 * 10 milliseconds.
989 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05),
990 * return an error. Reset to NORMAL_MODE (0x00) and do again.
991 * If cannot reset to NORMAL_MODE, return an error too.
992 */
993 for (i = 0; i < 2; i++) {
994 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
995 PRE_TEST_MODE);
996 /* Wait for 10ms before reading back. */
997 AdwSleepMilliSecond(10);
998 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
999 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) !=
1000 PRE_TEST_VALUE) {
1001 return ADW_IERR_BIST_PRE_TEST;
1002 }
1003
1004 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST,
1005 NORMAL_MODE);
1006 /* Wait for 10ms before reading back. */
1007 AdwSleepMilliSecond(10);
1008 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST)
1009 != NORMAL_VALUE) {
1010 return ADW_IERR_BIST_PRE_TEST;
1011 }
1012 }
1013
1014 /*
1015 * LRAM Test - It takes about 1.5 ms to run through the test.
1016 *
1017 * Write RAM_TEST_MODE (0x80) to register and wait for
1018 * 10 milliseconds.
1019 * If Done bit not set or Status not 0, save register byte,
1020 * set the err_code, and return an error.
1021 */
1022 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE);
1023 /* Wait for 10ms before checking status. */
1024 AdwSleepMilliSecond(10);
1025
1026 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST);
1027 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) {
1028 /* Get here if Done bit not set or Status not 0. */
1029 return ADW_IERR_BIST_RAM_TEST;
1030 }
1031
1032 /* We need to reset back to normal mode after LRAM test passes*/
1033 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE);
1034 }
1035
1036 return 0;
1037 }
1038
1039
1040 int
1041 AdwLoadMCode(iot, ioh, bios_mem, chip_type)
1042 bus_space_tag_t iot;
1043 bus_space_handle_t ioh;
1044 u_int16_t *bios_mem;
1045 u_int8_t chip_type;
1046 {
1047 const u_int8_t *mcode_data;
1048 u_int32_t mcode_chksum;
1049 u_int16_t mcode_size;
1050 u_int32_t sum;
1051 u_int16_t code_sum;
1052 int begin_addr;
1053 int end_addr;
1054 int word;
1055 int adw_memsize;
1056 int adw_mcode_expanded_size;
1057 int i, j;
1058
1059
1060 switch(chip_type) {
1061 case ADW_CHIP_ASC3550:
1062 mcode_data = (const u_int8_t *)adw_asc3550_mcode_data.mcode_data;
1063 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum;
1064 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size;
1065 adw_memsize = ADW_3550_MEMSIZE;
1066 break;
1067
1068 case ADW_CHIP_ASC38C0800:
1069 mcode_data = (const u_int8_t *)adw_asc38C0800_mcode_data.mcode_data;
1070 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum;
1071 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size;
1072 adw_memsize = ADW_38C0800_MEMSIZE;
1073 break;
1074
1075 case ADW_CHIP_ASC38C1600:
1076 mcode_data = (const u_int8_t *)adw_asc38C1600_mcode_data.mcode_data;
1077 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum;
1078 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size;
1079 adw_memsize = ADW_38C1600_MEMSIZE;
1080 break;
1081
1082 default:
1083 return (EINVAL);
1084 }
1085
1086 /*
1087 * Write the microcode image to RISC memory starting at address 0.
1088 */
1089 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1090
1091 /* Assume the following compressed format of the microcode buffer:
1092 *
1093 * 254 word (508 byte) table indexed by byte code followed
1094 * by the following byte codes:
1095 *
1096 * 1-Byte Code:
1097 * 00: Emit word 0 in table.
1098 * 01: Emit word 1 in table.
1099 * .
1100 * FD: Emit word 253 in table.
1101 *
1102 * Multi-Byte Code:
1103 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
1104 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
1105 */
1106 word = 0;
1107 for (i = 253 * 2; i < mcode_size; i++) {
1108 if (mcode_data[i] == 0xff) {
1109 for (j = 0; j < mcode_data[i + 1]; j++) {
1110 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1111 (((u_int16_t)mcode_data[i + 3] << 8) |
1112 mcode_data[i + 2]));
1113 word++;
1114 }
1115 i += 3;
1116 } else if (mcode_data[i] == 0xfe) {
1117 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh,
1118 (((u_int16_t)mcode_data[i + 2] << 8) |
1119 mcode_data[i + 1]));
1120 i += 2;
1121 word++;
1122 } else {
1123 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t)
1124 mcode_data[(mcode_data[i] * 2) + 1] <<8) |
1125 mcode_data[mcode_data[i] * 2]));
1126 word++;
1127 }
1128 }
1129
1130 /*
1131 * Set 'word' for later use to clear the rest of memory and save
1132 * the expanded mcode size.
1133 */
1134 word *= 2;
1135 adw_mcode_expanded_size = word;
1136
1137 /*
1138 * Clear the rest of the Internal RAM.
1139 */
1140 for (; word < adw_memsize; word += 2) {
1141 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0);
1142 }
1143
1144 /*
1145 * Verify the microcode checksum.
1146 */
1147 sum = 0;
1148 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0);
1149
1150 for (word = 0; word < adw_mcode_expanded_size; word += 2) {
1151 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1152 }
1153
1154 if (sum != mcode_chksum) {
1155 return ADW_IERR_MCODE_CHKSUM;
1156 }
1157
1158 /*
1159 * Restore the RISC memory BIOS region.
1160 */
1161 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) {
1162 if(chip_type == ADW_CHIP_ASC3550) {
1163 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1164 bios_mem[i]);
1165 } else {
1166 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i),
1167 bios_mem[i]);
1168 }
1169 }
1170
1171 /*
1172 * Calculate and write the microcode code checksum to the microcode
1173 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C).
1174 */
1175 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr);
1176 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr);
1177 code_sum = 0;
1178 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr);
1179 for (word = begin_addr; word < end_addr; word += 2) {
1180 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh);
1181 }
1182 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum);
1183
1184 /*
1185 * Set the chip type.
1186 */
1187 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type);
1188
1189 return 0;
1190 }
1191
1192
1193 int
1194 AdwASC3550Cabling(iot, ioh, cfg)
1195 bus_space_tag_t iot;
1196 bus_space_handle_t ioh;
1197 ADW_DVC_CFG *cfg;
1198 {
1199 u_int16_t scsi_cfg1;
1200
1201
1202 /*
1203 * Determine SCSI_CFG1 Microcode Default Value.
1204 *
1205 * The microcode will set the SCSI_CFG1 register using this value
1206 * after it is started below.
1207 */
1208
1209 /* Read current SCSI_CFG1 Register value. */
1210 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1211
1212 /*
1213 * If all three connectors are in use in ASC3550, return an error.
1214 */
1215 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
1216 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
1217 return ADW_IERR_ILLEGAL_CONNECTION;
1218 }
1219
1220 /*
1221 * If the cable is reversed all of the SCSI_CTRL register signals
1222 * will be set. Check for and return an error if this condition is
1223 * found.
1224 */
1225 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1226 return ADW_IERR_REVERSED_CABLE;
1227 }
1228
1229 /*
1230 * If this is a differential board and a single-ended device
1231 * is attached to one of the connectors, return an error.
1232 */
1233 if ((scsi_cfg1 & ADW_DIFF_MODE) &&
1234 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) {
1235 return ADW_IERR_SINGLE_END_DEVICE;
1236 }
1237
1238 /*
1239 * If automatic termination control is enabled, then set the
1240 * termination value based on a table listed in a_condor.h.
1241 *
1242 * If manual termination was specified with an EEPROM setting
1243 * then 'termination' was set-up in AdwInitFromEEPROM() and
1244 * is ready to be 'ored' into SCSI_CFG1.
1245 */
1246 if (cfg->termination == 0) {
1247 /*
1248 * The software always controls termination by setting
1249 * TERM_CTL_SEL.
1250 * If TERM_CTL_SEL were set to 0, the hardware would set
1251 * termination.
1252 */
1253 cfg->termination |= ADW_TERM_CTL_SEL;
1254
1255 switch(scsi_cfg1 & ADW_CABLE_DETECT) {
1256 /* TERM_CTL_H: on, TERM_CTL_L: on */
1257 case 0x3: case 0x7: case 0xB:
1258 case 0xD: case 0xE: case 0xF:
1259 cfg->termination |=
1260 (ADW_TERM_CTL_H | ADW_TERM_CTL_L);
1261 break;
1262
1263 /* TERM_CTL_H: on, TERM_CTL_L: off */
1264 case 0x1: case 0x5: case 0x9:
1265 case 0xA: case 0xC:
1266 cfg->termination |= ADW_TERM_CTL_H;
1267 break;
1268
1269 /* TERM_CTL_H: off, TERM_CTL_L: off */
1270 case 0x2: case 0x6:
1271 break;
1272 }
1273 }
1274
1275 /*
1276 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
1277 */
1278 scsi_cfg1 &= ~ADW_TERM_CTL;
1279
1280 /*
1281 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
1282 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
1283 * referenced, because the hardware internally inverts
1284 * the Termination High and Low bits if TERM_POL is set.
1285 */
1286 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL));
1287
1288 /*
1289 * Set SCSI_CFG1 Microcode Default Value
1290 *
1291 * Set filter value and possibly modified termination control
1292 * bits in the Microcode SCSI_CFG1 Register Value.
1293 *
1294 * The microcode will set the SCSI_CFG1 register using this value
1295 * after it is started below.
1296 */
1297 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1,
1298 ADW_FLTR_DISABLE | scsi_cfg1);
1299
1300 /*
1301 * Set MEM_CFG Microcode Default Value
1302 *
1303 * The microcode will set the MEM_CFG register using this value
1304 * after it is started below.
1305 *
1306 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1307 * are defined.
1308 *
1309 * ASC-3550 has 8KB internal memory.
1310 */
1311 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1312 ADW_BIOS_EN | ADW_RAM_SZ_8KB);
1313
1314 return 0;
1315 }
1316
1317
1318 int
1319 AdwASC38C0800Cabling(iot, ioh, cfg)
1320 bus_space_tag_t iot;
1321 bus_space_handle_t ioh;
1322 ADW_DVC_CFG *cfg;
1323 {
1324 u_int16_t scsi_cfg1;
1325
1326
1327 /*
1328 * Determine SCSI_CFG1 Microcode Default Value.
1329 *
1330 * The microcode will set the SCSI_CFG1 register using this value
1331 * after it is started below.
1332 */
1333
1334 /* Read current SCSI_CFG1 Register value. */
1335 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1336
1337 /*
1338 * If the cable is reversed all of the SCSI_CTRL register signals
1339 * will be set. Check for and return an error if this condition is
1340 * found.
1341 */
1342 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1343 return ADW_IERR_REVERSED_CABLE;
1344 }
1345
1346 /*
1347 * All kind of combinations of devices attached to one of four
1348 * connectors are acceptable except HVD device attached.
1349 * For example, LVD device can be attached to SE connector while
1350 * SE device attached to LVD connector.
1351 * If LVD device attached to SE connector, it only runs up to
1352 * Ultra speed.
1353 *
1354 * If an HVD device is attached to one of LVD connectors, return
1355 * an error.
1356 * However, there is no way to detect HVD device attached to
1357 * SE connectors.
1358 */
1359 if (scsi_cfg1 & ADW_HVD) {
1360 return ADW_IERR_HVD_DEVICE;
1361 }
1362
1363 /*
1364 * If either SE or LVD automatic termination control is enabled, then
1365 * set the termination value based on a table listed in a_condor.h.
1366 *
1367 * If manual termination was specified with an EEPROM setting then
1368 * 'termination' was set-up in AdwInitFromEEPROM() and is ready
1369 * to be 'ored' into SCSI_CFG1.
1370 */
1371 if ((cfg->termination & ADW_TERM_SE) == 0) {
1372 /* SE automatic termination control is enabled. */
1373 switch(scsi_cfg1 & ADW_C_DET_SE) {
1374 /* TERM_SE_HI: on, TERM_SE_LO: on */
1375 case 0x1: case 0x2: case 0x3:
1376 cfg->termination |= ADW_TERM_SE;
1377 break;
1378
1379 /* TERM_SE_HI: on, TERM_SE_LO: off */
1380 case 0x0:
1381 cfg->termination |= ADW_TERM_SE_HI;
1382 break;
1383 }
1384 }
1385
1386 if ((cfg->termination & ADW_TERM_LVD) == 0) {
1387 /* LVD automatic termination control is enabled. */
1388 switch(scsi_cfg1 & ADW_C_DET_LVD) {
1389 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
1390 case 0x4: case 0x8: case 0xC:
1391 cfg->termination |= ADW_TERM_LVD;
1392 break;
1393
1394 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
1395 case 0x0:
1396 break;
1397 }
1398 }
1399
1400 /*
1401 * Clear any set TERM_SE and TERM_LVD bits.
1402 */
1403 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD);
1404
1405 /*
1406 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
1407 */
1408 scsi_cfg1 |= (~cfg->termination & 0xF0);
1409
1410 /*
1411 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and
1412 * HVD/LVD/SE bits and set possibly modified termination control bits
1413 * in the Microcode SCSI_CFG1 Register Value.
1414 */
1415 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV &
1416 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE);
1417
1418 /*
1419 * Set SCSI_CFG1 Microcode Default Value
1420 *
1421 * Set possibly modified termination control and reset DIS_TERM_DRV
1422 * bits in the Microcode SCSI_CFG1 Register Value.
1423 *
1424 * The microcode will set the SCSI_CFG1 register using this value
1425 * after it is started below.
1426 */
1427 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1428
1429 /*
1430 * Set MEM_CFG Microcode Default Value
1431 *
1432 * The microcode will set the MEM_CFG register using this value
1433 * after it is started below.
1434 *
1435 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1436 * are defined.
1437 *
1438 * ASC-38C0800 has 16KB internal memory.
1439 */
1440 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1441 ADW_BIOS_EN | ADW_RAM_SZ_16KB);
1442
1443 return 0;
1444 }
1445
1446
1447 int
1448 AdwASC38C1600Cabling(iot, ioh, cfg)
1449 bus_space_tag_t iot;
1450 bus_space_handle_t ioh;
1451 ADW_DVC_CFG *cfg;
1452 {
1453 u_int16_t scsi_cfg1;
1454
1455
1456 /*
1457 * Determine SCSI_CFG1 Microcode Default Value.
1458 *
1459 * The microcode will set the SCSI_CFG1 register using this value
1460 * after it is started below.
1461 * Each ASC-38C1600 function has only two cable detect bits.
1462 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
1463 */
1464
1465 /* Read current SCSI_CFG1 Register value. */
1466 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1467
1468 /*
1469 * If the cable is reversed all of the SCSI_CTRL register signals
1470 * will be set. Check for and return an error if this condition is
1471 * found.
1472 */
1473 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){
1474 return ADW_IERR_REVERSED_CABLE;
1475 }
1476
1477 /*
1478 * Each ASC-38C1600 function has two connectors. Only an HVD device
1479 * cannot be connected to either connector. An LVD device or SE device
1480 * may be connected to either connector. If an SE device is connected,
1481 * then at most Ultra speed (20 MHz) can be used on both connectors.
1482 *
1483 * If an HVD device is attached, return an error.
1484 */
1485 if (scsi_cfg1 & ADW_HVD) {
1486 return ADW_IERR_HVD_DEVICE;
1487 }
1488
1489 /*
1490 * Each function in the ASC-38C1600 uses only the SE cable detect and
1491 * termination because there are two connectors for each function.
1492 * Each function may use either LVD or SE mode.
1493 * Corresponding the SE automatic termination control EEPROM bits are
1494 * used for each function.
1495 * Each function has its own EEPROM. If SE automatic control is enabled
1496 * for the function, then set the termination value based on a table
1497 * listed in adwlib.h.
1498 *
1499 * If manual termination is specified in the EEPROM for the function,
1500 * then 'termination' was set-up in AdwInitFromEEPROM() and is
1501 * ready to be 'ored' into SCSI_CFG1.
1502 */
1503 if ((cfg->termination & ADW_TERM_SE) == 0) {
1504 /* SE automatic termination control is enabled. */
1505 switch(scsi_cfg1 & ADW_C_DET_SE) {
1506 /* TERM_SE_HI: on, TERM_SE_LO: on */
1507 case 0x1: case 0x2: case 0x3:
1508 cfg->termination |= ADW_TERM_SE;
1509 break;
1510
1511 case 0x0:
1512 #if 0
1513 /* !!!!TODO!!!! */
1514 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) {
1515 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
1516 }
1517 else
1518 #endif
1519 {
1520 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
1521 cfg->termination |= ADW_TERM_SE_HI;
1522 }
1523 break;
1524 }
1525 }
1526
1527 /*
1528 * Clear any set TERM_SE bits.
1529 */
1530 scsi_cfg1 &= ~ADW_TERM_SE;
1531
1532 /*
1533 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
1534 */
1535 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE);
1536
1537 /*
1538 * Clear Big Endian and Terminator Polarity bits and set possibly
1539 * modified termination control bits in the Microcode SCSI_CFG1
1540 * Register Value.
1541 */
1542 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL);
1543
1544 /*
1545 * Set SCSI_CFG1 Microcode Default Value
1546 *
1547 * Set possibly modified termination control bits in the Microcode
1548 * SCSI_CFG1 Register Value.
1549 *
1550 * The microcode will set the SCSI_CFG1 register using this value
1551 * after it is started below.
1552 */
1553 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1554
1555 /*
1556 * Set MEM_CFG Microcode Default Value
1557 *
1558 * The microcode will set the MEM_CFG register using this value
1559 * after it is started below.
1560 *
1561 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
1562 * are defined.
1563 *
1564 * ASC-38C1600 has 32KB internal memory.
1565 */
1566 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG,
1567 ADW_BIOS_EN | ADW_RAM_SZ_32KB);
1568
1569 return 0;
1570 }
1571
1572
1573 /*
1574 * Read EEPROM configuration into the specified buffer.
1575 *
1576 * Return a checksum based on the EEPROM configuration read.
1577 */
1578 static u_int16_t
1579 AdwGetEEPROMConfig(iot, ioh, cfg_buf)
1580 bus_space_tag_t iot;
1581 bus_space_handle_t ioh;
1582 ADW_EEPROM *cfg_buf;
1583 {
1584 u_int16_t wval, chksum;
1585 u_int16_t *wbuf;
1586 int eep_addr;
1587
1588
1589 wbuf = (u_int16_t *) cfg_buf;
1590 chksum = 0;
1591
1592 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN;
1593 eep_addr < ASC_EEP_DVC_CFG_END;
1594 eep_addr++, wbuf++) {
1595 wval = AdwReadEEPWord(iot, ioh, eep_addr);
1596 chksum += wval;
1597 *wbuf = wval;
1598 }
1599
1600 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1601 wbuf++;
1602 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN;
1603 eep_addr < ASC_EEP_MAX_WORD_ADDR;
1604 eep_addr++, wbuf++) {
1605 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr);
1606 }
1607
1608 return chksum;
1609 }
1610
1611
1612 /*
1613 * Read the EEPROM from specified location
1614 */
1615 static u_int16_t
1616 AdwReadEEPWord(iot, ioh, eep_word_addr)
1617 bus_space_tag_t iot;
1618 bus_space_handle_t ioh;
1619 int eep_word_addr;
1620 {
1621 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1622 ASC_EEP_CMD_READ | eep_word_addr);
1623 AdwWaitEEPCmd(iot, ioh);
1624
1625 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA);
1626 }
1627
1628
1629 /*
1630 * Wait for EEPROM command to complete
1631 */
1632 static void
1633 AdwWaitEEPCmd(iot, ioh)
1634 bus_space_tag_t iot;
1635 bus_space_handle_t ioh;
1636 {
1637 int eep_delay_ms;
1638
1639
1640 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){
1641 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) &
1642 ASC_EEP_CMD_DONE) {
1643 break;
1644 }
1645 AdwSleepMilliSecond(1);
1646 }
1647
1648 (void)ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD);
1649 }
1650
1651
1652 /*
1653 * Write the EEPROM from 'cfg_buf'.
1654 */
1655 static void
1656 AdwSetEEPROMConfig(iot, ioh, cfg_buf)
1657 bus_space_tag_t iot;
1658 bus_space_handle_t ioh;
1659 ADW_EEPROM *cfg_buf;
1660 {
1661 u_int16_t *wbuf;
1662 u_int16_t addr, chksum;
1663
1664
1665 wbuf = (u_int16_t *) cfg_buf;
1666 chksum = 0;
1667
1668 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
1669 AdwWaitEEPCmd(iot, ioh);
1670
1671 /*
1672 * Write EEPROM from word 0 to word 20
1673 */
1674 for (addr = ASC_EEP_DVC_CFG_BEGIN;
1675 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) {
1676 chksum += *wbuf;
1677 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1678 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1679 ASC_EEP_CMD_WRITE | addr);
1680 AdwWaitEEPCmd(iot, ioh);
1681 AdwSleepMilliSecond(ASC_EEP_DELAY_MS);
1682 }
1683
1684 /*
1685 * Write EEPROM checksum at word 21
1686 */
1687 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum);
1688 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1689 ASC_EEP_CMD_WRITE | addr);
1690 AdwWaitEEPCmd(iot, ioh);
1691 wbuf++; /* skip over check_sum */
1692
1693 /*
1694 * Write EEPROM OEM name at words 22 to 29
1695 */
1696 for (addr = ASC_EEP_DVC_CTL_BEGIN;
1697 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
1698 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf);
1699 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1700 ASC_EEP_CMD_WRITE | addr);
1701 AdwWaitEEPCmd(iot, ioh);
1702 }
1703
1704 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD,
1705 ASC_EEP_CMD_WRITE_DISABLE);
1706 AdwWaitEEPCmd(iot, ioh);
1707
1708 return;
1709 }
1710
1711
1712 /*
1713 * AdwExeScsiQueue() - Send a request to the RISC microcode program.
1714 *
1715 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q,
1716 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
1717 * RISC to notify it a new command is ready to be executed.
1718 *
1719 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
1720 * set to SCSI_MAX_RETRY.
1721 *
1722 * Return:
1723 * ADW_SUCCESS(1) - The request was successfully queued.
1724 * ADW_BUSY(0) - Resource unavailable; Retry again after pending
1725 * request completes.
1726 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure
1727 * host IC error.
1728 */
1729 int
1730 AdwExeScsiQueue(sc, scsiq)
1731 ADW_SOFTC *sc;
1732 ADW_SCSI_REQ_Q *scsiq;
1733 {
1734 bus_space_tag_t iot = sc->sc_iot;
1735 bus_space_handle_t ioh = sc->sc_ioh;
1736 ADW_CCB *ccb;
1737 u_int32_t req_paddr;
1738 ADW_CARRIER *new_carrp;
1739
1740 /*
1741 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID.
1742 */
1743 if (scsiq->target_id > ADW_MAX_TID) {
1744 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
1745 scsiq->done_status = QD_WITH_ERROR;
1746 return ADW_ERROR;
1747 }
1748
1749 /*
1750 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair
1751 */
1752
1753 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr);
1754
1755 /*
1756 * Allocate a carrier and initialize fields.
1757 */
1758 if ((new_carrp = sc->carr_freelist) == NULL) {
1759 return ADW_BUSY;
1760 }
1761 sc->carr_freelist = ADW_CARRIER_VADDR(sc,
1762 ASC_GET_CARRP(new_carrp->next_ba));
1763 sc->carr_pending_cnt++;
1764
1765 /*
1766 * Set the carrier to be a stopper by setting 'next_ba'
1767 * to the stopper value. The current stopper will be changed
1768 * below to point to the new stopper.
1769 */
1770 new_carrp->next_ba = htole32(ASC_CQ_STOPPER);
1771
1772 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr +
1773 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq);
1774
1775 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */
1776 scsiq->scsiq_rptr = htole32(req_paddr);
1777
1778 /*
1779 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian
1780 * order during initialization.
1781 */
1782 scsiq->carr_ba = sc->icq_sp->carr_ba;
1783 scsiq->carr_va = sc->icq_sp->carr_ba;
1784
1785 /*
1786 * Use the current stopper to send the ADW_SCSI_REQ_Q command to
1787 * the microcode. The newly allocated stopper will become the new
1788 * stopper.
1789 */
1790 sc->icq_sp->areq_ba = htole32(req_paddr);
1791
1792 /*
1793 * Set the 'next_ba' pointer for the old stopper to be the
1794 * physical address of the new stopper. The RISC can only
1795 * follow physical addresses.
1796 */
1797 sc->icq_sp->next_ba = new_carrp->carr_ba;
1798
1799 #if ADW_DEBUG
1800 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n",
1801 sc->icq_sp->carr_id,
1802 sc->icq_sp->carr_ba,
1803 sc->icq_sp->areq_ba,
1804 sc->icq_sp->next_ba);
1805 #endif
1806 /*
1807 * Set the host adapter stopper pointer to point to the new carrier.
1808 */
1809 sc->icq_sp = new_carrp;
1810
1811 if (sc->chip_type == ADW_CHIP_ASC3550 ||
1812 sc->chip_type == ADW_CHIP_ASC38C0800) {
1813 /*
1814 * Tickle the RISC to tell it to read its Command Queue Head
1815 * pointer.
1816 */
1817 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A);
1818 if (sc->chip_type == ADW_CHIP_ASC3550) {
1819 /*
1820 * Clear the tickle value. In the ASC-3550 the RISC flag
1821 * command 'clr_tickle_a' does not work unless the host
1822 * value is cleared.
1823 */
1824 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE,
1825 ADW_TICKLE_NOP);
1826 }
1827 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1828 /*
1829 * Notify the RISC a carrier is ready by writing the physical
1830 * address of the new carrier stopper to the COMMA register.
1831 */
1832 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA,
1833 le32toh(new_carrp->carr_ba));
1834 }
1835
1836 /*
1837 * End of CRITICAL SECTION: Must be protected within splbio/splx pair
1838 */
1839
1840 return ADW_SUCCESS;
1841 }
1842
1843
1844 void
1845 AdwResetChip(iot, ioh)
1846 bus_space_tag_t iot;
1847 bus_space_handle_t ioh;
1848 {
1849
1850 /*
1851 * Reset Chip.
1852 */
1853 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1854 ADW_CTRL_REG_CMD_RESET);
1855 AdwSleepMilliSecond(100);
1856 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1857 ADW_CTRL_REG_CMD_WR_IO_REG);
1858 }
1859
1860
1861 /*
1862 * Reset SCSI Bus and purge all outstanding requests.
1863 *
1864 * Return Value:
1865 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset.
1866 * ADW_FALSE(0) - Microcode command failed.
1867 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC
1868 * may be hung which requires driver recovery.
1869 */
1870 int
1871 AdwResetCCB(sc)
1872 ADW_SOFTC *sc;
1873 {
1874 int status;
1875
1876 /*
1877 * Send the SCSI Bus Reset idle start idle command which asserts
1878 * the SCSI Bus Reset signal.
1879 */
1880 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L);
1881 if (status != ADW_TRUE) {
1882 return status;
1883 }
1884
1885 /*
1886 * Delay for the specified SCSI Bus Reset hold time.
1887 *
1888 * The hold time delay is done on the host because the RISC has no
1889 * microsecond accurate timer.
1890 */
1891 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US);
1892
1893 /*
1894 * Send the SCSI Bus Reset end idle command which de-asserts
1895 * the SCSI Bus Reset signal and purges any pending requests.
1896 */
1897 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L);
1898 if (status != ADW_TRUE) {
1899 return status;
1900 }
1901
1902 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000);
1903
1904 return status;
1905 }
1906
1907
1908 /*
1909 * Reset chip and SCSI Bus.
1910 *
1911 * Return Value:
1912 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
1913 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
1914 */
1915 int
1916 AdwResetSCSIBus(sc)
1917 ADW_SOFTC *sc;
1918 {
1919 bus_space_tag_t iot = sc->sc_iot;
1920 bus_space_handle_t ioh = sc->sc_ioh;
1921 int status;
1922 u_int16_t wdtr_able, sdtr_able, tagqng_able;
1923 u_int16_t ppr_able = 0; /* XXX: gcc */
1924 u_int8_t tid, max_cmd[ADW_MAX_TID + 1];
1925 u_int16_t bios_sig;
1926
1927
1928 /*
1929 * Save current per TID negotiated values.
1930 */
1931 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1932 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1933 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1934 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1935 }
1936 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1937 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1938 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1939 max_cmd[tid]);
1940 }
1941
1942 /*
1943 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset
1944 * by clearing the BIOS signature word.
1945 * The initialization functions assumes a SCSI Bus Reset is not
1946 * needed if the BIOS signature word is present.
1947 */
1948 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1949 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0);
1950
1951 /*
1952 * Stop chip and reset it.
1953 */
1954 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP);
1955 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1956 ADW_CTRL_REG_CMD_RESET);
1957 AdwSleepMilliSecond(100);
1958 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG,
1959 ADW_CTRL_REG_CMD_WR_IO_REG);
1960
1961 /*
1962 * Reset Adv Library error code, if any, and try
1963 * re-initializing the chip.
1964 * Then translate initialization return value to status value.
1965 */
1966 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE;
1967
1968 /*
1969 * Restore the BIOS signature word.
1970 */
1971 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig);
1972
1973 /*
1974 * Restore per TID negotiated values.
1975 */
1976 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able);
1977 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able);
1978 if (sc->chip_type == ADW_CHIP_ASC38C1600) {
1979 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able);
1980 }
1981 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able);
1982 for (tid = 0; tid <= ADW_MAX_TID; tid++) {
1983 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid,
1984 max_cmd[tid]);
1985 }
1986
1987 return status;
1988 }
1989
1990
1991 /*
1992 * Adv Library Interrupt Service Routine
1993 *
1994 * This function is called by a driver's interrupt service routine.
1995 * The function disables and re-enables interrupts.
1996 *
1997 * When a microcode idle command is completed, the ADV_DVC_VAR
1998 * 'idle_cmd_done' field is set to ADW_TRUE.
1999 *
2000 * Note: AdwISR() can be called when interrupts are disabled or even
2001 * when there is no hardware interrupt condition present. It will
2002 * always check for completed idle commands and microcode requests.
2003 * This is an important feature that shouldn't be changed because it
2004 * allows commands to be completed from polling mode loops.
2005 *
2006 * Return:
2007 * ADW_TRUE(1) - interrupt was pending
2008 * ADW_FALSE(0) - no interrupt was pending
2009 */
2010 int
2011 AdwISR(sc)
2012 ADW_SOFTC *sc;
2013 {
2014 bus_space_tag_t iot = sc->sc_iot;
2015 bus_space_handle_t ioh = sc->sc_ioh;
2016 u_int8_t int_stat;
2017 ADW_CARRIER *free_carrp/*, *ccb_carr*/;
2018 u_int32_t irq_next_pa;
2019 ADW_SCSI_REQ_Q *scsiq;
2020 ADW_CCB *ccb;
2021 int s;
2022
2023
2024 s = splbio();
2025
2026 /* Reading the register clears the interrupt. */
2027 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG);
2028
2029 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB |
2030 ADW_INTR_STATUS_INTRC)) == 0) {
2031 splx(s);
2032 return ADW_FALSE;
2033 }
2034
2035 /*
2036 * Notify the driver of an asynchronous microcode condition by
2037 * calling the ADV_DVC_VAR.async_callback function. The function
2038 * is passed the microcode ADW_MC_INTRB_CODE byte value.
2039 */
2040 if (int_stat & ADW_INTR_STATUS_INTRB) {
2041 u_int8_t intrb_code;
2042
2043 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code);
2044
2045 if (sc->chip_type == ADW_CHIP_ASC3550 ||
2046 sc->chip_type == ADW_CHIP_ASC38C0800) {
2047 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
2048 sc->carr_pending_cnt != 0) {
2049 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2050 IOPB_TICKLE, ADW_TICKLE_A);
2051 if (sc->chip_type == ADW_CHIP_ASC3550) {
2052 ADW_WRITE_BYTE_REGISTER(iot, ioh,
2053 IOPB_TICKLE, ADW_TICKLE_NOP);
2054 }
2055 }
2056 }
2057
2058 if (sc->async_callback != 0) {
2059 (*(ADW_ASYNC_CALLBACK)sc->async_callback)(sc, intrb_code);
2060 }
2061 }
2062
2063 /*
2064 * Check if the IRQ stopper carrier contains a completed request.
2065 */
2066 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0)
2067 {
2068 #if ADW_DEBUG
2069 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n",
2070 sc->irq_sp->carr_id,
2071 sc->irq_sp->carr_ba,
2072 sc->irq_sp->areq_ba,
2073 sc->irq_sp->next_ba);
2074 #endif
2075 /*
2076 * Get a pointer to the newly completed ADW_SCSI_REQ_Q
2077 * structure.
2078 * The RISC will have set 'areq_ba' to a virtual address.
2079 *
2080 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr
2081 * field to the carrier ADV_CARR_T.areq_ba field.
2082 * The conversion below complements the conversion of
2083 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue().
2084 */
2085 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba);
2086 scsiq = &ccb->scsiq;
2087 scsiq->ccb_ptr = sc->irq_sp->areq_ba;
2088
2089 /*
2090 * Request finished with good status and the queue was not
2091 * DMAed to host memory by the firmware. Set all status fields
2092 * to indicate good status.
2093 */
2094 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) {
2095 scsiq->done_status = QD_NO_ERROR;
2096 scsiq->host_status = scsiq->scsi_status = 0;
2097 scsiq->data_cnt = 0L;
2098 }
2099
2100 /*
2101 * Advance the stopper pointer to the next carrier
2102 * ignoring the lower four bits. Free the previous
2103 * stopper carrier.
2104 */
2105 free_carrp = sc->irq_sp;
2106 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa));
2107
2108 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0
2109 : sc->carr_freelist->carr_ba;
2110 sc->carr_freelist = free_carrp;
2111 sc->carr_pending_cnt--;
2112
2113 /*
2114 * Clear request microcode control flag.
2115 */
2116 scsiq->cntl = 0;
2117
2118 /*
2119 * Check Condition handling
2120 */
2121 /*
2122 * If the command that completed was a SCSI INQUIRY and
2123 * LUN 0 was sent the command, then process the INQUIRY
2124 * command information for the device.
2125 */
2126 if (scsiq->done_status == QD_NO_ERROR &&
2127 scsiq->cdb[0] == INQUIRY &&
2128 scsiq->target_lun == 0) {
2129 AdwInquiryHandling(sc, scsiq);
2130 }
2131
2132 /*
2133 * Notify the driver of the completed request by passing
2134 * the ADW_SCSI_REQ_Q pointer to its callback function.
2135 */
2136 (*(ADW_ISR_CALLBACK)sc->isr_callback)(sc, scsiq);
2137 /*
2138 * Note: After the driver callback function is called, 'scsiq'
2139 * can no longer be referenced.
2140 *
2141 * Fall through and continue processing other completed
2142 * requests...
2143 */
2144 }
2145
2146 splx(s);
2147
2148 return ADW_TRUE;
2149 }
2150
2151
2152 /*
2153 * Send an idle command to the chip and wait for completion.
2154 *
2155 * Command completion is polled for once per microsecond.
2156 *
2157 * The function can be called from anywhere including an interrupt handler.
2158 * But the function is not re-entrant, so it uses the splbio/splx()
2159 * functions to prevent reentrancy.
2160 *
2161 * Return Values:
2162 * ADW_TRUE - command completed successfully
2163 * ADW_FALSE - command failed
2164 * ADW_ERROR - command timed out
2165 */
2166 int
2167 AdwSendIdleCmd(sc, idle_cmd, idle_cmd_parameter)
2168 ADW_SOFTC *sc;
2169 u_int16_t idle_cmd;
2170 u_int32_t idle_cmd_parameter;
2171 {
2172 bus_space_tag_t iot = sc->sc_iot;
2173 bus_space_handle_t ioh = sc->sc_ioh;
2174 u_int16_t result;
2175 u_int32_t i, j, s;
2176
2177 s = splbio();
2178
2179 /*
2180 * Clear the idle command status which is set by the microcode
2181 * to a non-zero value to indicate when the command is completed.
2182 */
2183 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0);
2184
2185 /*
2186 * Write the idle command value after the idle command parameter
2187 * has been written to avoid a race condition. If the order is not
2188 * followed, the microcode may process the idle command before the
2189 * parameters have been written to LRAM.
2190 */
2191 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER,
2192 idle_cmd_parameter);
2193 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd);
2194
2195 /*
2196 * Tickle the RISC to tell it to process the idle command.
2197 */
2198 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B);
2199 if (sc->chip_type == ADW_CHIP_ASC3550) {
2200 /*
2201 * Clear the tickle value. In the ASC-3550 the RISC flag
2202 * command 'clr_tickle_b' does not work unless the host
2203 * value is cleared.
2204 */
2205 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP);
2206 }
2207
2208 /* Wait for up to 100 millisecond for the idle command to timeout. */
2209 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
2210 /* Poll once each microsecond for command completion. */
2211 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
2212 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS,
2213 result);
2214 if (result != 0) {
2215 splx(s);
2216 return result;
2217 }
2218 AdwDelayMicroSecond(1);
2219 }
2220 }
2221
2222 splx(s);
2223 return ADW_ERROR;
2224 }
2225
2226
2227 /*
2228 * Inquiry Information Byte 7 Handling
2229 *
2230 * Handle SCSI Inquiry Command information for a device by setting
2231 * microcode operating variables that affect WDTR, SDTR, and Tag
2232 * Queuing.
2233 */
2234 static void
2235 AdwInquiryHandling(sc, scsiq)
2236 ADW_SOFTC *sc;
2237 ADW_SCSI_REQ_Q *scsiq;
2238 {
2239 #ifndef FAILSAFE
2240 bus_space_tag_t iot = sc->sc_iot;
2241 bus_space_handle_t ioh = sc->sc_ioh;
2242 u_int8_t tid;
2243 struct scsipi_inquiry_data *inq;
2244 u_int16_t tidmask;
2245 u_int16_t cfg_word;
2246
2247
2248 /*
2249 * AdwInquiryHandling() requires up to INQUIRY information Byte 7
2250 * to be available.
2251 *
2252 * If less than 8 bytes of INQUIRY information were requested or less
2253 * than 8 bytes were transferred, then return. cdb[4] is the request
2254 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the
2255 * microcode to the transfer residual count.
2256 */
2257
2258 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) {
2259 return;
2260 }
2261
2262 tid = scsiq->target_id;
2263
2264 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr;
2265
2266 /*
2267 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
2268 */
2269 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ &&
2270 ((inq->version & SID_ANSII) < 2)) {
2271 return;
2272 } else {
2273 /*
2274 * INQUIRY Byte 7 Handling
2275 *
2276 * Use a device's INQUIRY byte 7 to determine whether it
2277 * supports WDTR, SDTR, and Tag Queuing. If the feature
2278 * is enabled in the EEPROM and the device supports the
2279 * feature, then enable it in the microcode.
2280 */
2281
2282 tidmask = ADW_TID_TO_TIDMASK(tid);
2283
2284 /*
2285 * Wide Transfers
2286 *
2287 * If the EEPROM enabled WDTR for the device and the device
2288 * supports wide bus (16 bit) transfers, then turn on the
2289 * device's 'wdtr_able' bit and write the new value to the
2290 * microcode.
2291 */
2292 #ifdef SCSI_ADW_WDTR_DISABLE
2293 if(!(tidmask & SCSI_ADW_WDTR_DISABLE))
2294 #endif /* SCSI_ADW_WDTR_DISABLE */
2295 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) {
2296 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2297 cfg_word);
2298 if ((cfg_word & tidmask) == 0) {
2299 cfg_word |= tidmask;
2300 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE,
2301 cfg_word);
2302
2303 /*
2304 * Clear the microcode "SDTR negotiation" and
2305 * "WDTR negotiation" done indicators for the
2306 * target to cause it to negotiate with the new
2307 * setting set above.
2308 * WDTR when accepted causes the target to enter
2309 * asynchronous mode, so SDTR must be negotiated
2310 */
2311 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2312 cfg_word);
2313 cfg_word &= ~tidmask;
2314 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2315 cfg_word);
2316 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2317 cfg_word);
2318 cfg_word &= ~tidmask;
2319 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE,
2320 cfg_word);
2321 }
2322 }
2323
2324 /*
2325 * Synchronous Transfers
2326 *
2327 * If the EEPROM enabled SDTR for the device and the device
2328 * supports synchronous transfers, then turn on the device's
2329 * 'sdtr_able' bit. Write the new value to the microcode.
2330 */
2331 #ifdef SCSI_ADW_SDTR_DISABLE
2332 if(!(tidmask & SCSI_ADW_SDTR_DISABLE))
2333 #endif /* SCSI_ADW_SDTR_DISABLE */
2334 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) {
2335 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word);
2336 if ((cfg_word & tidmask) == 0) {
2337 cfg_word |= tidmask;
2338 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,
2339 cfg_word);
2340
2341 /*
2342 * Clear the microcode "SDTR negotiation"
2343 * done indicator for the target to cause it
2344 * to negotiate with the new setting set above.
2345 */
2346 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2347 cfg_word);
2348 cfg_word &= ~tidmask;
2349 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE,
2350 cfg_word);
2351 }
2352 }
2353 /*
2354 * If the Inquiry data included enough space for the SPI-3
2355 * Clocking field, then check if DT mode is supported.
2356 */
2357 if (sc->chip_type == ADW_CHIP_ASC38C1600 &&
2358 (scsiq->cdb[4] >= 57 ||
2359 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) {
2360 /*
2361 * PPR (Parallel Protocol Request) Capable
2362 *
2363 * If the device supports DT mode, then it must be
2364 * PPR capable.
2365 * The PPR message will be used in place of the SDTR
2366 * and WDTR messages to negotiate synchronous speed
2367 * and offset, transfer width, and protocol options.
2368 */
2369 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){
2370 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2371 sc->ppr_able);
2372 sc->ppr_able |= tidmask;
2373 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE,
2374 sc->ppr_able);
2375 }
2376 }
2377
2378 /*
2379 * If the EEPROM enabled Tag Queuing for the device and the
2380 * device supports Tag Queueing, then turn on the device's
2381 * 'tagqng_enable' bit in the microcode and set the microcode
2382 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
2383 * value.
2384 *
2385 * Tag Queuing is disabled for the BIOS which runs in polled
2386 * mode and would see no benefit from Tag Queuing. Also by
2387 * disabling Tag Queuing in the BIOS devices with Tag Queuing
2388 * bugs will at least work with the BIOS.
2389 */
2390 #ifdef SCSI_ADW_TAGQ_DISABLE
2391 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE))
2392 #endif /* SCSI_ADW_TAGQ_DISABLE */
2393 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) {
2394 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2395 cfg_word);
2396 cfg_word |= tidmask;
2397 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE,
2398 cfg_word);
2399
2400 ADW_WRITE_BYTE_LRAM(iot, ioh,
2401 ADW_MC_NUMBER_OF_MAX_CMD + tid,
2402 sc->max_dvc_qng);
2403 }
2404 }
2405 #endif /* FAILSAFE */
2406 }
2407
2408
2409 static void
2410 AdwSleepMilliSecond(n)
2411 u_int32_t n;
2412 {
2413
2414 DELAY(n * 1000);
2415 }
2416
2417
2418 static void
2419 AdwDelayMicroSecond(n)
2420 u_int32_t n;
2421 {
2422
2423 DELAY(n);
2424 }
2425
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