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sys/dev/ic/adwlib.c
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1 /* $NetBSD: adwlib.c,v 1.45 2022/09/25 18:43:32 thorpej Exp $ */ 2 3 /* 4 * Low level routines for the Advanced Systems Inc. SCSI controllers chips 5 * 6 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * Author: Baldassare Dante Profeta <dante@mclink.it> 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from: 34 */ 35 /* 36 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 37 * 38 * Copyright (c) 1995-2000 Advanced System Products, Inc. 39 * All Rights Reserved. 40 * 41 * Redistribution and use in source and binary forms, with or without 42 * modification, are permitted provided that redistributions of source 43 * code retain the above copyright notice and this comment without 44 * modification. 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: adwlib.c,v 1.45 2022/09/25 18:43:32 thorpej Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/queue.h> 54 #include <sys/device.h> 55 56 #include <sys/bus.h> 57 #include <sys/intr.h> 58 59 #include <dev/scsipi/scsi_all.h> 60 #include <dev/scsipi/scsipi_all.h> 61 #include <dev/scsipi/scsiconf.h> 62 63 #include <dev/pci/pcidevs.h> 64 65 #include <dev/ic/adwlib.h> 66 #include <dev/ic/adwmcode.h> 67 #include <dev/ic/adw.h> 68 69 70 /* Static Functions */ 71 72 int AdwRamSelfTest(bus_space_tag_t, bus_space_handle_t, u_int8_t); 73 int AdwLoadMCode(bus_space_tag_t, bus_space_handle_t, u_int16_t *, u_int8_t); 74 int AdwASC3550Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 75 int AdwASC38C0800Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 76 int AdwASC38C1600Cabling(bus_space_tag_t, bus_space_handle_t, ADW_DVC_CFG *); 77 78 static u_int16_t AdwGetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 79 ADW_EEPROM *); 80 static void AdwSetEEPROMConfig(bus_space_tag_t, bus_space_handle_t, 81 ADW_EEPROM *); 82 static u_int16_t AdwReadEEPWord(bus_space_tag_t, bus_space_handle_t, int); 83 static void AdwWaitEEPCmd(bus_space_tag_t, bus_space_handle_t); 84 85 static void AdwInquiryHandling(ADW_SOFTC *, ADW_SCSI_REQ_Q *); 86 87 static void AdwSleepMilliSecond(u_int32_t); 88 static void AdwDelayMicroSecond(u_int32_t); 89 90 91 /* 92 * EEPROM Configuration. 93 * 94 * All drivers should use this structure to set the default EEPROM 95 * configuration. The BIOS now uses this structure when it is built. 96 * Additional structure information can be found in adwlib.h where 97 * the structure is defined. 98 */ 99 static const ADW_EEPROM adw_3550_Default_EEPROM = { 100 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 101 0x0000, /* 01 cfg_msw */ 102 0xFFFF, /* 02 disc_enable */ 103 0xFFFF, /* 03 wdtr_able */ 104 { 0xFFFF }, /* 04 sdtr_able */ 105 0xFFFF, /* 05 start_motor */ 106 0xFFFF, /* 06 tagqng_able */ 107 0xFFFF, /* 07 bios_scan */ 108 0, /* 08 scam_tolerant */ 109 7, /* 09 adapter_scsi_id */ 110 0, /* bios_boot_delay */ 111 3, /* 10 scsi_reset_delay */ 112 0, /* bios_id_lun */ 113 0, /* 11 termination */ 114 0, /* reserved1 */ 115 0xFFE7, /* 12 bios_ctrl */ 116 { 0xFFFF }, /* 13 ultra_able */ 117 { 0 }, /* 14 reserved2 */ 118 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 119 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 120 0, /* 16 dvc_cntl */ 121 { 0 }, /* 17 bug_fix */ 122 { 0,0,0 }, /* 18-20 serial_number[3] */ 123 0, /* 21 check_sum */ 124 { /* 22-29 oem_name[16] */ 125 0,0,0,0,0,0,0,0, 126 0,0,0,0,0,0,0,0 127 }, 128 0, /* 30 dvc_err_code */ 129 0, /* 31 adv_err_code */ 130 0, /* 32 adv_err_addr */ 131 0, /* 33 saved_dvc_err_code */ 132 0, /* 34 saved_adv_err_code */ 133 0, /* 35 saved_adv_err_addr */ 134 { /* 36-55 reserved1[16] */ 135 0,0,0,0,0,0,0,0,0,0, 136 0,0,0,0,0,0,0,0,0,0 137 }, 138 0, /* 56 cisptr_lsw */ 139 0, /* 57 cisprt_msw */ 140 0, /* 58 subsysvid */ 141 0, /* 59 subsysid */ 142 { 0,0,0,0 } /* 60-63 reserved2[4] */ 143 }; 144 145 static const ADW_EEPROM adw_38C0800_Default_EEPROM = { 146 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 147 0x0000, /* 01 cfg_msw */ 148 0xFFFF, /* 02 disc_enable */ 149 0xFFFF, /* 03 wdtr_able */ 150 { 0x4444 }, /* 04 sdtr_speed1 */ 151 0xFFFF, /* 05 start_motor */ 152 0xFFFF, /* 06 tagqng_able */ 153 0xFFFF, /* 07 bios_scan */ 154 0, /* 08 scam_tolerant */ 155 7, /* 09 adapter_scsi_id */ 156 0, /* bios_boot_delay */ 157 3, /* 10 scsi_reset_delay */ 158 0, /* bios_id_lun */ 159 0, /* 11 termination_se */ 160 0, /* termination_lvd */ 161 0xFFE7, /* 12 bios_ctrl */ 162 { 0x4444 }, /* 13 sdtr_speed2 */ 163 { 0x4444 }, /* 14 sdtr_speed3 */ 164 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 165 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 166 0, /* 16 dvc_cntl */ 167 { 0x4444 }, /* 17 sdtr_speed4 */ 168 { 0,0,0 }, /* 18-20 serial_number[3] */ 169 0, /* 21 check_sum */ 170 { /* 22-29 oem_name[16] */ 171 0,0,0,0,0,0,0,0, 172 0,0,0,0,0,0,0,0 173 }, 174 0, /* 30 dvc_err_code */ 175 0, /* 31 adv_err_code */ 176 0, /* 32 adv_err_addr */ 177 0, /* 33 saved_dvc_err_code */ 178 0, /* 34 saved_adv_err_code */ 179 0, /* 35 saved_adv_err_addr */ 180 { /* 36-55 reserved1[16] */ 181 0,0,0,0,0,0,0,0,0,0, 182 0,0,0,0,0,0,0,0,0,0 183 }, 184 0, /* 56 cisptr_lsw */ 185 0, /* 57 cisprt_msw */ 186 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 187 PCI_PRODUCT_ADVSYS_U2W, /* 59 subsysid */ 188 { 0,0,0,0 } /* 60-63 reserved2[4] */ 189 }; 190 191 static const ADW_EEPROM adw_38C1600_Default_EEPROM = { 192 ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 193 0x0000, /* 01 cfg_msw */ 194 0xFFFF, /* 02 disc_enable */ 195 0xFFFF, /* 03 wdtr_able */ 196 { 0x5555 }, /* 04 sdtr_speed1 */ 197 0xFFFF, /* 05 start_motor */ 198 0xFFFF, /* 06 tagqng_able */ 199 0xFFFF, /* 07 bios_scan */ 200 0, /* 08 scam_tolerant */ 201 7, /* 09 adapter_scsi_id */ 202 0, /* bios_boot_delay */ 203 3, /* 10 scsi_reset_delay */ 204 0, /* bios_id_lun */ 205 0, /* 11 termination_se */ 206 0, /* termination_lvd */ 207 0xFFE7, /* 12 bios_ctrl */ 208 { 0x5555 }, /* 13 sdtr_speed2 */ 209 { 0x5555 }, /* 14 sdtr_speed3 */ 210 ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 211 ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 212 0, /* 16 dvc_cntl */ 213 { 0x5555 }, /* 17 sdtr_speed4 */ 214 { 0,0,0 }, /* 18-20 serial_number[3] */ 215 0, /* 21 check_sum */ 216 { /* 22-29 oem_name[16] */ 217 0,0,0,0,0,0,0,0, 218 0,0,0,0,0,0,0,0 219 }, 220 0, /* 30 dvc_err_code */ 221 0, /* 31 adv_err_code */ 222 0, /* 32 adv_err_addr */ 223 0, /* 33 saved_dvc_err_code */ 224 0, /* 34 saved_adv_err_code */ 225 0, /* 35 saved_adv_err_addr */ 226 { /* 36-55 reserved1[16] */ 227 0,0,0,0,0,0,0,0,0,0, 228 0,0,0,0,0,0,0,0,0,0 229 }, 230 0, /* 56 cisptr_lsw */ 231 0, /* 57 cisprt_msw */ 232 PCI_VENDOR_ADVSYS, /* 58 subsysvid */ 233 PCI_PRODUCT_ADVSYS_U3W, /* 59 subsysid */ 234 { 0,0,0,0 } /* 60-63 reserved2[4] */ 235 }; 236 237 238 /* 239 * Read the board's EEPROM configuration. Set fields in ADW_SOFTC and 240 * ADW_DVC_CFG based on the EEPROM settings. The chip is stopped while 241 * all of this is done. 242 * 243 * For a non-fatal error return a warning code. If there are no warnings 244 * then 0 is returned. 245 * 246 * Note: Chip is stopped on entry. 247 */ 248 int 249 AdwInitFromEEPROM(ADW_SOFTC *sc) 250 { 251 bus_space_tag_t iot = sc->sc_iot; 252 bus_space_handle_t ioh = sc->sc_ioh; 253 ADW_EEPROM eep_config; 254 u_int16_t warn_code; 255 u_int16_t sdtr_speed = 0; 256 u_int8_t tid, termination; 257 int i, j; 258 259 260 warn_code = 0; 261 262 /* 263 * Read the board's EEPROM configuration. 264 * 265 * Set default values if a bad checksum is found. 266 * 267 * XXX - Don't handle big-endian access to EEPROM yet. 268 */ 269 if (AdwGetEEPROMConfig(iot, ioh, &eep_config) != eep_config.check_sum) { 270 warn_code |= ADW_WARN_EEPROM_CHKSUM; 271 272 /* 273 * Set EEPROM default values. 274 */ 275 switch(sc->chip_type) { 276 case ADW_CHIP_ASC3550: 277 eep_config = adw_3550_Default_EEPROM; 278 break; 279 case ADW_CHIP_ASC38C0800: 280 eep_config = adw_38C0800_Default_EEPROM; 281 break; 282 case ADW_CHIP_ASC38C1600: 283 eep_config = adw_38C1600_Default_EEPROM; 284 285 #if 0 286 XXX TODO!!! if (ASC_PCI_ID2FUNC(sc->cfg.pci_slot_info) != 0) { 287 #endif 288 if (sc->cfg.pci_slot_info != 0) { 289 u_int8_t lsw_msb; 290 291 lsw_msb = eep_config.cfg_lsw >> 8; 292 /* 293 * Set Function 1 EEPROM Word 0 MSB 294 * 295 * Clear the BIOS_ENABLE (bit 14) and 296 * INTAB (bit 11) EEPROM bits. 297 * 298 * Disable Bit 14 (BIOS_ENABLE) to fix 299 * SPARC Ultra 60 and old Mac system booting 300 * problem. The Expansion ROM must 301 * be disabled in Function 1 for these systems. 302 */ 303 lsw_msb &= ~(((ADW_EEPROM_BIOS_ENABLE | 304 ADW_EEPROM_INTAB) >> 8) & 0xFF); 305 /* 306 * Set the INTAB (bit 11) if the GPIO 0 input 307 * indicates the Function 1 interrupt line is 308 * wired to INTA. 309 * 310 * Set/Clear Bit 11 (INTAB) from 311 * the GPIO bit 0 input: 312 * 1 - Function 1 intr line wired to INT A. 313 * 0 - Function 1 intr line wired to INT B. 314 * 315 * Note: Adapter boards always have Function 0 316 * wired to INTA. 317 * Put all 5 GPIO bits in input mode and then 318 * read their input values. 319 */ 320 ADW_WRITE_BYTE_REGISTER(iot, ioh, 321 IOPB_GPIO_CNTL, 0); 322 if (ADW_READ_BYTE_REGISTER(iot, ioh, 323 IOPB_GPIO_DATA) & 0x01) { 324 /* 325 * Function 1 interrupt wired to INTA; 326 * Set EEPROM bit. 327 */ 328 lsw_msb |= (ADW_EEPROM_INTAB >> 8) 329 & 0xFF; 330 } 331 eep_config.cfg_lsw &= 0x00FF; 332 eep_config.cfg_lsw |= lsw_msb << 8; 333 } 334 break; 335 } 336 337 /* 338 * Assume the 6 byte board serial number that was read 339 * from EEPROM is correct even if the EEPROM checksum 340 * failed. 341 */ 342 for (i=2, j=1; i>=0; i--, j++) { 343 eep_config.serial_number[i] = 344 AdwReadEEPWord(iot, ioh, ASC_EEP_DVC_CFG_END - j); 345 } 346 347 AdwSetEEPROMConfig(iot, ioh, &eep_config); 348 } 349 /* 350 * Set sc and sc->cfg variables from the EEPROM configuration 351 * that was read. 352 * 353 * This is the mapping of EEPROM fields to Adw Library fields. 354 */ 355 sc->wdtr_able = eep_config.wdtr_able; 356 if (sc->chip_type == ADW_CHIP_ASC3550) { 357 sc->sdtr_able = eep_config.sdtr1.sdtr_able; 358 sc->ultra_able = eep_config.sdtr2.ultra_able; 359 } else { 360 sc->sdtr_speed1 = eep_config.sdtr1.sdtr_speed1; 361 sc->sdtr_speed2 = eep_config.sdtr2.sdtr_speed2; 362 sc->sdtr_speed3 = eep_config.sdtr3.sdtr_speed3; 363 sc->sdtr_speed4 = eep_config.sdtr4.sdtr_speed4; 364 } 365 sc->ppr_able = 0; 366 sc->tagqng_able = eep_config.tagqng_able; 367 sc->cfg.disc_enable = eep_config.disc_enable; 368 sc->max_host_qng = eep_config.max_host_qng; 369 sc->max_dvc_qng = eep_config.max_dvc_qng; 370 sc->chip_scsi_id = (eep_config.adapter_scsi_id & ADW_MAX_TID); 371 sc->start_motor = eep_config.start_motor; 372 sc->scsi_reset_wait = eep_config.scsi_reset_delay; 373 sc->bios_ctrl = eep_config.bios_ctrl; 374 sc->no_scam = eep_config.scam_tolerant; 375 sc->cfg.serial1 = eep_config.serial_number[0]; 376 sc->cfg.serial2 = eep_config.serial_number[1]; 377 sc->cfg.serial3 = eep_config.serial_number[2]; 378 379 if (sc->chip_type == ADW_CHIP_ASC38C0800 || 380 sc->chip_type == ADW_CHIP_ASC38C1600) { 381 sc->sdtr_able = 0; 382 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 383 if (tid == 0) { 384 sdtr_speed = sc->sdtr_speed1; 385 } else if (tid == 4) { 386 sdtr_speed = sc->sdtr_speed2; 387 } else if (tid == 8) { 388 sdtr_speed = sc->sdtr_speed3; 389 } else if (tid == 12) { 390 sdtr_speed = sc->sdtr_speed4; 391 } 392 if (sdtr_speed & ADW_MAX_TID) { 393 sc->sdtr_able |= (1 << tid); 394 } 395 sdtr_speed >>= 4; 396 } 397 } 398 399 /* 400 * Set the host maximum queuing (max. 253, min. 16) and the per device 401 * maximum queuing (max. 63, min. 4). 402 */ 403 if (eep_config.max_host_qng > ADW_DEF_MAX_HOST_QNG) { 404 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 405 } else if (eep_config.max_host_qng < ADW_DEF_MIN_HOST_QNG) 406 { 407 /* If the value is zero, assume it is uninitialized. */ 408 if (eep_config.max_host_qng == 0) { 409 eep_config.max_host_qng = ADW_DEF_MAX_HOST_QNG; 410 } else { 411 eep_config.max_host_qng = ADW_DEF_MIN_HOST_QNG; 412 } 413 } 414 415 if (eep_config.max_dvc_qng > ADW_DEF_MAX_DVC_QNG) { 416 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 417 } else if (eep_config.max_dvc_qng < ADW_DEF_MIN_DVC_QNG) { 418 /* If the value is zero, assume it is uninitialized. */ 419 if (eep_config.max_dvc_qng == 0) { 420 eep_config.max_dvc_qng = ADW_DEF_MAX_DVC_QNG; 421 } else { 422 eep_config.max_dvc_qng = ADW_DEF_MIN_DVC_QNG; 423 } 424 } 425 426 /* 427 * If 'max_dvc_qng' is greater than 'max_host_qng', then 428 * set 'max_dvc_qng' to 'max_host_qng'. 429 */ 430 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 431 eep_config.max_dvc_qng = eep_config.max_host_qng; 432 } 433 434 /* 435 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 436 * values based on possibly adjusted EEPROM values. 437 */ 438 sc->max_host_qng = eep_config.max_host_qng; 439 sc->max_dvc_qng = eep_config.max_dvc_qng; 440 441 442 /* 443 * If the EEPROM 'termination' field is set to automatic (0), then set 444 * the ADV_DVC_CFG 'termination' field to automatic also. 445 * 446 * If the termination is specified with a non-zero 'termination' 447 * value check that a legal value is set and set the ADV_DVC_CFG 448 * 'termination' field appropriately. 449 */ 450 451 switch(sc->chip_type) { 452 case ADW_CHIP_ASC3550: 453 sc->cfg.termination = 0; /* auto termination */ 454 switch(eep_config.termination_se) { 455 case 3: 456 /* Enable manual control with low on / high on. */ 457 sc->cfg.termination |= ADW_TERM_CTL_L; 458 /* FALLTHROUGH */ 459 case 2: 460 /* Enable manual control with low off / high on. */ 461 sc->cfg.termination |= ADW_TERM_CTL_H; 462 /* FALLTHROUGH */ 463 case 1: 464 /* Enable manual control with low off / high off. */ 465 sc->cfg.termination |= ADW_TERM_CTL_SEL; 466 /* FALLTHROUGH */ 467 case 0: 468 break; 469 default: 470 warn_code |= ADW_WARN_EEPROM_TERMINATION; 471 } 472 break; 473 474 case ADW_CHIP_ASC38C0800: 475 case ADW_CHIP_ASC38C1600: 476 switch(eep_config.termination_se) { 477 case 0: 478 /* auto termination for SE */ 479 termination = 0; 480 break; 481 case 1: 482 /* Enable manual control with low off / high off. */ 483 termination = 0; 484 break; 485 case 2: 486 /* Enable manual control with low off / high on. */ 487 termination = ADW_TERM_SE_HI; 488 break; 489 case 3: 490 /* Enable manual control with low on / high on. */ 491 termination = ADW_TERM_SE; 492 break; 493 default: 494 /* 495 * The EEPROM 'termination_se' field contains a 496 * bad value. Use automatic termination instead. 497 */ 498 termination = 0; 499 warn_code |= ADW_WARN_EEPROM_TERMINATION; 500 } 501 502 switch(eep_config.termination_lvd) { 503 case 0: 504 /* auto termination for LVD */ 505 sc->cfg.termination = termination; 506 break; 507 case 1: 508 /* Enable manual control with low off / high off. */ 509 sc->cfg.termination = termination; 510 break; 511 case 2: 512 /* Enable manual control with low off / high on. */ 513 sc->cfg.termination = termination | ADW_TERM_LVD_HI; 514 break; 515 case 3: 516 /* Enable manual control with low on / high on. */ 517 sc->cfg.termination = termination | ADW_TERM_LVD; 518 break; 519 default: 520 /* 521 * The EEPROM 'termination_lvd' field contains a 522 * bad value. Use automatic termination instead. 523 */ 524 sc->cfg.termination = termination; 525 warn_code |= ADW_WARN_EEPROM_TERMINATION; 526 } 527 break; 528 } 529 530 return warn_code; 531 } 532 533 534 /* 535 * Initialize the ASC-3550/ASC-38C0800/ASC-38C1600. 536 * 537 * On failure return the error code. 538 */ 539 int 540 AdwInitDriver(ADW_SOFTC *sc) 541 { 542 bus_space_tag_t iot = sc->sc_iot; 543 bus_space_handle_t ioh = sc->sc_ioh; 544 u_int16_t error_code; 545 int word; 546 int i; 547 u_int16_t bios_mem[ADW_MC_BIOSLEN/2]; /* BIOS RISC Memory 548 0x40-0x8F. */ 549 u_int16_t wdtr_able = 0, sdtr_able, /* ppr_able, */ tagqng_able; 550 u_int8_t max_cmd[ADW_MAX_TID + 1]; 551 u_int8_t tid; 552 553 554 error_code = 0; 555 556 /* 557 * Save the RISC memory BIOS region before writing the microcode. 558 * The BIOS may already be loaded and using its RISC LRAM region 559 * so its region must be saved and restored. 560 * 561 * Note: This code makes the assumption, which is currently true, 562 * that a chip reset does not clear RISC LRAM. 563 */ 564 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 565 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM+(2*i), bios_mem[i]); 566 } 567 568 /* 569 * Save current per TID negotiated values. 570 */ 571 switch (sc->chip_type) { 572 case ADW_CHIP_ASC3550: 573 if (bios_mem[(ADW_MC_BIOS_SIGNATURE-ADW_MC_BIOSMEM)/2]==0x55AA){ 574 575 u_int16_t bios_version, major, minor; 576 577 bios_version = bios_mem[(ADW_MC_BIOS_VERSION - 578 ADW_MC_BIOSMEM) / 2]; 579 major = (bios_version >> 12) & 0xF; 580 minor = (bios_version >> 8) & 0xF; 581 if (major < 3 || (major == 3 && minor == 1)) { 582 /* 583 * BIOS 3.1 and earlier location of 584 * 'wdtr_able' variable. 585 */ 586 ADW_READ_WORD_LRAM(iot, ioh, 0x120, wdtr_able); 587 } else { 588 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 589 wdtr_able); 590 } 591 } 592 break; 593 594 case ADW_CHIP_ASC38C1600: 595 /* ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); */ 596 /* FALLTHROUGH */ 597 case ADW_CHIP_ASC38C0800: 598 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 599 break; 600 } 601 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 602 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 603 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 604 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 605 max_cmd[tid]); 606 } 607 608 /* 609 * Perform a RAM Built-In Self Test 610 */ 611 if((error_code = AdwRamSelfTest(iot, ioh, sc->chip_type))) { 612 return error_code; 613 } 614 615 /* 616 * Load the Microcode 617 */ 618 ; 619 if((error_code = AdwLoadMCode(iot, ioh, bios_mem, sc->chip_type))) { 620 return error_code; 621 } 622 623 /* 624 * Read microcode version and date. 625 */ 626 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_DATE, sc->cfg.mcode_date); 627 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_VERSION_NUM, sc->cfg.mcode_version); 628 629 /* 630 * If the PCI Configuration Command Register "Parity Error Response 631 * Control" Bit was clear (0), then set the microcode variable 632 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 633 * to ignore DMA parity errors. 634 */ 635 if (sc->cfg.control_flag & CONTROL_FLAG_IGNORE_PERR) { 636 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 637 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 638 word | CONTROL_FLAG_IGNORE_PERR); 639 } 640 641 switch (sc->chip_type) { 642 case ADW_CHIP_ASC3550: 643 /* 644 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a 645 * FIFO threshold of 128 bytes. 646 * This register is only accessible to the host. 647 */ 648 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 649 START_CTL_EMFU | READ_CMD_MRM); 650 break; 651 652 case ADW_CHIP_ASC38C0800: 653 /* 654 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 655 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 656 * cable detection and then we are able to read C_DET[3:0]. 657 * 658 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 659 * Microcode Default Value' section below. 660 */ 661 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 662 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 663 | ADW_DIS_TERM_DRV); 664 665 /* 666 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and 667 * START_CTL_TH [3:2] bits for the default FIFO threshold. 668 * 669 * Note: ASC-38C0800 FIFO threshold has been changed to 670 * 256 bytes. 671 * 672 * For DMA Errata #4 set the BC_THRESH_ENB bit. 673 */ 674 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 675 BC_THRESH_ENB | FIFO_THRESH_80B 676 | START_CTL_TH | READ_CMD_MRM); 677 break; 678 679 case ADW_CHIP_ASC38C1600: 680 /* 681 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 682 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 683 * cable detection and then we are able to read C_DET[3:0]. 684 * 685 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 686 * Microcode Default Value' section below. 687 */ 688 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1, 689 ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1) 690 | ADW_DIS_TERM_DRV); 691 692 /* 693 * If the BIOS control flag AIPP (Asynchronous Information 694 * Phase Protection) disable bit is not set, then set the 695 * firmware 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to 696 * enable AIPP checking and encoding. 697 */ 698 if ((sc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 699 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, word); 700 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CONTROL_FLAG, 701 word | CONTROL_FLAG_ENABLE_AIPP); 702 } 703 704 /* 705 * For ASC-38C1600 use DMA_CFG0 default values: 706 * FIFO_THRESH_80B [6:4], and START_CTL_TH [3:2]. 707 */ 708 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_DMA_CFG0, 709 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 710 break; 711 } 712 713 /* 714 * Microcode operating variables for WDTR, SDTR, and command tag 715 * queuing will be set in AdvInquiryHandling() based on what a 716 * device reports it is capable of in Inquiry byte 7. 717 * 718 * If SCSI Bus Resets have been disabled, then directly set 719 * SDTR and WDTR from the EEPROM configuration. This will allow 720 * the BIOS and warm boot to work without a SCSI bus hang on 721 * the Inquiry caused by host and target mismatched DTR values. 722 * Without the SCSI Bus Reset, before an Inquiry a device can't 723 * be assumed to be in Asynchronous, Narrow mode. 724 */ 725 if ((sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 726 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, sc->wdtr_able); 727 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sc->sdtr_able); 728 } 729 730 /* 731 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 732 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 733 * bitmask. These values determine the maximum SDTR speed negotiated 734 * with a device. 735 * 736 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 737 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 738 * without determining here whether the device supports SDTR. 739 */ 740 switch (sc->chip_type) { 741 case ADW_CHIP_ASC3550: 742 word = 0; 743 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 744 if (ADW_TID_TO_TIDMASK(tid) & sc->ultra_able) { 745 /* Set Ultra speed for TID 'tid'. */ 746 word |= (0x3 << (4 * (tid % 4))); 747 } else { 748 /* Set Fast speed for TID 'tid'. */ 749 word |= (0x2 << (4 * (tid % 4))); 750 } 751 /* Check if done with sdtr_speed1. */ 752 if (tid == 3) { 753 ADW_WRITE_WORD_LRAM(iot, ioh, 754 ADW_MC_SDTR_SPEED1, word); 755 word = 0; 756 /* Check if done with sdtr_speed2. */ 757 } else if (tid == 7) { 758 ADW_WRITE_WORD_LRAM(iot, ioh, 759 ADW_MC_SDTR_SPEED2, word); 760 word = 0; 761 /* Check if done with sdtr_speed3. */ 762 } else if (tid == 11) { 763 ADW_WRITE_WORD_LRAM(iot, ioh, 764 ADW_MC_SDTR_SPEED3, word); 765 word = 0; 766 /* Check if done with sdtr_speed4. */ 767 } else if (tid == 15) { 768 ADW_WRITE_WORD_LRAM(iot, ioh, 769 ADW_MC_SDTR_SPEED4, word); 770 /* End of loop. */ 771 } 772 } 773 774 /* 775 * Set microcode operating variable for the 776 * disconnect per TID bitmask. 777 */ 778 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 779 sc->cfg.disc_enable); 780 break; 781 782 case ADW_CHIP_ASC38C0800: 783 /* FALLTHROUGH */ 784 case ADW_CHIP_ASC38C1600: 785 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DISC_ENABLE, 786 sc->cfg.disc_enable); 787 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED1, 788 sc->sdtr_speed1); 789 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED2, 790 sc->sdtr_speed2); 791 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED3, 792 sc->sdtr_speed3); 793 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_SPEED4, 794 sc->sdtr_speed4); 795 break; 796 } 797 798 799 /* 800 * Set SCSI_CFG0 Microcode Default Value. 801 * 802 * The microcode will set the SCSI_CFG0 register using this value 803 * after it is started below. 804 */ 805 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG0, 806 ADW_PARITY_EN | ADW_QUEUE_128 | ADW_SEL_TMO_LONG | 807 ADW_OUR_ID_EN | sc->chip_scsi_id); 808 809 810 switch(sc->chip_type) { 811 case ADW_CHIP_ASC3550: 812 error_code = AdwASC3550Cabling(iot, ioh, &sc->cfg); 813 break; 814 815 case ADW_CHIP_ASC38C0800: 816 error_code = AdwASC38C0800Cabling(iot, ioh, &sc->cfg); 817 break; 818 819 case ADW_CHIP_ASC38C1600: 820 error_code = AdwASC38C1600Cabling(iot, ioh, &sc->cfg); 821 break; 822 } 823 if(error_code) { 824 return error_code; 825 } 826 827 /* 828 * Set SEL_MASK Microcode Default Value 829 * 830 * The microcode will set the SEL_MASK register using this value 831 * after it is started below. 832 */ 833 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SEL_MASK, 834 ADW_TID_TO_TIDMASK(sc->chip_scsi_id)); 835 836 /* 837 * Create and Initialize Host->RISC Carrier lists 838 */ 839 sc->carr_freelist = AdwInitCarriers(sc->sc_dmamap_carrier, 840 sc->sc_control->carriers); 841 842 /* 843 * Set-up the Host->RISC Initiator Command Queue (ICQ). 844 */ 845 846 if ((sc->icq_sp = sc->carr_freelist) == NULL) { 847 return ADW_IERR_NO_CARRIER; 848 } 849 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 850 ASC_GET_CARRP(sc->icq_sp->next_ba)); 851 852 /* 853 * The first command issued will be placed in the stopper carrier. 854 */ 855 sc->icq_sp->next_ba = htole32(ASC_CQ_STOPPER); 856 857 /* 858 * Set RISC ICQ physical address start value. 859 */ 860 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_ICQ, le32toh(sc->icq_sp->carr_ba)); 861 862 /* 863 * Initialize the COMMA register to the same value otherwise 864 * the RISC will prematurely detect a command is available. 865 */ 866 if(sc->chip_type == ADW_CHIP_ASC38C1600) { 867 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 868 le32toh(sc->icq_sp->carr_ba)); 869 } 870 871 /* 872 * Set-up the RISC->Host Initiator Response Queue (IRQ). 873 */ 874 if ((sc->irq_sp = sc->carr_freelist) == NULL) { 875 return ADW_IERR_NO_CARRIER; 876 } 877 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 878 ASC_GET_CARRP(sc->irq_sp->next_ba)); 879 880 /* 881 * The first command completed by the RISC will be placed in 882 * the stopper. 883 * 884 * Note: Set 'next_ba' to ASC_CQ_STOPPER. When the request is 885 * completed the RISC will set the ASC_RQ_DONE bit. 886 */ 887 sc->irq_sp->next_ba = htole32(ASC_CQ_STOPPER); 888 889 /* 890 * Set RISC IRQ physical address start value. 891 */ 892 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IRQ, le32toh(sc->irq_sp->carr_ba)); 893 sc->carr_pending_cnt = 0; 894 895 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_INTR_ENABLES, 896 (ADW_INTR_ENABLE_HOST_INTR | ADW_INTR_ENABLE_GLOBAL_INTR)); 897 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, word); 898 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_PC, word); 899 900 /* finally, finally, gentlemen, start your engine */ 901 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_RUN); 902 903 /* 904 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 905 * Resets should be performed. The RISC has to be running 906 * to issue a SCSI Bus Reset. 907 */ 908 if (sc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) 909 { 910 /* 911 * If the BIOS Signature is present in memory, restore the 912 * BIOS Handshake Configuration Table and do not perform 913 * a SCSI Bus Reset. 914 */ 915 if (bios_mem[(ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM)/2] == 916 0x55AA) { 917 /* 918 * Restore per TID negotiated values. 919 */ 920 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 921 wdtr_able); 922 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 923 sdtr_able); 924 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 925 tagqng_able); 926 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 927 ADW_WRITE_BYTE_LRAM(iot, ioh, 928 ADW_MC_NUMBER_OF_MAX_CMD + tid, 929 max_cmd[tid]); 930 } 931 } else { 932 if (AdwResetCCB(sc) != ADW_TRUE) { 933 error_code = ADW_WARN_BUSRESET_ERROR; 934 } 935 } 936 } 937 938 return error_code; 939 } 940 941 942 int 943 AdwRamSelfTest(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t chip_type) 944 { 945 int i; 946 u_int8_t byte; 947 948 949 if ((chip_type == ADW_CHIP_ASC38C0800) || 950 (chip_type == ADW_CHIP_ASC38C1600)) { 951 /* 952 * RAM BIST (RAM Built-In Self Test) 953 * 954 * Address : I/O base + offset 0x38h register (byte). 955 * Function: Bit 7-6(RW) : RAM mode 956 * Normal Mode : 0x00 957 * Pre-test Mode : 0x40 958 * RAM Test Mode : 0x80 959 * Bit 5 : unused 960 * Bit 4(RO) : Done bit 961 * Bit 3-0(RO) : Status 962 * Host Error : 0x08 963 * Int_RAM Error : 0x04 964 * RISC Error : 0x02 965 * SCSI Error : 0x01 966 * No Error : 0x00 967 * 968 * Note: RAM BIST code should be put right here, before loading 969 * the microcode and after saving the RISC memory BIOS region. 970 */ 971 972 /* 973 * LRAM Pre-test 974 * 975 * Write PRE_TEST_MODE (0x40) to register and wait for 976 * 10 milliseconds. 977 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), 978 * return an error. Reset to NORMAL_MODE (0x00) and do again. 979 * If cannot reset to NORMAL_MODE, return an error too. 980 */ 981 for (i = 0; i < 2; i++) { 982 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 983 PRE_TEST_MODE); 984 /* Wait for 10ms before reading back. */ 985 AdwSleepMilliSecond(10); 986 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 987 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != 988 PRE_TEST_VALUE) { 989 return ADW_IERR_BIST_PRE_TEST; 990 } 991 992 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, 993 NORMAL_MODE); 994 /* Wait for 10ms before reading back. */ 995 AdwSleepMilliSecond(10); 996 if (ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST) 997 != NORMAL_VALUE) { 998 return ADW_IERR_BIST_PRE_TEST; 999 } 1000 } 1001 1002 /* 1003 * LRAM Test - It takes about 1.5 ms to run through the test. 1004 * 1005 * Write RAM_TEST_MODE (0x80) to register and wait for 1006 * 10 milliseconds. 1007 * If Done bit not set or Status not 0, save register byte, 1008 * set the err_code, and return an error. 1009 */ 1010 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, RAM_TEST_MODE); 1011 /* Wait for 10ms before checking status. */ 1012 AdwSleepMilliSecond(10); 1013 1014 byte = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST); 1015 if ((byte & RAM_TEST_DONE)==0 || (byte & RAM_TEST_STATUS)!=0) { 1016 /* Get here if Done bit not set or Status not 0. */ 1017 return ADW_IERR_BIST_RAM_TEST; 1018 } 1019 1020 /* We need to reset back to normal mode after LRAM test passes*/ 1021 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_RAM_BIST, NORMAL_MODE); 1022 } 1023 1024 return 0; 1025 } 1026 1027 1028 int 1029 AdwLoadMCode(bus_space_tag_t iot, bus_space_handle_t ioh, u_int16_t *bios_mem, u_int8_t chip_type) 1030 { 1031 const u_int8_t *mcode_data; 1032 u_int32_t mcode_chksum; 1033 u_int16_t mcode_size; 1034 u_int32_t sum; 1035 u_int16_t code_sum; 1036 int begin_addr; 1037 int end_addr; 1038 int word; 1039 int adw_memsize; 1040 int adw_mcode_expanded_size; 1041 int i, j; 1042 1043 1044 switch(chip_type) { 1045 case ADW_CHIP_ASC3550: 1046 mcode_data = (const u_int8_t *)adw_asc3550_mcode_data.mcode_data; 1047 mcode_chksum = (u_int32_t)adw_asc3550_mcode_data.mcode_chksum; 1048 mcode_size = (u_int16_t)adw_asc3550_mcode_data.mcode_size; 1049 adw_memsize = ADW_3550_MEMSIZE; 1050 break; 1051 1052 case ADW_CHIP_ASC38C0800: 1053 mcode_data = (const u_int8_t *)adw_asc38C0800_mcode_data.mcode_data; 1054 mcode_chksum =(u_int32_t)adw_asc38C0800_mcode_data.mcode_chksum; 1055 mcode_size = (u_int16_t)adw_asc38C0800_mcode_data.mcode_size; 1056 adw_memsize = ADW_38C0800_MEMSIZE; 1057 break; 1058 1059 case ADW_CHIP_ASC38C1600: 1060 mcode_data = (const u_int8_t *)adw_asc38C1600_mcode_data.mcode_data; 1061 mcode_chksum =(u_int32_t)adw_asc38C1600_mcode_data.mcode_chksum; 1062 mcode_size = (u_int16_t)adw_asc38C1600_mcode_data.mcode_size; 1063 adw_memsize = ADW_38C1600_MEMSIZE; 1064 break; 1065 1066 default: 1067 return (EINVAL); 1068 } 1069 1070 /* 1071 * Write the microcode image to RISC memory starting at address 0. 1072 */ 1073 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1074 1075 /* Assume the following compressed format of the microcode buffer: 1076 * 1077 * 254 word (508 byte) table indexed by byte code followed 1078 * by the following byte codes: 1079 * 1080 * 1-Byte Code: 1081 * 00: Emit word 0 in table. 1082 * 01: Emit word 1 in table. 1083 * . 1084 * FD: Emit word 253 in table. 1085 * 1086 * Multi-Byte Code: 1087 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 1088 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 1089 */ 1090 word = 0; 1091 for (i = 253 * 2; i < mcode_size; i++) { 1092 if (mcode_data[i] == 0xff) { 1093 for (j = 0; j < mcode_data[i + 1]; j++) { 1094 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1095 (((u_int16_t)mcode_data[i + 3] << 8) | 1096 mcode_data[i + 2])); 1097 word++; 1098 } 1099 i += 3; 1100 } else if (mcode_data[i] == 0xfe) { 1101 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 1102 (((u_int16_t)mcode_data[i + 2] << 8) | 1103 mcode_data[i + 1])); 1104 i += 2; 1105 word++; 1106 } else { 1107 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, (((u_int16_t) 1108 mcode_data[(mcode_data[i] * 2) + 1] <<8) | 1109 mcode_data[mcode_data[i] * 2])); 1110 word++; 1111 } 1112 } 1113 1114 /* 1115 * Set 'word' for later use to clear the rest of memory and save 1116 * the expanded mcode size. 1117 */ 1118 word *= 2; 1119 adw_mcode_expanded_size = word; 1120 1121 /* 1122 * Clear the rest of the Internal RAM. 1123 */ 1124 for (; word < adw_memsize; word += 2) { 1125 ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, 0); 1126 } 1127 1128 /* 1129 * Verify the microcode checksum. 1130 */ 1131 sum = 0; 1132 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, 0); 1133 1134 for (word = 0; word < adw_mcode_expanded_size; word += 2) { 1135 sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1136 } 1137 1138 if (sum != mcode_chksum) { 1139 return ADW_IERR_MCODE_CHKSUM; 1140 } 1141 1142 /* 1143 * Restore the RISC memory BIOS region. 1144 */ 1145 for (i = 0; i < ADW_MC_BIOSLEN/2; i++) { 1146 if(chip_type == ADW_CHIP_ASC3550) { 1147 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1148 bios_mem[i]); 1149 } else { 1150 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOSMEM + (2 * i), 1151 bios_mem[i]); 1152 } 1153 } 1154 1155 /* 1156 * Calculate and write the microcode code checksum to the microcode 1157 * code checksum location ADW_MC_CODE_CHK_SUM (0x2C). 1158 */ 1159 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_BEGIN_ADDR, begin_addr); 1160 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_CODE_END_ADDR, end_addr); 1161 code_sum = 0; 1162 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RAM_ADDR, begin_addr); 1163 for (word = begin_addr; word < end_addr; word += 2) { 1164 code_sum += ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh); 1165 } 1166 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CODE_CHK_SUM, code_sum); 1167 1168 /* 1169 * Set the chip type. 1170 */ 1171 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_CHIP_TYPE, chip_type); 1172 1173 return 0; 1174 } 1175 1176 1177 int 1178 AdwASC3550Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1179 { 1180 u_int16_t scsi_cfg1; 1181 1182 1183 /* 1184 * Determine SCSI_CFG1 Microcode Default Value. 1185 * 1186 * The microcode will set the SCSI_CFG1 register using this value 1187 * after it is started below. 1188 */ 1189 1190 /* Read current SCSI_CFG1 Register value. */ 1191 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1192 1193 /* 1194 * If all three connectors are in use in ASC3550, return an error. 1195 */ 1196 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 1197 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 1198 return ADW_IERR_ILLEGAL_CONNECTION; 1199 } 1200 1201 /* 1202 * If the cable is reversed all of the SCSI_CTRL register signals 1203 * will be set. Check for and return an error if this condition is 1204 * found. 1205 */ 1206 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1207 return ADW_IERR_REVERSED_CABLE; 1208 } 1209 1210 /* 1211 * If this is a differential board and a single-ended device 1212 * is attached to one of the connectors, return an error. 1213 */ 1214 if ((scsi_cfg1 & ADW_DIFF_MODE) && 1215 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) { 1216 return ADW_IERR_SINGLE_END_DEVICE; 1217 } 1218 1219 /* 1220 * If automatic termination control is enabled, then set the 1221 * termination value based on a table listed in a_condor.h. 1222 * 1223 * If manual termination was specified with an EEPROM setting 1224 * then 'termination' was set-up in AdwInitFromEEPROM() and 1225 * is ready to be 'ored' into SCSI_CFG1. 1226 */ 1227 if (cfg->termination == 0) { 1228 /* 1229 * The software always controls termination by setting 1230 * TERM_CTL_SEL. 1231 * If TERM_CTL_SEL were set to 0, the hardware would set 1232 * termination. 1233 */ 1234 cfg->termination |= ADW_TERM_CTL_SEL; 1235 1236 switch(scsi_cfg1 & ADW_CABLE_DETECT) { 1237 /* TERM_CTL_H: on, TERM_CTL_L: on */ 1238 case 0x3: case 0x7: case 0xB: 1239 case 0xD: case 0xE: case 0xF: 1240 cfg->termination |= 1241 (ADW_TERM_CTL_H | ADW_TERM_CTL_L); 1242 break; 1243 1244 /* TERM_CTL_H: on, TERM_CTL_L: off */ 1245 case 0x1: case 0x5: case 0x9: 1246 case 0xA: case 0xC: 1247 cfg->termination |= ADW_TERM_CTL_H; 1248 break; 1249 1250 /* TERM_CTL_H: off, TERM_CTL_L: off */ 1251 case 0x2: case 0x6: 1252 break; 1253 } 1254 } 1255 1256 /* 1257 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 1258 */ 1259 scsi_cfg1 &= ~ADW_TERM_CTL; 1260 1261 /* 1262 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 1263 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 1264 * referenced, because the hardware internally inverts 1265 * the Termination High and Low bits if TERM_POL is set. 1266 */ 1267 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL)); 1268 1269 /* 1270 * Set SCSI_CFG1 Microcode Default Value 1271 * 1272 * Set filter value and possibly modified termination control 1273 * bits in the Microcode SCSI_CFG1 Register Value. 1274 * 1275 * The microcode will set the SCSI_CFG1 register using this value 1276 * after it is started below. 1277 */ 1278 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, 1279 ADW_FLTR_DISABLE | scsi_cfg1); 1280 1281 /* 1282 * Set MEM_CFG Microcode Default Value 1283 * 1284 * The microcode will set the MEM_CFG register using this value 1285 * after it is started below. 1286 * 1287 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1288 * are defined. 1289 * 1290 * ASC-3550 has 8KB internal memory. 1291 */ 1292 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1293 ADW_BIOS_EN | ADW_RAM_SZ_8KB); 1294 1295 return 0; 1296 } 1297 1298 1299 int 1300 AdwASC38C0800Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1301 { 1302 u_int16_t scsi_cfg1; 1303 1304 1305 /* 1306 * Determine SCSI_CFG1 Microcode Default Value. 1307 * 1308 * The microcode will set the SCSI_CFG1 register using this value 1309 * after it is started below. 1310 */ 1311 1312 /* Read current SCSI_CFG1 Register value. */ 1313 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1314 1315 /* 1316 * If the cable is reversed all of the SCSI_CTRL register signals 1317 * will be set. Check for and return an error if this condition is 1318 * found. 1319 */ 1320 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1321 return ADW_IERR_REVERSED_CABLE; 1322 } 1323 1324 /* 1325 * All kind of combinations of devices attached to one of four 1326 * connectors are acceptable except HVD device attached. 1327 * For example, LVD device can be attached to SE connector while 1328 * SE device attached to LVD connector. 1329 * If LVD device attached to SE connector, it only runs up to 1330 * Ultra speed. 1331 * 1332 * If an HVD device is attached to one of LVD connectors, return 1333 * an error. 1334 * However, there is no way to detect HVD device attached to 1335 * SE connectors. 1336 */ 1337 if (scsi_cfg1 & ADW_HVD) { 1338 return ADW_IERR_HVD_DEVICE; 1339 } 1340 1341 /* 1342 * If either SE or LVD automatic termination control is enabled, then 1343 * set the termination value based on a table listed in a_condor.h. 1344 * 1345 * If manual termination was specified with an EEPROM setting then 1346 * 'termination' was set-up in AdwInitFromEEPROM() and is ready 1347 * to be 'ored' into SCSI_CFG1. 1348 */ 1349 if ((cfg->termination & ADW_TERM_SE) == 0) { 1350 /* SE automatic termination control is enabled. */ 1351 switch(scsi_cfg1 & ADW_C_DET_SE) { 1352 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1353 case 0x1: case 0x2: case 0x3: 1354 cfg->termination |= ADW_TERM_SE; 1355 break; 1356 1357 /* TERM_SE_HI: on, TERM_SE_LO: off */ 1358 case 0x0: 1359 cfg->termination |= ADW_TERM_SE_HI; 1360 break; 1361 } 1362 } 1363 1364 if ((cfg->termination & ADW_TERM_LVD) == 0) { 1365 /* LVD automatic termination control is enabled. */ 1366 switch(scsi_cfg1 & ADW_C_DET_LVD) { 1367 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 1368 case 0x4: case 0x8: case 0xC: 1369 cfg->termination |= ADW_TERM_LVD; 1370 break; 1371 1372 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 1373 case 0x0: 1374 break; 1375 } 1376 } 1377 1378 /* 1379 * Clear any set TERM_SE and TERM_LVD bits. 1380 */ 1381 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD); 1382 1383 /* 1384 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 1385 */ 1386 scsi_cfg1 |= (~cfg->termination & 0xF0); 1387 1388 /* 1389 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and 1390 * HVD/LVD/SE bits and set possibly modified termination control bits 1391 * in the Microcode SCSI_CFG1 Register Value. 1392 */ 1393 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & 1394 ~ADW_TERM_POL & ~ADW_HVD_LVD_SE); 1395 1396 /* 1397 * Set SCSI_CFG1 Microcode Default Value 1398 * 1399 * Set possibly modified termination control and reset DIS_TERM_DRV 1400 * bits in the Microcode SCSI_CFG1 Register Value. 1401 * 1402 * The microcode will set the SCSI_CFG1 register using this value 1403 * after it is started below. 1404 */ 1405 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1406 1407 /* 1408 * Set MEM_CFG Microcode Default Value 1409 * 1410 * The microcode will set the MEM_CFG register using this value 1411 * after it is started below. 1412 * 1413 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1414 * are defined. 1415 * 1416 * ASC-38C0800 has 16KB internal memory. 1417 */ 1418 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1419 ADW_BIOS_EN | ADW_RAM_SZ_16KB); 1420 1421 return 0; 1422 } 1423 1424 1425 int 1426 AdwASC38C1600Cabling(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_DVC_CFG *cfg) 1427 { 1428 u_int16_t scsi_cfg1; 1429 1430 1431 /* 1432 * Determine SCSI_CFG1 Microcode Default Value. 1433 * 1434 * The microcode will set the SCSI_CFG1 register using this value 1435 * after it is started below. 1436 * Each ASC-38C1600 function has only two cable detect bits. 1437 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 1438 */ 1439 1440 /* Read current SCSI_CFG1 Register value. */ 1441 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1); 1442 1443 /* 1444 * If the cable is reversed all of the SCSI_CTRL register signals 1445 * will be set. Check for and return an error if this condition is 1446 * found. 1447 */ 1448 if ((ADW_READ_WORD_REGISTER(iot,ioh, IOPW_SCSI_CTRL) & 0x3F07)==0x3F07){ 1449 return ADW_IERR_REVERSED_CABLE; 1450 } 1451 1452 /* 1453 * Each ASC-38C1600 function has two connectors. Only an HVD device 1454 * cannot be connected to either connector. An LVD device or SE device 1455 * may be connected to either connector. If an SE device is connected, 1456 * then at most Ultra speed (20 MHz) can be used on both connectors. 1457 * 1458 * If an HVD device is attached, return an error. 1459 */ 1460 if (scsi_cfg1 & ADW_HVD) { 1461 return ADW_IERR_HVD_DEVICE; 1462 } 1463 1464 /* 1465 * Each function in the ASC-38C1600 uses only the SE cable detect and 1466 * termination because there are two connectors for each function. 1467 * Each function may use either LVD or SE mode. 1468 * Corresponding the SE automatic termination control EEPROM bits are 1469 * used for each function. 1470 * Each function has its own EEPROM. If SE automatic control is enabled 1471 * for the function, then set the termination value based on a table 1472 * listed in adwlib.h. 1473 * 1474 * If manual termination is specified in the EEPROM for the function, 1475 * then 'termination' was set-up in AdwInitFromEEPROM() and is 1476 * ready to be 'ored' into SCSI_CFG1. 1477 */ 1478 if ((cfg->termination & ADW_TERM_SE) == 0) { 1479 /* SE automatic termination control is enabled. */ 1480 switch(scsi_cfg1 & ADW_C_DET_SE) { 1481 /* TERM_SE_HI: on, TERM_SE_LO: on */ 1482 case 0x1: case 0x2: case 0x3: 1483 cfg->termination |= ADW_TERM_SE; 1484 break; 1485 1486 case 0x0: 1487 #if 0 1488 /* !!!!TODO!!!! */ 1489 if (ASC_PCI_ID2FUNC(cfg->pci_slot_info) == 0) { 1490 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 1491 } 1492 else 1493 #endif 1494 { 1495 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 1496 cfg->termination |= ADW_TERM_SE_HI; 1497 } 1498 break; 1499 } 1500 } 1501 1502 /* 1503 * Clear any set TERM_SE bits. 1504 */ 1505 scsi_cfg1 &= ~ADW_TERM_SE; 1506 1507 /* 1508 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 1509 */ 1510 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE); 1511 1512 /* 1513 * Clear Big Endian and Terminator Polarity bits and set possibly 1514 * modified termination control bits in the Microcode SCSI_CFG1 1515 * Register Value. 1516 */ 1517 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL); 1518 1519 /* 1520 * Set SCSI_CFG1 Microcode Default Value 1521 * 1522 * Set possibly modified termination control bits in the Microcode 1523 * SCSI_CFG1 Register Value. 1524 * 1525 * The microcode will set the SCSI_CFG1 register using this value 1526 * after it is started below. 1527 */ 1528 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 1529 1530 /* 1531 * Set MEM_CFG Microcode Default Value 1532 * 1533 * The microcode will set the MEM_CFG register using this value 1534 * after it is started below. 1535 * 1536 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 1537 * are defined. 1538 * 1539 * ASC-38C1600 has 32KB internal memory. 1540 */ 1541 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_MEM_CFG, 1542 ADW_BIOS_EN | ADW_RAM_SZ_32KB); 1543 1544 return 0; 1545 } 1546 1547 1548 /* 1549 * Read EEPROM configuration into the specified buffer. 1550 * 1551 * Return a checksum based on the EEPROM configuration read. 1552 */ 1553 static u_int16_t 1554 AdwGetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1555 { 1556 u_int16_t wval, chksum; 1557 u_int16_t *wbuf; 1558 int eep_addr; 1559 1560 1561 wbuf = (u_int16_t *) cfg_buf; 1562 chksum = 0; 1563 1564 for (eep_addr = ASC_EEP_DVC_CFG_BEGIN; 1565 eep_addr < ASC_EEP_DVC_CFG_END; 1566 eep_addr++, wbuf++) { 1567 wval = AdwReadEEPWord(iot, ioh, eep_addr); 1568 chksum += wval; 1569 *wbuf = wval; 1570 } 1571 1572 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1573 wbuf++; 1574 for (eep_addr = ASC_EEP_DVC_CTL_BEGIN; 1575 eep_addr < ASC_EEP_MAX_WORD_ADDR; 1576 eep_addr++, wbuf++) { 1577 *wbuf = AdwReadEEPWord(iot, ioh, eep_addr); 1578 } 1579 1580 return chksum; 1581 } 1582 1583 1584 /* 1585 * Read the EEPROM from specified location 1586 */ 1587 static u_int16_t 1588 AdwReadEEPWord(bus_space_tag_t iot, bus_space_handle_t ioh, int eep_word_addr) 1589 { 1590 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1591 ASC_EEP_CMD_READ | eep_word_addr); 1592 AdwWaitEEPCmd(iot, ioh); 1593 1594 return ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_DATA); 1595 } 1596 1597 1598 /* 1599 * Wait for EEPROM command to complete 1600 */ 1601 static void 1602 AdwWaitEEPCmd(bus_space_tag_t iot, bus_space_handle_t ioh) 1603 { 1604 int eep_delay_ms; 1605 1606 1607 for (eep_delay_ms = 0; eep_delay_ms < ASC_EEP_DELAY_MS; eep_delay_ms++){ 1608 if (ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD) & 1609 ASC_EEP_CMD_DONE) { 1610 break; 1611 } 1612 AdwSleepMilliSecond(1); 1613 } 1614 1615 (void)ADW_READ_WORD_REGISTER(iot, ioh, IOPW_EE_CMD); 1616 } 1617 1618 1619 /* 1620 * Write the EEPROM from 'cfg_buf'. 1621 */ 1622 static void 1623 AdwSetEEPROMConfig(bus_space_tag_t iot, bus_space_handle_t ioh, ADW_EEPROM *cfg_buf) 1624 { 1625 u_int16_t *wbuf; 1626 u_int16_t addr, chksum; 1627 1628 1629 wbuf = (u_int16_t *) cfg_buf; 1630 chksum = 0; 1631 1632 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 1633 AdwWaitEEPCmd(iot, ioh); 1634 1635 /* 1636 * Write EEPROM from word 0 to word 20 1637 */ 1638 for (addr = ASC_EEP_DVC_CFG_BEGIN; 1639 addr < ASC_EEP_DVC_CFG_END; addr++, wbuf++) { 1640 chksum += *wbuf; 1641 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1642 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1643 ASC_EEP_CMD_WRITE | addr); 1644 AdwWaitEEPCmd(iot, ioh); 1645 AdwSleepMilliSecond(ASC_EEP_DELAY_MS); 1646 } 1647 1648 /* 1649 * Write EEPROM checksum at word 21 1650 */ 1651 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, chksum); 1652 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1653 ASC_EEP_CMD_WRITE | addr); 1654 AdwWaitEEPCmd(iot, ioh); 1655 wbuf++; /* skip over check_sum */ 1656 1657 /* 1658 * Write EEPROM OEM name at words 22 to 29 1659 */ 1660 for (addr = ASC_EEP_DVC_CTL_BEGIN; 1661 addr < ASC_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 1662 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_DATA, *wbuf); 1663 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1664 ASC_EEP_CMD_WRITE | addr); 1665 AdwWaitEEPCmd(iot, ioh); 1666 } 1667 1668 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_EE_CMD, 1669 ASC_EEP_CMD_WRITE_DISABLE); 1670 AdwWaitEEPCmd(iot, ioh); 1671 1672 return; 1673 } 1674 1675 1676 /* 1677 * AdwExeScsiQueue() - Send a request to the RISC microcode program. 1678 * 1679 * Allocate a carrier structure, point the carrier to the ADW_SCSI_REQ_Q, 1680 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 1681 * RISC to notify it a new command is ready to be executed. 1682 * 1683 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 1684 * set to SCSI_MAX_RETRY. 1685 * 1686 * Return: 1687 * ADW_SUCCESS(1) - The request was successfully queued. 1688 * ADW_BUSY(0) - Resource unavailable; Retry again after pending 1689 * request completes. 1690 * ADW_ERROR(-1) - Invalid ADW_SCSI_REQ_Q request structure 1691 * host IC error. 1692 */ 1693 int 1694 AdwExeScsiQueue(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 1695 { 1696 bus_space_tag_t iot = sc->sc_iot; 1697 bus_space_handle_t ioh = sc->sc_ioh; 1698 ADW_CCB *ccb; 1699 u_int32_t req_paddr; 1700 ADW_CARRIER *new_carrp; 1701 1702 /* 1703 * The ADW_SCSI_REQ_Q 'target_id' field should never exceed ADW_MAX_TID. 1704 */ 1705 if (scsiq->target_id > ADW_MAX_TID) { 1706 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 1707 scsiq->done_status = QD_WITH_ERROR; 1708 return ADW_ERROR; 1709 } 1710 1711 /* 1712 * Begin of CRITICAL SECTION: Must be protected within splbio/splx pair 1713 */ 1714 1715 ccb = adw_ccb_phys_kv(sc, scsiq->ccb_ptr); 1716 1717 /* 1718 * Allocate a carrier and initialize fields. 1719 */ 1720 if ((new_carrp = sc->carr_freelist) == NULL) { 1721 return ADW_BUSY; 1722 } 1723 sc->carr_freelist = ADW_CARRIER_VADDR(sc, 1724 ASC_GET_CARRP(new_carrp->next_ba)); 1725 sc->carr_pending_cnt++; 1726 1727 /* 1728 * Set the carrier to be a stopper by setting 'next_ba' 1729 * to the stopper value. The current stopper will be changed 1730 * below to point to the new stopper. 1731 */ 1732 new_carrp->next_ba = htole32(ASC_CQ_STOPPER); 1733 1734 req_paddr = sc->sc_dmamap_control->dm_segs[0].ds_addr + 1735 ADW_CCB_OFF(ccb) + offsetof(struct adw_ccb, scsiq); 1736 1737 /* Save physical address of ADW_SCSI_REQ_Q and Carrier. */ 1738 scsiq->scsiq_rptr = htole32(req_paddr); 1739 1740 /* 1741 * Every ADV_CARR_T.carr_ba is byte swapped to little-endian 1742 * order during initialization. 1743 */ 1744 scsiq->carr_ba = sc->icq_sp->carr_ba; 1745 scsiq->carr_va = sc->icq_sp->carr_ba; 1746 1747 /* 1748 * Use the current stopper to send the ADW_SCSI_REQ_Q command to 1749 * the microcode. The newly allocated stopper will become the new 1750 * stopper. 1751 */ 1752 sc->icq_sp->areq_ba = htole32(req_paddr); 1753 1754 /* 1755 * Set the 'next_ba' pointer for the old stopper to be the 1756 * physical address of the new stopper. The RISC can only 1757 * follow physical addresses. 1758 */ 1759 sc->icq_sp->next_ba = new_carrp->carr_ba; 1760 1761 #if ADW_DEBUG 1762 printf("icq 0x%x, 0x%x, 0x%x, 0x%x\n", 1763 sc->icq_sp->carr_id, 1764 sc->icq_sp->carr_ba, 1765 sc->icq_sp->areq_ba, 1766 sc->icq_sp->next_ba); 1767 #endif 1768 /* 1769 * Set the host adapter stopper pointer to point to the new carrier. 1770 */ 1771 sc->icq_sp = new_carrp; 1772 1773 if (sc->chip_type == ADW_CHIP_ASC3550 || 1774 sc->chip_type == ADW_CHIP_ASC38C0800) { 1775 /* 1776 * Tickle the RISC to tell it to read its Command Queue Head 1777 * pointer. 1778 */ 1779 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_A); 1780 if (sc->chip_type == ADW_CHIP_ASC3550) { 1781 /* 1782 * Clear the tickle value. In the ASC-3550 the RISC flag 1783 * command 'clr_tickle_a' does not work unless the host 1784 * value is cleared. 1785 */ 1786 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, 1787 ADW_TICKLE_NOP); 1788 } 1789 } else if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1790 /* 1791 * Notify the RISC a carrier is ready by writing the physical 1792 * address of the new carrier stopper to the COMMA register. 1793 */ 1794 ADW_WRITE_DWORD_REGISTER(iot, ioh, IOPDW_COMMA, 1795 le32toh(new_carrp->carr_ba)); 1796 } 1797 1798 /* 1799 * End of CRITICAL SECTION: Must be protected within splbio/splx pair 1800 */ 1801 1802 return ADW_SUCCESS; 1803 } 1804 1805 1806 void 1807 AdwResetChip(bus_space_tag_t iot, bus_space_handle_t ioh) 1808 { 1809 1810 /* 1811 * Reset Chip. 1812 */ 1813 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1814 ADW_CTRL_REG_CMD_RESET); 1815 AdwSleepMilliSecond(100); 1816 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1817 ADW_CTRL_REG_CMD_WR_IO_REG); 1818 } 1819 1820 1821 /* 1822 * Reset SCSI Bus and purge all outstanding requests. 1823 * 1824 * Return Value: 1825 * ADW_TRUE(1) - All requests are purged and SCSI Bus is reset. 1826 * ADW_FALSE(0) - Microcode command failed. 1827 * ADW_ERROR(-1) - Microcode command timed-out. Microcode or IC 1828 * may be hung which requires driver recovery. 1829 */ 1830 int 1831 AdwResetCCB(ADW_SOFTC *sc) 1832 { 1833 int status; 1834 1835 /* 1836 * Send the SCSI Bus Reset idle start idle command which asserts 1837 * the SCSI Bus Reset signal. 1838 */ 1839 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_START, 0L); 1840 if (status != ADW_TRUE) { 1841 return status; 1842 } 1843 1844 /* 1845 * Delay for the specified SCSI Bus Reset hold time. 1846 * 1847 * The hold time delay is done on the host because the RISC has no 1848 * microsecond accurate timer. 1849 */ 1850 AdwDelayMicroSecond((u_int16_t) ASC_SCSI_RESET_HOLD_TIME_US); 1851 1852 /* 1853 * Send the SCSI Bus Reset end idle command which de-asserts 1854 * the SCSI Bus Reset signal and purges any pending requests. 1855 */ 1856 status = AdwSendIdleCmd(sc, (u_int16_t) IDLE_CMD_SCSI_RESET_END, 0L); 1857 if (status != ADW_TRUE) { 1858 return status; 1859 } 1860 1861 AdwSleepMilliSecond((u_int32_t) sc->scsi_reset_wait * 1000); 1862 1863 return status; 1864 } 1865 1866 1867 /* 1868 * Reset chip and SCSI Bus. 1869 * 1870 * Return Value: 1871 * ADW_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 1872 * ADW_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 1873 */ 1874 int 1875 AdwResetSCSIBus(ADW_SOFTC *sc) 1876 { 1877 bus_space_tag_t iot = sc->sc_iot; 1878 bus_space_handle_t ioh = sc->sc_ioh; 1879 int status; 1880 u_int16_t wdtr_able, sdtr_able, tagqng_able; 1881 u_int16_t ppr_able = 0; /* XXX: gcc */ 1882 u_int8_t tid, max_cmd[ADW_MAX_TID + 1]; 1883 u_int16_t bios_sig; 1884 1885 1886 /* 1887 * Save current per TID negotiated values. 1888 */ 1889 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1890 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1891 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1892 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1893 } 1894 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1895 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1896 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1897 max_cmd[tid]); 1898 } 1899 1900 /* 1901 * Force the AdwInitAscDriver() function to perform a SCSI Bus Reset 1902 * by clearing the BIOS signature word. 1903 * The initialization functions assumes a SCSI Bus Reset is not 1904 * needed if the BIOS signature word is present. 1905 */ 1906 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1907 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, 0); 1908 1909 /* 1910 * Stop chip and reset it. 1911 */ 1912 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_RISC_CSR, ADW_RISC_CSR_STOP); 1913 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1914 ADW_CTRL_REG_CMD_RESET); 1915 AdwSleepMilliSecond(100); 1916 ADW_WRITE_WORD_REGISTER(iot, ioh, IOPW_CTRL_REG, 1917 ADW_CTRL_REG_CMD_WR_IO_REG); 1918 1919 /* 1920 * Reset Adv Library error code, if any, and try 1921 * re-initializing the chip. 1922 * Then translate initialization return value to status value. 1923 */ 1924 status = (AdwInitDriver(sc) == 0)? ADW_TRUE : ADW_FALSE; 1925 1926 /* 1927 * Restore the BIOS signature word. 1928 */ 1929 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_BIOS_SIGNATURE, bios_sig); 1930 1931 /* 1932 * Restore per TID negotiated values. 1933 */ 1934 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, wdtr_able); 1935 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, sdtr_able); 1936 if (sc->chip_type == ADW_CHIP_ASC38C1600) { 1937 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, ppr_able); 1938 } 1939 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, tagqng_able); 1940 for (tid = 0; tid <= ADW_MAX_TID; tid++) { 1941 ADW_WRITE_BYTE_LRAM(iot, ioh, ADW_MC_NUMBER_OF_MAX_CMD + tid, 1942 max_cmd[tid]); 1943 } 1944 1945 return status; 1946 } 1947 1948 1949 /* 1950 * Adv Library Interrupt Service Routine 1951 * 1952 * This function is called by a driver's interrupt service routine. 1953 * The function disables and re-enables interrupts. 1954 * 1955 * When a microcode idle command is completed, the ADV_DVC_VAR 1956 * 'idle_cmd_done' field is set to ADW_TRUE. 1957 * 1958 * Note: AdwISR() can be called when interrupts are disabled or even 1959 * when there is no hardware interrupt condition present. It will 1960 * always check for completed idle commands and microcode requests. 1961 * This is an important feature that shouldn't be changed because it 1962 * allows commands to be completed from polling mode loops. 1963 * 1964 * Return: 1965 * ADW_TRUE(1) - interrupt was pending 1966 * ADW_FALSE(0) - no interrupt was pending 1967 */ 1968 int 1969 AdwISR(ADW_SOFTC *sc) 1970 { 1971 bus_space_tag_t iot = sc->sc_iot; 1972 bus_space_handle_t ioh = sc->sc_ioh; 1973 u_int8_t int_stat; 1974 ADW_CARRIER *free_carrp/*, *ccb_carr*/; 1975 u_int32_t irq_next_pa; 1976 ADW_SCSI_REQ_Q *scsiq; 1977 ADW_CCB *ccb; 1978 int s; 1979 1980 1981 s = splbio(); 1982 1983 /* Reading the register clears the interrupt. */ 1984 int_stat = ADW_READ_BYTE_REGISTER(iot, ioh, IOPB_INTR_STATUS_REG); 1985 1986 if ((int_stat & (ADW_INTR_STATUS_INTRA | ADW_INTR_STATUS_INTRB | 1987 ADW_INTR_STATUS_INTRC)) == 0) { 1988 splx(s); 1989 return ADW_FALSE; 1990 } 1991 1992 /* 1993 * Notify the driver of an asynchronous microcode condition by 1994 * calling the ADV_DVC_VAR.async_callback function. The function 1995 * is passed the microcode ADW_MC_INTRB_CODE byte value. 1996 */ 1997 if (int_stat & ADW_INTR_STATUS_INTRB) { 1998 u_int8_t intrb_code; 1999 2000 ADW_READ_BYTE_LRAM(iot, ioh, ADW_MC_INTRB_CODE, intrb_code); 2001 2002 if (sc->chip_type == ADW_CHIP_ASC3550 || 2003 sc->chip_type == ADW_CHIP_ASC38C0800) { 2004 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 2005 sc->carr_pending_cnt != 0) { 2006 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2007 IOPB_TICKLE, ADW_TICKLE_A); 2008 if (sc->chip_type == ADW_CHIP_ASC3550) { 2009 ADW_WRITE_BYTE_REGISTER(iot, ioh, 2010 IOPB_TICKLE, ADW_TICKLE_NOP); 2011 } 2012 } 2013 } 2014 2015 if (sc->async_callback != 0) { 2016 (*sc->async_callback)(sc, intrb_code); 2017 } 2018 } 2019 2020 /* 2021 * Check if the IRQ stopper carrier contains a completed request. 2022 */ 2023 while (((le32toh(irq_next_pa = sc->irq_sp->next_ba)) & ASC_RQ_DONE) != 0) 2024 { 2025 #if ADW_DEBUG 2026 printf("irq 0x%x, 0x%x, 0x%x, 0x%x\n", 2027 sc->irq_sp->carr_id, 2028 sc->irq_sp->carr_ba, 2029 sc->irq_sp->areq_ba, 2030 sc->irq_sp->next_ba); 2031 #endif 2032 /* 2033 * Get a pointer to the newly completed ADW_SCSI_REQ_Q 2034 * structure. 2035 * The RISC will have set 'areq_ba' to a virtual address. 2036 * 2037 * The firmware will have copied the ASC_SCSI_REQ_Q.ccb_ptr 2038 * field to the carrier ADV_CARR_T.areq_ba field. 2039 * The conversion below complements the conversion of 2040 * ASC_SCSI_REQ_Q.scsiq_ptr' in AdwExeScsiQueue(). 2041 */ 2042 ccb = adw_ccb_phys_kv(sc, sc->irq_sp->areq_ba); 2043 scsiq = &ccb->scsiq; 2044 scsiq->ccb_ptr = sc->irq_sp->areq_ba; 2045 2046 /* 2047 * Request finished with good status and the queue was not 2048 * DMAed to host memory by the firmware. Set all status fields 2049 * to indicate good status. 2050 */ 2051 if ((le32toh(irq_next_pa) & ASC_RQ_GOOD) != 0) { 2052 scsiq->done_status = QD_NO_ERROR; 2053 scsiq->host_status = scsiq->scsi_status = 0; 2054 scsiq->data_cnt = 0L; 2055 } 2056 2057 /* 2058 * Advance the stopper pointer to the next carrier 2059 * ignoring the lower four bits. Free the previous 2060 * stopper carrier. 2061 */ 2062 free_carrp = sc->irq_sp; 2063 sc->irq_sp = ADW_CARRIER_VADDR(sc, ASC_GET_CARRP(irq_next_pa)); 2064 2065 free_carrp->next_ba = (sc->carr_freelist == NULL) ? 0 2066 : sc->carr_freelist->carr_ba; 2067 sc->carr_freelist = free_carrp; 2068 sc->carr_pending_cnt--; 2069 2070 /* 2071 * Clear request microcode control flag. 2072 */ 2073 scsiq->cntl = 0; 2074 2075 /* 2076 * Check Condition handling 2077 */ 2078 /* 2079 * If the command that completed was a SCSI INQUIRY and 2080 * LUN 0 was sent the command, then process the INQUIRY 2081 * command information for the device. 2082 */ 2083 if (scsiq->done_status == QD_NO_ERROR && 2084 scsiq->cdb[0] == INQUIRY && 2085 scsiq->target_lun == 0) { 2086 AdwInquiryHandling(sc, scsiq); 2087 } 2088 2089 /* 2090 * Notify the driver of the completed request by passing 2091 * the ADW_SCSI_REQ_Q pointer to its callback function. 2092 */ 2093 (*sc->isr_callback)(sc, scsiq); 2094 /* 2095 * Note: After the driver callback function is called, 'scsiq' 2096 * can no longer be referenced. 2097 * 2098 * Fall through and continue processing other completed 2099 * requests... 2100 */ 2101 } 2102 2103 splx(s); 2104 2105 return ADW_TRUE; 2106 } 2107 2108 2109 /* 2110 * Send an idle command to the chip and wait for completion. 2111 * 2112 * Command completion is polled for once per microsecond. 2113 * 2114 * The function can be called from anywhere including an interrupt handler. 2115 * But the function is not re-entrant, so it uses the splbio/splx() 2116 * functions to prevent reentrancy. 2117 * 2118 * Return Values: 2119 * ADW_TRUE - command completed successfully 2120 * ADW_FALSE - command failed 2121 * ADW_ERROR - command timed out 2122 */ 2123 int 2124 AdwSendIdleCmd(ADW_SOFTC *sc, u_int16_t idle_cmd, u_int32_t idle_cmd_parameter) 2125 { 2126 bus_space_tag_t iot = sc->sc_iot; 2127 bus_space_handle_t ioh = sc->sc_ioh; 2128 u_int16_t result; 2129 u_int32_t i, j, s; 2130 2131 s = splbio(); 2132 2133 /* 2134 * Clear the idle command status which is set by the microcode 2135 * to a non-zero value to indicate when the command is completed. 2136 */ 2137 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, (u_int16_t) 0); 2138 2139 /* 2140 * Write the idle command value after the idle command parameter 2141 * has been written to avoid a race condition. If the order is not 2142 * followed, the microcode may process the idle command before the 2143 * parameters have been written to LRAM. 2144 */ 2145 ADW_WRITE_DWORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_PARAMETER, 2146 idle_cmd_parameter); 2147 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD, idle_cmd); 2148 2149 /* 2150 * Tickle the RISC to tell it to process the idle command. 2151 */ 2152 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_B); 2153 if (sc->chip_type == ADW_CHIP_ASC3550) { 2154 /* 2155 * Clear the tickle value. In the ASC-3550 the RISC flag 2156 * command 'clr_tickle_b' does not work unless the host 2157 * value is cleared. 2158 */ 2159 ADW_WRITE_BYTE_REGISTER(iot, ioh, IOPB_TICKLE, ADW_TICKLE_NOP); 2160 } 2161 2162 /* Wait for up to 100 millisecond for the idle command to timeout. */ 2163 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 2164 /* Poll once each microsecond for command completion. */ 2165 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 2166 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_IDLE_CMD_STATUS, 2167 result); 2168 if (result != 0) { 2169 splx(s); 2170 return result; 2171 } 2172 AdwDelayMicroSecond(1); 2173 } 2174 } 2175 2176 splx(s); 2177 return ADW_ERROR; 2178 } 2179 2180 2181 /* 2182 * Inquiry Information Byte 7 Handling 2183 * 2184 * Handle SCSI Inquiry Command information for a device by setting 2185 * microcode operating variables that affect WDTR, SDTR, and Tag 2186 * Queuing. 2187 */ 2188 static void 2189 AdwInquiryHandling(ADW_SOFTC *sc, ADW_SCSI_REQ_Q *scsiq) 2190 { 2191 #ifndef FAILSAFE 2192 bus_space_tag_t iot = sc->sc_iot; 2193 bus_space_handle_t ioh = sc->sc_ioh; 2194 u_int8_t tid; 2195 struct scsipi_inquiry_data *inq; 2196 u_int16_t tidmask; 2197 u_int16_t cfg_word; 2198 2199 2200 /* 2201 * AdwInquiryHandling() requires up to INQUIRY information Byte 7 2202 * to be available. 2203 * 2204 * If less than 8 bytes of INQUIRY information were requested or less 2205 * than 8 bytes were transferred, then return. cdb[4] is the request 2206 * length and the ADW_SCSI_REQ_Q 'data_cnt' field is set by the 2207 * microcode to the transfer residual count. 2208 */ 2209 2210 if (scsiq->cdb[4] < 8 || (scsiq->cdb[4] - scsiq->data_cnt) < 8) { 2211 return; 2212 } 2213 2214 tid = scsiq->target_id; 2215 2216 inq = (struct scsipi_inquiry_data *) scsiq->vdata_addr; 2217 2218 /* 2219 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices. 2220 */ 2221 if (((inq->response_format & SID_RespDataFmt) < 2) /*SCSI-1 | CCS*/ && 2222 ((inq->version & SID_ANSII) < 2)) { 2223 return; 2224 } else { 2225 /* 2226 * INQUIRY Byte 7 Handling 2227 * 2228 * Use a device's INQUIRY byte 7 to determine whether it 2229 * supports WDTR, SDTR, and Tag Queuing. If the feature 2230 * is enabled in the EEPROM and the device supports the 2231 * feature, then enable it in the microcode. 2232 */ 2233 2234 tidmask = ADW_TID_TO_TIDMASK(tid); 2235 2236 /* 2237 * Wide Transfers 2238 * 2239 * If the EEPROM enabled WDTR for the device and the device 2240 * supports wide bus (16 bit) transfers, then turn on the 2241 * device's 'wdtr_able' bit and write the new value to the 2242 * microcode. 2243 */ 2244 #ifdef SCSI_ADW_WDTR_DISABLE 2245 if(!(tidmask & SCSI_ADW_WDTR_DISABLE)) 2246 #endif /* SCSI_ADW_WDTR_DISABLE */ 2247 if ((sc->wdtr_able & tidmask) && (inq->flags3 & SID_WBus16)) { 2248 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2249 cfg_word); 2250 if ((cfg_word & tidmask) == 0) { 2251 cfg_word |= tidmask; 2252 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_ABLE, 2253 cfg_word); 2254 2255 /* 2256 * Clear the microcode "SDTR negotiation" and 2257 * "WDTR negotiation" done indicators for the 2258 * target to cause it to negotiate with the new 2259 * setting set above. 2260 * WDTR when accepted causes the target to enter 2261 * asynchronous mode, so SDTR must be negotiated 2262 */ 2263 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2264 cfg_word); 2265 cfg_word &= ~tidmask; 2266 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2267 cfg_word); 2268 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2269 cfg_word); 2270 cfg_word &= ~tidmask; 2271 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_WDTR_DONE, 2272 cfg_word); 2273 } 2274 } 2275 2276 /* 2277 * Synchronous Transfers 2278 * 2279 * If the EEPROM enabled SDTR for the device and the device 2280 * supports synchronous transfers, then turn on the device's 2281 * 'sdtr_able' bit. Write the new value to the microcode. 2282 */ 2283 #ifdef SCSI_ADW_SDTR_DISABLE 2284 if(!(tidmask & SCSI_ADW_SDTR_DISABLE)) 2285 #endif /* SCSI_ADW_SDTR_DISABLE */ 2286 if ((sc->sdtr_able & tidmask) && (inq->flags3 & SID_Sync)) { 2287 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE,cfg_word); 2288 if ((cfg_word & tidmask) == 0) { 2289 cfg_word |= tidmask; 2290 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_ABLE, 2291 cfg_word); 2292 2293 /* 2294 * Clear the microcode "SDTR negotiation" 2295 * done indicator for the target to cause it 2296 * to negotiate with the new setting set above. 2297 */ 2298 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2299 cfg_word); 2300 cfg_word &= ~tidmask; 2301 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_SDTR_DONE, 2302 cfg_word); 2303 } 2304 } 2305 /* 2306 * If the Inquiry data included enough space for the SPI-3 2307 * Clocking field, then check if DT mode is supported. 2308 */ 2309 if (sc->chip_type == ADW_CHIP_ASC38C1600 && 2310 (scsiq->cdb[4] >= 57 || 2311 (scsiq->cdb[4] - scsiq->data_cnt) >= 57)) { 2312 /* 2313 * PPR (Parallel Protocol Request) Capable 2314 * 2315 * If the device supports DT mode, then it must be 2316 * PPR capable. 2317 * The PPR message will be used in place of the SDTR 2318 * and WDTR messages to negotiate synchronous speed 2319 * and offset, transfer width, and protocol options. 2320 */ 2321 if((inq->flags4 & SID_Clocking) & SID_CLOCKING_DT_ONLY){ 2322 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2323 sc->ppr_able); 2324 sc->ppr_able |= tidmask; 2325 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_PPR_ABLE, 2326 sc->ppr_able); 2327 } 2328 } 2329 2330 /* 2331 * If the EEPROM enabled Tag Queuing for the device and the 2332 * device supports Tag Queueing, then turn on the device's 2333 * 'tagqng_enable' bit in the microcode and set the microcode 2334 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng' 2335 * value. 2336 * 2337 * Tag Queuing is disabled for the BIOS which runs in polled 2338 * mode and would see no benefit from Tag Queuing. Also by 2339 * disabling Tag Queuing in the BIOS devices with Tag Queuing 2340 * bugs will at least work with the BIOS. 2341 */ 2342 #ifdef SCSI_ADW_TAGQ_DISABLE 2343 if(!(tidmask & SCSI_ADW_TAGQ_DISABLE)) 2344 #endif /* SCSI_ADW_TAGQ_DISABLE */ 2345 if ((sc->tagqng_able & tidmask) && (inq->flags3 & SID_CmdQue)) { 2346 ADW_READ_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2347 cfg_word); 2348 cfg_word |= tidmask; 2349 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_TAGQNG_ABLE, 2350 cfg_word); 2351 2352 ADW_WRITE_BYTE_LRAM(iot, ioh, 2353 ADW_MC_NUMBER_OF_MAX_CMD + tid, 2354 sc->max_dvc_qng); 2355 } 2356 } 2357 #endif /* FAILSAFE */ 2358 } 2359 2360 2361 static void 2362 AdwSleepMilliSecond(u_int32_t n) 2363 { 2364 2365 DELAY(n * 1000); 2366 } 2367 2368 2369 static void 2370 AdwDelayMicroSecond(u_int32_t n) 2371 { 2372 2373 DELAY(n); 2374 } 2375
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