FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/adwlib.h
1 /* $NetBSD: adwlib.h,v 1.23 2019/12/15 16:48:27 tsutsui Exp $ */
2
3 /*
4 * Definitions for low level routines and data structures
5 * for the Advanced Systems Inc. SCSI controllers chips.
6 *
7 * Copyright (c) 1998, 1999, 2000 The NetBSD Foundation, Inc.
8 * All rights reserved.
9 *
10 * Author: Baldassare Dante Profeta <dante@mclink.it>
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33 /*
34 * Ported from:
35 */
36 /*
37 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
38 *
39 * Copyright (c) 1995-2000 Advanced System Products, Inc.
40 * All Rights Reserved.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that redistributions of source
44 * code retain the above copyright notice and this comment without
45 * modification.
46 */
47
48 #ifndef _ADVANSYS_WIDE_LIBRARY_H_
49 #define _ADVANSYS_WIDE_LIBRARY_H_
50
51
52 /*
53 * --- Adw Library Constants and Macros
54 */
55
56 #define ADW_LIB_VERSION_MAJOR 5
57 #define ADW_LIB_VERSION_MINOR 8
58
59
60 /* If the result wraps when calculating tenths, return 0. */
61 #define ADW_TENTHS(num, den) \
62 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
63 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
64
65
66 /*
67 * Define Adw Reset Hold Time grater than 25 uSec.
68 * See AdwResetSCSIBus() for more info.
69 */
70 #define ASC_SCSI_RESET_HOLD_TIME_US 60
71
72 /*
73 * Define Adw EEPROM constants.
74 */
75
76 #define ASC_EEP_DVC_CFG_BEGIN (0x00)
77 #define ASC_EEP_DVC_CFG_END (0x15)
78 #define ASC_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
79 #define ASC_EEP_MAX_WORD_ADDR (0x1E)
80
81 #define ASC_EEP_DELAY_MS 100
82
83 /*
84 * EEPROM bits reference by the RISC after initialization.
85 */
86 #define ADW_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
87 #define ADW_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
88 #define ADW_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
89
90 /*
91 * EEPROM configuration format
92 *
93 * Field naming convention:
94 *
95 * *_enable indicates the field enables or disables the feature. The
96 * value is never reset.
97 *
98 * *_able indicates both whether a feature should be enabled or disabled
99 * and whether a device isi capable of the feature. At initialization
100 * this field may be set, but later if a device is found to be incapable
101 * of the feature, the field is cleared.
102 *
103 * Default values are maintained in the structure Default_EEPROM_Config.
104 */
105 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
106 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
107 /*
108 * For the ASC3550 Bit 13 is Termination Polarity control bit.
109 * For later ICs Bit 13 controls whether the CIS (Card Information
110 * Service Section) is loaded from EEPROM.
111 */
112 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
113 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
114
115 /*
116 * ASC38C1600 Bit 11
117 *
118 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
119 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
120 * Function 0 will specify INT B.
121 *
122 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
123 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
124 * Function 1 will specify INT A.
125 */
126 #define ADW_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
127
128 typedef struct adw_eeprom
129 {
130 /* Word Offset, Description */
131
132 u_int16_t cfg_lsw; /* 00 power up initialization */
133 /* bit 13 set - Term Polarity Control */
134 /* bit 14 set - BIOS Enable */
135 /* bit 15 set - Big Endian Mode */
136 u_int16_t cfg_msw; /* 01 unused */
137 u_int16_t disc_enable; /* 02 disconnect enable */
138 u_int16_t wdtr_able; /* 03 Wide DTR able */
139 union {
140 u_int16_t sdtr_able; /* 04 Synchronous DTR able */
141 u_int16_t sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
142 } sdtr1;
143 u_int16_t start_motor; /* 05 send start up motor */
144 u_int16_t tagqng_able; /* 06 tag queuing able */
145 u_int16_t bios_scan; /* 07 BIOS device control */
146 u_int16_t scam_tolerant; /* 08 no scam */
147
148 u_int8_t adapter_scsi_id; /* 09 Host Adapter ID */
149 u_int8_t bios_boot_delay; /* power up wait */
150
151 u_int8_t scsi_reset_delay; /* 10 reset delay */
152 u_int8_t bios_id_lun; /* first boot device scsi id & lun */
153 /* high nibble is lun */
154 /* low nibble is scsi id */
155
156 u_int8_t termination_se; /* 11 0 - automatic */
157 /* 1 - low off / high off */
158 /* 2 - low off / high on */
159 /* 3 - low on / high on */
160 /* There is no low on / high off */
161
162 u_int8_t termination_lvd; /* 11 0 - automatic */
163 /* 1 - low off / high off */
164 /* 2 - low off / high on */
165 /* 3 - low on / high on */
166 /* There is no low on / high off */
167
168 u_int16_t bios_ctrl; /* 12 BIOS control bits */
169 /* bit 0 BIOS don't act as initiator. */
170 /* bit 1 BIOS > 1 GB support */
171 /* bit 2 BIOS > 2 Disk Support */
172 /* bit 3 BIOS don't support removables */
173 /* bit 4 BIOS support bootable CD */
174 /* bit 5 BIOS scan enabled */
175 /* bit 6 BIOS support multiple LUNs */
176 /* bit 7 BIOS display of message */
177 /* bit 8 SCAM disabled */
178 /* bit 9 Reset SCSI bus during init. */
179 /* bit 10 */
180 /* bit 11 No verbose initialization. */
181 /* bit 12 SCSI parity enabled */
182 /* bit 13 */
183 /* bit 14 */
184 /* bit 15 */
185 union {
186 u_int16_t ultra_able; /* 13 ULTRA speed able */
187 u_int16_t sdtr_speed2; /* 13 SDTR speed TID 4-7 */
188 } sdtr2;
189 union {
190 u_int16_t reserved2; /* 14 reserved */
191 u_int16_t sdtr_speed3; /* 14 SDTR speed TID 8-11 */
192 } sdtr3;
193 u_int8_t max_host_qng; /* 15 maximum host queuing */
194 u_int8_t max_dvc_qng; /* maximum per device queuing */
195 u_int16_t dvc_cntl; /* 16 control bit for driver */
196 union {
197 u_int16_t bug_fix; /* 17 control bit for bug fix */
198 u_int16_t sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
199 } sdtr4;
200 u_int16_t serial_number[3]; /* 18 - 20 Board serial number */
201 u_int16_t check_sum; /* 21 EEP check sum */
202 u_int8_t oem_name[16]; /* 22 OEM name */
203 u_int16_t dvc_err_code; /* 30 last device driver error code */
204 u_int16_t adv_err_code; /* 31 last uc and Adw Lib error code */
205 u_int16_t adv_err_addr; /* 32 last uc error address */
206 u_int16_t saved_dvc_err_code; /* 33 saved last dev. driver error code */
207 u_int16_t saved_adv_err_code; /* 34 saved last uc and Adw Lib error code */
208 u_int16_t saved_adv_err_addr; /* 35 saved last uc error address */
209 u_int16_t reserved1[20]; /* 36 - 55 reserved */
210 u_int16_t cisptr_lsw; /* 56 CIS PTR LSW */
211 u_int16_t cisprt_msw; /* 57 CIS PTR MSW */
212 u_int16_t subsysvid; /* 58 SubSystem Vendor ID */
213 u_int16_t subsysid; /* 59 SubSystem ID */
214 u_int16_t reserved2[4]; /* 60 - 63 reserved */
215 } ADW_EEPROM;
216
217
218 /*
219 * EEPROM Commands
220 */
221 #define ASC_EEP_CMD_READ 0x80
222 #define ASC_EEP_CMD_WRITE 0x40
223 #define ASC_EEP_CMD_WRITE_ABLE 0x30
224 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
225
226 #define ASC_EEP_CMD_DONE 0x0200
227 #define ASC_EEP_CMD_DONE_ERR 0x0001
228
229 /* cfg_word */
230 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
231
232 /* bios_ctrl */
233 #define BIOS_CTRL_BIOS 0x0001
234 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
235 #define BIOS_CTRL_GT_2_DISK 0x0004
236 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
237 #define BIOS_CTRL_BOOTABLE_CD 0x0010
238 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
239 #define BIOS_CTRL_DISPLAY_MSG 0x0080
240 #define BIOS_CTRL_NO_SCAM 0x0100
241 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
242 #define BIOS_CTRL_INIT_VERBOSE 0x0800
243 #define BIOS_CTRL_SCSI_PARITY 0x1000
244 #define BIOS_CTRL_AIPP_DIS 0x2000
245
246 #define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
247 #define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */
248
249 #define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
250 #define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
251
252 #define ADW_38C1600_MEMSIZE 0x8000 /* 32 KB Internal Memory */
253 #define ADW_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
254 #define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
255
256 /*
257 * Byte I/O register address from base of 'iop_base'.
258 */
259 #define IOPB_INTR_STATUS_REG 0x00
260 #define IOPB_CHIP_ID_1 0x01
261 #define IOPB_INTR_ENABLES 0x02
262 #define IOPB_CHIP_TYPE_REV 0x03
263 #define IOPB_RES_ADDR_4 0x04
264 #define IOPB_RES_ADDR_5 0x05
265 #define IOPB_RAM_DATA 0x06
266 #define IOPB_RES_ADDR_7 0x07
267 #define IOPB_FLAG_REG 0x08
268 #define IOPB_RES_ADDR_9 0x09
269 #define IOPB_RISC_CSR 0x0A
270 #define IOPB_RES_ADDR_B 0x0B
271 #define IOPB_RES_ADDR_C 0x0C
272 #define IOPB_RES_ADDR_D 0x0D
273 #define IOPB_SOFT_OVER_WR 0x0E
274 #define IOPB_RES_ADDR_F 0x0F
275 #define IOPB_MEM_CFG 0x10
276 #define IOPB_RES_ADDR_11 0x11
277 #define IOPB_GPIO_DATA 0x12
278 #define IOPB_RES_ADDR_13 0x13
279 #define IOPB_FLASH_PAGE 0x14
280 #define IOPB_RES_ADDR_15 0x15
281 #define IOPB_GPIO_CNTL 0x16
282 #define IOPB_RES_ADDR_17 0x17
283 #define IOPB_FLASH_DATA 0x18
284 #define IOPB_RES_ADDR_19 0x19
285 #define IOPB_RES_ADDR_1A 0x1A
286 #define IOPB_RES_ADDR_1B 0x1B
287 #define IOPB_RES_ADDR_1C 0x1C
288 #define IOPB_RES_ADDR_1D 0x1D
289 #define IOPB_RES_ADDR_1E 0x1E
290 #define IOPB_RES_ADDR_1F 0x1F
291 #define IOPB_DMA_CFG0 0x20
292 #define IOPB_DMA_CFG1 0x21
293 #define IOPB_TICKLE 0x22
294 #define IOPB_DMA_REG_WR 0x23
295 #define IOPB_SDMA_STATUS 0x24
296 #define IOPB_SCSI_BYTE_CNT 0x25
297 #define IOPB_HOST_BYTE_CNT 0x26
298 #define IOPB_BYTE_LEFT_TO_XFER 0x27
299 #define IOPB_BYTE_TO_XFER_0 0x28
300 #define IOPB_BYTE_TO_XFER_1 0x29
301 #define IOPB_BYTE_TO_XFER_2 0x2A
302 #define IOPB_BYTE_TO_XFER_3 0x2B
303 #define IOPB_ACC_GRP 0x2C
304 #define IOPB_RES_ADDR_2D 0x2D
305 #define IOPB_DEV_ID 0x2E
306 #define IOPB_RES_ADDR_2F 0x2F
307 #define IOPB_SCSI_DATA 0x30
308 #define IOPB_RES_ADDR_31 0x31
309 #define IOPB_RES_ADDR_32 0x32
310 #define IOPB_SCSI_DATA_HSHK 0x33
311 #define IOPB_SCSI_CTRL 0x34
312 #define IOPB_RES_ADDR_35 0x35
313 #define IOPB_RES_ADDR_36 0x36
314 #define IOPB_RES_ADDR_37 0x37
315 #define IOPB_RAM_BIST 0x38
316 #define IOPB_PLL_TEST 0x39
317 #define IOPB_PCI_INT_CFG 0x3A
318 #define IOPB_RES_ADDR_3B 0x3B
319 #define IOPB_RFIFO_CNT 0x3C
320 #define IOPB_RES_ADDR_3D 0x3D
321 #define IOPB_RES_ADDR_3E 0x3E
322 #define IOPB_RES_ADDR_3F 0x3F
323
324 /*
325 * Word I/O register address from base of 'iop_base'.
326 */
327 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
328 #define IOPW_CTRL_REG 0x02 /* CC */
329 #define IOPW_RAM_ADDR 0x04 /* LA */
330 #define IOPW_RAM_DATA 0x06 /* LD */
331 #define IOPW_RES_ADDR_08 0x08
332 #define IOPW_RISC_CSR 0x0A /* CSR */
333 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
334 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
335 #define IOPW_RES_ADDR_10 0x10
336 #define IOPW_SEL_MASK 0x12 /* SM */
337 #define IOPW_RES_ADDR_14 0x14
338 #define IOPW_FLASH_ADDR 0x16 /* FA */
339 #define IOPW_RES_ADDR_18 0x18
340 #define IOPW_EE_CMD 0x1A /* EC */
341 #define IOPW_EE_DATA 0x1C /* ED */
342 #define IOPW_SFIFO_CNT 0x1E /* SFC */
343 #define IOPW_RES_ADDR_20 0x20
344 #define IOPW_Q_BASE 0x22 /* QB */
345 #define IOPW_QP 0x24 /* QP */
346 #define IOPW_IX 0x26 /* IX */
347 #define IOPW_SP 0x28 /* SP */
348 #define IOPW_PC 0x2A /* PC */
349 #define IOPW_RES_ADDR_2C 0x2C
350 #define IOPW_RES_ADDR_2E 0x2E
351 #define IOPW_SCSI_DATA 0x30 /* SD */
352 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
353 #define IOPW_SCSI_CTRL 0x34 /* SC */
354 #define IOPW_HSHK_CFG 0x36 /* HCFG */
355 #define IOPW_SXFR_STATUS 0x36 /* SXS */
356 #define IOPW_SXFR_CNTL 0x38 /* SXL */
357 #define IOPW_SXFR_CNTH 0x3A /* SXH */
358 #define IOPW_RES_ADDR_3C 0x3C
359 #define IOPW_RFIFO_DATA 0x3E /* RFD */
360
361 /*
362 * Doubleword I/O register address from base of 'iop_base'.
363 */
364 #define IOPDW_RES_ADDR_0 0x00
365 #define IOPDW_RAM_DATA 0x04
366 #define IOPDW_RES_ADDR_8 0x08
367 #define IOPDW_RES_ADDR_C 0x0C
368 #define IOPDW_RES_ADDR_10 0x10
369 #define IOPDW_COMMA 0x14
370 #define IOPDW_COMMB 0x18
371 #define IOPDW_RES_ADDR_1C 0x1C
372 #define IOPDW_SDMA_ADDR0 0x20
373 #define IOPDW_SDMA_ADDR1 0x24
374 #define IOPDW_SDMA_COUNT 0x28
375 #define IOPDW_SDMA_ERROR 0x2C
376 #define IOPDW_RDMA_ADDR0 0x30
377 #define IOPDW_RDMA_ADDR1 0x34
378 #define IOPDW_RDMA_COUNT 0x38
379 #define IOPDW_RDMA_ERROR 0x3C
380
381 #define ADW_CHIP_ID_BYTE 0x25
382 #define ADW_CHIP_ID_WORD 0x04C1
383
384 #define ADW_SC_SCSI_BUS_RESET 0x2000
385
386 #define ADW_INTR_ENABLE_HOST_INTR 0x01
387 #define ADW_INTR_ENABLE_SEL_INTR 0x02
388 #define ADW_INTR_ENABLE_DPR_INTR 0x04
389 #define ADW_INTR_ENABLE_RTA_INTR 0x08
390 #define ADW_INTR_ENABLE_RMA_INTR 0x10
391 #define ADW_INTR_ENABLE_RST_INTR 0x20
392 #define ADW_INTR_ENABLE_DPE_INTR 0x40
393 #define ADW_INTR_ENABLE_GLOBAL_INTR 0x80
394
395 #define ADW_INTR_STATUS_INTRA 0x01
396 #define ADW_INTR_STATUS_INTRB 0x02
397 #define ADW_INTR_STATUS_INTRC 0x04
398
399 #define ADW_RISC_CSR_STOP (0x0000)
400 #define ADW_RISC_TEST_COND (0x2000)
401 #define ADW_RISC_CSR_RUN (0x4000)
402 #define ADW_RISC_CSR_SINGLE_STEP (0x8000)
403
404 #define ADW_CTRL_REG_HOST_INTR 0x0100
405 #define ADW_CTRL_REG_SEL_INTR 0x0200
406 #define ADW_CTRL_REG_DPR_INTR 0x0400
407 #define ADW_CTRL_REG_RTA_INTR 0x0800
408 #define ADW_CTRL_REG_RMA_INTR 0x1000
409 #define ADW_CTRL_REG_RES_BIT14 0x2000
410 #define ADW_CTRL_REG_DPE_INTR 0x4000
411 #define ADW_CTRL_REG_POWER_DONE 0x8000
412 #define ADW_CTRL_REG_ANY_INTR 0xFF00
413
414 #define ADW_CTRL_REG_CMD_RESET 0x00C6
415 #define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5
416 #define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4
417 #define ADW_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
418 #define ADW_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
419
420 #define ADW_TICKLE_NOP 0x00
421 #define ADW_TICKLE_A 0x01
422 #define ADW_TICKLE_B 0x02
423 #define ADW_TICKLE_C 0x03
424
425 #define ADW_SCSI_CTRL_RSTOUT 0x2000
426
427 #define ADW_IS_INT_PENDING(iot, ioh) \
428 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CTRL_REG) & ADW_CTRL_REG_HOST_INTR)
429
430 /*
431 * SCSI_CFG0 Register bit definitions
432 */
433 #define ADW_TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
434 #define ADW_PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
435 #define ADW_EVEN_PARITY 0x1000 /* Select Even Parity */
436 #define ADW_WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
437 #define ADW_QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
438 #define ADW_PRIM_MODE 0x0100 /* Primitive SCSI mode */
439 #define ADW_SCAM_EN 0x0080 /* Enable SCAM selection */
440 #define ADW_SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
441 #define ADW_CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
442 #define ADW_OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
443 #define ADW_OUR_ID 0x000F /* SCSI ID */
444
445 /*
446 * SCSI_CFG1 Register bit definitions
447 */
448 #define ADW_BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
449 #define ADW_TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
450 #define ADW_SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
451 #define ADW_FILTER_SEL 0x0C00 /* Filter Period Selection */
452 #define ADW_FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
453 #define ADW_FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
454 #define ADW_FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
455 #define ADW_ACTIVE_DBL 0x0200 /* Disable Active Negation */
456 #define ADW_DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
457 #define ADW_DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
458 #define ADW_TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
459 #define ADW_TERM_CTL 0x0030 /* External SCSI Termination Bits */
460 #define ADW_TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
461 #define ADW_TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
462 #define ADW_CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
463
464 /*
465 * Addendum for ASC-38C0800 Chip
466 *
467 * The ASC-38C1600 Chip uses the same definitions except that the
468 * bus mode override bits [12:10] have been moved to byte register
469 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
470 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
471 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
472 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
473 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
474 */
475 #define ADW_DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
476 #define ADW_HVD_LVD_SE 0x1C00 /* Device Detect Bits */
477 #define ADW_HVD 0x1000 /* HVD Device Detect */
478 #define ADW_LVD 0x0800 /* LVD Device Detect */
479 #define ADW_SE 0x0400 /* SE Device Detect */
480 #define ADW_TERM_LVD 0x00C0 /* LVD Termination Bits */
481 #define ADW_TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
482 #define ADW_TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
483 #define ADW_TERM_SE 0x0030 /* SE Termination Bits */
484 #define ADW_TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
485 #define ADW_TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
486 #define ADW_C_DET_LVD 0x000C /* LVD Cable Detect Bits */
487 #define ADW_C_DET3 0x0008 /* Cable Detect for LVD External Wide */
488 #define ADW_C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
489 #define ADW_C_DET_SE 0x0003 /* SE Cable Detect Bits */
490 #define ADW_C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
491 #define ADW_C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
492
493
494 #define CABLE_ILLEGAL_A 0x7
495 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
496
497 #define CABLE_ILLEGAL_B 0xB
498 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
499
500 /*
501 The following table details the SCSI_CFG1 Termination Polarity,
502 Termination Control and Cable Detect bits.
503
504 Cable Detect | Termination
505 Bit 3 2 1 0 | 5 4 | Notes
506 _____________|________|____________________
507 1 1 1 0 | on on | Internal wide only
508 1 1 0 1 | on on | Internal narrow only
509 1 0 1 1 | on on | External narrow only
510 0 x 1 1 | on on | External wide only
511 1 1 0 0 | on off| Internal wide and internal narrow
512 1 0 1 0 | on off| Internal wide and external narrow
513 0 x 1 0 | off off| Internal wide and external wide
514 1 0 0 1 | on off| Internal narrow and external narrow
515 0 x 0 1 | on off| Internal narrow and external wide
516 1 1 1 1 | on on | No devices are attached
517 x 0 0 0 | on on | Illegal (all 3 connectors are used)
518 0 x 0 0 | on on | Illegal (all 3 connectors are used)
519
520 x means don't-care (either '' or '1')
521
522 If term_pol (bit 13) is '' (active-low terminator enable), then:
523 'on' is '' and 'off' is '1'.
524
525 If term_pol bit is '1' (meaning active-hi terminator enable), then:
526 'on' is '1' and 'off' is ''.
527 */
528
529 /*
530 * MEM_CFG Register bit definitions
531 */
532 #define ADW_BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
533 #define ADW_FAST_EE_CLK 0x20 /* Diagnostic Bit */
534 #define ADW_RAM_SZ 0x1C /* Specify size of RAM to RISC */
535 #define ADW_RAM_SZ_2KB 0x00 /* 2 KB */
536 #define ADW_RAM_SZ_4KB 0x04 /* 4 KB */
537 #define ADW_RAM_SZ_8KB 0x08 /* 8 KB */
538 #define ADW_RAM_SZ_16KB 0x0C /* 16 KB */
539 #define ADW_RAM_SZ_32KB 0x10 /* 32 KB */
540 #define ADW_RAM_SZ_64KB 0x14 /* 64 KB */
541
542 /*
543 * DMA_CFG0 Register bit definitions
544 *
545 * This register is only accessible to the host.
546 */
547 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
548 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
549 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
550 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
551 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
552 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
553 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
554 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
555 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
556 #define START_CTL 0x0C /* DMA start conditions */
557 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
558 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
559 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
560 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
561 #define READ_CMD 0x03 /* Memory Read Method */
562 #define READ_CMD_MR 0x00 /* Memory Read */
563 #define READ_CMD_MRL 0x02 /* Memory Read Long */
564 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
565
566 /*
567 * ASC-38C0800 RAM BIST Register bit definitions
568 */
569 #define RAM_TEST_MODE 0x80
570 #define PRE_TEST_MODE 0x40
571 #define NORMAL_MODE 0x00
572 #define RAM_TEST_DONE 0x10
573 #define RAM_TEST_STATUS 0x0F
574 #define RAM_TEST_HOST_ERROR 0x08
575 #define RAM_TEST_INTRAM_ERROR 0x04
576 #define RAM_TEST_RISC_ERROR 0x02
577 #define RAM_TEST_SCSI_ERROR 0x01
578 #define RAM_TEST_SUCCESS 0x00
579 #define PRE_TEST_VALUE 0x05
580 #define NORMAL_VALUE 0x00
581
582 /*
583 * ASC38C1600 Definitions
584 *
585 * IOPB_PCI_INT_CFG Bit Field Definitions
586 */
587
588 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
589
590 /*
591 * Bit 1 can be set to change the interrupt for the Function to operate in
592 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
593 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
594 * mode, otherwise the operating mode is undefined.
595 */
596 #define TOTEMPOLE 0x02
597
598 /*
599 * Bit 0 can be used to change the Int Pin for the Function. The value is
600 * 0 by default for both Functions with Function 0 using INT A and Function
601 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
602 * INT A is used.
603 *
604 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
605 * value specified in the PCI Configuration Space.
606 */
607 #define INTAB 0x01
608
609
610 #define ADW_MAX_TID 15 /* max. target identifier */
611 #define ADW_MAX_LUN 7 /* max. logical unit number */
612
613
614 /*
615 * Adw Library Status Definitions
616 */
617 #define ADW_TRUE 1
618 #define ADW_FALSE 0
619 #define ADW_NOERROR 1
620 #define ADW_SUCCESS 1
621 #define ADW_BUSY 0
622 #define ADW_ERROR (-1)
623
624
625 /*
626 * Warning code values for AdwInitFrom*EEP() functions
627 */
628 #define ADW_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
629 #define ADW_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
630 #define ADW_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
631 #define ADW_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
632 #define ADW_WARN_ERROR 0xFFFF /* ADW_ERROR return */
633
634 /*
635 * Error code values for AdwInitAsc*Driver() functions
636 */
637 #define ADW_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
638 #define ADW_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
639 #define ADW_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
640 #define ADW_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
641 #define ADW_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
642 #define ADW_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
643 #define ADW_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
644 #define ADW_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
645 #define ADW_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
646 #define ADW_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
647 #define ADW_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
648 #define ADW_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
649 #define ADW_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
650 #define ADW_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
651
652 /*
653 * BIOS LRAM variable absolute offsets.
654 */
655 #define BIOS_CODESEG 0x54
656 #define BIOS_CODELEN 0x56
657 #define BIOS_SIGNATURE 0x58
658 #define BIOS_VERSION 0x5A
659
660 /*
661 * Chip Type flag values
662 */
663 #define ADW_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
664 #define ADW_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
665 #define ADW_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
666
667 /*
668 * Adapter temporary configuration structure
669 *
670 * This structure can be discarded after initialization. Don't add
671 * fields here needed after initialization.
672 *
673 * Field naming convention:
674 *
675 * *_enable indicates the field enables or disables a feature. The
676 * value of the field is never reset.
677 */
678 typedef struct adw_dvc_cfg {
679 u_int16_t disc_enable; /* enable disconnection */
680 u_int8_t chip_version; /* chip version */
681 u_int8_t termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 */
682 u_int16_t pci_device_id; /* PCI device code number */
683 u_int16_t lib_version; /* Adw Library version number */
684 u_int16_t control_flag; /* Microcode Control Flag */
685 u_int16_t mcode_date; /* Microcode date */
686 u_int16_t mcode_version; /* Microcode version */
687 u_int16_t pci_slot_info; /* high byte device/function number
688 bits 7-3 device num.,
689 bits 2-0 function num.
690 low byte bus num. */
691 u_int16_t serial1; /* EEPROM serial number word 1 */
692 u_int16_t serial2; /* EEPROM serial number word 2 */
693 u_int16_t serial3; /* EEPROM serial number word 3 */
694 } ADW_DVC_CFG;
695
696
697 #define NO_OF_SG_PER_BLOCK 15
698
699 typedef struct adw_sg_block {
700 u_int8_t reserved1;
701 u_int8_t reserved2;
702 u_int8_t reserved3;
703 u_int8_t sg_cnt; /* Valid entries in block. */
704 u_int32_t sg_ptr; /* links to next sg block */
705 struct {
706 u_int32_t sg_addr; /* SG element address */
707 u_int32_t sg_count; /* SG element count */
708 } sg_list[NO_OF_SG_PER_BLOCK];
709 } ADW_SG_BLOCK;
710
711
712 /*
713 * ADW_SCSI_REQ_Q - microcode request structure
714 *
715 * All fields in this structure up to byte 60 are used by the microcode.
716 * The microcode makes assumptions about the size and ordering of fields
717 * in this structure. Do not change the structure definition here without
718 * coordinating the change with the microcode.
719 */
720 typedef struct adw_scsi_req_q {
721 u_int8_t cntl; /* Ucode flags and state (ADW_MC_QC_*). */
722 u_int8_t target_cmd;
723 u_int8_t target_id; /* Device target identifier. */
724 u_int8_t target_lun; /* Device target logical unit number. */
725 u_int32_t data_addr; /* Data buffer physical address. */
726 u_int32_t data_cnt; /* Data count. Ucode sets to residual. */
727 u_int32_t sense_addr; /* Sense buffer physical address. */
728 u_int32_t carr_ba; /* Carrier p-address */
729 u_int8_t mflag; /* Adw Library flag field. */
730 u_int8_t sense_len; /* Auto-sense length. uCode sets to residual. */
731 u_int8_t cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
732 u_int8_t scsi_cntl;
733 u_int8_t done_status; /* Completion status. (see below) */
734 u_int8_t scsi_status; /* SCSI status byte. (see below) */
735 u_int8_t host_status; /* ,uCode host status. (see below) */
736 u_int8_t sg_working_ix; /* ,uCode working SG variable. */
737 u_int8_t cdb[12]; /* SCSI CDB bytes 0-11. */
738 u_int32_t sg_real_addr; /* SG list physical address. */
739 u_int32_t scsiq_rptr; /* Internal pointer to ADW_SCSI_REQ_Q */
740 u_int8_t cdb16[4]; /* SCSI CDB bytes 12-15. */
741 u_int32_t ccb_ptr; /* CCB Physical Address */
742 u_int32_t carr_va; /* Carrier v-address (unused) */
743 /*
744 * End of microcode structure - 60 bytes. The rest of the structure
745 * is used by the Adw Library and ignored by the microcode.
746 */
747 struct scsi_sense_data *vsense_addr; /* Sense buffer virtual address. */
748 u_char *vdata_addr; /* Data buffer virtual address. */
749 } ADW_SCSI_REQ_Q;
750
751 /*
752 * ASC_SCSI_REQ_Q 'done_status' return values.
753 */
754 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
755 #define QD_NO_ERROR 0x01
756 #define QD_ABORTED_BY_HOST 0x02
757 #define QD_WITH_ERROR 0x04
758
759 /*
760 * ASC_SCSI_REQ_Q 'host_status' return values.
761 */
762 #define QHSTA_NO_ERROR 0x00
763 #define QHSTA_M_SEL_TIMEOUT 0x11
764 #define QHSTA_M_DATA_OVER_RUN 0x12
765 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
766 #define QHSTA_M_QUEUE_ABORTED 0x15
767 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
768 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
769 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
770 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
771 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
772 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
773 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
774 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
775 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
776 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
777 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
778 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
779 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
780 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
781 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
782 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
783 #define QHSTA_M_WTM_TIMEOUT 0x41
784 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
785 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
786 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
787 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
788 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
789 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
790
791 /*
792 * ASC_SCSI_REQ_Q 'scsi_status' return values.
793 */
794 #define SCSI_STATUS_GOOD 0x00
795 #define SCSI_STATUS_CHECK_CONDITION 0x02
796 #define SCSI_STATUS_CONDITION_MET 0x04
797 #define SCSI_STATUS_TARGET_BUSY 0x08
798 #define SCSI_STATUS_INTERMID 0x10
799 #define SCSI_STATUS_INTERMID_COND_MET 0x14
800 #define SCSI_STATUS_RSERV_CONFLICT 0x18
801 #define SCSI_STATUS_CMD_TERMINATED 0x22
802 #define SCSI_STATUS_QUEUE_FULL 0x28
803
804
805 /*
806 * Adapter operation variable structure.
807 *
808 * One structure is required per host adapter.
809 *
810 * Field naming convention:
811 *
812 * *_able indicates both whether a feature should be enabled or disabled
813 * and whether a device is capable of the feature. At initialization
814 * this field may be set, but later if a device is found to be incapable
815 * of the feature, the field is cleared.
816 */
817 #define CCB_HASH_SIZE 32 /* hash table size for phystokv */
818 #define CCB_HASH_SHIFT 9
819 #define CCB_HASH(x) ((((x)) >> CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1))
820
821 typedef struct adw_softc {
822
823 device_t sc_dev;
824
825 bus_space_tag_t sc_iot;
826 bus_space_handle_t sc_ioh;
827 bus_dma_tag_t sc_dmat;
828 bus_dmamap_t sc_dmamap_control; /* maps the control structures */
829 bus_dmamap_t sc_dmamap_carrier; /* maps the carrier structures */
830 void *sc_ih;
831
832 struct adw_control *sc_control; /* control structures */
833
834 struct adw_ccb *sc_ccbhash[CCB_HASH_SIZE];
835 TAILQ_HEAD(, adw_ccb) sc_free_ccb, sc_waiting_ccb;
836 TAILQ_HEAD(adw_pending_ccb, adw_ccb) sc_pending_ccb;
837 struct scsipi_adapter sc_adapter;
838 struct scsipi_channel sc_channel;
839
840 int sc_freeze_dev[ADW_MAX_TID+1];
841
842 /* pointers to functions, called in AdwISR() */
843 void (*isr_callback)(struct adw_softc *, ADW_SCSI_REQ_Q *);
844 void (*async_callback)(struct adw_softc *, u_int8_t);
845
846 u_int16_t bios_ctrl; /* BIOS control word, EEPROM word 12 */
847 u_int16_t wdtr_able; /* try WDTR for a device */
848 u_int16_t sdtr_able; /* try SDTR for a device */
849 u_int16_t ultra_able; /* try SDTR Ultra speed for a device */
850 u_int16_t sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
851 u_int16_t sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
852 u_int16_t sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
853 u_int16_t sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
854 u_int16_t tagqng_able; /* try tagged queuing with a device */
855 u_int16_t ppr_able; /* PPR message capable per TID bitmask. */
856 u_int16_t start_motor; /* start motor command allowed */
857 u_int8_t max_dvc_qng; /* maximum number of tagged commands per device */
858 u_int8_t scsi_reset_wait; /* delay in seconds after scsi bus reset */
859 u_int8_t chip_no; /* should be assigned by caller */
860 u_int8_t max_host_qng; /* maximum number of Q'ed command allowed */
861 u_int8_t irq_no; /* IRQ number */
862 u_int8_t chip_type; /* chip SCSI target ID */
863 u_int16_t no_scam; /* scam_tolerant of EEPROM */
864 u_int32_t drv_ptr; /* driver pointer to private structure */
865 u_int8_t chip_scsi_id; /* chip SCSI target ID */
866 u_int8_t bist_err_code;
867 u_int16_t carr_pending_cnt; /* Count of pending carriers. */
868 struct adw_carrier *carr_freelist; /* Carrier free list. */
869 struct adw_carrier *icq_sp; /* Initiator command queue stopper pointer. */
870 struct adw_carrier *irq_sp; /* Initiator response queue stopper pointer. */
871 /*
872 * Note: The following fields will not be used after initialization. The
873 * driver may discard the buffer after initialization is done.
874 */
875 ADW_DVC_CFG cfg; /* temporary configuration structure */
876 } ADW_SOFTC;
877
878
879 /*
880 * Microcode idle loop commands
881 */
882 #define IDLE_CMD_COMPLETED 0
883 #define IDLE_CMD_STOP_CHIP 0x0001
884 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
885 #define IDLE_CMD_SEND_INT 0x0004
886 #define IDLE_CMD_ABORT 0x0008
887 #define IDLE_CMD_DEVICE_RESET 0x0010
888 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
889 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
890 #define IDLE_CMD_SCSIREQ 0x0080
891
892 #define IDLE_CMD_STATUS_SUCCESS 0x0001
893 #define IDLE_CMD_STATUS_FAILURE 0x0002
894
895 /*
896 * AdwSendIdleCmd() flag definitions.
897 */
898 #define ADW_NOWAIT 0x01
899
900 /*
901 * Wait loop time out values.
902 */
903 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
904 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
905 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
906 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
907 #define SCSI_MAX_RETRY 10 /* retry count */
908
909 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
910 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
911 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
912
913 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
914
915
916 /* Read byte from a register. */
917 #define ADW_READ_BYTE_REGISTER(iot, ioh, reg_off) \
918 bus_space_read_1((iot), (ioh), (reg_off))
919
920 /* Write byte to a register. */
921 #define ADW_WRITE_BYTE_REGISTER(iot, ioh, reg_off, byte) \
922 bus_space_write_1((iot), (ioh), (reg_off), (byte))
923
924 /* Read word (2 bytes) from a register. */
925 #define ADW_READ_WORD_REGISTER(iot, ioh, reg_off) \
926 bus_space_read_2((iot), (ioh), (reg_off))
927
928 /* Write word (2 bytes) to a register. */
929 #define ADW_WRITE_WORD_REGISTER(iot, ioh, reg_off, word) \
930 bus_space_write_2((iot), (ioh), (reg_off), (word))
931
932 /* Write double word (4 bytes) to a register. */
933 #define ADW_WRITE_DWORD_REGISTER(iot, ioh, reg_off, dword) \
934 bus_space_write_4((iot), (ioh), (reg_off), (dword))
935
936 /* Read byte from LRAM. */
937 #define ADW_READ_BYTE_LRAM(iot, ioh, addr, byte) \
938 do { \
939 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
940 (byte) = bus_space_read_1((iot), (ioh), IOPB_RAM_DATA); \
941 } while (0)
942
943 /* Write byte to LRAM. */
944 #define ADW_WRITE_BYTE_LRAM(iot, ioh, addr, byte) \
945 do { \
946 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
947 bus_space_write_1((iot), (ioh), IOPB_RAM_DATA, (byte)); \
948 } while (0)
949
950 /* Read word (2 bytes) from LRAM. */
951 #define ADW_READ_WORD_LRAM(iot, ioh, addr, word) \
952 do { \
953 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
954 (word) = bus_space_read_2((iot), (ioh), IOPW_RAM_DATA); \
955 } while (0)
956
957 /* Write word (2 bytes) to LRAM. */
958 #define ADW_WRITE_WORD_LRAM(iot, ioh, addr, word) \
959 do { \
960 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
961 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word)); \
962 } while (0)
963
964 /* Write double word (4 bytes) to LRAM */
965 /* Because of unspecified C language ordering don't use auto-increment. */
966 #define ADW_WRITE_DWORD_LRAM(iot, ioh, addr, dword) \
967 do { \
968 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr)); \
969 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \
970 (u_int16_t) ((dword) & 0xFFFF)); \
971 bus_space_write_2((iot), (ioh), IOPW_RAM_ADDR, (addr) + 2); \
972 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, \
973 (u_int16_t) ((dword >> 16) & 0xFFFF)); \
974 } while (0)
975
976 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
977 #define ADW_READ_WORD_AUTO_INC_LRAM(iot, ioh) \
978 bus_space_read_2((iot), (ioh), IOPW_RAM_DATA) \
979
980 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
981 #define ADW_WRITE_WORD_AUTO_INC_LRAM(iot, ioh, word) \
982 bus_space_write_2((iot), (ioh), IOPW_RAM_DATA, (word))
983
984 /*
985 * Define macro to check for Condor signature.
986 *
987 * Evaluate to ADW_TRUE if a Condor chip is found the specified port
988 * address 'iop_base'. Otherwise evalue to ADW_FALSE.
989 */
990 #define ADW_FIND_SIGNATURE(iot, ioh) \
991 (((ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_ID_1) == \
992 ADW_CHIP_ID_BYTE) && \
993 (ADW_READ_WORD_REGISTER((iot), (ioh), IOPW_CHIP_ID_0) == \
994 ADW_CHIP_ID_WORD)) ? ADW_TRUE : ADW_FALSE)
995
996 /*
997 * Define macro to Return the version number of the chip at 'iop_base'.
998 *
999 * The second parameter 'bus_type' is currently unused.
1000 */
1001 #define ADW_GET_CHIP_VERSION(iot, ioh, bus_type) \
1002 ADW_READ_BYTE_REGISTER((iot), (ioh), IOPB_CHIP_TYPE_REV)
1003
1004 /*
1005 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
1006 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
1007 *
1008 * If the request has not yet been sent to the device it will simply be
1009 * aborted from RISC memory. If the request is disconnected it will be
1010 * aborted on reselection by sending an Abort Message to the target ID.
1011 *
1012 * Return value:
1013 * ADW_TRUE(1) - Queue was successfully aborted.
1014 * ADW_FALSE(0) - Queue was not found on the active queue list.
1015 */
1016 #define ADW_ABORT_CCB(sc, ccb_ptr) \
1017 AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_ABORT, (ccb_ptr)->hashkey)
1018
1019 /*
1020 * Send a Bus Device Reset Message to the specified target ID.
1021 *
1022 * All outstanding commands will be purged if sending the
1023 * Bus Device Reset Message is successful.
1024 *
1025 * Return Value:
1026 * ADW_TRUE(1) - All requests on the target are purged.
1027 * ADW_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
1028 * are not purged.
1029 */
1030 #define ADW_RESET_DEVICE(sc, target_id) \
1031 AdwSendIdleCmd((sc), (u_int16_t) IDLE_CMD_DEVICE_RESET, (target_id), 0)
1032
1033 /*
1034 * SCSI Wide Type definition.
1035 */
1036 #define ADW_SCSI_BIT_ID_TYPE u_int16_t
1037
1038 /*
1039 * AdwInitScsiTarget() 'cntl_flag' options.
1040 */
1041 #define ADW_SCAN_LUN 0x01
1042 #define ADW_CAPINFO_NOLUN 0x02
1043
1044 /*
1045 * Convert target id to target id bit mask.
1046 */
1047 #define ADW_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADW_MAX_TID))
1048
1049 /*
1050 * Adv Library functions available to drivers.
1051 */
1052
1053 int AdwInitFromEEPROM(ADW_SOFTC *);
1054 int AdwInitDriver(ADW_SOFTC *);
1055 int AdwExeScsiQueue(ADW_SOFTC *, ADW_SCSI_REQ_Q *);
1056 int AdwISR(ADW_SOFTC *);
1057 void AdwResetChip(bus_space_tag_t, bus_space_handle_t);
1058 int AdwSendIdleCmd(ADW_SOFTC *, u_int16_t, u_int32_t);
1059 int AdwResetSCSIBus(ADW_SOFTC *);
1060 int AdwResetCCB(ADW_SOFTC *);
1061
1062 #endif /* _ADVANSYS_WIDE_LIBRARY_H_ */
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