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sys/dev/ic/ahcisata_core.c
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1 /* $NetBSD: ahcisata_core.c,v 1.18.4.5 2011/01/16 13:06:49 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: ahcisata_core.c,v 1.18.4.5 2011/01/16 13:06:49 bouyer Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/malloc.h> 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/disklabel.h> 42 #include <sys/proc.h> 43 #include <sys/buf.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #include <dev/ic/wdcreg.h> 48 #include <dev/ata/atareg.h> 49 #include <dev/ata/satavar.h> 50 #include <dev/ata/satareg.h> 51 #include <dev/ic/ahcisatavar.h> 52 53 #include <dev/scsipi/scsi_all.h> /* for SCSI status */ 54 55 #include "atapibus.h" 56 57 #ifdef AHCI_DEBUG 58 int ahcidebug_mask = 0x0; 59 #endif 60 61 void ahci_probe_drive(struct ata_channel *); 62 void ahci_setup_channel(struct ata_channel *); 63 64 int ahci_ata_bio(struct ata_drive_datas *, struct ata_bio *); 65 void ahci_reset_drive(struct ata_drive_datas *, int); 66 void ahci_reset_channel(struct ata_channel *, int); 67 int ahci_exec_command(struct ata_drive_datas *, struct ata_command *); 68 int ahci_ata_addref(struct ata_drive_datas *); 69 void ahci_ata_delref(struct ata_drive_datas *); 70 void ahci_killpending(struct ata_drive_datas *); 71 72 void ahci_cmd_start(struct ata_channel *, struct ata_xfer *); 73 int ahci_cmd_complete(struct ata_channel *, struct ata_xfer *, int); 74 void ahci_cmd_done(struct ata_channel *, struct ata_xfer *, int); 75 void ahci_cmd_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 76 void ahci_bio_start(struct ata_channel *, struct ata_xfer *); 77 int ahci_bio_complete(struct ata_channel *, struct ata_xfer *, int); 78 void ahci_bio_kill_xfer(struct ata_channel *, struct ata_xfer *, int) ; 79 void ahci_channel_stop(struct ahci_softc *, struct ata_channel *, int); 80 void ahci_channel_start(struct ahci_softc *, struct ata_channel *); 81 void ahci_timeout(void *); 82 int ahci_dma_setup(struct ata_channel *, int, void *, size_t, int); 83 84 #if NATAPIBUS > 0 85 void ahci_atapibus_attach(struct atabus_softc *); 86 void ahci_atapi_kill_pending(struct scsipi_periph *); 87 void ahci_atapi_minphys(struct buf *); 88 void ahci_atapi_scsipi_request(struct scsipi_channel *, 89 scsipi_adapter_req_t, void *); 90 void ahci_atapi_start(struct ata_channel *, struct ata_xfer *); 91 int ahci_atapi_complete(struct ata_channel *, struct ata_xfer *, int); 92 void ahci_atapi_kill_xfer(struct ata_channel *, struct ata_xfer *, int); 93 void ahci_atapi_probe_device(struct atapibus_softc *, int); 94 95 static const struct scsipi_bustype ahci_atapi_bustype = { 96 SCSIPI_BUSTYPE_ATAPI, 97 atapi_scsipi_cmd, 98 atapi_interpret_sense, 99 atapi_print_addr, 100 ahci_atapi_kill_pending, 101 }; 102 #endif /* NATAPIBUS */ 103 104 #define ATA_DELAY 10000 /* 10s for a drive I/O */ 105 #define ATA_RESET_DELAY 31000 /* 31s for a drive reset */ 106 #define AHCI_RST_WAIT (ATA_RESET_DELAY / 10) 107 108 const struct ata_bustype ahci_ata_bustype = { 109 SCSIPI_BUSTYPE_ATA, 110 ahci_ata_bio, 111 ahci_reset_drive, 112 ahci_reset_channel, 113 ahci_exec_command, 114 ata_get_params, 115 ahci_ata_addref, 116 ahci_ata_delref, 117 ahci_killpending 118 }; 119 120 void ahci_intr_port(struct ahci_softc *, struct ahci_channel *); 121 122 static void ahci_setup_port(struct ahci_softc *sc, int i); 123 124 int 125 ahci_reset(struct ahci_softc *sc) 126 { 127 int i; 128 129 /* reset controller */ 130 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_HR); 131 /* wait up to 1s for reset to complete */ 132 for (i = 0; i < 1000; i++) { 133 delay(1000); 134 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR) == 0) 135 break; 136 } 137 if ((AHCI_READ(sc, AHCI_GHC) & AHCI_GHC_HR)) { 138 aprint_error("%s: reset failed\n", AHCINAME(sc)); 139 return -1; 140 } 141 /* enable ahci mode */ 142 AHCI_WRITE(sc, AHCI_GHC, AHCI_GHC_AE); 143 return 0; 144 } 145 146 void 147 ahci_setup_ports(struct ahci_softc *sc) 148 { 149 u_int32_t ahci_ports; 150 int i, port; 151 152 ahci_ports = AHCI_READ(sc, AHCI_PI); 153 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 154 if ((ahci_ports & (1 << i)) == 0) 155 continue; 156 if (port >= sc->sc_atac.atac_nchannels) { 157 aprint_error("%s: more ports than announced\n", 158 AHCINAME(sc)); 159 break; 160 } 161 ahci_setup_port(sc, i); 162 } 163 } 164 165 void 166 ahci_reprobe_drives(struct ahci_softc *sc) 167 { 168 u_int32_t ahci_ports; 169 int i, port; 170 struct ahci_channel *achp; 171 struct ata_channel *chp; 172 173 ahci_ports = AHCI_READ(sc, AHCI_PI); 174 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 175 if ((ahci_ports & (1 << i)) == 0) 176 continue; 177 if (port >= sc->sc_atac.atac_nchannels) { 178 aprint_error("%s: more ports than announced\n", 179 AHCINAME(sc)); 180 break; 181 } 182 achp = &sc->sc_channels[i]; 183 chp = &achp->ata_channel; 184 185 ahci_probe_drive(chp); 186 } 187 } 188 189 static void 190 ahci_setup_port(struct ahci_softc *sc, int i) 191 { 192 struct ahci_channel *achp; 193 194 achp = &sc->sc_channels[i]; 195 196 AHCI_WRITE(sc, AHCI_P_CLB(i), achp->ahcic_bus_cmdh); 197 AHCI_WRITE(sc, AHCI_P_CLBU(i), 0); 198 AHCI_WRITE(sc, AHCI_P_FB(i), achp->ahcic_bus_rfis); 199 AHCI_WRITE(sc, AHCI_P_FBU(i), 0); 200 } 201 202 void 203 ahci_enable_intrs(struct ahci_softc *sc) 204 { 205 206 /* clear interrupts */ 207 AHCI_WRITE(sc, AHCI_IS, AHCI_READ(sc, AHCI_IS)); 208 /* enable interrupts */ 209 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 210 } 211 212 void 213 ahci_attach(struct ahci_softc *sc) 214 { 215 u_int32_t ahci_cap, ahci_rev, ahci_ports; 216 int i, j, port; 217 struct ahci_channel *achp; 218 struct ata_channel *chp; 219 int error; 220 bus_dma_segment_t seg; 221 int rseg; 222 int dmasize; 223 void *cmdhp; 224 void *cmdtblp; 225 226 if (ahci_reset(sc) != 0) 227 return; 228 229 ahci_cap = AHCI_READ(sc, AHCI_CAP); 230 sc->sc_atac.atac_nchannels = (ahci_cap & AHCI_CAP_NPMASK) + 1; 231 sc->sc_ncmds = ((ahci_cap & AHCI_CAP_NCS) >> 8) + 1; 232 ahci_rev = AHCI_READ(sc, AHCI_VS); 233 aprint_normal("%s: AHCI revision ", AHCINAME(sc)); 234 switch(ahci_rev) { 235 case AHCI_VS_10: 236 aprint_normal("1.0"); 237 break; 238 case AHCI_VS_11: 239 aprint_normal("1.1"); 240 break; 241 case AHCI_VS_12: 242 aprint_normal("1.2"); 243 break; 244 default: 245 aprint_normal("0x%x", ahci_rev); 246 break; 247 } 248 249 aprint_normal(", %d ports, %d command slots, features 0x%x\n", 250 sc->sc_atac.atac_nchannels, sc->sc_ncmds, 251 ahci_cap & ~(AHCI_CAP_NPMASK|AHCI_CAP_NCS)); 252 sc->sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DMA | ATAC_CAP_UDMA; 253 sc->sc_atac.atac_cap |= sc->sc_atac_capflags; 254 sc->sc_atac.atac_pio_cap = 4; 255 sc->sc_atac.atac_dma_cap = 2; 256 sc->sc_atac.atac_udma_cap = 6; 257 sc->sc_atac.atac_channels = sc->sc_chanarray; 258 sc->sc_atac.atac_probe = ahci_probe_drive; 259 sc->sc_atac.atac_bustype_ata = &ahci_ata_bustype; 260 sc->sc_atac.atac_set_modes = ahci_setup_channel; 261 #if NATAPIBUS > 0 262 sc->sc_atac.atac_atapibus_attach = ahci_atapibus_attach; 263 #endif 264 265 dmasize = 266 (AHCI_RFIS_SIZE + AHCI_CMDH_SIZE) * sc->sc_atac.atac_nchannels; 267 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 268 &seg, 1, &rseg, BUS_DMA_NOWAIT); 269 if (error) { 270 aprint_error("%s: unable to allocate command header memory" 271 ", error=%d\n", AHCINAME(sc), error); 272 return; 273 } 274 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 275 &cmdhp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 276 if (error) { 277 aprint_error("%s: unable to map command header memory" 278 ", error=%d\n", AHCINAME(sc), error); 279 return; 280 } 281 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 282 BUS_DMA_NOWAIT, &sc->sc_cmd_hdrd); 283 if (error) { 284 aprint_error("%s: unable to create command header map" 285 ", error=%d\n", AHCINAME(sc), error); 286 return; 287 } 288 error = bus_dmamap_load(sc->sc_dmat, sc->sc_cmd_hdrd, 289 cmdhp, dmasize, NULL, BUS_DMA_NOWAIT); 290 if (error) { 291 aprint_error("%s: unable to load command header map" 292 ", error=%d\n", AHCINAME(sc), error); 293 return; 294 } 295 sc->sc_cmd_hdr = cmdhp; 296 297 ahci_enable_intrs(sc); 298 299 ahci_ports = AHCI_READ(sc, AHCI_PI); 300 for (i = 0, port = 0; i < AHCI_MAX_PORTS; i++) { 301 if ((ahci_ports & (1 << i)) == 0) 302 continue; 303 if (port >= sc->sc_atac.atac_nchannels) { 304 aprint_error("%s: more ports than announced\n", 305 AHCINAME(sc)); 306 break; 307 } 308 achp = &sc->sc_channels[i]; 309 chp = (struct ata_channel *)achp; 310 sc->sc_chanarray[i] = chp; 311 chp->ch_channel = i; 312 chp->ch_atac = &sc->sc_atac; 313 chp->ch_queue = malloc(sizeof(struct ata_queue), 314 M_DEVBUF, M_NOWAIT); 315 if (chp->ch_queue == NULL) { 316 aprint_error("%s port %d: can't allocate memory for " 317 "command queue", AHCINAME(sc), i); 318 break; 319 } 320 dmasize = AHCI_CMDTBL_SIZE * sc->sc_ncmds; 321 error = bus_dmamem_alloc(sc->sc_dmat, dmasize, PAGE_SIZE, 0, 322 &seg, 1, &rseg, BUS_DMA_NOWAIT); 323 if (error) { 324 aprint_error("%s: unable to allocate command table " 325 "memory, error=%d\n", AHCINAME(sc), error); 326 break; 327 } 328 error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, dmasize, 329 &cmdtblp, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 330 if (error) { 331 aprint_error("%s: unable to map command table memory" 332 ", error=%d\n", AHCINAME(sc), error); 333 break; 334 } 335 error = bus_dmamap_create(sc->sc_dmat, dmasize, 1, dmasize, 0, 336 BUS_DMA_NOWAIT, &achp->ahcic_cmd_tbld); 337 if (error) { 338 aprint_error("%s: unable to create command table map" 339 ", error=%d\n", AHCINAME(sc), error); 340 break; 341 } 342 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_cmd_tbld, 343 cmdtblp, dmasize, NULL, BUS_DMA_NOWAIT); 344 if (error) { 345 aprint_error("%s: unable to load command table map" 346 ", error=%d\n", AHCINAME(sc), error); 347 break; 348 } 349 achp->ahcic_cmdh = (struct ahci_cmd_header *) 350 ((char *)cmdhp + AHCI_CMDH_SIZE * port); 351 achp->ahcic_bus_cmdh = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 352 AHCI_CMDH_SIZE * port; 353 achp->ahcic_rfis = (struct ahci_r_fis *) 354 ((char *)cmdhp + 355 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 356 AHCI_RFIS_SIZE * port); 357 achp->ahcic_bus_rfis = sc->sc_cmd_hdrd->dm_segs[0].ds_addr + 358 AHCI_CMDH_SIZE * sc->sc_atac.atac_nchannels + 359 AHCI_RFIS_SIZE * port; 360 AHCIDEBUG_PRINT(("port %d cmdh %p (0x%x) rfis %p (0x%x)\n", i, 361 achp->ahcic_cmdh, (u_int)achp->ahcic_bus_cmdh, 362 achp->ahcic_rfis, (u_int)achp->ahcic_bus_rfis), 363 DEBUG_PROBE); 364 365 for (j = 0; j < sc->sc_ncmds; j++) { 366 achp->ahcic_cmd_tbl[j] = (struct ahci_cmd_tbl *) 367 ((char *)cmdtblp + AHCI_CMDTBL_SIZE * j); 368 achp->ahcic_bus_cmd_tbl[j] = 369 achp->ahcic_cmd_tbld->dm_segs[0].ds_addr + 370 AHCI_CMDTBL_SIZE * j; 371 achp->ahcic_cmdh[j].cmdh_cmdtba = 372 htole32(achp->ahcic_bus_cmd_tbl[j]); 373 achp->ahcic_cmdh[j].cmdh_cmdtbau = htole32(0); 374 AHCIDEBUG_PRINT(("port %d/%d tbl %p (0x%x)\n", i, j, 375 achp->ahcic_cmd_tbl[j], 376 (u_int)achp->ahcic_bus_cmd_tbl[j]), DEBUG_PROBE); 377 /* The xfer DMA map */ 378 error = bus_dmamap_create(sc->sc_dmat, MAXPHYS, 379 AHCI_NPRD, 0x400000 /* 4MB */, 0, 380 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 381 &achp->ahcic_datad[j]); 382 if (error) { 383 aprint_error("%s: couldn't alloc xfer DMA map, " 384 "error=%d\n", AHCINAME(sc), error); 385 goto end; 386 } 387 } 388 ahci_setup_port(sc, i); 389 chp->ch_ndrive = 1; 390 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 391 AHCI_P_SSTS(i), 1, &achp->ahcic_sstatus) != 0) { 392 aprint_error("%s: couldn't map channel %d " 393 "sata_status regs\n", AHCINAME(sc), i); 394 break; 395 } 396 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 397 AHCI_P_SCTL(i), 1, &achp->ahcic_scontrol) != 0) { 398 aprint_error("%s: couldn't map channel %d " 399 "sata_control regs\n", AHCINAME(sc), i); 400 break; 401 } 402 if (bus_space_subregion(sc->sc_ahcit, sc->sc_ahcih, 403 AHCI_P_SERR(i), 1, &achp->ahcic_serror) != 0) { 404 aprint_error("%s: couldn't map channel %d " 405 "sata_error regs\n", AHCINAME(sc), i); 406 break; 407 } 408 ata_channel_attach(chp); 409 port++; 410 end: 411 continue; 412 } 413 } 414 415 int 416 ahci_intr(void *v) 417 { 418 struct ahci_softc *sc = v; 419 u_int32_t is; 420 int i, r = 0; 421 422 while ((is = AHCI_READ(sc, AHCI_IS))) { 423 AHCIDEBUG_PRINT(("%s ahci_intr 0x%x\n", AHCINAME(sc), is), 424 DEBUG_INTR); 425 r = 1; 426 AHCI_WRITE(sc, AHCI_IS, is); 427 for (i = 0; i < AHCI_MAX_PORTS; i++) 428 if (is & (1 << i)) 429 ahci_intr_port(sc, &sc->sc_channels[i]); 430 } 431 return r; 432 } 433 434 void 435 ahci_intr_port(struct ahci_softc *sc, struct ahci_channel *achp) 436 { 437 u_int32_t is, tfd; 438 struct ata_channel *chp = &achp->ata_channel; 439 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 440 int slot; 441 442 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 443 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), is); 444 AHCIDEBUG_PRINT(("ahci_intr_port %s port %d is 0x%x CI 0x%x\n", AHCINAME(sc), 445 chp->ch_channel, is, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 446 DEBUG_INTR); 447 448 if (is & (AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 449 AHCI_P_IX_OFS | AHCI_P_IX_UFS)) { 450 slot = (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) 451 & AHCI_P_CMD_CCS_MASK) >> AHCI_P_CMD_CCS_SHIFT; 452 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 453 return; 454 /* stop channel */ 455 ahci_channel_stop(sc, chp, 0); 456 if (slot != 0) { 457 printf("ahci_intr_port: slot %d\n", slot); 458 panic("ahci_intr_port"); 459 } 460 if (is & AHCI_P_IX_TFES) { 461 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 462 chp->ch_error = 463 (tfd & AHCI_P_TFD_ERR_MASK) >> AHCI_P_TFD_ERR_SHIFT; 464 chp->ch_status = (tfd & 0xff); 465 } else { 466 /* emulate a CRC error */ 467 chp->ch_error = WDCE_CRC; 468 chp->ch_status = WDCS_ERR; 469 } 470 xfer->c_intr(chp, xfer, is); 471 /* if channel has not been restarted, do it now */ 472 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 473 == 0) 474 ahci_channel_start(sc, chp); 475 } else { 476 slot = 0; /* XXX */ 477 is = AHCI_READ(sc, AHCI_P_IS(chp->ch_channel)); 478 AHCIDEBUG_PRINT(("ahci_intr_port port %d is 0x%x act 0x%x CI 0x%x\n", 479 chp->ch_channel, is, achp->ahcic_cmds_active, 480 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_INTR); 481 if ((achp->ahcic_cmds_active & (1 << slot)) == 0) 482 return; 483 if ((AHCI_READ(sc, AHCI_P_CI(chp->ch_channel)) & (1 << slot)) 484 == 0) { 485 xfer->c_intr(chp, xfer, 0); 486 } 487 } 488 } 489 490 void 491 ahci_reset_drive(struct ata_drive_datas *drvp, int flags) 492 { 493 struct ata_channel *chp = drvp->chnl_softc; 494 ata_reset_channel(chp, flags); 495 return; 496 } 497 498 void 499 ahci_reset_channel(struct ata_channel *chp, int flags) 500 { 501 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 502 struct ahci_channel *achp = (struct ahci_channel *)chp; 503 int i, tfd; 504 505 ahci_channel_stop(sc, chp, flags); 506 if (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 507 achp->ahcic_sstatus) != SStatus_DET_DEV) { 508 printf("%s: port reset failed\n", AHCINAME(sc)); 509 /* XXX and then ? */ 510 } 511 if (chp->ch_queue->active_xfer) { 512 chp->ch_queue->active_xfer->c_kill_xfer(chp, 513 chp->ch_queue->active_xfer, KILL_RESET); 514 } 515 tsleep(&sc, PRIBIO, "ahcirst", mstohz(500)); 516 /* clear port interrupt register */ 517 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 518 /* clear SErrors and start operations */ 519 ahci_channel_start(sc, chp); 520 /* wait 31s for BSY to clear */ 521 for (i = 0; i <AHCI_RST_WAIT; i++) { 522 tfd = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 523 if ((((tfd & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 524 & WDCS_BSY) == 0) 525 break; 526 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 527 } 528 if (i == AHCI_RST_WAIT) 529 aprint_error("%s: BSY never cleared, TD 0x%x\n", 530 AHCINAME(sc), tfd); 531 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 532 DEBUG_PROBE); 533 /* clear port interrupt register */ 534 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 535 536 return; 537 } 538 539 int 540 ahci_ata_addref(struct ata_drive_datas *drvp) 541 { 542 return 0; 543 } 544 545 void 546 ahci_ata_delref(struct ata_drive_datas *drvp) 547 { 548 return; 549 } 550 551 void 552 ahci_killpending(struct ata_drive_datas *drvp) 553 { 554 return; 555 } 556 557 void 558 ahci_probe_drive(struct ata_channel *chp) 559 { 560 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 561 struct ahci_channel *achp = (struct ahci_channel *)chp; 562 int i, s; 563 u_int32_t sig; 564 565 /* XXX This should be done by other code. */ 566 for (i = 0; i < chp->ch_ndrive; i++) { 567 chp->ch_drive[i].chnl_softc = chp; 568 chp->ch_drive[i].drive = i; 569 } 570 571 /* bring interface up, accept FISs, power up and spin up device */ 572 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 573 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_FRE | 574 AHCI_P_CMD_POD | AHCI_P_CMD_SUD); 575 /* reset the PHY and bring online */ 576 switch (sata_reset_interface(chp, sc->sc_ahcit, achp->ahcic_scontrol, 577 achp->ahcic_sstatus)) { 578 case SStatus_DET_DEV: 579 tsleep(&sc, PRIBIO, "ahcidv", mstohz(500)); 580 /* clear port interrupt register */ 581 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 582 /* clear SErrors and start operations */ 583 ahci_channel_start(sc, chp); 584 /* wait 31s for BSY to clear */ 585 for (i = 0; i <AHCI_RST_WAIT; i++) { 586 sig = AHCI_READ(sc, AHCI_P_TFD(chp->ch_channel)); 587 if ((((sig & AHCI_P_TFD_ST) >> AHCI_P_TFD_ST_SHIFT) 588 & WDCS_BSY) == 0) 589 break; 590 tsleep(&sc, PRIBIO, "ahcid2h", mstohz(10)); 591 } 592 if (i == AHCI_RST_WAIT) { 593 aprint_error("%s: BSY never cleared, TD 0x%x\n", 594 AHCINAME(sc), sig); 595 return; 596 } 597 AHCIDEBUG_PRINT(("%s: BSY took %d ms\n", AHCINAME(sc), i * 10), 598 DEBUG_PROBE); 599 sig = AHCI_READ(sc, AHCI_P_SIG(chp->ch_channel)); 600 AHCIDEBUG_PRINT(("%s: port %d: sig=0x%x CMD=0x%x\n", 601 AHCINAME(sc), chp->ch_channel, sig, 602 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel))), DEBUG_PROBE); 603 /* 604 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 605 * cases we get wrong values here, so ignore it. 606 */ 607 s = splbio(); 608 if ((sig & 0xffff0000) == 0xeb140000) { 609 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 610 } else 611 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 612 splx(s); 613 /* clear port interrupt register */ 614 AHCI_WRITE(sc, AHCI_P_IS(chp->ch_channel), 0xffffffff); 615 /* and enable interrupts */ 616 AHCI_WRITE(sc, AHCI_P_IE(chp->ch_channel), 617 AHCI_P_IX_TFES | AHCI_P_IX_HBFS | AHCI_P_IX_IFS | 618 AHCI_P_IX_OFS | AHCI_P_IX_DPS | AHCI_P_IX_UFS | 619 AHCI_P_IX_DHRS); 620 /* wait 500ms before actually starting operations */ 621 tsleep(&sc, PRIBIO, "ahciprb", mstohz(500)); 622 break; 623 624 default: 625 break; 626 } 627 } 628 629 void 630 ahci_setup_channel(struct ata_channel *chp) 631 { 632 return; 633 } 634 635 int 636 ahci_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 637 { 638 struct ata_channel *chp = drvp->chnl_softc; 639 struct ata_xfer *xfer; 640 int ret; 641 int s; 642 643 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 644 AHCIDEBUG_PRINT(("ahci_exec_command port %d CI 0x%x\n", 645 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 646 DEBUG_XFERS); 647 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 648 ATAXF_NOSLEEP); 649 if (xfer == NULL) { 650 return ATACMD_TRY_AGAIN; 651 } 652 if (ata_c->flags & AT_POLL) 653 xfer->c_flags |= C_POLL; 654 if (ata_c->flags & AT_WAIT) 655 xfer->c_flags |= C_WAIT; 656 xfer->c_drive = drvp->drive; 657 xfer->c_databuf = ata_c->data; 658 xfer->c_bcount = ata_c->bcount; 659 xfer->c_cmd = ata_c; 660 xfer->c_start = ahci_cmd_start; 661 xfer->c_intr = ahci_cmd_complete; 662 xfer->c_kill_xfer = ahci_cmd_kill_xfer; 663 s = splbio(); 664 ata_exec_xfer(chp, xfer); 665 #ifdef DIAGNOSTIC 666 if ((ata_c->flags & AT_POLL) != 0 && 667 (ata_c->flags & AT_DONE) == 0) 668 panic("ahci_exec_command: polled command not done"); 669 #endif 670 if (ata_c->flags & AT_DONE) { 671 ret = ATACMD_COMPLETE; 672 } else { 673 if (ata_c->flags & AT_WAIT) { 674 while ((ata_c->flags & AT_DONE) == 0) { 675 tsleep(ata_c, PRIBIO, "ahcicmd", 0); 676 } 677 ret = ATACMD_COMPLETE; 678 } else { 679 ret = ATACMD_QUEUED; 680 } 681 } 682 splx(s); 683 return ret; 684 } 685 686 void 687 ahci_cmd_start(struct ata_channel *chp, struct ata_xfer *xfer) 688 { 689 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 690 struct ahci_channel *achp = (struct ahci_channel *)chp; 691 struct ata_command *ata_c = xfer->c_cmd; 692 int slot = 0 /* XXX slot */; 693 struct ahci_cmd_tbl *cmd_tbl; 694 struct ahci_cmd_header *cmd_h; 695 u_int8_t *fis; 696 int i; 697 int channel = chp->ch_channel; 698 699 AHCIDEBUG_PRINT(("ahci_cmd_start CI 0x%x\n", 700 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 701 702 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 703 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 704 cmd_tbl), DEBUG_XFERS); 705 fis = cmd_tbl->cmdt_cfis; 706 707 fis[0] = 0x27; /* host to device */ 708 fis[1] = 0x80; /* command FIS */ 709 fis[2] = ata_c->r_command; 710 fis[3] = ata_c->r_features; 711 fis[4] = ata_c->r_sector; 712 fis[5] = ata_c->r_cyl & 0xff; 713 fis[6] = (ata_c->r_cyl >> 8) & 0xff; 714 fis[7] = ata_c->r_head & 0x0f; 715 fis[8] = 0; 716 fis[9] = 0; 717 fis[10] = 0; 718 fis[11] = 0; 719 fis[12] = ata_c->r_count; 720 fis[13] = 0; 721 fis[14] = 0; 722 fis[15] = WDCTL_4BIT; 723 fis[16] = 0; 724 fis[17] = 0; 725 fis[18] = 0; 726 fis[19] = 0; 727 728 cmd_h = &achp->ahcic_cmdh[slot]; 729 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 730 chp->ch_channel, cmd_h), DEBUG_XFERS); 731 if (ahci_dma_setup(chp, slot, 732 (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) ? 733 ata_c->data : NULL, 734 ata_c->bcount, 735 (ata_c->flags & AT_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 736 ata_c->flags |= AT_DF; 737 ahci_cmd_complete(chp, xfer, slot); 738 return; 739 } 740 cmd_h->cmdh_flags = htole16( 741 ((ata_c->flags & AT_WRITE) ? AHCI_CMDH_F_WR : 0) | 742 20 /* fis lenght */ / 4); 743 cmd_h->cmdh_prdbc = 0; 744 AHCI_CMDH_SYNC(sc, achp, slot, 745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 747 if (ata_c->flags & AT_POLL) { 748 /* polled command, disable interrupts */ 749 AHCI_WRITE(sc, AHCI_GHC, 750 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 751 } 752 chp->ch_flags |= ATACH_IRQ_WAIT; 753 chp->ch_status = 0; 754 /* start command */ 755 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 756 /* and says we started this command */ 757 achp->ahcic_cmds_active |= 1 << slot; 758 759 if ((ata_c->flags & AT_POLL) == 0) { 760 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 761 callout_reset(&chp->ch_callout, mstohz(ata_c->timeout), 762 ahci_timeout, chp); 763 return; 764 } 765 /* 766 * Polled command. 767 */ 768 for (i = 0; i < ata_c->timeout / 10; i++) { 769 if (ata_c->flags & AT_DONE) 770 break; 771 ahci_intr_port(sc, achp); 772 if (ata_c->flags & AT_WAIT) 773 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 774 else 775 delay(10000); 776 } 777 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 778 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 779 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 780 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 781 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 782 DEBUG_XFERS); 783 if ((ata_c->flags & AT_DONE) == 0) { 784 ata_c->flags |= AT_TIMEOU; 785 ahci_cmd_complete(chp, xfer, slot); 786 } 787 /* reenable interrupts */ 788 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 789 } 790 791 void 792 ahci_cmd_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 793 { 794 struct ata_command *ata_c = xfer->c_cmd; 795 AHCIDEBUG_PRINT(("ahci_cmd_kill_xfer channel %d\n", chp->ch_channel), 796 DEBUG_FUNCS); 797 798 switch (reason) { 799 case KILL_GONE: 800 ata_c->flags |= AT_GONE; 801 break; 802 case KILL_RESET: 803 ata_c->flags |= AT_RESET; 804 break; 805 default: 806 printf("ahci_cmd_kill_xfer: unknown reason %d\n", reason); 807 panic("ahci_cmd_kill_xfer"); 808 } 809 ahci_cmd_done(chp, xfer, 0 /* XXX slot */); 810 } 811 812 int 813 ahci_cmd_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 814 { 815 int slot = 0; /* XXX slot */ 816 struct ata_command *ata_c = xfer->c_cmd; 817 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 818 819 AHCIDEBUG_PRINT(("ahci_cmd_complete channel %d CMD 0x%x CI 0x%x\n", 820 chp->ch_channel, AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)), 821 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 822 DEBUG_FUNCS); 823 chp->ch_flags &= ~ATACH_IRQ_WAIT; 824 if (xfer->c_flags & C_TIMEOU) { 825 ata_c->flags |= AT_TIMEOU; 826 } else 827 callout_stop(&chp->ch_callout); 828 829 chp->ch_queue->active_xfer = NULL; 830 831 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 832 ahci_cmd_kill_xfer(chp, xfer, KILL_GONE); 833 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 834 wakeup(&chp->ch_queue->active_xfer); 835 return 0; 836 } 837 if (is) { 838 ata_c->r_head = 0; 839 ata_c->r_count = 0; 840 ata_c->r_sector = 0; 841 ata_c->r_cyl = 0; 842 if (chp->ch_status & WDCS_BSY) { 843 ata_c->flags |= AT_TIMEOU; 844 } else if (chp->ch_status & WDCS_ERR) { 845 ata_c->r_error = chp->ch_error; 846 ata_c->flags |= AT_ERROR; 847 } 848 } 849 ahci_cmd_done(chp, xfer, slot); 850 return 0; 851 } 852 853 void 854 ahci_cmd_done(struct ata_channel *chp, struct ata_xfer *xfer, int slot) 855 { 856 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 857 struct ahci_channel *achp = (struct ahci_channel *)chp; 858 struct ata_command *ata_c = xfer->c_cmd; 859 860 AHCIDEBUG_PRINT(("ahci_cmd_done channel %d\n", chp->ch_channel), 861 DEBUG_FUNCS); 862 863 /* this comamnd is not active any more */ 864 achp->ahcic_cmds_active &= ~(1 << slot); 865 866 if (ata_c->flags & (AT_READ|AT_WRITE) && ata_c->bcount > 0) { 867 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 868 achp->ahcic_datad[slot]->dm_mapsize, 869 (ata_c->flags & AT_READ) ? BUS_DMASYNC_POSTREAD : 870 BUS_DMASYNC_POSTWRITE); 871 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 872 } 873 874 AHCI_CMDH_SYNC(sc, achp, slot, 875 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 876 877 ata_c->flags |= AT_DONE; 878 if (achp->ahcic_cmdh[slot].cmdh_prdbc) 879 ata_c->flags |= AT_XFDONE; 880 881 ata_free_xfer(chp, xfer); 882 if (ata_c->flags & AT_WAIT) 883 wakeup(ata_c); 884 else if (ata_c->callback) 885 ata_c->callback(ata_c->callback_arg); 886 atastart(chp); 887 return; 888 } 889 890 int 891 ahci_ata_bio(struct ata_drive_datas *drvp, struct ata_bio *ata_bio) 892 { 893 struct ata_channel *chp = drvp->chnl_softc; 894 struct ata_xfer *xfer; 895 896 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 897 AHCIDEBUG_PRINT(("ahci_ata_bio port %d CI 0x%x\n", 898 chp->ch_channel, AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), 899 DEBUG_XFERS); 900 xfer = ata_get_xfer(ATAXF_NOSLEEP); 901 if (xfer == NULL) { 902 return ATACMD_TRY_AGAIN; 903 } 904 if (ata_bio->flags & ATA_POLL) 905 xfer->c_flags |= C_POLL; 906 xfer->c_drive = drvp->drive; 907 xfer->c_cmd = ata_bio; 908 xfer->c_databuf = ata_bio->databuf; 909 xfer->c_bcount = ata_bio->bcount; 910 xfer->c_start = ahci_bio_start; 911 xfer->c_intr = ahci_bio_complete; 912 xfer->c_kill_xfer = ahci_bio_kill_xfer; 913 ata_exec_xfer(chp, xfer); 914 return (ata_bio->flags & ATA_ITSDONE) ? ATACMD_COMPLETE : ATACMD_QUEUED; 915 } 916 917 void 918 ahci_bio_start(struct ata_channel *chp, struct ata_xfer *xfer) 919 { 920 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 921 struct ahci_channel *achp = (struct ahci_channel *)chp; 922 struct ata_bio *ata_bio = xfer->c_cmd; 923 int slot = 0 /* XXX slot */; 924 struct ahci_cmd_tbl *cmd_tbl; 925 struct ahci_cmd_header *cmd_h; 926 u_int8_t *fis; 927 int i, nblks; 928 int channel = chp->ch_channel; 929 930 AHCIDEBUG_PRINT(("ahci_bio_start CI 0x%x\n", 931 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 932 933 nblks = xfer->c_bcount / ata_bio->lp->d_secsize; 934 935 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 936 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 937 cmd_tbl), DEBUG_XFERS); 938 fis = cmd_tbl->cmdt_cfis; 939 940 fis[0] = 0x27; /* host to device */ 941 fis[1] = 0x80; /* command FIS */ 942 if (ata_bio->flags & ATA_LBA48) { 943 fis[2] = (ata_bio->flags & ATA_READ) ? 944 WDCC_READDMA_EXT : WDCC_WRITEDMA_EXT; 945 } else { 946 fis[2] = 947 (ata_bio->flags & ATA_READ) ? WDCC_READDMA : WDCC_WRITEDMA; 948 } 949 fis[3] = 0; /* features */ 950 fis[4] = ata_bio->blkno & 0xff; 951 fis[5] = (ata_bio->blkno >> 8) & 0xff; 952 fis[6] = (ata_bio->blkno >> 16) & 0xff; 953 if (ata_bio->flags & ATA_LBA48) { 954 fis[7] = WDSD_LBA; 955 fis[8] = (ata_bio->blkno >> 24) & 0xff; 956 fis[9] = (ata_bio->blkno >> 32) & 0xff; 957 fis[10] = (ata_bio->blkno >> 40) & 0xff; 958 } else { 959 fis[7] = ((ata_bio->blkno >> 24) & 0x0f) | WDSD_LBA; 960 fis[8] = 0; 961 fis[9] = 0; 962 fis[10] = 0; 963 } 964 fis[11] = 0; /* ext features */ 965 fis[12] = nblks & 0xff; 966 fis[13] = (ata_bio->flags & ATA_LBA48) ? 967 ((nblks >> 8) & 0xff) : 0; 968 fis[14] = 0; 969 fis[15] = WDCTL_4BIT; 970 fis[16] = 0; 971 fis[17] = 0; 972 fis[18] = 0; 973 fis[19] = 0; 974 975 cmd_h = &achp->ahcic_cmdh[slot]; 976 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 977 chp->ch_channel, cmd_h), DEBUG_XFERS); 978 if (ahci_dma_setup(chp, slot, ata_bio->databuf, ata_bio->bcount, 979 (ata_bio->flags & ATA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE)) { 980 ata_bio->error = ERR_DMA; 981 ata_bio->r_error = 0; 982 ahci_bio_complete(chp, xfer, slot); 983 return; 984 } 985 cmd_h->cmdh_flags = htole16( 986 ((ata_bio->flags & ATA_READ) ? 0 : AHCI_CMDH_F_WR) | 987 20 /* fis lenght */ / 4); 988 cmd_h->cmdh_prdbc = 0; 989 AHCI_CMDH_SYNC(sc, achp, slot, 990 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 991 992 if (xfer->c_flags & C_POLL) { 993 /* polled command, disable interrupts */ 994 AHCI_WRITE(sc, AHCI_GHC, 995 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 996 } 997 chp->ch_flags |= ATACH_IRQ_WAIT; 998 chp->ch_status = 0; 999 /* start command */ 1000 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1001 /* and says we started this command */ 1002 achp->ahcic_cmds_active |= 1 << slot; 1003 1004 if ((xfer->c_flags & C_POLL) == 0) { 1005 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1006 callout_reset(&chp->ch_callout, mstohz(ATA_DELAY), 1007 ahci_timeout, chp); 1008 return; 1009 } 1010 /* 1011 * Polled command. 1012 */ 1013 for (i = 0; i < ATA_DELAY / 10; i++) { 1014 if (ata_bio->flags & ATA_ITSDONE) 1015 break; 1016 ahci_intr_port(sc, achp); 1017 if (ata_bio->flags & ATA_NOSLEEP) 1018 delay(10000); 1019 else 1020 tsleep(&xfer, PRIBIO, "ahcipl", mstohz(10)); 1021 } 1022 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1023 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1024 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1025 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1026 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1027 DEBUG_XFERS); 1028 if ((ata_bio->flags & ATA_ITSDONE) == 0) { 1029 ata_bio->error = TIMEOUT; 1030 ahci_bio_complete(chp, xfer, slot); 1031 } 1032 /* reenable interrupts */ 1033 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1034 } 1035 1036 void 1037 ahci_bio_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1038 { 1039 int slot = 0; /* XXX slot */ 1040 int drive = xfer->c_drive; 1041 struct ata_bio *ata_bio = xfer->c_cmd; 1042 struct ahci_channel *achp = (struct ahci_channel *)chp; 1043 AHCIDEBUG_PRINT(("ahci_bio_kill_xfer channel %d\n", chp->ch_channel), 1044 DEBUG_FUNCS); 1045 1046 achp->ahcic_cmds_active &= ~(1 << slot); 1047 ata_free_xfer(chp, xfer); 1048 ata_bio->flags |= ATA_ITSDONE; 1049 switch (reason) { 1050 case KILL_GONE: 1051 ata_bio->error = ERR_NODEV; 1052 break; 1053 case KILL_RESET: 1054 ata_bio->error = ERR_RESET; 1055 break; 1056 default: 1057 printf("ahci_bio_kill_xfer: unknown reason %d\n", reason); 1058 panic("ahci_bio_kill_xfer"); 1059 } 1060 ata_bio->r_error = WDCE_ABRT; 1061 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1062 } 1063 1064 int 1065 ahci_bio_complete(struct ata_channel *chp, struct ata_xfer *xfer, int is) 1066 { 1067 int slot = 0; /* XXX slot */ 1068 struct ata_bio *ata_bio = xfer->c_cmd; 1069 int drive = xfer->c_drive; 1070 struct ahci_channel *achp = (struct ahci_channel *)chp; 1071 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1072 1073 AHCIDEBUG_PRINT(("ahci_bio_complete channel %d\n", chp->ch_channel), 1074 DEBUG_FUNCS); 1075 1076 achp->ahcic_cmds_active &= ~(1 << slot); 1077 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1078 if (xfer->c_flags & C_TIMEOU) { 1079 ata_bio->error = TIMEOUT; 1080 } else { 1081 callout_stop(&chp->ch_callout); 1082 ata_bio->error = NOERROR; 1083 } 1084 1085 chp->ch_queue->active_xfer = NULL; 1086 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1087 achp->ahcic_datad[slot]->dm_mapsize, 1088 (ata_bio->flags & ATA_READ) ? BUS_DMASYNC_POSTREAD : 1089 BUS_DMASYNC_POSTWRITE); 1090 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1091 1092 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1093 ahci_bio_kill_xfer(chp, xfer, KILL_GONE); 1094 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1095 wakeup(&chp->ch_queue->active_xfer); 1096 return 0; 1097 } 1098 ata_free_xfer(chp, xfer); 1099 ata_bio->flags |= ATA_ITSDONE; 1100 if (chp->ch_status & WDCS_DWF) { 1101 ata_bio->error = ERR_DF; 1102 } else if (chp->ch_status & WDCS_ERR) { 1103 ata_bio->error = ERROR; 1104 ata_bio->r_error = chp->ch_error; 1105 } else if (chp->ch_status & WDCS_CORR) 1106 ata_bio->flags |= ATA_CORR; 1107 1108 AHCI_CMDH_SYNC(sc, achp, slot, 1109 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1110 AHCIDEBUG_PRINT(("ahci_bio_complete bcount %ld", 1111 ata_bio->bcount), DEBUG_XFERS); 1112 /* 1113 * if it was a write, complete data buffer may have been transfered 1114 * before error detection; in this case don't use cmdh_prdbc 1115 * as it won't reflect what was written to media. Assume nothing 1116 * was transfered and leave bcount as-is. 1117 */ 1118 if ((ata_bio->flags & ATA_READ) || ata_bio->error == NOERROR) 1119 ata_bio->bcount -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1120 AHCIDEBUG_PRINT((" now %ld\n", ata_bio->bcount), DEBUG_XFERS); 1121 (*chp->ch_drive[drive].drv_done)(chp->ch_drive[drive].drv_softc); 1122 atastart(chp); 1123 return 0; 1124 } 1125 1126 void 1127 ahci_channel_stop(struct ahci_softc *sc, struct ata_channel *chp, int flags) 1128 { 1129 int i; 1130 /* stop channel */ 1131 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1132 AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & ~AHCI_P_CMD_ST); 1133 /* wait 1s for channel to stop */ 1134 for (i = 0; i <100; i++) { 1135 if ((AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) 1136 == 0) 1137 break; 1138 if (flags & AT_WAIT) 1139 tsleep(&sc, PRIBIO, "ahcirst", mstohz(10)); 1140 else 1141 delay(10000); 1142 } 1143 if (AHCI_READ(sc, AHCI_P_CMD(chp->ch_channel)) & AHCI_P_CMD_CR) { 1144 printf("%s: channel wouldn't stop\n", AHCINAME(sc)); 1145 /* XXX controller reset ? */ 1146 return; 1147 } 1148 } 1149 1150 void 1151 ahci_channel_start(struct ahci_softc *sc, struct ata_channel *chp) 1152 { 1153 /* clear error */ 1154 AHCI_WRITE(sc, AHCI_P_SERR(chp->ch_channel), 1155 AHCI_READ(sc, AHCI_P_SERR(chp->ch_channel))); 1156 1157 /* and start controller */ 1158 AHCI_WRITE(sc, AHCI_P_CMD(chp->ch_channel), 1159 AHCI_P_CMD_ICC_AC | AHCI_P_CMD_POD | AHCI_P_CMD_SUD | 1160 AHCI_P_CMD_FRE | AHCI_P_CMD_ST); 1161 } 1162 1163 void 1164 ahci_timeout(void *v) 1165 { 1166 struct ata_channel *chp = (struct ata_channel *)v; 1167 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1168 int s = splbio(); 1169 AHCIDEBUG_PRINT(("ahci_timeout xfer %p\n", xfer), DEBUG_INTR); 1170 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1171 xfer->c_flags |= C_TIMEOU; 1172 xfer->c_intr(chp, xfer, 0); 1173 } 1174 splx(s); 1175 } 1176 1177 int 1178 ahci_dma_setup(struct ata_channel *chp, int slot, void *data, 1179 size_t count, int op) 1180 { 1181 int error, seg; 1182 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1183 struct ahci_channel *achp = (struct ahci_channel *)chp; 1184 struct ahci_cmd_tbl *cmd_tbl; 1185 struct ahci_cmd_header *cmd_h; 1186 1187 cmd_h = &achp->ahcic_cmdh[slot]; 1188 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1189 1190 if (data == NULL) { 1191 cmd_h->cmdh_prdtl = 0; 1192 goto end; 1193 } 1194 1195 error = bus_dmamap_load(sc->sc_dmat, achp->ahcic_datad[slot], 1196 data, count, NULL, 1197 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | op); 1198 if (error) { 1199 printf("%s port %d: failed to load xfer: %d\n", 1200 AHCINAME(sc), chp->ch_channel, error); 1201 return error; 1202 } 1203 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1204 achp->ahcic_datad[slot]->dm_mapsize, 1205 (op == BUS_DMA_READ) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 1206 for (seg = 0; seg < achp->ahcic_datad[slot]->dm_nsegs; seg++) { 1207 cmd_tbl->cmdt_prd[seg].prd_dba = htole32( 1208 achp->ahcic_datad[slot]->dm_segs[seg].ds_addr); 1209 cmd_tbl->cmdt_prd[seg].prd_dbau = 0; 1210 cmd_tbl->cmdt_prd[seg].prd_dbc = htole32( 1211 achp->ahcic_datad[slot]->dm_segs[seg].ds_len - 1); 1212 } 1213 cmd_tbl->cmdt_prd[seg - 1].prd_dbc |= htole32(AHCI_PRD_DBC_IPC); 1214 cmd_h->cmdh_prdtl = htole16(achp->ahcic_datad[slot]->dm_nsegs); 1215 end: 1216 AHCI_CMDTBL_SYNC(sc, achp, slot, BUS_DMASYNC_PREWRITE); 1217 return 0; 1218 } 1219 1220 #if NATAPIBUS > 0 1221 void 1222 ahci_atapibus_attach(struct atabus_softc * ata_sc) 1223 { 1224 struct ata_channel *chp = ata_sc->sc_chan; 1225 struct atac_softc *atac = chp->ch_atac; 1226 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 1227 struct scsipi_channel *chan = &chp->ch_atapi_channel; 1228 /* 1229 * Fill in the scsipi_adapter. 1230 */ 1231 adapt->adapt_dev = atac->atac_dev; 1232 adapt->adapt_nchannels = atac->atac_nchannels; 1233 adapt->adapt_request = ahci_atapi_scsipi_request; 1234 adapt->adapt_minphys = ahci_atapi_minphys; 1235 atac->atac_atapi_adapter.atapi_probe_device = ahci_atapi_probe_device; 1236 1237 /* 1238 * Fill in the scsipi_channel. 1239 */ 1240 memset(chan, 0, sizeof(*chan)); 1241 chan->chan_adapter = adapt; 1242 chan->chan_bustype = &ahci_atapi_bustype; 1243 chan->chan_channel = chp->ch_channel; 1244 chan->chan_flags = SCSIPI_CHAN_OPENINGS; 1245 chan->chan_openings = 1; 1246 chan->chan_max_periph = 1; 1247 chan->chan_ntargets = 1; 1248 chan->chan_nluns = 1; 1249 chp->atapibus = config_found_ia(ata_sc->sc_dev, "atapi", chan, 1250 atapiprint); 1251 } 1252 1253 void 1254 ahci_atapi_minphys(struct buf *bp) 1255 { 1256 if (bp->b_bcount > MAXPHYS) 1257 bp->b_bcount = MAXPHYS; 1258 minphys(bp); 1259 } 1260 1261 /* 1262 * Kill off all pending xfers for a periph. 1263 * 1264 * Must be called at splbio(). 1265 */ 1266 void 1267 ahci_atapi_kill_pending(struct scsipi_periph *periph) 1268 { 1269 struct atac_softc *atac = 1270 device_private(periph->periph_channel->chan_adapter->adapt_dev); 1271 struct ata_channel *chp = 1272 atac->atac_channels[periph->periph_channel->chan_channel]; 1273 1274 ata_kill_pending(&chp->ch_drive[periph->periph_target]); 1275 } 1276 1277 void 1278 ahci_atapi_scsipi_request(struct scsipi_channel *chan, 1279 scsipi_adapter_req_t req, void *arg) 1280 { 1281 struct scsipi_adapter *adapt = chan->chan_adapter; 1282 struct scsipi_periph *periph; 1283 struct scsipi_xfer *sc_xfer; 1284 struct ahci_softc *sc = device_private(adapt->adapt_dev); 1285 struct atac_softc *atac = &sc->sc_atac; 1286 struct ata_xfer *xfer; 1287 int channel = chan->chan_channel; 1288 int drive, s; 1289 1290 switch (req) { 1291 case ADAPTER_REQ_RUN_XFER: 1292 sc_xfer = arg; 1293 periph = sc_xfer->xs_periph; 1294 drive = periph->periph_target; 1295 if (!device_is_active(atac->atac_dev)) { 1296 sc_xfer->error = XS_DRIVER_STUFFUP; 1297 scsipi_done(sc_xfer); 1298 return; 1299 } 1300 xfer = ata_get_xfer(ATAXF_NOSLEEP); 1301 if (xfer == NULL) { 1302 sc_xfer->error = XS_RESOURCE_SHORTAGE; 1303 scsipi_done(sc_xfer); 1304 return; 1305 } 1306 1307 if (sc_xfer->xs_control & XS_CTL_POLL) 1308 xfer->c_flags |= C_POLL; 1309 xfer->c_drive = drive; 1310 xfer->c_flags |= C_ATAPI; 1311 xfer->c_cmd = sc_xfer; 1312 xfer->c_databuf = sc_xfer->data; 1313 xfer->c_bcount = sc_xfer->datalen; 1314 xfer->c_start = ahci_atapi_start; 1315 xfer->c_intr = ahci_atapi_complete; 1316 xfer->c_kill_xfer = ahci_atapi_kill_xfer; 1317 xfer->c_dscpoll = 0; 1318 s = splbio(); 1319 ata_exec_xfer(atac->atac_channels[channel], xfer); 1320 #ifdef DIAGNOSTIC 1321 if ((sc_xfer->xs_control & XS_CTL_POLL) != 0 && 1322 (sc_xfer->xs_status & XS_STS_DONE) == 0) 1323 panic("ahci_atapi_scsipi_request: polled command " 1324 "not done"); 1325 #endif 1326 splx(s); 1327 return; 1328 default: 1329 /* Not supported, nothing to do. */ 1330 ; 1331 } 1332 } 1333 1334 void 1335 ahci_atapi_start(struct ata_channel *chp, struct ata_xfer *xfer) 1336 { 1337 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1338 struct ahci_channel *achp = (struct ahci_channel *)chp; 1339 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1340 int slot = 0 /* XXX slot */; 1341 struct ahci_cmd_tbl *cmd_tbl; 1342 struct ahci_cmd_header *cmd_h; 1343 u_int8_t *fis; 1344 int i; 1345 int channel = chp->ch_channel; 1346 1347 AHCIDEBUG_PRINT(("ahci_atapi_start CI 0x%x\n", 1348 AHCI_READ(sc, AHCI_P_CI(chp->ch_channel))), DEBUG_XFERS); 1349 1350 cmd_tbl = achp->ahcic_cmd_tbl[slot]; 1351 AHCIDEBUG_PRINT(("%s port %d tbl %p\n", AHCINAME(sc), chp->ch_channel, 1352 cmd_tbl), DEBUG_XFERS); 1353 fis = cmd_tbl->cmdt_cfis; 1354 1355 fis[0] = 0x27; /* host to device */ 1356 fis[1] = 0x80; /* command FIS */ 1357 fis[2] = ATAPI_PKT_CMD; 1358 memset(&cmd_tbl->cmdt_acmd, 0, sizeof(cmd_tbl->cmdt_acmd)); 1359 memcpy(cmd_tbl->cmdt_acmd, sc_xfer->cmd, sc_xfer->cmdlen); 1360 fis[3] = (sc_xfer->datalen ? ATAPI_PKT_CMD_FTRE_DMA : 0); 1361 fis[4] = 0; 1362 fis[5] = 0; 1363 fis[6] = 0; 1364 fis[7] = WDSD_LBA; 1365 fis[8] = 0; 1366 fis[9] = 0; 1367 fis[10] = 0; 1368 fis[11] = 0; /* ext features */ 1369 fis[12] = 0; 1370 fis[13] = 0; 1371 fis[14] = 0; 1372 fis[15] = WDCTL_4BIT; 1373 fis[16] = 0; 1374 fis[17] = 0; 1375 fis[18] = 0; 1376 fis[19] = 0; 1377 1378 cmd_h = &achp->ahcic_cmdh[slot]; 1379 AHCIDEBUG_PRINT(("%s port %d header %p\n", AHCINAME(sc), 1380 chp->ch_channel, cmd_h), DEBUG_XFERS); 1381 if (ahci_dma_setup(chp, slot, sc_xfer->datalen ? sc_xfer->data : NULL, 1382 sc_xfer->datalen, 1383 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? 1384 BUS_DMA_READ : BUS_DMA_WRITE)) { 1385 sc_xfer->error = XS_DRIVER_STUFFUP; 1386 ahci_atapi_complete(chp, xfer, slot); 1387 return; 1388 } 1389 cmd_h->cmdh_flags = htole16( 1390 ((sc_xfer->xs_control & XS_CTL_DATA_OUT) ? AHCI_CMDH_F_WR : 0) | 1391 20 /* fis lenght */ / 4 | AHCI_CMDH_F_A); 1392 cmd_h->cmdh_prdbc = 0; 1393 AHCI_CMDH_SYNC(sc, achp, slot, 1394 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1395 1396 if (xfer->c_flags & C_POLL) { 1397 /* polled command, disable interrupts */ 1398 AHCI_WRITE(sc, AHCI_GHC, 1399 AHCI_READ(sc, AHCI_GHC) & ~AHCI_GHC_IE); 1400 } 1401 chp->ch_flags |= ATACH_IRQ_WAIT; 1402 chp->ch_status = 0; 1403 /* start command */ 1404 AHCI_WRITE(sc, AHCI_P_CI(chp->ch_channel), 1 << slot); 1405 /* and says we started this command */ 1406 achp->ahcic_cmds_active |= 1 << slot; 1407 1408 if ((xfer->c_flags & C_POLL) == 0) { 1409 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1410 callout_reset(&chp->ch_callout, mstohz(sc_xfer->timeout), 1411 ahci_timeout, chp); 1412 return; 1413 } 1414 /* 1415 * Polled command. 1416 */ 1417 for (i = 0; i < ATA_DELAY / 10; i++) { 1418 if (sc_xfer->xs_status & XS_STS_DONE) 1419 break; 1420 ahci_intr_port(sc, achp); 1421 delay(10000); 1422 } 1423 AHCIDEBUG_PRINT(("%s port %d poll end GHC 0x%x IS 0x%x list 0x%x%x fis 0x%x%x CMD 0x%x CI 0x%x\n", AHCINAME(sc), channel, 1424 AHCI_READ(sc, AHCI_GHC), AHCI_READ(sc, AHCI_IS), 1425 AHCI_READ(sc, AHCI_P_CLBU(channel)), AHCI_READ(sc, AHCI_P_CLB(channel)), 1426 AHCI_READ(sc, AHCI_P_FBU(channel)), AHCI_READ(sc, AHCI_P_FB(channel)), 1427 AHCI_READ(sc, AHCI_P_CMD(channel)), AHCI_READ(sc, AHCI_P_CI(channel))), 1428 DEBUG_XFERS); 1429 if ((sc_xfer->xs_status & XS_STS_DONE) == 0) { 1430 sc_xfer->error = XS_TIMEOUT; 1431 ahci_atapi_complete(chp, xfer, slot); 1432 } 1433 /* reenable interrupts */ 1434 AHCI_WRITE(sc, AHCI_GHC, AHCI_READ(sc, AHCI_GHC) | AHCI_GHC_IE); 1435 } 1436 1437 int 1438 ahci_atapi_complete(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1439 { 1440 int slot = 0; /* XXX slot */ 1441 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1442 int drive = xfer->c_drive; 1443 struct ahci_channel *achp = (struct ahci_channel *)chp; 1444 struct ahci_softc *sc = (struct ahci_softc *)chp->ch_atac; 1445 1446 AHCIDEBUG_PRINT(("ahci_atapi_complete channel %d\n", chp->ch_channel), 1447 DEBUG_FUNCS); 1448 1449 achp->ahcic_cmds_active &= ~(1 << slot); 1450 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1451 if (xfer->c_flags & C_TIMEOU) { 1452 sc_xfer->error = XS_TIMEOUT; 1453 } else { 1454 callout_stop(&chp->ch_callout); 1455 sc_xfer->error = 0; 1456 } 1457 1458 chp->ch_queue->active_xfer = NULL; 1459 bus_dmamap_sync(sc->sc_dmat, achp->ahcic_datad[slot], 0, 1460 achp->ahcic_datad[slot]->dm_mapsize, 1461 (sc_xfer->xs_control & XS_CTL_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1462 BUS_DMASYNC_POSTWRITE); 1463 bus_dmamap_unload(sc->sc_dmat, achp->ahcic_datad[slot]); 1464 1465 if (chp->ch_drive[drive].drive_flags & DRIVE_WAITDRAIN) { 1466 ahci_atapi_kill_xfer(chp, xfer, KILL_GONE); 1467 chp->ch_drive[drive].drive_flags &= ~DRIVE_WAITDRAIN; 1468 wakeup(&chp->ch_queue->active_xfer); 1469 return 0; 1470 } 1471 ata_free_xfer(chp, xfer); 1472 1473 AHCI_CMDH_SYNC(sc, achp, slot, 1474 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1475 sc_xfer->resid = sc_xfer->datalen; 1476 sc_xfer->resid -= le32toh(achp->ahcic_cmdh[slot].cmdh_prdbc); 1477 AHCIDEBUG_PRINT(("ahci_atapi_complete datalen %d resid %d\n", 1478 sc_xfer->datalen, sc_xfer->resid), DEBUG_XFERS); 1479 if (chp->ch_status & WDCS_ERR && 1480 ((sc_xfer->xs_control & XS_CTL_REQSENSE) == 0 || 1481 sc_xfer->resid == sc_xfer->datalen)) { 1482 sc_xfer->error = XS_SHORTSENSE; 1483 sc_xfer->sense.atapi_sense = chp->ch_error; 1484 if ((sc_xfer->xs_periph->periph_quirks & 1485 PQUIRK_NOSENSE) == 0) { 1486 /* ask scsipi to send a REQUEST_SENSE */ 1487 sc_xfer->error = XS_BUSY; 1488 sc_xfer->status = SCSI_CHECK; 1489 } 1490 } 1491 scsipi_done(sc_xfer); 1492 atastart(chp); 1493 return 0; 1494 } 1495 1496 void 1497 ahci_atapi_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, int reason) 1498 { 1499 struct scsipi_xfer *sc_xfer = xfer->c_cmd; 1500 struct ahci_channel *achp = (struct ahci_channel *)chp; 1501 int slot = 0; /* XXX slot */ 1502 1503 achp->ahcic_cmds_active &= ~(1 << slot); 1504 1505 /* remove this command from xfer queue */ 1506 switch (reason) { 1507 case KILL_GONE: 1508 sc_xfer->error = XS_DRIVER_STUFFUP; 1509 break; 1510 case KILL_RESET: 1511 sc_xfer->error = XS_RESET; 1512 break; 1513 default: 1514 printf("ahci_ata_atapi_kill_xfer: unknown reason %d\n", reason); 1515 panic("ahci_ata_atapi_kill_xfer"); 1516 } 1517 ata_free_xfer(chp, xfer); 1518 scsipi_done(sc_xfer); 1519 } 1520 1521 void 1522 ahci_atapi_probe_device(struct atapibus_softc *sc, int target) 1523 { 1524 struct scsipi_channel *chan = sc->sc_channel; 1525 struct scsipi_periph *periph; 1526 struct ataparams ids; 1527 struct ataparams *id = &ids; 1528 struct ahci_softc *ahcic = 1529 device_private(chan->chan_adapter->adapt_dev); 1530 struct atac_softc *atac = &ahcic->sc_atac; 1531 struct ata_channel *chp = atac->atac_channels[chan->chan_channel]; 1532 struct ata_drive_datas *drvp = &chp->ch_drive[target]; 1533 struct scsipibus_attach_args sa; 1534 char serial_number[21], model[41], firmware_revision[9]; 1535 int s; 1536 1537 /* skip if already attached */ 1538 if (scsipi_lookup_periph(chan, target, 0) != NULL) 1539 return; 1540 1541 /* if no ATAPI device detected at attach time, skip */ 1542 if ((drvp->drive_flags & DRIVE_ATAPI) == 0) { 1543 AHCIDEBUG_PRINT(("ahci_atapi_probe_device: drive %d " 1544 "not present\n", target), DEBUG_PROBE); 1545 return; 1546 } 1547 1548 /* Some ATAPI devices need a bit more time after software reset. */ 1549 delay(5000); 1550 if (ata_get_params(drvp, AT_WAIT, id) == 0) { 1551 #ifdef ATAPI_DEBUG_PROBE 1552 printf("%s drive %d: cmdsz 0x%x drqtype 0x%x\n", 1553 AHCINAME(ahcic), target, 1554 id->atap_config & ATAPI_CFG_CMD_MASK, 1555 id->atap_config & ATAPI_CFG_DRQ_MASK); 1556 #endif 1557 periph = scsipi_alloc_periph(M_NOWAIT); 1558 if (periph == NULL) { 1559 aprint_error_dev(sc->sc_dev, 1560 "unable to allocate periph for drive %d\n", 1561 target); 1562 return; 1563 } 1564 periph->periph_dev = NULL; 1565 periph->periph_channel = chan; 1566 periph->periph_switch = &atapi_probe_periphsw; 1567 periph->periph_target = target; 1568 periph->periph_lun = 0; 1569 periph->periph_quirks = PQUIRK_ONLYBIG; 1570 1571 #ifdef SCSIPI_DEBUG 1572 if (SCSIPI_DEBUG_TYPE == SCSIPI_BUSTYPE_ATAPI && 1573 SCSIPI_DEBUG_TARGET == target) 1574 periph->periph_dbflags |= SCSIPI_DEBUG_FLAGS; 1575 #endif 1576 periph->periph_type = ATAPI_CFG_TYPE(id->atap_config); 1577 if (id->atap_config & ATAPI_CFG_REMOV) 1578 periph->periph_flags |= PERIPH_REMOVABLE; 1579 if (periph->periph_type == T_SEQUENTIAL) { 1580 s = splbio(); 1581 drvp->drive_flags |= DRIVE_ATAPIST; 1582 splx(s); 1583 } 1584 1585 sa.sa_periph = periph; 1586 sa.sa_inqbuf.type = ATAPI_CFG_TYPE(id->atap_config); 1587 sa.sa_inqbuf.removable = id->atap_config & ATAPI_CFG_REMOV ? 1588 T_REMOV : T_FIXED; 1589 scsipi_strvis((u_char *)model, 40, id->atap_model, 40); 1590 scsipi_strvis((u_char *)serial_number, 20, id->atap_serial, 1591 20); 1592 scsipi_strvis((u_char *)firmware_revision, 8, 1593 id->atap_revision, 8); 1594 sa.sa_inqbuf.vendor = model; 1595 sa.sa_inqbuf.product = serial_number; 1596 sa.sa_inqbuf.revision = firmware_revision; 1597 1598 /* 1599 * Determine the operating mode capabilities of the device. 1600 */ 1601 if ((id->atap_config & ATAPI_CFG_CMD_MASK) == ATAPI_CFG_CMD_16) 1602 periph->periph_cap |= PERIPH_CAP_CMD16; 1603 /* XXX This is gross. */ 1604 periph->periph_cap |= (id->atap_config & ATAPI_CFG_DRQ_MASK); 1605 1606 drvp->drv_softc = atapi_probe_device(sc, target, periph, &sa); 1607 1608 if (drvp->drv_softc) 1609 ata_probe_caps(drvp); 1610 else { 1611 s = splbio(); 1612 drvp->drive_flags &= ~DRIVE_ATAPI; 1613 splx(s); 1614 } 1615 } else { 1616 AHCIDEBUG_PRINT(("ahci_atapi_get_params: ATAPI_IDENTIFY_DEVICE " 1617 "failed for drive %s:%d:%d: error 0x%x\n", 1618 AHCINAME(ahcic), chp->ch_channel, target, 1619 chp->ch_error), DEBUG_PROBE); 1620 s = splbio(); 1621 drvp->drive_flags &= ~DRIVE_ATAPI; 1622 splx(s); 1623 } 1624 } 1625 #endif /* NATAPIBUS */
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