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sys/dev/ic/aic6360.c
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1 /* $NetBSD: aic6360.c,v 1.80 2003/11/02 11:07:44 wiz Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Copyright (c) 1994 Jarle Greipsland 21 * All rights reserved. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 3. The name of the author may not be used to endorse or promote products 32 * derived from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 37 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 38 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 42 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 43 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 44 * POSSIBILITY OF SUCH DAMAGE. 45 */ 46 47 /* 48 * Acknowledgements: Many of the algorithms used in this driver are 49 * inspired by the work of Julian Elischer (julian@tfs.com) and 50 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 51 */ 52 53 /* TODO list: 54 * 1) Get the DMA stuff working. 55 * 2) Get the iov/uio stuff working. Is this a good thing ??? 56 * 3) Get the synch stuff working. 57 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: aic6360.c,v 1.80 2003/11/02 11:07:44 wiz Exp $"); 62 63 #include "opt_ddb.h" 64 #ifdef DDB 65 #define integrate 66 #else 67 #define integrate static inline 68 #endif 69 70 /* 71 * A few customizable items: 72 */ 73 74 /* Use doubleword transfers to/from SCSI chip. Note: This requires 75 * motherboard support. Basicly, some motherboard chipsets are able to 76 * split a 32 bit I/O operation into two 16 bit I/O operations, 77 * transparently to the processor. This speeds up some things, notably long 78 * data transfers. 79 */ 80 #define AIC_USE_DWORDS 0 81 82 /* Synchronous data transfers? */ 83 #define AIC_USE_SYNCHRONOUS 0 84 #define AIC_SYNC_REQ_ACK_OFS 8 85 86 /* Wide data transfers? */ 87 #define AIC_USE_WIDE 0 88 #define AIC_MAX_WIDTH 0 89 90 /* Max attempts made to transmit a message */ 91 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 92 93 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 94 #define AIC_USE_EISA_DMA 0 95 #define AIC_USE_ISA_DMA 0 96 97 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 98 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 99 100 /* Some spin loop parameters (essentially how long to wait some places) 101 * The problem(?) is that sometimes we expect either to be able to transmit a 102 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 103 * returning from the interrupt just to get yanked back for the next byte we 104 * may spin in the interrupt routine waiting for this byte to come. How long? 105 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 106 */ 107 #define AIC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 108 #define AIC_MSGOUT_SPIN 1 109 110 /* Include debug functions? At the end of this file there are a bunch of 111 * functions that will print out various information regarding queued SCSI 112 * commands, driver state and chip contents. You can call them from the 113 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 114 * kernel uses less memory) but you lose the debugging facilities. 115 */ 116 #define AIC_DEBUG 1 117 118 #define AIC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 119 120 /* End of customizable parameters */ 121 122 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 123 #error "I said not yet! Start paying attention... grumble" 124 #endif 125 126 #include <sys/param.h> 127 #include <sys/systm.h> 128 #include <sys/callout.h> 129 #include <sys/kernel.h> 130 #include <sys/errno.h> 131 #include <sys/ioctl.h> 132 #include <sys/device.h> 133 #include <sys/buf.h> 134 #include <sys/proc.h> 135 #include <sys/user.h> 136 #include <sys/queue.h> 137 138 #include <machine/bus.h> 139 #include <machine/intr.h> 140 141 #include <dev/scsipi/scsi_all.h> 142 #include <dev/scsipi/scsipi_all.h> 143 #include <dev/scsipi/scsi_message.h> 144 #include <dev/scsipi/scsiconf.h> 145 146 #include <dev/ic/aic6360reg.h> 147 #include <dev/ic/aic6360var.h> 148 149 #ifndef DDB 150 #define Debugger() panic("should call debugger here (aic6360.c)") 151 #endif /* ! DDB */ 152 153 #if AIC_DEBUG 154 int aic_debug = 0x00; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRACE; */ 155 #endif 156 157 void aic_minphys(struct buf *); 158 void aic_done(struct aic_softc *, struct aic_acb *); 159 void aic_dequeue(struct aic_softc *, struct aic_acb *); 160 void aic_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 161 void *); 162 int aic_poll(struct aic_softc *, struct scsipi_xfer *, int); 163 integrate void aic_sched_msgout(struct aic_softc *, u_char); 164 integrate void aic_setsync(struct aic_softc *, struct aic_tinfo *); 165 void aic_select(struct aic_softc *, struct aic_acb *); 166 void aic_timeout(void *); 167 void aic_sched(struct aic_softc *); 168 void aic_scsi_reset(struct aic_softc *); 169 void aic_reset(struct aic_softc *); 170 void aic_free_acb(struct aic_softc *, struct aic_acb *); 171 struct aic_acb* aic_get_acb(struct aic_softc *); 172 int aic_reselect(struct aic_softc *, int); 173 void aic_sense(struct aic_softc *, struct aic_acb *); 174 void aic_msgin(struct aic_softc *); 175 void aic_abort(struct aic_softc *, struct aic_acb *); 176 void aic_msgout(struct aic_softc *); 177 int aic_dataout_pio(struct aic_softc *, u_char *, int); 178 int aic_datain_pio(struct aic_softc *, u_char *, int); 179 void aic_update_xfer_mode(struct aic_softc *, int); 180 #if AIC_DEBUG 181 void aic_print_acb(struct aic_acb *); 182 void aic_dump_driver(struct aic_softc *); 183 void aic_dump6360(struct aic_softc *); 184 void aic_show_scsi_cmd(struct aic_acb *); 185 void aic_print_active_acb(void); 186 #endif 187 188 /* 189 * INITIALIZATION ROUTINES (probe, attach ++) 190 */ 191 192 /* Do the real search-for-device. 193 * Prerequisite: sc->sc_iobase should be set to the proper value 194 */ 195 int 196 aic_find(bus_space_tag_t iot, bus_space_handle_t ioh) 197 { 198 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 199 int i; 200 201 /* Remove aic6360 from possible powerdown mode */ 202 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 203 204 /* Thanks to mark@aggregate.com for the new method for detecting 205 * whether the chip is present or not. Bonus: may also work for 206 * the AIC-6260! 207 */ 208 AIC_TRACE(("aic: probing for aic-chip\n")); 209 /* 210 * Linux also init's the stack to 1-16 and then clears it, 211 * 6260's don't appear to have an ID reg - mpg 212 */ 213 /* Push the sequence 0,1,..,15 on the stack */ 214 #define STSIZE 16 215 bus_space_write_1(iot, ioh, DMACNTRL1, 0); /* Reset stack pointer */ 216 for (i = 0; i < STSIZE; i++) 217 bus_space_write_1(iot, ioh, STACK, i); 218 219 /* See if we can pull out the same sequence */ 220 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 221 for (i = 0; i < STSIZE && bus_space_read_1(iot, ioh, STACK) == i; i++) 222 ; 223 if (i != STSIZE) { 224 AIC_START(("STACK futzed at %d.\n", i)); 225 return 0; 226 } 227 228 /* See if we can pull the id string out of the ID register, 229 * now only used for informational purposes. 230 */ 231 memset(chip_id, 0, sizeof(chip_id)); 232 bus_space_read_multi_1(iot, ioh, ID, chip_id, sizeof(IDSTRING) - 1); 233 AIC_START(("AIC found ID: %s ",chip_id)); 234 AIC_START(("chip revision %d\n", 235 (int)bus_space_read_1(iot, ioh, REV))); 236 237 return 1; 238 } 239 240 /* 241 * Attach the AIC6360, fill out some high and low level data structures 242 */ 243 void 244 aicattach(struct aic_softc *sc) 245 { 246 struct scsipi_adapter *adapt = &sc->sc_adapter; 247 struct scsipi_channel *chan = &sc->sc_channel; 248 249 AIC_TRACE(("aicattach ")); 250 sc->sc_state = AIC_INIT; 251 252 sc->sc_initiator = 7; 253 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 254 255 /* 256 * These are the bounds of the sync period, based on the frequency of 257 * the chip's clock input and the size and offset of the sync period 258 * register. 259 * 260 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 261 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 262 * minimum transfer rate. 263 */ 264 sc->sc_minsync = (2 * 250) / sc->sc_freq; 265 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 266 267 /* 268 * Fill in the scsipi_adapter. 269 */ 270 adapt->adapt_dev = &sc->sc_dev; 271 adapt->adapt_nchannels = 1; 272 adapt->adapt_openings = 8; 273 adapt->adapt_max_periph = 1; 274 adapt->adapt_request = aic_scsipi_request; 275 adapt->adapt_minphys = aic_minphys; 276 277 /* 278 * Fill in the scsipi_channel. 279 */ 280 chan->chan_adapter = adapt; 281 chan->chan_bustype = &scsi_bustype; 282 chan->chan_channel = 0; 283 chan->chan_ntargets = 8; 284 chan->chan_nluns = 8; 285 chan->chan_id = sc->sc_initiator; 286 287 /* 288 * Add reference to adapter so that we drop the reference after 289 * config_found() to make sure the adatper is disabled. 290 */ 291 if (scsipi_adapter_addref(adapt) != 0) { 292 printf("%s: unable to enable controller\n", 293 sc->sc_dev.dv_xname); 294 return; 295 } 296 297 aic_init(sc, 1); /* Init chip and driver */ 298 299 /* 300 * Ask the adapter what subunits are present 301 */ 302 sc->sc_child = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 303 scsipi_adapter_delref(adapt); 304 } 305 306 int 307 aic_activate(struct device *self, enum devact act) 308 { 309 struct aic_softc *sc = (struct aic_softc *) self; 310 int s, rv = 0; 311 312 s = splhigh(); 313 switch (act) { 314 case DVACT_ACTIVATE: 315 rv = EOPNOTSUPP; 316 break; 317 318 case DVACT_DEACTIVATE: 319 if (sc->sc_child != NULL) 320 rv = config_deactivate(sc->sc_child); 321 break; 322 } 323 splx(s); 324 325 return (rv); 326 } 327 328 int 329 aic_detach(struct device *self, int flags) 330 { 331 struct aic_softc *sc = (struct aic_softc *) self; 332 int rv = 0; 333 334 if (sc->sc_child != NULL) 335 rv = config_detach(sc->sc_child, flags); 336 337 return (rv); 338 } 339 340 /* Initialize AIC6360 chip itself 341 * The following conditions should hold: 342 * aic_isa_probe should have succeeded, i.e. the iobase address in aic_softc 343 * must be valid. 344 */ 345 void 346 aic_reset(struct aic_softc *sc) 347 { 348 bus_space_tag_t iot = sc->sc_iot; 349 bus_space_handle_t ioh = sc->sc_ioh; 350 351 /* 352 * Doc. recommends to clear these two registers before 353 * operations commence 354 */ 355 bus_space_write_1(iot, ioh, SCSITEST, 0); 356 bus_space_write_1(iot, ioh, TEST, 0); 357 358 /* Reset SCSI-FIFO and abort any transfers */ 359 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH | CLRSTCNT); 360 361 /* Reset DMA-FIFO */ 362 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 363 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 364 365 /* Disable all selection features */ 366 bus_space_write_1(iot, ioh, SCSISEQ, 0); 367 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 368 369 /* Disable some interrupts */ 370 bus_space_write_1(iot, ioh, SIMODE0, 0x00); 371 /* Clear a slew of interrupts */ 372 bus_space_write_1(iot, ioh, CLRSINT0, 0x7f); 373 374 /* Disable some more interrupts */ 375 bus_space_write_1(iot, ioh, SIMODE1, 0x00); 376 /* Clear another slew of interrupts */ 377 bus_space_write_1(iot, ioh, CLRSINT1, 0xef); 378 379 /* Disable synchronous transfers */ 380 bus_space_write_1(iot, ioh, SCSIRATE, 0); 381 382 /* Haven't seen ant errors (yet) */ 383 bus_space_write_1(iot, ioh, CLRSERR, 0x07); 384 385 /* Set our SCSI-ID */ 386 bus_space_write_1(iot, ioh, SCSIID, sc->sc_initiator << OID_S); 387 bus_space_write_1(iot, ioh, BRSTCNTRL, EISA_BRST_TIM); 388 } 389 390 /* Pull the SCSI RST line for 500 us */ 391 void 392 aic_scsi_reset(struct aic_softc *sc) 393 { 394 bus_space_tag_t iot = sc->sc_iot; 395 bus_space_handle_t ioh = sc->sc_ioh; 396 397 bus_space_write_1(iot, ioh, SCSISEQ, SCSIRSTO); 398 delay(500); 399 bus_space_write_1(iot, ioh, SCSISEQ, 0); 400 delay(50); 401 } 402 403 /* 404 * Initialize aic SCSI driver. 405 */ 406 void 407 aic_init(struct aic_softc *sc, int bus_reset) 408 { 409 struct aic_acb *acb; 410 int r; 411 412 if (bus_reset) { 413 aic_reset(sc); 414 aic_scsi_reset(sc); 415 } 416 aic_reset(sc); 417 418 if (sc->sc_state == AIC_INIT) { 419 /* First time through; initialize. */ 420 TAILQ_INIT(&sc->ready_list); 421 TAILQ_INIT(&sc->nexus_list); 422 TAILQ_INIT(&sc->free_list); 423 sc->sc_nexus = NULL; 424 acb = sc->sc_acb; 425 memset(acb, 0, sizeof(sc->sc_acb)); 426 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 427 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 428 acb++; 429 } 430 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 431 } else { 432 /* Cancel any active commands. */ 433 sc->sc_state = AIC_CLEANING; 434 if ((acb = sc->sc_nexus) != NULL) { 435 acb->xs->error = XS_DRIVER_STUFFUP; 436 callout_stop(&acb->xs->xs_callout); 437 aic_done(sc, acb); 438 } 439 while ((acb = sc->nexus_list.tqh_first) != NULL) { 440 acb->xs->error = XS_DRIVER_STUFFUP; 441 callout_stop(&acb->xs->xs_callout); 442 aic_done(sc, acb); 443 } 444 } 445 446 sc->sc_prevphase = PH_INVALID; 447 for (r = 0; r < 8; r++) { 448 struct aic_tinfo *ti = &sc->sc_tinfo[r]; 449 450 ti->flags = 0; 451 ti->period = ti->offset = 0; 452 ti->width = 0; 453 } 454 455 sc->sc_state = AIC_IDLE; 456 bus_space_write_1(sc->sc_iot, sc->sc_ioh, DMACNTRL0, INTEN); 457 } 458 459 void 460 aic_free_acb(struct aic_softc *sc, struct aic_acb *acb) 461 { 462 int s; 463 464 s = splbio(); 465 acb->flags = 0; 466 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 467 splx(s); 468 } 469 470 struct aic_acb * 471 aic_get_acb(struct aic_softc *sc) 472 { 473 struct aic_acb *acb; 474 int s; 475 476 s = splbio(); 477 acb = TAILQ_FIRST(&sc->free_list); 478 if (acb != NULL) { 479 TAILQ_REMOVE(&sc->free_list, acb, chain); 480 acb->flags |= ACB_ALLOC; 481 } 482 splx(s); 483 return (acb); 484 } 485 486 /* 487 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 488 */ 489 490 /* 491 * Expected sequence: 492 * 1) Command inserted into ready list 493 * 2) Command selected for execution 494 * 3) Command won arbitration and has selected target device 495 * 4) Send message out (identify message, eventually also sync.negotiations) 496 * 5) Send command 497 * 5a) Receive disconnect message, disconnect. 498 * 5b) Reselected by target 499 * 5c) Receive identify message from target. 500 * 6) Send or receive data 501 * 7) Receive status 502 * 8) Receive message (command complete etc.) 503 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 504 * Repeat 2-8 (no disconnects please...) 505 */ 506 507 /* 508 * Perform a request from the SCSIPI midlayer. 509 */ 510 void 511 aic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 512 void *arg) 513 { 514 struct scsipi_xfer *xs; 515 struct scsipi_periph *periph; 516 struct aic_softc *sc = (void *)chan->chan_adapter->adapt_dev; 517 struct aic_acb *acb; 518 int s, flags; 519 520 AIC_TRACE(("aic_request ")); 521 522 switch (req) { 523 case ADAPTER_REQ_RUN_XFER: 524 xs = arg; 525 periph = xs->xs_periph; 526 527 AIC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 528 periph->periph_target)); 529 530 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 531 xs->error = XS_DRIVER_STUFFUP; 532 scsipi_done(xs); 533 return; 534 } 535 536 flags = xs->xs_control; 537 acb = aic_get_acb(sc); 538 #ifdef DIAGNOSTIC 539 /* 540 * This should never happen as we track the resources 541 * in the mid-layer. 542 */ 543 if (acb == NULL) { 544 scsipi_printaddr(periph); 545 printf("unable to allocate acb\n"); 546 panic("aic_scsipi_request"); 547 } 548 #endif 549 550 /* Initialize acb */ 551 acb->xs = xs; 552 acb->timeout = xs->timeout; 553 554 if (xs->xs_control & XS_CTL_RESET) { 555 acb->flags |= ACB_RESET; 556 acb->scsipi_cmd_length = 0; 557 acb->data_length = 0; 558 } else { 559 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen); 560 acb->scsipi_cmd_length = xs->cmdlen; 561 acb->data_addr = xs->data; 562 acb->data_length = xs->datalen; 563 } 564 acb->target_stat = 0; 565 566 s = splbio(); 567 568 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 569 if (sc->sc_state == AIC_IDLE) 570 aic_sched(sc); 571 572 splx(s); 573 574 if ((flags & XS_CTL_POLL) == 0) 575 return; 576 577 /* Not allowed to use interrupts, use polling instead */ 578 if (aic_poll(sc, xs, acb->timeout)) { 579 aic_timeout(acb); 580 if (aic_poll(sc, xs, acb->timeout)) 581 aic_timeout(acb); 582 } 583 return; 584 585 case ADAPTER_REQ_GROW_RESOURCES: 586 /* XXX Not supported. */ 587 return; 588 589 case ADAPTER_REQ_SET_XFER_MODE: 590 { 591 struct aic_tinfo *ti; 592 struct scsipi_xfer_mode *xm = arg; 593 594 ti = &sc->sc_tinfo[xm->xm_target]; 595 ti->flags &= ~(DO_SYNC|DO_WIDE); 596 ti->period = 0; 597 ti->offset = 0; 598 599 #if AIC_USE_SYNCHRONOUS 600 if (xm->xm_mode & PERIPH_CAP_SYNC) { 601 ti->flags |= DO_SYNC; 602 ti->period = sc->sc_minsync; 603 ti->offset = AIC_SYNC_REQ_ACK_OFS; 604 } 605 #endif 606 #if AIC_USE_WIDE 607 if (xm->xm_mode & PERIPH_CAP_WIDE16) { 608 ti->flags |= DO_WIDE; 609 ti->width = AIC_MAX_WIDTH; 610 } 611 #endif 612 /* 613 * If we're not going to negotiate, send the notification 614 * now, since it won't happen later. 615 */ 616 if ((ti->flags & (DO_SYNC|DO_WIDE)) == 0) 617 aic_update_xfer_mode(sc, xm->xm_target); 618 return; 619 } 620 } 621 } 622 623 void 624 aic_update_xfer_mode(struct aic_softc *sc, int target) 625 { 626 struct scsipi_xfer_mode xm; 627 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 628 629 xm.xm_target = target; 630 xm.xm_mode = 0; 631 xm.xm_period = 0; 632 xm.xm_offset = 0; 633 634 if (ti->offset != 0) { 635 xm.xm_mode |= PERIPH_CAP_SYNC; 636 xm.xm_period = ti->period; 637 xm.xm_offset = ti->offset; 638 } 639 switch (ti->width) { 640 case 2: 641 xm.xm_mode |= PERIPH_CAP_WIDE32; 642 break; 643 case 1: 644 xm.xm_mode |= PERIPH_CAP_WIDE16; 645 break; 646 } 647 648 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 649 } 650 651 /* 652 * Adjust transfer size in buffer structure 653 */ 654 void 655 aic_minphys(struct buf *bp) 656 { 657 658 AIC_TRACE(("aic_minphys ")); 659 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 660 bp->b_bcount = (AIC_NSEG << PGSHIFT); 661 minphys(bp); 662 } 663 664 /* 665 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 666 */ 667 int 668 aic_poll(struct aic_softc *sc, struct scsipi_xfer *xs, int count) 669 { 670 bus_space_tag_t iot = sc->sc_iot; 671 bus_space_handle_t ioh = sc->sc_ioh; 672 673 AIC_TRACE(("aic_poll ")); 674 while (count) { 675 /* 676 * If we had interrupts enabled, would we 677 * have got an interrupt? 678 */ 679 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 0) 680 aicintr(sc); 681 if ((xs->xs_status & XS_STS_DONE) != 0) 682 return 0; 683 delay(1000); 684 count--; 685 } 686 return 1; 687 } 688 689 /* 690 * LOW LEVEL SCSI UTILITIES 691 */ 692 693 integrate void 694 aic_sched_msgout(struct aic_softc *sc, u_char m) 695 { 696 bus_space_tag_t iot = sc->sc_iot; 697 bus_space_handle_t ioh = sc->sc_ioh; 698 699 if (sc->sc_msgpriq == 0) 700 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase | ATNO); 701 sc->sc_msgpriq |= m; 702 } 703 704 /* 705 * Set synchronous transfer offset and period. 706 */ 707 #if !AIC_USE_SYNCHRONOUS 708 /* ARGSUSED */ 709 #endif 710 integrate void 711 aic_setsync(struct aic_softc *sc, struct aic_tinfo *ti) 712 { 713 #if AIC_USE_SYNCHRONOUS 714 bus_space_tag_t iot = sc->sc_iot; 715 bus_space_handle_t ioh = sc->sc_ioh; 716 717 if (ti->offset != 0) 718 bus_space_write_1(iot, ioh, SCSIRATE, 719 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 720 else 721 bus_space_write_1(iot, ioh, SCSIRATE, 0); 722 #endif 723 } 724 725 /* 726 * Start a selection. This is used by aic_sched() to select an idle target, 727 * and by aic_done() to immediately reselect a target to get sense information. 728 */ 729 void 730 aic_select(struct aic_softc *sc, struct aic_acb *acb) 731 { 732 struct scsipi_periph *periph = acb->xs->xs_periph; 733 int target = periph->periph_target; 734 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 735 bus_space_tag_t iot = sc->sc_iot; 736 bus_space_handle_t ioh = sc->sc_ioh; 737 738 bus_space_write_1(iot, ioh, SCSIID, 739 sc->sc_initiator << OID_S | target); 740 aic_setsync(sc, ti); 741 bus_space_write_1(iot, ioh, SXFRCTL1, STIMO_256ms | ENSTIMER); 742 743 /* Always enable reselections. */ 744 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI | ENSELDO); 745 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSELTIMO); 746 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI | ENSELO | ENAUTOATNO); 747 748 sc->sc_state = AIC_SELECTING; 749 } 750 751 int 752 aic_reselect(struct aic_softc *sc, int message) 753 { 754 u_char selid, target, lun; 755 struct aic_acb *acb; 756 struct scsipi_periph *periph; 757 struct aic_tinfo *ti; 758 759 /* 760 * The SCSI chip made a snapshot of the data bus while the reselection 761 * was being negotiated. This enables us to determine which target did 762 * the reselect. 763 */ 764 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 765 if (selid & (selid - 1)) { 766 printf("%s: reselect with invalid selid %02x; " 767 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 768 AIC_BREAK(); 769 goto reset; 770 } 771 772 /* Search wait queue for disconnected cmd 773 * The list should be short, so I haven't bothered with 774 * any more sophisticated structures than a simple 775 * singly linked list. 776 */ 777 target = ffs(selid) - 1; 778 lun = message & 0x07; 779 for (acb = sc->nexus_list.tqh_first; acb != NULL; 780 acb = acb->chain.tqe_next) { 781 periph = acb->xs->xs_periph; 782 if (periph->periph_target == target && 783 periph->periph_lun == lun) 784 break; 785 } 786 if (acb == NULL) { 787 printf("%s: reselect from target %d lun %d with no nexus; " 788 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 789 AIC_BREAK(); 790 goto abort; 791 } 792 793 /* Make this nexus active again. */ 794 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 795 sc->sc_state = AIC_CONNECTED; 796 sc->sc_nexus = acb; 797 ti = &sc->sc_tinfo[target]; 798 ti->lubusy |= (1 << lun); 799 aic_setsync(sc, ti); 800 801 if (acb->flags & ACB_RESET) 802 aic_sched_msgout(sc, SEND_DEV_RESET); 803 else if (acb->flags & ACB_ABORT) 804 aic_sched_msgout(sc, SEND_ABORT); 805 806 /* Do an implicit RESTORE POINTERS. */ 807 sc->sc_dp = acb->data_addr; 808 sc->sc_dleft = acb->data_length; 809 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 810 sc->sc_cleft = acb->scsipi_cmd_length; 811 812 return (0); 813 814 reset: 815 aic_sched_msgout(sc, SEND_DEV_RESET); 816 return (1); 817 818 abort: 819 aic_sched_msgout(sc, SEND_ABORT); 820 return (1); 821 } 822 823 /* 824 * Schedule a SCSI operation. This has now been pulled out of the interrupt 825 * handler so that we may call it from aic_scsipi_request and aic_done. This 826 * may save us an unnecessary interrupt just to get things going. Should only 827 * be called when state == AIC_IDLE and at bio pl. 828 */ 829 void 830 aic_sched(struct aic_softc *sc) 831 { 832 struct aic_acb *acb; 833 struct scsipi_periph *periph; 834 struct aic_tinfo *ti; 835 bus_space_tag_t iot = sc->sc_iot; 836 bus_space_handle_t ioh = sc->sc_ioh; 837 838 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 839 return; 840 841 /* 842 * Find first acb in ready queue that is for a target/lunit pair that 843 * is not busy. 844 */ 845 bus_space_write_1(iot, ioh, CLRSINT1, 846 CLRSELTIMO | CLRBUSFREE | CLRSCSIPERR); 847 for (acb = sc->ready_list.tqh_first; acb != NULL; 848 acb = acb->chain.tqe_next) { 849 periph = acb->xs->xs_periph; 850 ti = &sc->sc_tinfo[periph->periph_target]; 851 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 852 AIC_MISC(("selecting %d:%d ", 853 periph->periph_target, periph->periph_lun)); 854 TAILQ_REMOVE(&sc->ready_list, acb, chain); 855 sc->sc_nexus = acb; 856 aic_select(sc, acb); 857 return; 858 } else 859 AIC_MISC(("%d:%d busy\n", 860 periph->periph_target, periph->periph_lun)); 861 } 862 AIC_MISC(("idle ")); 863 /* Nothing to start; just enable reselections and wait. */ 864 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI); 865 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST); 866 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 867 } 868 869 void 870 aic_sense(struct aic_softc *sc, struct aic_acb *acb) 871 { 872 struct scsipi_xfer *xs = acb->xs; 873 struct scsipi_periph *periph = xs->xs_periph; 874 struct aic_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 875 struct scsipi_sense *ss = (void *)&acb->scsipi_cmd; 876 877 AIC_MISC(("requesting sense ")); 878 /* Next, setup a request sense command block */ 879 memset(ss, 0, sizeof(*ss)); 880 ss->opcode = REQUEST_SENSE; 881 ss->byte2 = periph->periph_lun << 5; 882 ss->length = sizeof(struct scsipi_sense_data); 883 acb->scsipi_cmd_length = sizeof(*ss); 884 acb->data_addr = (char *)&xs->sense.scsi_sense; 885 acb->data_length = sizeof(struct scsipi_sense_data); 886 acb->flags |= ACB_SENSE; 887 ti->senses++; 888 if (acb->flags & ACB_NEXUS) 889 ti->lubusy &= ~(1 << periph->periph_lun); 890 if (acb == sc->sc_nexus) { 891 aic_select(sc, acb); 892 } else { 893 aic_dequeue(sc, acb); 894 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 895 if (sc->sc_state == AIC_IDLE) 896 aic_sched(sc); 897 } 898 } 899 900 /* 901 * POST PROCESSING OF SCSI_CMD (usually current) 902 */ 903 void 904 aic_done(struct aic_softc *sc, struct aic_acb *acb) 905 { 906 struct scsipi_xfer *xs = acb->xs; 907 struct scsipi_periph *periph = xs->xs_periph; 908 struct aic_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 909 910 AIC_TRACE(("aic_done ")); 911 912 /* 913 * Now, if we've come here with no error code, i.e. we've kept the 914 * initial XS_NOERROR, and the status code signals that we should 915 * check sense, we'll need to set up a request sense cmd block and 916 * push the command back into the ready queue *before* any other 917 * commands for this target/lunit, else we lose the sense info. 918 * We don't support chk sense conditions for the request sense cmd. 919 */ 920 if (xs->error == XS_NOERROR) { 921 if (acb->flags & ACB_ABORT) { 922 xs->error = XS_DRIVER_STUFFUP; 923 } else if (acb->flags & ACB_SENSE) { 924 xs->error = XS_SENSE; 925 } else if (acb->target_stat == SCSI_CHECK) { 926 /* First, save the return values */ 927 xs->resid = acb->data_length; 928 xs->status = acb->target_stat; 929 aic_sense(sc, acb); 930 return; 931 } else { 932 xs->resid = acb->data_length; 933 } 934 } 935 936 #if AIC_DEBUG 937 if ((aic_debug & AIC_SHOWMISC) != 0) { 938 if (xs->resid != 0) 939 printf("resid=%d ", xs->resid); 940 if (xs->error == XS_SENSE) 941 printf("sense=0x%02x\n", xs->sense.scsi_sense.error_code); 942 else 943 printf("error=%d\n", xs->error); 944 } 945 #endif 946 947 /* 948 * Remove the ACB from whatever queue it happens to be on. 949 */ 950 if (acb->flags & ACB_NEXUS) 951 ti->lubusy &= ~(1 << periph->periph_lun); 952 if (acb == sc->sc_nexus) { 953 sc->sc_nexus = NULL; 954 sc->sc_state = AIC_IDLE; 955 aic_sched(sc); 956 } else 957 aic_dequeue(sc, acb); 958 959 aic_free_acb(sc, acb); 960 ti->cmds++; 961 scsipi_done(xs); 962 } 963 964 void 965 aic_dequeue(struct aic_softc *sc, struct aic_acb *acb) 966 { 967 968 if (acb->flags & ACB_NEXUS) { 969 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 970 } else { 971 TAILQ_REMOVE(&sc->ready_list, acb, chain); 972 } 973 } 974 975 /* 976 * INTERRUPT/PROTOCOL ENGINE 977 */ 978 979 /* 980 * Precondition: 981 * The SCSI bus is already in the MSGI phase and there is a message byte 982 * on the bus, along with an asserted REQ signal. 983 */ 984 void 985 aic_msgin(struct aic_softc *sc) 986 { 987 bus_space_tag_t iot = sc->sc_iot; 988 bus_space_handle_t ioh = sc->sc_ioh; 989 u_char sstat1; 990 int n; 991 992 AIC_TRACE(("aic_msgin ")); 993 994 if (sc->sc_prevphase == PH_MSGIN) { 995 /* This is a continuation of the previous message. */ 996 n = sc->sc_imp - sc->sc_imess; 997 goto nextbyte; 998 } 999 1000 /* This is a new MESSAGE IN phase. Clean up our state. */ 1001 sc->sc_flags &= ~AIC_DROP_MSGIN; 1002 1003 nextmsg: 1004 n = 0; 1005 sc->sc_imp = &sc->sc_imess[n]; 1006 1007 nextbyte: 1008 /* 1009 * Read a whole message, but don't ack the last byte. If we reject the 1010 * message, we have to assert ATN during the message transfer phase 1011 * itself. 1012 */ 1013 for (;;) { 1014 for (;;) { 1015 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1016 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1017 break; 1018 /* Wait for REQINIT. XXX Need timeout. */ 1019 } 1020 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1021 /* 1022 * Target left MESSAGE IN, probably because it 1023 * a) noticed our ATN signal, or 1024 * b) ran out of messages. 1025 */ 1026 goto out; 1027 } 1028 1029 /* If parity error, just dump everything on the floor. */ 1030 if ((sstat1 & SCSIPERR) != 0) { 1031 sc->sc_flags |= AIC_DROP_MSGIN; 1032 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1033 } 1034 1035 /* Gather incoming message bytes if needed. */ 1036 if ((sc->sc_flags & AIC_DROP_MSGIN) == 0) { 1037 if (n >= AIC_MAX_MSG_LEN) { 1038 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1039 sc->sc_flags |= AIC_DROP_MSGIN; 1040 aic_sched_msgout(sc, SEND_REJECT); 1041 } else { 1042 *sc->sc_imp++ = bus_space_read_1(iot, ioh, 1043 SCSIDAT); 1044 n++; 1045 /* 1046 * This testing is suboptimal, but most 1047 * messages will be of the one byte variety, so 1048 * it should not affect performance 1049 * significantly. 1050 */ 1051 if (n == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1052 break; 1053 if (n == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1054 break; 1055 if (n >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1056 n == sc->sc_imess[1] + 2) 1057 break; 1058 } 1059 } else 1060 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1061 1062 /* 1063 * If we reach this spot we're either: 1064 * a) in the middle of a multi-byte message, or 1065 * b) dropping bytes. 1066 */ 1067 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1068 /* Ack the last byte read. */ 1069 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1070 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1071 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1072 ; 1073 } 1074 1075 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1076 1077 /* We now have a complete message. Parse it. */ 1078 switch (sc->sc_state) { 1079 struct aic_acb *acb; 1080 struct scsipi_periph *periph; 1081 struct aic_tinfo *ti; 1082 1083 case AIC_CONNECTED: 1084 AIC_ASSERT(sc->sc_nexus != NULL); 1085 acb = sc->sc_nexus; 1086 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1087 1088 switch (sc->sc_imess[0]) { 1089 case MSG_CMDCOMPLETE: 1090 if (sc->sc_dleft < 0) { 1091 periph = acb->xs->xs_periph; 1092 printf("%s: %ld extra bytes from %d:%d\n", 1093 sc->sc_dev.dv_xname, (long)-sc->sc_dleft, 1094 periph->periph_target, 1095 periph->periph_lun); 1096 acb->data_length = 0; 1097 } 1098 acb->xs->resid = acb->data_length = sc->sc_dleft; 1099 sc->sc_state = AIC_CMDCOMPLETE; 1100 break; 1101 1102 case MSG_PARITY_ERROR: 1103 /* Resend the last message. */ 1104 aic_sched_msgout(sc, sc->sc_lastmsg); 1105 break; 1106 1107 case MSG_MESSAGE_REJECT: 1108 AIC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1109 switch (sc->sc_lastmsg) { 1110 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1111 case SEND_IDENTIFY: 1112 ti->flags &= ~(DO_SYNC | DO_WIDE); 1113 ti->period = ti->offset = 0; 1114 aic_setsync(sc, ti); 1115 ti->width = 0; 1116 break; 1117 #endif 1118 #if AIC_USE_SYNCHRONOUS 1119 case SEND_SDTR: 1120 ti->flags &= ~DO_SYNC; 1121 ti->period = ti->offset = 0; 1122 aic_setsync(sc, ti); 1123 aic_update_xfer_mode(sc, 1124 acb->xs->xs_periph->periph_target); 1125 break; 1126 #endif 1127 #if AIC_USE_WIDE 1128 case SEND_WDTR: 1129 ti->flags &= ~DO_WIDE; 1130 ti->width = 0; 1131 aic_update_xfer_mode(sc, 1132 acb->xs->xs_periph->periph_target); 1133 break; 1134 #endif 1135 case SEND_INIT_DET_ERR: 1136 aic_sched_msgout(sc, SEND_ABORT); 1137 break; 1138 } 1139 break; 1140 1141 case MSG_NOOP: 1142 break; 1143 1144 case MSG_DISCONNECT: 1145 ti->dconns++; 1146 sc->sc_state = AIC_DISCONNECT; 1147 break; 1148 1149 case MSG_SAVEDATAPOINTER: 1150 acb->data_addr = sc->sc_dp; 1151 acb->data_length = sc->sc_dleft; 1152 break; 1153 1154 case MSG_RESTOREPOINTERS: 1155 sc->sc_dp = acb->data_addr; 1156 sc->sc_dleft = acb->data_length; 1157 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1158 sc->sc_cleft = acb->scsipi_cmd_length; 1159 break; 1160 1161 case MSG_EXTENDED: 1162 switch (sc->sc_imess[2]) { 1163 #if AIC_USE_SYNCHRONOUS 1164 case MSG_EXT_SDTR: 1165 if (sc->sc_imess[1] != 3) 1166 goto reject; 1167 ti->period = sc->sc_imess[3]; 1168 ti->offset = sc->sc_imess[4]; 1169 ti->flags &= ~DO_SYNC; 1170 if (ti->offset == 0) { 1171 } else if (ti->period < sc->sc_minsync || 1172 ti->period > sc->sc_maxsync || 1173 ti->offset > 8) { 1174 ti->period = ti->offset = 0; 1175 aic_sched_msgout(sc, SEND_SDTR); 1176 } else { 1177 aic_update_xfer_mode(sc, 1178 acb->xs->xs_periph->periph_target); 1179 } 1180 aic_setsync(sc, ti); 1181 break; 1182 #endif 1183 1184 #if AIC_USE_WIDE 1185 case MSG_EXT_WDTR: 1186 if (sc->sc_imess[1] != 2) 1187 goto reject; 1188 ti->width = sc->sc_imess[3]; 1189 ti->flags &= ~DO_WIDE; 1190 if (ti->width == 0) { 1191 } else if (ti->width > AIC_MAX_WIDTH) { 1192 ti->width = 0; 1193 aic_sched_msgout(sc, SEND_WDTR); 1194 } else { 1195 aic_update_xfer_mode(sc, 1196 acb->xs->xs_periph->periph_target); 1197 } 1198 break; 1199 #endif 1200 1201 default: 1202 printf("%s: unrecognized MESSAGE EXTENDED; " 1203 "sending REJECT\n", sc->sc_dev.dv_xname); 1204 AIC_BREAK(); 1205 goto reject; 1206 } 1207 break; 1208 1209 default: 1210 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1211 sc->sc_dev.dv_xname); 1212 AIC_BREAK(); 1213 reject: 1214 aic_sched_msgout(sc, SEND_REJECT); 1215 break; 1216 } 1217 break; 1218 1219 case AIC_RESELECTED: 1220 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1221 printf("%s: reselect without IDENTIFY; " 1222 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1223 AIC_BREAK(); 1224 goto reset; 1225 } 1226 1227 (void) aic_reselect(sc, sc->sc_imess[0]); 1228 break; 1229 1230 default: 1231 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1232 sc->sc_dev.dv_xname); 1233 AIC_BREAK(); 1234 reset: 1235 aic_sched_msgout(sc, SEND_DEV_RESET); 1236 break; 1237 1238 #ifdef notdef 1239 abort: 1240 aic_sched_msgout(sc, SEND_ABORT); 1241 break; 1242 #endif 1243 } 1244 1245 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1246 /* Ack the last message byte. */ 1247 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1248 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1249 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1250 ; 1251 1252 /* Go get the next message, if any. */ 1253 goto nextmsg; 1254 1255 out: 1256 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1257 } 1258 1259 /* 1260 * Send the highest priority, scheduled message. 1261 */ 1262 void 1263 aic_msgout(struct aic_softc *sc) 1264 { 1265 bus_space_tag_t iot = sc->sc_iot; 1266 bus_space_handle_t ioh = sc->sc_ioh; 1267 #if AIC_USE_SYNCHRONOUS 1268 struct aic_tinfo *ti; 1269 #endif 1270 u_char sstat1; 1271 int n; 1272 1273 AIC_TRACE(("aic_msgout ")); 1274 1275 /* Reset the FIFO. */ 1276 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1277 /* Enable REQ/ACK protocol. */ 1278 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1279 1280 if (sc->sc_prevphase == PH_MSGOUT) { 1281 if (sc->sc_omp == sc->sc_omess) { 1282 /* 1283 * This is a retransmission. 1284 * 1285 * We get here if the target stayed in MESSAGE OUT 1286 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1287 * that all of the previously transmitted messages must 1288 * be sent again, in the same order. Therefore, we 1289 * requeue all the previously transmitted messages, and 1290 * start again from the top. Our simple priority 1291 * scheme keeps the messages in the right order. 1292 */ 1293 AIC_MISC(("retransmitting ")); 1294 sc->sc_msgpriq |= sc->sc_msgoutq; 1295 /* 1296 * Set ATN. If we're just sending a trivial 1-byte 1297 * message, we'll clear ATN later on anyway. 1298 */ 1299 bus_space_write_1(iot, ioh, SCSISIG, PH_MSGOUT | ATNO); 1300 } else { 1301 /* This is a continuation of the previous message. */ 1302 n = sc->sc_omp - sc->sc_omess; 1303 goto nextbyte; 1304 } 1305 } 1306 1307 /* No messages transmitted so far. */ 1308 sc->sc_msgoutq = 0; 1309 sc->sc_lastmsg = 0; 1310 1311 nextmsg: 1312 /* Pick up highest priority message. */ 1313 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1314 sc->sc_msgpriq &= ~sc->sc_currmsg; 1315 sc->sc_msgoutq |= sc->sc_currmsg; 1316 1317 /* Build the outgoing message data. */ 1318 switch (sc->sc_currmsg) { 1319 case SEND_IDENTIFY: 1320 AIC_ASSERT(sc->sc_nexus != NULL); 1321 sc->sc_omess[0] = 1322 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1323 n = 1; 1324 break; 1325 1326 #if AIC_USE_SYNCHRONOUS 1327 case SEND_SDTR: 1328 AIC_ASSERT(sc->sc_nexus != NULL); 1329 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1330 sc->sc_omess[4] = MSG_EXTENDED; 1331 sc->sc_omess[3] = 3; 1332 sc->sc_omess[2] = MSG_EXT_SDTR; 1333 sc->sc_omess[1] = ti->period >> 2; 1334 sc->sc_omess[0] = ti->offset; 1335 n = 5; 1336 break; 1337 #endif 1338 1339 #if AIC_USE_WIDE 1340 case SEND_WDTR: 1341 AIC_ASSERT(sc->sc_nexus != NULL); 1342 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1343 sc->sc_omess[3] = MSG_EXTENDED; 1344 sc->sc_omess[2] = 2; 1345 sc->sc_omess[1] = MSG_EXT_WDTR; 1346 sc->sc_omess[0] = ti->width; 1347 n = 4; 1348 break; 1349 #endif 1350 1351 case SEND_DEV_RESET: 1352 sc->sc_flags |= AIC_ABORTING; 1353 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1354 n = 1; 1355 break; 1356 1357 case SEND_REJECT: 1358 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1359 n = 1; 1360 break; 1361 1362 case SEND_PARITY_ERROR: 1363 sc->sc_omess[0] = MSG_PARITY_ERROR; 1364 n = 1; 1365 break; 1366 1367 case SEND_INIT_DET_ERR: 1368 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1369 n = 1; 1370 break; 1371 1372 case SEND_ABORT: 1373 sc->sc_flags |= AIC_ABORTING; 1374 sc->sc_omess[0] = MSG_ABORT; 1375 n = 1; 1376 break; 1377 1378 default: 1379 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1380 sc->sc_dev.dv_xname); 1381 AIC_BREAK(); 1382 sc->sc_omess[0] = MSG_NOOP; 1383 n = 1; 1384 break; 1385 } 1386 sc->sc_omp = &sc->sc_omess[n]; 1387 1388 nextbyte: 1389 /* Send message bytes. */ 1390 for (;;) { 1391 for (;;) { 1392 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1393 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1394 break; 1395 /* Wait for REQINIT. XXX Need timeout. */ 1396 } 1397 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1398 /* 1399 * Target left MESSAGE OUT, possibly to reject 1400 * our message. 1401 * 1402 * If this is the last message being sent, then we 1403 * deassert ATN, since either the target is going to 1404 * ignore this message, or it's going to ask for a 1405 * retransmission via MESSAGE PARITY ERROR (in which 1406 * case we reassert ATN anyway). 1407 */ 1408 if (sc->sc_msgpriq == 0) 1409 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1410 goto out; 1411 } 1412 1413 /* Clear ATN before last byte if this is the last message. */ 1414 if (n == 1 && sc->sc_msgpriq == 0) 1415 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1416 /* Send message byte. */ 1417 bus_space_write_1(iot, ioh, SCSIDAT, *--sc->sc_omp); 1418 --n; 1419 /* Keep track of the last message we've sent any bytes of. */ 1420 sc->sc_lastmsg = sc->sc_currmsg; 1421 /* Wait for ACK to be negated. XXX Need timeout. */ 1422 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1423 ; 1424 1425 if (n == 0) 1426 break; 1427 } 1428 1429 /* We get here only if the entire message has been transmitted. */ 1430 if (sc->sc_msgpriq != 0) { 1431 /* There are more outgoing messages. */ 1432 goto nextmsg; 1433 } 1434 1435 /* 1436 * The last message has been transmitted. We need to remember the last 1437 * message transmitted (in case the target switches to MESSAGE IN phase 1438 * and sends a MESSAGE REJECT), and the list of messages transmitted 1439 * this time around (in case the target stays in MESSAGE OUT phase to 1440 * request a retransmit). 1441 */ 1442 1443 out: 1444 /* Disable REQ/ACK protocol. */ 1445 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1446 } 1447 1448 /* aic_dataout_pio: perform a data transfer using the FIFO datapath in the 1449 * aic6360 1450 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1451 * and ACK deasserted (i.e. waiting for a data byte) 1452 * This new revision has been optimized (I tried) to make the common case fast, 1453 * and the rarer cases (as a result) somewhat more comlex 1454 */ 1455 int 1456 aic_dataout_pio(struct aic_softc *sc, u_char *p, int n) 1457 { 1458 bus_space_tag_t iot = sc->sc_iot; 1459 bus_space_handle_t ioh = sc->sc_ioh; 1460 u_char dmastat = 0; 1461 int out = 0; 1462 #define DOUTAMOUNT 128 /* Full FIFO */ 1463 1464 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1465 bus_space_read_1(iot, ioh, SSTAT2))); 1466 1467 /* Clear host FIFO and counter. */ 1468 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO | WRITE); 1469 /* Enable FIFOs. */ 1470 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1471 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1472 1473 /* Turn off ENREQINIT for now. */ 1474 bus_space_write_1(iot, ioh, SIMODE1, 1475 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1476 1477 /* I have tried to make the main loop as tight as possible. This 1478 * means that some of the code following the loop is a bit more 1479 * complex than otherwise. 1480 */ 1481 while (n > 0) { 1482 for (;;) { 1483 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1484 if ((dmastat & (DFIFOEMP | INTSTAT)) != 0) 1485 break; 1486 } 1487 1488 if ((dmastat & INTSTAT) != 0) 1489 goto phasechange; 1490 1491 if (n >= DOUTAMOUNT) { 1492 n -= DOUTAMOUNT; 1493 out += DOUTAMOUNT; 1494 1495 #if AIC_USE_DWORDS 1496 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1497 (u_int32_t *) p, DOUTAMOUNT >> 2); 1498 #else 1499 bus_space_write_multi_2(iot, ioh, DMADATA, 1500 (u_int16_t *) p, DOUTAMOUNT >> 1); 1501 #endif 1502 1503 p += DOUTAMOUNT; 1504 } else { 1505 int xfer; 1506 1507 xfer = n; 1508 AIC_MISC(("%d> ", xfer)); 1509 1510 n -= xfer; 1511 out += xfer; 1512 1513 #if AIC_USE_DWORDS 1514 if (xfer >= 12) { 1515 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1516 (u_int32_t *) p, xfer >> 2); 1517 p += xfer & ~3; 1518 xfer &= 3; 1519 } 1520 #else 1521 if (xfer >= 8) { 1522 bus_space_write_multi_2(iot, ioh, DMADATA, 1523 (u_int16_t *) p, xfer >> 1); 1524 p += xfer & ~1; 1525 xfer &= 1; 1526 } 1527 #endif 1528 1529 if (xfer > 0) { 1530 bus_space_write_1(iot, ioh, DMACNTRL0, 1531 ENDMA | B8MODE | WRITE); 1532 bus_space_write_multi_1(iot, ioh, DMADATA, 1533 p, xfer); 1534 p += xfer; 1535 bus_space_write_1(iot, ioh, DMACNTRL0, 1536 ENDMA | DWORDPIO | WRITE); 1537 } 1538 } 1539 } 1540 1541 if (out == 0) { 1542 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1543 for (;;) { 1544 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1545 != 0) 1546 break; 1547 } 1548 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1549 AIC_MISC(("extra data ")); 1550 } else { 1551 /* See the bytes off chip */ 1552 for (;;) { 1553 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1554 if ((dmastat & INTSTAT) != 0) 1555 goto phasechange; 1556 if ((dmastat & DFIFOEMP) != 0 && 1557 (bus_space_read_1(iot, ioh, SSTAT2) & SEMPTY) != 0) 1558 break; 1559 } 1560 } 1561 1562 phasechange: 1563 if ((dmastat & INTSTAT) != 0) { 1564 /* Some sort of phase change. */ 1565 int amount; 1566 1567 /* Stop transfers, do some accounting */ 1568 amount = bus_space_read_1(iot, ioh, FIFOSTAT) 1569 + (bus_space_read_1(iot, ioh, SSTAT2) & 15); 1570 if (amount > 0) { 1571 out -= amount; 1572 bus_space_write_1(iot, ioh, DMACNTRL0, 1573 RSTFIFO | WRITE); 1574 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH); 1575 AIC_MISC(("+%d ", amount)); 1576 } 1577 } 1578 1579 /* Turn on ENREQINIT again. */ 1580 bus_space_write_1(iot, ioh, SIMODE1, 1581 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1582 1583 /* Stop the FIFO data path. */ 1584 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1585 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1586 1587 return out; 1588 } 1589 1590 /* aic_datain_pio: perform data transfers using the FIFO datapath in the 1591 * aic6360 1592 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1593 * and ACK deasserted (i.e. at least one byte is ready). 1594 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1595 * transferred. This, is OK for fast targets, but not so smart for slow 1596 * targets which don't disconnect or for huge transfers. 1597 */ 1598 int 1599 aic_datain_pio(struct aic_softc *sc, u_char *p, int n) 1600 { 1601 bus_space_tag_t iot = sc->sc_iot; 1602 bus_space_handle_t ioh = sc->sc_ioh; 1603 u_char dmastat; 1604 int in = 0; 1605 #define DINAMOUNT 128 /* Full FIFO */ 1606 1607 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1608 bus_space_read_1(iot, ioh, SSTAT2))); 1609 1610 /* Clear host FIFO and counter. */ 1611 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1612 /* Enable FIFOs. */ 1613 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO); 1614 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1615 1616 /* Turn off ENREQINIT for now. */ 1617 bus_space_write_1(iot, ioh, SIMODE1, 1618 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1619 1620 /* We leave this loop if one or more of the following is true: 1621 * a) phase != PH_DATAIN && FIFOs are empty 1622 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 1623 */ 1624 while (n > 0) { 1625 /* Wait for fifo half full or phase mismatch */ 1626 for (;;) { 1627 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1628 if ((dmastat & (DFIFOFULL | INTSTAT)) != 0) 1629 break; 1630 } 1631 1632 if ((dmastat & DFIFOFULL) != 0) { 1633 n -= DINAMOUNT; 1634 in += DINAMOUNT; 1635 1636 #if AIC_USE_DWORDS 1637 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1638 (u_int32_t *) p, DINAMOUNT >> 2); 1639 #else 1640 bus_space_read_multi_2(iot, ioh, DMADATA, 1641 (u_int16_t *) p, DINAMOUNT >> 1); 1642 #endif 1643 1644 p += DINAMOUNT; 1645 } else { 1646 int xfer; 1647 1648 xfer = min(bus_space_read_1(iot, ioh, FIFOSTAT), n); 1649 AIC_MISC((">%d ", xfer)); 1650 1651 n -= xfer; 1652 in += xfer; 1653 1654 #if AIC_USE_DWORDS 1655 if (xfer >= 12) { 1656 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1657 (u_int32_t *) p, xfer >> 2); 1658 p += xfer & ~3; 1659 xfer &= 3; 1660 } 1661 #else 1662 if (xfer >= 8) { 1663 bus_space_read_multi_2(iot, ioh, DMADATA, 1664 (u_int16_t *) p, xfer >> 1); 1665 p += xfer & ~1; 1666 xfer &= 1; 1667 } 1668 #endif 1669 1670 if (xfer > 0) { 1671 bus_space_write_1(iot, ioh, DMACNTRL0, 1672 ENDMA | B8MODE); 1673 bus_space_read_multi_1(iot, ioh, DMADATA, 1674 p, xfer); 1675 p += xfer; 1676 bus_space_write_1(iot, ioh, DMACNTRL0, 1677 ENDMA | DWORDPIO); 1678 } 1679 } 1680 1681 if ((dmastat & INTSTAT) != 0) 1682 goto phasechange; 1683 } 1684 1685 /* Some SCSI-devices are rude enough to transfer more data than what 1686 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1687 * requested 512. Test for progress, i.e. real transfers. If no real 1688 * transfers have been performed (n is probably already zero) and the 1689 * FIFO is not empty, waste some bytes.... 1690 */ 1691 if (in == 0) { 1692 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1693 for (;;) { 1694 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1695 != 0) 1696 break; 1697 } 1698 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1699 AIC_MISC(("extra data ")); 1700 } 1701 1702 phasechange: 1703 /* Turn on ENREQINIT again. */ 1704 bus_space_write_1(iot, ioh, SIMODE1, 1705 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1706 1707 /* Stop the FIFO data path. */ 1708 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1709 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1710 1711 return in; 1712 } 1713 1714 /* 1715 * This is the workhorse routine of the driver. 1716 * Deficiencies (for now): 1717 * 1) always uses programmed I/O 1718 */ 1719 int 1720 aicintr(void *arg) 1721 { 1722 struct aic_softc *sc = arg; 1723 bus_space_tag_t iot = sc->sc_iot; 1724 bus_space_handle_t ioh = sc->sc_ioh; 1725 u_char sstat0, sstat1; 1726 struct aic_acb *acb; 1727 struct scsipi_periph *periph; 1728 struct aic_tinfo *ti; 1729 int n; 1730 1731 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1732 return (0); 1733 1734 /* 1735 * Clear INTEN. We enable it again before returning. This makes the 1736 * interrupt esssentially level-triggered. 1737 */ 1738 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1739 1740 AIC_TRACE(("aicintr ")); 1741 1742 loop: 1743 /* 1744 * First check for abnormal conditions, such as reset. 1745 */ 1746 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1747 AIC_MISC(("sstat1:0x%02x ", sstat1)); 1748 1749 if ((sstat1 & SCSIRSTI) != 0) { 1750 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1751 goto reset; 1752 } 1753 1754 /* 1755 * Check for less serious errors. 1756 */ 1757 if ((sstat1 & SCSIPERR) != 0) { 1758 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1759 bus_space_write_1(iot, ioh, CLRSINT1, CLRSCSIPERR); 1760 if (sc->sc_prevphase == PH_MSGIN) { 1761 sc->sc_flags |= AIC_DROP_MSGIN; 1762 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1763 } else 1764 aic_sched_msgout(sc, SEND_INIT_DET_ERR); 1765 } 1766 1767 /* 1768 * If we're not already busy doing something test for the following 1769 * conditions: 1770 * 1) We have been reselected by something 1771 * 2) We have selected something successfully 1772 * 3) Our selection process has timed out 1773 * 4) This is really a bus free interrupt just to get a new command 1774 * going? 1775 * 5) Spurious interrupt? 1776 */ 1777 switch (sc->sc_state) { 1778 case AIC_IDLE: 1779 case AIC_SELECTING: 1780 sstat0 = bus_space_read_1(iot, ioh, SSTAT0); 1781 AIC_MISC(("sstat0:0x%02x ", sstat0)); 1782 1783 if ((sstat0 & TARGET) != 0) { 1784 /* 1785 * We don't currently support target mode. 1786 */ 1787 printf("%s: target mode selected; going to BUS FREE\n", 1788 sc->sc_dev.dv_xname); 1789 bus_space_write_1(iot, ioh, SCSISIG, 0); 1790 1791 goto sched; 1792 } else if ((sstat0 & SELDI) != 0) { 1793 AIC_MISC(("reselected ")); 1794 1795 /* 1796 * If we're trying to select a target ourselves, 1797 * push our command back into the ready list. 1798 */ 1799 if (sc->sc_state == AIC_SELECTING) { 1800 AIC_MISC(("backoff selector ")); 1801 AIC_ASSERT(sc->sc_nexus != NULL); 1802 acb = sc->sc_nexus; 1803 sc->sc_nexus = NULL; 1804 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1805 } 1806 1807 /* Save reselection ID. */ 1808 sc->sc_selid = bus_space_read_1(iot, ioh, SELID); 1809 1810 sc->sc_state = AIC_RESELECTED; 1811 } else if ((sstat0 & SELDO) != 0) { 1812 AIC_MISC(("selected ")); 1813 1814 /* We have selected a target. Things to do: 1815 * a) Determine what message(s) to send. 1816 * b) Verify that we're still selecting the target. 1817 * c) Mark device as busy. 1818 */ 1819 if (sc->sc_state != AIC_SELECTING) { 1820 printf("%s: selection out while idle; " 1821 "resetting\n", sc->sc_dev.dv_xname); 1822 AIC_BREAK(); 1823 goto reset; 1824 } 1825 AIC_ASSERT(sc->sc_nexus != NULL); 1826 acb = sc->sc_nexus; 1827 periph = acb->xs->xs_periph; 1828 ti = &sc->sc_tinfo[periph->periph_target]; 1829 1830 sc->sc_msgpriq = SEND_IDENTIFY; 1831 if (acb->flags & ACB_RESET) 1832 sc->sc_msgpriq |= SEND_DEV_RESET; 1833 else if (acb->flags & ACB_ABORT) 1834 sc->sc_msgpriq |= SEND_ABORT; 1835 else { 1836 #if AIC_USE_SYNCHRONOUS 1837 if ((ti->flags & DO_SYNC) != 0) 1838 sc->sc_msgpriq |= SEND_SDTR; 1839 #endif 1840 #if AIC_USE_WIDE 1841 if ((ti->flags & DO_WIDE) != 0) 1842 sc->sc_msgpriq |= SEND_WDTR; 1843 #endif 1844 } 1845 1846 acb->flags |= ACB_NEXUS; 1847 ti->lubusy |= (1 << periph->periph_lun); 1848 1849 /* Do an implicit RESTORE POINTERS. */ 1850 sc->sc_dp = acb->data_addr; 1851 sc->sc_dleft = acb->data_length; 1852 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1853 sc->sc_cleft = acb->scsipi_cmd_length; 1854 1855 /* On our first connection, schedule a timeout. */ 1856 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1857 callout_reset(&acb->xs->xs_callout, 1858 mstohz(acb->timeout), aic_timeout, acb); 1859 1860 sc->sc_state = AIC_CONNECTED; 1861 } else if ((sstat1 & SELTO) != 0) { 1862 AIC_MISC(("selection timeout ")); 1863 1864 if (sc->sc_state != AIC_SELECTING) { 1865 printf("%s: selection timeout while idle; " 1866 "resetting\n", sc->sc_dev.dv_xname); 1867 AIC_BREAK(); 1868 goto reset; 1869 } 1870 AIC_ASSERT(sc->sc_nexus != NULL); 1871 acb = sc->sc_nexus; 1872 1873 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1874 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 1875 bus_space_write_1(iot, ioh, CLRSINT1, CLRSELTIMO); 1876 delay(250); 1877 1878 acb->xs->error = XS_SELTIMEOUT; 1879 goto finish; 1880 } else { 1881 if (sc->sc_state != AIC_IDLE) { 1882 printf("%s: BUS FREE while not idle; " 1883 "state=%d\n", 1884 sc->sc_dev.dv_xname, sc->sc_state); 1885 AIC_BREAK(); 1886 goto out; 1887 } 1888 1889 goto sched; 1890 } 1891 1892 /* 1893 * Turn off selection stuff, and prepare to catch bus free 1894 * interrupts, parity errors, and phase changes. 1895 */ 1896 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRSTCNT | CLRCH); 1897 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1898 bus_space_write_1(iot, ioh, SCSISEQ, ENAUTOATNP); 1899 bus_space_write_1(iot, ioh, CLRSINT0, CLRSELDI | CLRSELDO); 1900 bus_space_write_1(iot, ioh, CLRSINT1, 1901 CLRBUSFREE | CLRPHASECHG); 1902 bus_space_write_1(iot, ioh, SIMODE0, 0); 1903 bus_space_write_1(iot, ioh, SIMODE1, 1904 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | 1905 ENPHASECHG); 1906 1907 sc->sc_flags = 0; 1908 sc->sc_prevphase = PH_INVALID; 1909 goto dophase; 1910 } 1911 1912 if ((sstat1 & BUSFREE) != 0) { 1913 /* We've gone to BUS FREE phase. */ 1914 bus_space_write_1(iot, ioh, CLRSINT1, 1915 CLRBUSFREE | CLRPHASECHG); 1916 1917 switch (sc->sc_state) { 1918 case AIC_RESELECTED: 1919 goto sched; 1920 1921 case AIC_CONNECTED: 1922 AIC_ASSERT(sc->sc_nexus != NULL); 1923 acb = sc->sc_nexus; 1924 1925 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1926 if (sc->sc_prevphase == PH_MSGOUT) { 1927 /* 1928 * If the target went to BUS FREE phase during 1929 * or immediately after sending a SDTR or WDTR 1930 * message, disable negotiation. 1931 */ 1932 periph = acb->xs->xs_periph; 1933 ti = &sc->sc_tinfo[periph->periph_target]; 1934 switch (sc->sc_lastmsg) { 1935 #if AIC_USE_SYNCHRONOUS 1936 case SEND_SDTR: 1937 ti->flags &= ~DO_SYNC; 1938 ti->period = ti->offset = 0; 1939 break; 1940 #endif 1941 #if AIC_USE_WIDE 1942 case SEND_WDTR: 1943 ti->flags &= ~DO_WIDE; 1944 ti->width = 0; 1945 break; 1946 #endif 1947 } 1948 } 1949 #endif 1950 1951 if ((sc->sc_flags & AIC_ABORTING) == 0) { 1952 /* 1953 * Section 5.1.1 of the SCSI 2 spec suggests 1954 * issuing a REQUEST SENSE following an 1955 * unexpected disconnect. Some devices go into 1956 * a contingent allegiance condition when 1957 * disconnecting, and this is necessary to 1958 * clean up their state. 1959 */ 1960 printf("%s: unexpected disconnect; " 1961 "sending REQUEST SENSE\n", 1962 sc->sc_dev.dv_xname); 1963 AIC_BREAK(); 1964 aic_sense(sc, acb); 1965 goto out; 1966 } 1967 1968 acb->xs->error = XS_DRIVER_STUFFUP; 1969 goto finish; 1970 1971 case AIC_DISCONNECT: 1972 AIC_ASSERT(sc->sc_nexus != NULL); 1973 acb = sc->sc_nexus; 1974 #if 1 /* XXXX */ 1975 acb->data_addr = sc->sc_dp; 1976 acb->data_length = sc->sc_dleft; 1977 #endif 1978 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1979 sc->sc_nexus = NULL; 1980 goto sched; 1981 1982 case AIC_CMDCOMPLETE: 1983 AIC_ASSERT(sc->sc_nexus != NULL); 1984 acb = sc->sc_nexus; 1985 goto finish; 1986 } 1987 } 1988 1989 bus_space_write_1(iot, ioh, CLRSINT1, CLRPHASECHG); 1990 1991 dophase: 1992 if ((sstat1 & REQINIT) == 0) { 1993 /* Wait for REQINIT. */ 1994 goto out; 1995 } 1996 1997 sc->sc_phase = bus_space_read_1(iot, ioh, SCSISIG) & PH_MASK; 1998 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase); 1999 2000 switch (sc->sc_phase) { 2001 case PH_MSGOUT: 2002 if (sc->sc_state != AIC_CONNECTED && 2003 sc->sc_state != AIC_RESELECTED) 2004 break; 2005 aic_msgout(sc); 2006 sc->sc_prevphase = PH_MSGOUT; 2007 goto loop; 2008 2009 case PH_MSGIN: 2010 if (sc->sc_state != AIC_CONNECTED && 2011 sc->sc_state != AIC_RESELECTED) 2012 break; 2013 aic_msgin(sc); 2014 sc->sc_prevphase = PH_MSGIN; 2015 goto loop; 2016 2017 case PH_CMD: 2018 if (sc->sc_state != AIC_CONNECTED) 2019 break; 2020 #if AIC_DEBUG 2021 if ((aic_debug & AIC_SHOWMISC) != 0) { 2022 AIC_ASSERT(sc->sc_nexus != NULL); 2023 acb = sc->sc_nexus; 2024 printf("cmd=0x%02x+%d ", 2025 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length-1); 2026 } 2027 #endif 2028 n = aic_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 2029 sc->sc_cp += n; 2030 sc->sc_cleft -= n; 2031 sc->sc_prevphase = PH_CMD; 2032 goto loop; 2033 2034 case PH_DATAOUT: 2035 if (sc->sc_state != AIC_CONNECTED) 2036 break; 2037 AIC_MISC(("dataout %ld ", (long)sc->sc_dleft)); 2038 n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 2039 sc->sc_dp += n; 2040 sc->sc_dleft -= n; 2041 sc->sc_prevphase = PH_DATAOUT; 2042 goto loop; 2043 2044 case PH_DATAIN: 2045 if (sc->sc_state != AIC_CONNECTED) 2046 break; 2047 AIC_MISC(("datain %ld ", (long)sc->sc_dleft)); 2048 n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 2049 sc->sc_dp += n; 2050 sc->sc_dleft -= n; 2051 sc->sc_prevphase = PH_DATAIN; 2052 goto loop; 2053 2054 case PH_STAT: 2055 if (sc->sc_state != AIC_CONNECTED) 2056 break; 2057 AIC_ASSERT(sc->sc_nexus != NULL); 2058 acb = sc->sc_nexus; 2059 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 2060 acb->target_stat = bus_space_read_1(iot, ioh, SCSIDAT); 2061 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 2062 AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2063 sc->sc_prevphase = PH_STAT; 2064 goto loop; 2065 } 2066 2067 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2068 AIC_BREAK(); 2069 reset: 2070 aic_init(sc, 1); 2071 return 1; 2072 2073 finish: 2074 callout_stop(&acb->xs->xs_callout); 2075 aic_done(sc, acb); 2076 goto out; 2077 2078 sched: 2079 sc->sc_state = AIC_IDLE; 2080 aic_sched(sc); 2081 goto out; 2082 2083 out: 2084 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 2085 return 1; 2086 } 2087 2088 void 2089 aic_abort(struct aic_softc *sc, struct aic_acb *acb) 2090 { 2091 2092 /* 2 secs for the abort */ 2093 acb->timeout = AIC_ABORT_TIMEOUT; 2094 acb->flags |= ACB_ABORT; 2095 2096 if (acb == sc->sc_nexus) { 2097 /* 2098 * If we're still selecting, the message will be scheduled 2099 * after selection is complete. 2100 */ 2101 if (sc->sc_state == AIC_CONNECTED) 2102 aic_sched_msgout(sc, SEND_ABORT); 2103 } else { 2104 aic_dequeue(sc, acb); 2105 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2106 if (sc->sc_state == AIC_IDLE) 2107 aic_sched(sc); 2108 } 2109 } 2110 2111 void 2112 aic_timeout(void *arg) 2113 { 2114 struct aic_acb *acb = arg; 2115 struct scsipi_xfer *xs = acb->xs; 2116 struct scsipi_periph *periph = xs->xs_periph; 2117 struct aic_softc *sc = 2118 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2119 int s; 2120 2121 scsipi_printaddr(periph); 2122 printf("timed out"); 2123 2124 s = splbio(); 2125 2126 if (acb->flags & ACB_ABORT) { 2127 /* abort timed out */ 2128 printf(" AGAIN\n"); 2129 /* XXX Must reset! */ 2130 } else { 2131 /* abort the operation that has timed out */ 2132 printf("\n"); 2133 acb->xs->error = XS_TIMEOUT; 2134 aic_abort(sc, acb); 2135 } 2136 2137 splx(s); 2138 } 2139 2140 #ifdef AIC_DEBUG 2141 /* 2142 * The following functions are mostly used for debugging purposes, either 2143 * directly called from the driver or from the kernel debugger. 2144 */ 2145 2146 void 2147 aic_show_scsi_cmd(struct aic_acb *acb) 2148 { 2149 u_char *b = (u_char *)&acb->scsipi_cmd; 2150 struct scsipi_periph *periph = acb->xs->xs_periph; 2151 int i; 2152 2153 scsipi_printaddr(periph); 2154 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2155 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2156 if (i) 2157 printf(","); 2158 printf("%x", b[i]); 2159 } 2160 printf("\n"); 2161 } else 2162 printf("RESET\n"); 2163 } 2164 2165 void 2166 aic_print_acb(struct aic_acb *acb) 2167 { 2168 2169 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2170 printf(" dp=%p dleft=%d target_stat=%x\n", 2171 acb->data_addr, acb->data_length, acb->target_stat); 2172 aic_show_scsi_cmd(acb); 2173 } 2174 2175 void 2176 aic_print_active_acb(void) 2177 { 2178 extern struct cfdriver aic_cd; 2179 struct aic_acb *acb; 2180 struct aic_softc *sc = aic_cd.cd_devs[0]; 2181 2182 printf("ready list:\n"); 2183 for (acb = sc->ready_list.tqh_first; acb != NULL; 2184 acb = acb->chain.tqe_next) 2185 aic_print_acb(acb); 2186 printf("nexus:\n"); 2187 if (sc->sc_nexus != NULL) 2188 aic_print_acb(sc->sc_nexus); 2189 printf("nexus list:\n"); 2190 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2191 acb = acb->chain.tqe_next) 2192 aic_print_acb(acb); 2193 } 2194 2195 void 2196 aic_dump6360(struct aic_softc *sc) 2197 { 2198 bus_space_tag_t iot = sc->sc_iot; 2199 bus_space_handle_t ioh = sc->sc_ioh; 2200 2201 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIG=%x\n", 2202 bus_space_read_1(iot, ioh, SCSISEQ), 2203 bus_space_read_1(iot, ioh, SXFRCTL0), 2204 bus_space_read_1(iot, ioh, SXFRCTL1), 2205 bus_space_read_1(iot, ioh, SCSISIG)); 2206 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2207 bus_space_read_1(iot, ioh, SSTAT0), 2208 bus_space_read_1(iot, ioh, SSTAT1), 2209 bus_space_read_1(iot, ioh, SSTAT2), 2210 bus_space_read_1(iot, ioh, SSTAT3), 2211 bus_space_read_1(iot, ioh, SSTAT4)); 2212 printf(" SIMODE0=%x SIMODE1=%x DMACNTRL0=%x DMACNTRL1=%x " 2213 "DMASTAT=%x\n", 2214 bus_space_read_1(iot, ioh, SIMODE0), 2215 bus_space_read_1(iot, ioh, SIMODE1), 2216 bus_space_read_1(iot, ioh, DMACNTRL0), 2217 bus_space_read_1(iot, ioh, DMACNTRL1), 2218 bus_space_read_1(iot, ioh, DMASTAT)); 2219 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2220 bus_space_read_1(iot, ioh, FIFOSTAT), 2221 bus_space_read_1(iot, ioh, SCSIBUS)); 2222 } 2223 2224 void 2225 aic_dump_driver(struct aic_softc *sc) 2226 { 2227 struct aic_tinfo *ti; 2228 int i; 2229 2230 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2231 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2232 "currmsg=%x\n", 2233 sc->sc_state, sc->sc_imess[0], 2234 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2235 for (i = 0; i < 7; i++) { 2236 ti = &sc->sc_tinfo[i]; 2237 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2238 i, ti->cmds, ti->dconns, ti->touts); 2239 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2240 } 2241 } 2242 #endif
Cache object: af56f0a4b5234fb427cfb12dff63edd2
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