Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/aic6360.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: aic6360.c,v 1.92 2006/11/16 01:32:50 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1995, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * Copyright (c) 1994 Jarle Greipsland 21 * All rights reserved. 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 1. Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * 2. Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in the 30 * documentation and/or other materials provided with the distribution. 31 * 3. The name of the author may not be used to endorse or promote products 32 * derived from this software without specific prior written permission. 33 * 34 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 35 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 36 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 37 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 38 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 39 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 40 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 41 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 42 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 43 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 44 * POSSIBILITY OF SUCH DAMAGE. 45 */ 46 47 /* 48 * Acknowledgements: Many of the algorithms used in this driver are 49 * inspired by the work of Julian Elischer (julian@tfs.com) and 50 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 51 */ 52 53 /* TODO list: 54 * 1) Get the DMA stuff working. 55 * 2) Get the iov/uio stuff working. Is this a good thing ??? 56 * 3) Get the synch stuff working. 57 * 4) Rewrite it to use malloc for the acb structs instead of static alloc.? 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: aic6360.c,v 1.92 2006/11/16 01:32:50 christos Exp $"); 62 63 #include "opt_ddb.h" 64 65 /* 66 * A few customizable items: 67 */ 68 69 /* Use doubleword transfers to/from SCSI chip. Note: This requires 70 * motherboard support. Basicly, some motherboard chipsets are able to 71 * split a 32 bit I/O operation into two 16 bit I/O operations, 72 * transparently to the processor. This speeds up some things, notably long 73 * data transfers. 74 */ 75 #define AIC_USE_DWORDS 0 76 77 /* Synchronous data transfers? */ 78 #define AIC_USE_SYNCHRONOUS 0 79 #define AIC_SYNC_REQ_ACK_OFS 8 80 81 /* Wide data transfers? */ 82 #define AIC_USE_WIDE 0 83 #define AIC_MAX_WIDTH 0 84 85 /* Max attempts made to transmit a message */ 86 #define AIC_MSG_MAX_ATTEMPT 3 /* Not used now XXX */ 87 88 /* Use DMA (else we do programmed I/O using string instructions) (not yet!)*/ 89 #define AIC_USE_EISA_DMA 0 90 #define AIC_USE_ISA_DMA 0 91 92 /* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 93 #define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 94 95 /* Some spin loop parameters (essentially how long to wait some places) 96 * The problem(?) is that sometimes we expect either to be able to transmit a 97 * byte or to get a new one from the SCSI bus pretty soon. In order to avoid 98 * returning from the interrupt just to get yanked back for the next byte we 99 * may spin in the interrupt routine waiting for this byte to come. How long? 100 * This is really (SCSI) device and processor dependent. Tuneable, I guess. 101 */ 102 #define AIC_MSGIN_SPIN 1 /* Will spinwait upto ?ms for a new msg byte */ 103 #define AIC_MSGOUT_SPIN 1 104 105 /* Include debug functions? At the end of this file there are a bunch of 106 * functions that will print out various information regarding queued SCSI 107 * commands, driver state and chip contents. You can call them from the 108 * kernel debugger. If you set AIC_DEBUG to 0 they are not included (the 109 * kernel uses less memory) but you lose the debugging facilities. 110 */ 111 #define AIC_DEBUG 1 112 113 #define AIC_ABORT_TIMEOUT 2000 /* time to wait for abort */ 114 115 /* End of customizable parameters */ 116 117 #if AIC_USE_EISA_DMA || AIC_USE_ISA_DMA 118 #error "I said not yet! Start paying attention... grumble" 119 #endif 120 121 #include <sys/param.h> 122 #include <sys/systm.h> 123 #include <sys/callout.h> 124 #include <sys/kernel.h> 125 #include <sys/errno.h> 126 #include <sys/ioctl.h> 127 #include <sys/device.h> 128 #include <sys/buf.h> 129 #include <sys/proc.h> 130 #include <sys/user.h> 131 #include <sys/queue.h> 132 133 #include <machine/bus.h> 134 #include <machine/intr.h> 135 136 #include <dev/scsipi/scsi_spc.h> 137 #include <dev/scsipi/scsi_all.h> 138 #include <dev/scsipi/scsipi_all.h> 139 #include <dev/scsipi/scsi_message.h> 140 #include <dev/scsipi/scsiconf.h> 141 142 #include <dev/ic/aic6360reg.h> 143 #include <dev/ic/aic6360var.h> 144 145 #ifndef DDB 146 #define Debugger() panic("should call debugger here (aic6360.c)") 147 #endif /* ! DDB */ 148 149 #if AIC_DEBUG 150 int aic_debug = 0x00; /* AIC_SHOWSTART|AIC_SHOWMISC|AIC_SHOWTRACE; */ 151 #endif 152 153 static void aic_minphys(struct buf *); 154 static void aic_done(struct aic_softc *, struct aic_acb *); 155 static void aic_dequeue(struct aic_softc *, struct aic_acb *); 156 static void aic_scsipi_request(struct scsipi_channel *, 157 scsipi_adapter_req_t, void *); 158 static int aic_poll(struct aic_softc *, struct scsipi_xfer *, int); 159 static void aic_select(struct aic_softc *, struct aic_acb *); 160 static void aic_timeout(void *); 161 static void aic_sched(struct aic_softc *); 162 static void aic_scsi_reset(struct aic_softc *); 163 static void aic_reset(struct aic_softc *); 164 static void aic_free_acb(struct aic_softc *, struct aic_acb *); 165 static struct aic_acb* aic_get_acb(struct aic_softc *); 166 static int aic_reselect(struct aic_softc *, int); 167 static void aic_sense(struct aic_softc *, struct aic_acb *); 168 static void aic_msgin(struct aic_softc *); 169 static void aic_abort(struct aic_softc *, struct aic_acb *); 170 static void aic_msgout(struct aic_softc *); 171 static int aic_dataout_pio(struct aic_softc *, u_char *, int); 172 static int aic_datain_pio(struct aic_softc *, u_char *, int); 173 static void aic_update_xfer_mode(struct aic_softc *, int); 174 #if AIC_DEBUG 175 static void aic_print_acb(struct aic_acb *); 176 void aic_dump_driver(struct aic_softc *); 177 void aic_dump6360(struct aic_softc *); 178 static void aic_show_scsi_cmd(struct aic_acb *); 179 void aic_print_active_acb(void); 180 #endif 181 182 /* 183 * INITIALIZATION ROUTINES (probe, attach ++) 184 */ 185 186 /* Do the real search-for-device. 187 * Prerequisite: sc->sc_iobase should be set to the proper value 188 */ 189 int 190 aic_find(bus_space_tag_t iot, bus_space_handle_t ioh) 191 { 192 char chip_id[sizeof(IDSTRING)]; /* For chips that support it */ 193 int i; 194 195 /* Remove aic6360 from possible powerdown mode */ 196 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 197 198 /* Thanks to mark@aggregate.com for the new method for detecting 199 * whether the chip is present or not. Bonus: may also work for 200 * the AIC-6260! 201 */ 202 AIC_TRACE(("aic: probing for aic-chip\n")); 203 /* 204 * Linux also init's the stack to 1-16 and then clears it, 205 * 6260's don't appear to have an ID reg - mpg 206 */ 207 /* Push the sequence 0,1,..,15 on the stack */ 208 #define STSIZE 16 209 bus_space_write_1(iot, ioh, DMACNTRL1, 0); /* Reset stack pointer */ 210 for (i = 0; i < STSIZE; i++) 211 bus_space_write_1(iot, ioh, STACK, i); 212 213 /* See if we can pull out the same sequence */ 214 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 215 for (i = 0; i < STSIZE && bus_space_read_1(iot, ioh, STACK) == i; i++) 216 ; 217 if (i != STSIZE) { 218 AIC_START(("STACK futzed at %d.\n", i)); 219 return 0; 220 } 221 222 /* See if we can pull the id string out of the ID register, 223 * now only used for informational purposes. 224 */ 225 memset(chip_id, 0, sizeof(chip_id)); 226 bus_space_read_multi_1(iot, ioh, ID, chip_id, sizeof(IDSTRING) - 1); 227 AIC_START(("AIC found ID: %s ",chip_id)); 228 AIC_START(("chip revision %d\n", 229 (int)bus_space_read_1(iot, ioh, REV))); 230 231 return 1; 232 } 233 234 /* 235 * Attach the AIC6360, fill out some high and low level data structures 236 */ 237 void 238 aicattach(struct aic_softc *sc) 239 { 240 struct scsipi_adapter *adapt = &sc->sc_adapter; 241 struct scsipi_channel *chan = &sc->sc_channel; 242 243 AIC_TRACE(("aicattach ")); 244 sc->sc_state = AIC_INIT; 245 246 sc->sc_initiator = 7; 247 sc->sc_freq = 20; /* XXXX Assume 20 MHz. */ 248 249 /* 250 * These are the bounds of the sync period, based on the frequency of 251 * the chip's clock input and the size and offset of the sync period 252 * register. 253 * 254 * For a 20MHz clock, this gives us 25, or 100nS, or 10MB/s, as a 255 * maximum transfer rate, and 112.5, or 450nS, or 2.22MB/s, as a 256 * minimum transfer rate. 257 */ 258 sc->sc_minsync = (2 * 250) / sc->sc_freq; 259 sc->sc_maxsync = (9 * 250) / sc->sc_freq; 260 261 /* 262 * Fill in the scsipi_adapter. 263 */ 264 adapt->adapt_dev = &sc->sc_dev; 265 adapt->adapt_nchannels = 1; 266 adapt->adapt_openings = 8; 267 adapt->adapt_max_periph = 1; 268 adapt->adapt_request = aic_scsipi_request; 269 adapt->adapt_minphys = aic_minphys; 270 271 /* 272 * Fill in the scsipi_channel. 273 */ 274 chan->chan_adapter = adapt; 275 chan->chan_bustype = &scsi_bustype; 276 chan->chan_channel = 0; 277 chan->chan_ntargets = 8; 278 chan->chan_nluns = 8; 279 chan->chan_id = sc->sc_initiator; 280 281 /* 282 * Add reference to adapter so that we drop the reference after 283 * config_found() to make sure the adatper is disabled. 284 */ 285 if (scsipi_adapter_addref(adapt) != 0) { 286 printf("%s: unable to enable controller\n", 287 sc->sc_dev.dv_xname); 288 return; 289 } 290 291 aic_init(sc, 1); /* Init chip and driver */ 292 293 /* 294 * Ask the adapter what subunits are present 295 */ 296 sc->sc_child = config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 297 scsipi_adapter_delref(adapt); 298 } 299 300 int 301 aic_activate(struct device *self, enum devact act) 302 { 303 struct aic_softc *sc = (struct aic_softc *) self; 304 int s, rv = 0; 305 306 s = splhigh(); 307 switch (act) { 308 case DVACT_ACTIVATE: 309 rv = EOPNOTSUPP; 310 break; 311 312 case DVACT_DEACTIVATE: 313 if (sc->sc_child != NULL) 314 rv = config_deactivate(sc->sc_child); 315 break; 316 } 317 splx(s); 318 319 return (rv); 320 } 321 322 int 323 aic_detach(struct device *self, int flags) 324 { 325 struct aic_softc *sc = (struct aic_softc *) self; 326 int rv = 0; 327 328 if (sc->sc_child != NULL) 329 rv = config_detach(sc->sc_child, flags); 330 331 return (rv); 332 } 333 334 /* Initialize AIC6360 chip itself 335 * The following conditions should hold: 336 * aic_isa_probe should have succeeded, i.e. the iobase address in aic_softc 337 * must be valid. 338 */ 339 static void 340 aic_reset(struct aic_softc *sc) 341 { 342 bus_space_tag_t iot = sc->sc_iot; 343 bus_space_handle_t ioh = sc->sc_ioh; 344 345 /* 346 * Doc. recommends to clear these two registers before 347 * operations commence 348 */ 349 bus_space_write_1(iot, ioh, SCSITEST, 0); 350 bus_space_write_1(iot, ioh, TEST, 0); 351 352 /* Reset SCSI-FIFO and abort any transfers */ 353 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH | CLRSTCNT); 354 355 /* Reset DMA-FIFO */ 356 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 357 bus_space_write_1(iot, ioh, DMACNTRL1, 0); 358 359 /* Disable all selection features */ 360 bus_space_write_1(iot, ioh, SCSISEQ, 0); 361 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 362 363 /* Disable some interrupts */ 364 bus_space_write_1(iot, ioh, SIMODE0, 0x00); 365 /* Clear a slew of interrupts */ 366 bus_space_write_1(iot, ioh, CLRSINT0, 0x7f); 367 368 /* Disable some more interrupts */ 369 bus_space_write_1(iot, ioh, SIMODE1, 0x00); 370 /* Clear another slew of interrupts */ 371 bus_space_write_1(iot, ioh, CLRSINT1, 0xef); 372 373 /* Disable synchronous transfers */ 374 bus_space_write_1(iot, ioh, SCSIRATE, 0); 375 376 /* Haven't seen ant errors (yet) */ 377 bus_space_write_1(iot, ioh, CLRSERR, 0x07); 378 379 /* Set our SCSI-ID */ 380 bus_space_write_1(iot, ioh, SCSIID, sc->sc_initiator << OID_S); 381 bus_space_write_1(iot, ioh, BRSTCNTRL, EISA_BRST_TIM); 382 } 383 384 /* Pull the SCSI RST line for 500 us */ 385 static void 386 aic_scsi_reset(struct aic_softc *sc) 387 { 388 bus_space_tag_t iot = sc->sc_iot; 389 bus_space_handle_t ioh = sc->sc_ioh; 390 391 bus_space_write_1(iot, ioh, SCSISEQ, SCSIRSTO); 392 delay(500); 393 bus_space_write_1(iot, ioh, SCSISEQ, 0); 394 delay(50); 395 } 396 397 /* 398 * Initialize aic SCSI driver. 399 */ 400 void 401 aic_init(struct aic_softc *sc, int bus_reset) 402 { 403 struct aic_acb *acb; 404 int r; 405 406 if (bus_reset) { 407 aic_reset(sc); 408 aic_scsi_reset(sc); 409 } 410 aic_reset(sc); 411 412 if (sc->sc_state == AIC_INIT) { 413 /* First time through; initialize. */ 414 TAILQ_INIT(&sc->ready_list); 415 TAILQ_INIT(&sc->nexus_list); 416 TAILQ_INIT(&sc->free_list); 417 sc->sc_nexus = NULL; 418 acb = sc->sc_acb; 419 memset(acb, 0, sizeof(sc->sc_acb)); 420 for (r = 0; r < sizeof(sc->sc_acb) / sizeof(*acb); r++) { 421 TAILQ_INSERT_TAIL(&sc->free_list, acb, chain); 422 acb++; 423 } 424 memset(&sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 425 } else { 426 /* Cancel any active commands. */ 427 sc->sc_state = AIC_CLEANING; 428 if ((acb = sc->sc_nexus) != NULL) { 429 acb->xs->error = XS_DRIVER_STUFFUP; 430 callout_stop(&acb->xs->xs_callout); 431 aic_done(sc, acb); 432 } 433 while ((acb = sc->nexus_list.tqh_first) != NULL) { 434 acb->xs->error = XS_DRIVER_STUFFUP; 435 callout_stop(&acb->xs->xs_callout); 436 aic_done(sc, acb); 437 } 438 } 439 440 sc->sc_prevphase = PH_INVALID; 441 for (r = 0; r < 8; r++) { 442 struct aic_tinfo *ti = &sc->sc_tinfo[r]; 443 444 ti->flags = 0; 445 ti->period = ti->offset = 0; 446 ti->width = 0; 447 } 448 449 sc->sc_state = AIC_IDLE; 450 bus_space_write_1(sc->sc_iot, sc->sc_ioh, DMACNTRL0, INTEN); 451 } 452 453 static void 454 aic_free_acb(struct aic_softc *sc, struct aic_acb *acb) 455 { 456 int s; 457 458 s = splbio(); 459 acb->flags = 0; 460 TAILQ_INSERT_HEAD(&sc->free_list, acb, chain); 461 splx(s); 462 } 463 464 static struct aic_acb * 465 aic_get_acb(struct aic_softc *sc) 466 { 467 struct aic_acb *acb; 468 int s; 469 470 s = splbio(); 471 acb = TAILQ_FIRST(&sc->free_list); 472 if (acb != NULL) { 473 TAILQ_REMOVE(&sc->free_list, acb, chain); 474 acb->flags |= ACB_ALLOC; 475 } 476 splx(s); 477 return (acb); 478 } 479 480 /* 481 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS 482 */ 483 484 /* 485 * Expected sequence: 486 * 1) Command inserted into ready list 487 * 2) Command selected for execution 488 * 3) Command won arbitration and has selected target device 489 * 4) Send message out (identify message, eventually also sync.negotiations) 490 * 5) Send command 491 * 5a) Receive disconnect message, disconnect. 492 * 5b) Reselected by target 493 * 5c) Receive identify message from target. 494 * 6) Send or receive data 495 * 7) Receive status 496 * 8) Receive message (command complete etc.) 497 * 9) If status == SCSI_CHECK construct a synthetic request sense SCSI cmd. 498 * Repeat 2-8 (no disconnects please...) 499 */ 500 501 /* 502 * Perform a request from the SCSIPI midlayer. 503 */ 504 static void 505 aic_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 506 void *arg) 507 { 508 struct scsipi_xfer *xs; 509 struct scsipi_periph *periph; 510 struct aic_softc *sc = (void *)chan->chan_adapter->adapt_dev; 511 struct aic_acb *acb; 512 int s, flags; 513 514 AIC_TRACE(("aic_request ")); 515 516 switch (req) { 517 case ADAPTER_REQ_RUN_XFER: 518 xs = arg; 519 periph = xs->xs_periph; 520 521 AIC_CMDS(("[0x%x, %d]->%d ", (int)xs->cmd->opcode, xs->cmdlen, 522 periph->periph_target)); 523 524 if (! device_is_active(&sc->sc_dev)) { 525 xs->error = XS_DRIVER_STUFFUP; 526 scsipi_done(xs); 527 return; 528 } 529 530 flags = xs->xs_control; 531 acb = aic_get_acb(sc); 532 #ifdef DIAGNOSTIC 533 /* 534 * This should never happen as we track the resources 535 * in the mid-layer. 536 */ 537 if (acb == NULL) { 538 scsipi_printaddr(periph); 539 printf("unable to allocate acb\n"); 540 panic("aic_scsipi_request"); 541 } 542 #endif 543 544 /* Initialize acb */ 545 acb->xs = xs; 546 acb->timeout = xs->timeout; 547 548 if (xs->xs_control & XS_CTL_RESET) { 549 acb->flags |= ACB_RESET; 550 acb->scsipi_cmd_length = 0; 551 acb->data_length = 0; 552 } else { 553 memcpy(&acb->scsipi_cmd, xs->cmd, xs->cmdlen); 554 acb->scsipi_cmd_length = xs->cmdlen; 555 acb->data_addr = xs->data; 556 acb->data_length = xs->datalen; 557 } 558 acb->target_stat = 0; 559 560 s = splbio(); 561 562 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain); 563 if (sc->sc_state == AIC_IDLE) 564 aic_sched(sc); 565 566 splx(s); 567 568 if ((flags & XS_CTL_POLL) == 0) 569 return; 570 571 /* Not allowed to use interrupts, use polling instead */ 572 if (aic_poll(sc, xs, acb->timeout)) { 573 aic_timeout(acb); 574 if (aic_poll(sc, xs, acb->timeout)) 575 aic_timeout(acb); 576 } 577 return; 578 579 case ADAPTER_REQ_GROW_RESOURCES: 580 /* XXX Not supported. */ 581 return; 582 583 case ADAPTER_REQ_SET_XFER_MODE: 584 { 585 struct aic_tinfo *ti; 586 struct scsipi_xfer_mode *xm = arg; 587 588 ti = &sc->sc_tinfo[xm->xm_target]; 589 ti->flags &= ~(DO_SYNC|DO_WIDE); 590 ti->period = 0; 591 ti->offset = 0; 592 593 #if AIC_USE_SYNCHRONOUS 594 if (xm->xm_mode & PERIPH_CAP_SYNC) { 595 ti->flags |= DO_SYNC; 596 ti->period = sc->sc_minsync; 597 ti->offset = AIC_SYNC_REQ_ACK_OFS; 598 } 599 #endif 600 #if AIC_USE_WIDE 601 if (xm->xm_mode & PERIPH_CAP_WIDE16) { 602 ti->flags |= DO_WIDE; 603 ti->width = AIC_MAX_WIDTH; 604 } 605 #endif 606 /* 607 * If we're not going to negotiate, send the notification 608 * now, since it won't happen later. 609 */ 610 if ((ti->flags & (DO_SYNC|DO_WIDE)) == 0) 611 aic_update_xfer_mode(sc, xm->xm_target); 612 return; 613 } 614 } 615 } 616 617 static void 618 aic_update_xfer_mode(struct aic_softc *sc, int target) 619 { 620 struct scsipi_xfer_mode xm; 621 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 622 623 xm.xm_target = target; 624 xm.xm_mode = 0; 625 xm.xm_period = 0; 626 xm.xm_offset = 0; 627 628 if (ti->offset != 0) { 629 xm.xm_mode |= PERIPH_CAP_SYNC; 630 xm.xm_period = ti->period; 631 xm.xm_offset = ti->offset; 632 } 633 switch (ti->width) { 634 case 2: 635 xm.xm_mode |= PERIPH_CAP_WIDE32; 636 break; 637 case 1: 638 xm.xm_mode |= PERIPH_CAP_WIDE16; 639 break; 640 } 641 642 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 643 } 644 645 /* 646 * Adjust transfer size in buffer structure 647 */ 648 static void 649 aic_minphys(struct buf *bp) 650 { 651 652 AIC_TRACE(("aic_minphys ")); 653 if (bp->b_bcount > (AIC_NSEG << PGSHIFT)) 654 bp->b_bcount = (AIC_NSEG << PGSHIFT); 655 minphys(bp); 656 } 657 658 /* 659 * Used when interrupt driven I/O isn't allowed, e.g. during boot. 660 */ 661 static int 662 aic_poll(struct aic_softc *sc, struct scsipi_xfer *xs, int count) 663 { 664 bus_space_tag_t iot = sc->sc_iot; 665 bus_space_handle_t ioh = sc->sc_ioh; 666 667 AIC_TRACE(("aic_poll ")); 668 while (count) { 669 /* 670 * If we had interrupts enabled, would we 671 * have got an interrupt? 672 */ 673 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) != 0) 674 aicintr(sc); 675 if ((xs->xs_status & XS_STS_DONE) != 0) 676 return 0; 677 delay(1000); 678 count--; 679 } 680 return 1; 681 } 682 683 /* 684 * LOW LEVEL SCSI UTILITIES 685 */ 686 687 static inline void 688 aic_sched_msgout(struct aic_softc *sc, u_char m) 689 { 690 bus_space_tag_t iot = sc->sc_iot; 691 bus_space_handle_t ioh = sc->sc_ioh; 692 693 if (sc->sc_msgpriq == 0) 694 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase | ATNO); 695 sc->sc_msgpriq |= m; 696 } 697 698 /* 699 * Set synchronous transfer offset and period. 700 */ 701 #if !AIC_USE_SYNCHRONOUS 702 /* ARGSUSED */ 703 #endif 704 static inline void 705 aic_setsync(struct aic_softc *sc, struct aic_tinfo *ti) 706 { 707 #if AIC_USE_SYNCHRONOUS 708 bus_space_tag_t iot = sc->sc_iot; 709 bus_space_handle_t ioh = sc->sc_ioh; 710 711 if (ti->offset != 0) 712 bus_space_write_1(iot, ioh, SCSIRATE, 713 ((ti->period * sc->sc_freq) / 250 - 2) << 4 | ti->offset); 714 else 715 bus_space_write_1(iot, ioh, SCSIRATE, 0); 716 #endif 717 } 718 719 /* 720 * Start a selection. This is used by aic_sched() to select an idle target, 721 * and by aic_done() to immediately reselect a target to get sense information. 722 */ 723 static void 724 aic_select(struct aic_softc *sc, struct aic_acb *acb) 725 { 726 struct scsipi_periph *periph = acb->xs->xs_periph; 727 int target = periph->periph_target; 728 struct aic_tinfo *ti = &sc->sc_tinfo[target]; 729 bus_space_tag_t iot = sc->sc_iot; 730 bus_space_handle_t ioh = sc->sc_ioh; 731 732 bus_space_write_1(iot, ioh, SCSIID, 733 sc->sc_initiator << OID_S | target); 734 aic_setsync(sc, ti); 735 bus_space_write_1(iot, ioh, SXFRCTL1, STIMO_256ms | ENSTIMER); 736 737 /* Always enable reselections. */ 738 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI | ENSELDO); 739 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST | ENSELTIMO); 740 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI | ENSELO | ENAUTOATNO); 741 742 sc->sc_state = AIC_SELECTING; 743 } 744 745 static int 746 aic_reselect(struct aic_softc *sc, int message) 747 { 748 u_char selid, target, lun; 749 struct aic_acb *acb; 750 struct scsipi_periph *periph; 751 struct aic_tinfo *ti; 752 753 /* 754 * The SCSI chip made a snapshot of the data bus while the reselection 755 * was being negotiated. This enables us to determine which target did 756 * the reselect. 757 */ 758 selid = sc->sc_selid & ~(1 << sc->sc_initiator); 759 if (selid & (selid - 1)) { 760 printf("%s: reselect with invalid selid %02x; " 761 "sending DEVICE RESET\n", sc->sc_dev.dv_xname, selid); 762 AIC_BREAK(); 763 goto reset; 764 } 765 766 /* Search wait queue for disconnected cmd 767 * The list should be short, so I haven't bothered with 768 * any more sophisticated structures than a simple 769 * singly linked list. 770 */ 771 target = ffs(selid) - 1; 772 lun = message & 0x07; 773 for (acb = sc->nexus_list.tqh_first; acb != NULL; 774 acb = acb->chain.tqe_next) { 775 periph = acb->xs->xs_periph; 776 if (periph->periph_target == target && 777 periph->periph_lun == lun) 778 break; 779 } 780 if (acb == NULL) { 781 printf("%s: reselect from target %d lun %d with no nexus; " 782 "sending ABORT\n", sc->sc_dev.dv_xname, target, lun); 783 AIC_BREAK(); 784 goto abort; 785 } 786 787 /* Make this nexus active again. */ 788 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 789 sc->sc_state = AIC_CONNECTED; 790 sc->sc_nexus = acb; 791 ti = &sc->sc_tinfo[target]; 792 ti->lubusy |= (1 << lun); 793 aic_setsync(sc, ti); 794 795 if (acb->flags & ACB_RESET) 796 aic_sched_msgout(sc, SEND_DEV_RESET); 797 else if (acb->flags & ACB_ABORT) 798 aic_sched_msgout(sc, SEND_ABORT); 799 800 /* Do an implicit RESTORE POINTERS. */ 801 sc->sc_dp = acb->data_addr; 802 sc->sc_dleft = acb->data_length; 803 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 804 sc->sc_cleft = acb->scsipi_cmd_length; 805 806 return (0); 807 808 reset: 809 aic_sched_msgout(sc, SEND_DEV_RESET); 810 return (1); 811 812 abort: 813 aic_sched_msgout(sc, SEND_ABORT); 814 return (1); 815 } 816 817 /* 818 * Schedule a SCSI operation. This has now been pulled out of the interrupt 819 * handler so that we may call it from aic_scsipi_request and aic_done. This 820 * may save us an unnecessary interrupt just to get things going. Should only 821 * be called when state == AIC_IDLE and at bio pl. 822 */ 823 static void 824 aic_sched(struct aic_softc *sc) 825 { 826 struct aic_acb *acb; 827 struct scsipi_periph *periph; 828 struct aic_tinfo *ti; 829 bus_space_tag_t iot = sc->sc_iot; 830 bus_space_handle_t ioh = sc->sc_ioh; 831 832 if (! device_is_active(&sc->sc_dev)) 833 return; 834 835 /* 836 * Find first acb in ready queue that is for a target/lunit pair that 837 * is not busy. 838 */ 839 bus_space_write_1(iot, ioh, CLRSINT1, 840 CLRSELTIMO | CLRBUSFREE | CLRSCSIPERR); 841 for (acb = sc->ready_list.tqh_first; acb != NULL; 842 acb = acb->chain.tqe_next) { 843 periph = acb->xs->xs_periph; 844 ti = &sc->sc_tinfo[periph->periph_target]; 845 if ((ti->lubusy & (1 << periph->periph_lun)) == 0) { 846 AIC_MISC(("selecting %d:%d ", 847 periph->periph_target, periph->periph_lun)); 848 TAILQ_REMOVE(&sc->ready_list, acb, chain); 849 sc->sc_nexus = acb; 850 aic_select(sc, acb); 851 return; 852 } else 853 AIC_MISC(("%d:%d busy\n", 854 periph->periph_target, periph->periph_lun)); 855 } 856 AIC_MISC(("idle ")); 857 /* Nothing to start; just enable reselections and wait. */ 858 bus_space_write_1(iot, ioh, SIMODE0, ENSELDI); 859 bus_space_write_1(iot, ioh, SIMODE1, ENSCSIRST); 860 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 861 } 862 863 static void 864 aic_sense(struct aic_softc *sc, struct aic_acb *acb) 865 { 866 struct scsipi_xfer *xs = acb->xs; 867 struct scsipi_periph *periph = xs->xs_periph; 868 struct aic_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 869 struct scsi_request_sense *ss = (void *)&acb->scsipi_cmd; 870 871 AIC_MISC(("requesting sense ")); 872 /* Next, setup a request sense command block */ 873 memset(ss, 0, sizeof(*ss)); 874 ss->opcode = SCSI_REQUEST_SENSE; 875 ss->byte2 = periph->periph_lun << 5; 876 ss->length = sizeof(struct scsi_sense_data); 877 acb->scsipi_cmd_length = sizeof(*ss); 878 acb->data_addr = (char *)&xs->sense.scsi_sense; 879 acb->data_length = sizeof(struct scsi_sense_data); 880 acb->flags |= ACB_SENSE; 881 ti->senses++; 882 if (acb->flags & ACB_NEXUS) 883 ti->lubusy &= ~(1 << periph->periph_lun); 884 if (acb == sc->sc_nexus) { 885 aic_select(sc, acb); 886 } else { 887 aic_dequeue(sc, acb); 888 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 889 if (sc->sc_state == AIC_IDLE) 890 aic_sched(sc); 891 } 892 } 893 894 /* 895 * POST PROCESSING OF SCSI_CMD (usually current) 896 */ 897 static void 898 aic_done(struct aic_softc *sc, struct aic_acb *acb) 899 { 900 struct scsipi_xfer *xs = acb->xs; 901 struct scsipi_periph *periph = xs->xs_periph; 902 struct aic_tinfo *ti = &sc->sc_tinfo[periph->periph_target]; 903 904 AIC_TRACE(("aic_done ")); 905 906 /* 907 * Now, if we've come here with no error code, i.e. we've kept the 908 * initial XS_NOERROR, and the status code signals that we should 909 * check sense, we'll need to set up a request sense cmd block and 910 * push the command back into the ready queue *before* any other 911 * commands for this target/lunit, else we lose the sense info. 912 * We don't support chk sense conditions for the request sense cmd. 913 */ 914 if (xs->error == XS_NOERROR) { 915 if (acb->flags & ACB_ABORT) { 916 xs->error = XS_DRIVER_STUFFUP; 917 } else if (acb->flags & ACB_SENSE) { 918 xs->error = XS_SENSE; 919 } else if (acb->target_stat == SCSI_CHECK) { 920 /* First, save the return values */ 921 xs->resid = acb->data_length; 922 xs->status = acb->target_stat; 923 aic_sense(sc, acb); 924 return; 925 } else { 926 xs->resid = acb->data_length; 927 } 928 } 929 930 #if AIC_DEBUG 931 if ((aic_debug & AIC_SHOWMISC) != 0) { 932 if (xs->resid != 0) 933 printf("resid=%d ", xs->resid); 934 if (xs->error == XS_SENSE) 935 printf("sense=0x%02x\n", xs->sense.scsi_sense.response_code); 936 else 937 printf("error=%d\n", xs->error); 938 } 939 #endif 940 941 /* 942 * Remove the ACB from whatever queue it happens to be on. 943 */ 944 if (acb->flags & ACB_NEXUS) 945 ti->lubusy &= ~(1 << periph->periph_lun); 946 if (acb == sc->sc_nexus) { 947 sc->sc_nexus = NULL; 948 sc->sc_state = AIC_IDLE; 949 aic_sched(sc); 950 } else 951 aic_dequeue(sc, acb); 952 953 aic_free_acb(sc, acb); 954 ti->cmds++; 955 scsipi_done(xs); 956 } 957 958 static void 959 aic_dequeue(struct aic_softc *sc, struct aic_acb *acb) 960 { 961 962 if (acb->flags & ACB_NEXUS) { 963 TAILQ_REMOVE(&sc->nexus_list, acb, chain); 964 } else { 965 TAILQ_REMOVE(&sc->ready_list, acb, chain); 966 } 967 } 968 969 /* 970 * INTERRUPT/PROTOCOL ENGINE 971 */ 972 973 /* 974 * Precondition: 975 * The SCSI bus is already in the MSGI phase and there is a message byte 976 * on the bus, along with an asserted REQ signal. 977 */ 978 static void 979 aic_msgin(struct aic_softc *sc) 980 { 981 bus_space_tag_t iot = sc->sc_iot; 982 bus_space_handle_t ioh = sc->sc_ioh; 983 u_char sstat1; 984 int n; 985 986 AIC_TRACE(("aic_msgin ")); 987 988 if (sc->sc_prevphase == PH_MSGIN) { 989 /* This is a continuation of the previous message. */ 990 n = sc->sc_imp - sc->sc_imess; 991 goto nextbyte; 992 } 993 994 /* This is a new MESSAGE IN phase. Clean up our state. */ 995 sc->sc_flags &= ~AIC_DROP_MSGIN; 996 997 nextmsg: 998 n = 0; 999 sc->sc_imp = &sc->sc_imess[n]; 1000 1001 nextbyte: 1002 /* 1003 * Read a whole message, but don't ack the last byte. If we reject the 1004 * message, we have to assert ATN during the message transfer phase 1005 * itself. 1006 */ 1007 for (;;) { 1008 for (;;) { 1009 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1010 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1011 break; 1012 /* Wait for REQINIT. XXX Need timeout. */ 1013 } 1014 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1015 /* 1016 * Target left MESSAGE IN, probably because it 1017 * a) noticed our ATN signal, or 1018 * b) ran out of messages. 1019 */ 1020 goto out; 1021 } 1022 1023 /* If parity error, just dump everything on the floor. */ 1024 if ((sstat1 & SCSIPERR) != 0) { 1025 sc->sc_flags |= AIC_DROP_MSGIN; 1026 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1027 } 1028 1029 /* Gather incoming message bytes if needed. */ 1030 if ((sc->sc_flags & AIC_DROP_MSGIN) == 0) { 1031 if (n >= AIC_MAX_MSG_LEN) { 1032 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1033 sc->sc_flags |= AIC_DROP_MSGIN; 1034 aic_sched_msgout(sc, SEND_REJECT); 1035 } else { 1036 *sc->sc_imp++ = bus_space_read_1(iot, ioh, 1037 SCSIDAT); 1038 n++; 1039 /* 1040 * This testing is suboptimal, but most 1041 * messages will be of the one byte variety, so 1042 * it should not affect performance 1043 * significantly. 1044 */ 1045 if (n == 1 && MSG_IS1BYTE(sc->sc_imess[0])) 1046 break; 1047 if (n == 2 && MSG_IS2BYTE(sc->sc_imess[0])) 1048 break; 1049 if (n >= 3 && MSG_ISEXTENDED(sc->sc_imess[0]) && 1050 n == sc->sc_imess[1] + 2) 1051 break; 1052 } 1053 } else 1054 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1055 1056 /* 1057 * If we reach this spot we're either: 1058 * a) in the middle of a multi-byte message, or 1059 * b) dropping bytes. 1060 */ 1061 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1062 /* Ack the last byte read. */ 1063 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1064 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1065 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1066 ; 1067 } 1068 1069 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1070 1071 /* We now have a complete message. Parse it. */ 1072 switch (sc->sc_state) { 1073 struct aic_acb *acb; 1074 struct aic_tinfo *ti; 1075 1076 case AIC_CONNECTED: 1077 AIC_ASSERT(sc->sc_nexus != NULL); 1078 acb = sc->sc_nexus; 1079 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target]; 1080 1081 switch (sc->sc_imess[0]) { 1082 case MSG_CMDCOMPLETE: 1083 #if 0 1084 /* impossible dleft is unsigned */ 1085 if (sc->sc_dleft < 0) { 1086 periph = acb->xs->xs_periph; 1087 printf("%s: %ld extra bytes from %d:%d\n", 1088 sc->sc_dev.dv_xname, (long)-sc->sc_dleft, 1089 periph->periph_target, periph->periph_lun); 1090 sc->sc_dleft = 0; 1091 } 1092 #endif 1093 acb->xs->resid = acb->data_length = sc->sc_dleft; 1094 sc->sc_state = AIC_CMDCOMPLETE; 1095 break; 1096 1097 case MSG_PARITY_ERROR: 1098 /* Resend the last message. */ 1099 aic_sched_msgout(sc, sc->sc_lastmsg); 1100 break; 1101 1102 case MSG_MESSAGE_REJECT: 1103 AIC_MISC(("message rejected %02x ", sc->sc_lastmsg)); 1104 switch (sc->sc_lastmsg) { 1105 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1106 case SEND_IDENTIFY: 1107 ti->flags &= ~(DO_SYNC | DO_WIDE); 1108 ti->period = ti->offset = 0; 1109 aic_setsync(sc, ti); 1110 ti->width = 0; 1111 break; 1112 #endif 1113 #if AIC_USE_SYNCHRONOUS 1114 case SEND_SDTR: 1115 ti->flags &= ~DO_SYNC; 1116 ti->period = ti->offset = 0; 1117 aic_setsync(sc, ti); 1118 aic_update_xfer_mode(sc, 1119 acb->xs->xs_periph->periph_target); 1120 break; 1121 #endif 1122 #if AIC_USE_WIDE 1123 case SEND_WDTR: 1124 ti->flags &= ~DO_WIDE; 1125 ti->width = 0; 1126 aic_update_xfer_mode(sc, 1127 acb->xs->xs_periph->periph_target); 1128 break; 1129 #endif 1130 case SEND_INIT_DET_ERR: 1131 aic_sched_msgout(sc, SEND_ABORT); 1132 break; 1133 } 1134 break; 1135 1136 case MSG_NOOP: 1137 break; 1138 1139 case MSG_DISCONNECT: 1140 ti->dconns++; 1141 sc->sc_state = AIC_DISCONNECT; 1142 break; 1143 1144 case MSG_SAVEDATAPOINTER: 1145 acb->data_addr = sc->sc_dp; 1146 acb->data_length = sc->sc_dleft; 1147 break; 1148 1149 case MSG_RESTOREPOINTERS: 1150 sc->sc_dp = acb->data_addr; 1151 sc->sc_dleft = acb->data_length; 1152 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1153 sc->sc_cleft = acb->scsipi_cmd_length; 1154 break; 1155 1156 case MSG_EXTENDED: 1157 switch (sc->sc_imess[2]) { 1158 #if AIC_USE_SYNCHRONOUS 1159 case MSG_EXT_SDTR: 1160 if (sc->sc_imess[1] != 3) 1161 goto reject; 1162 ti->period = sc->sc_imess[3]; 1163 ti->offset = sc->sc_imess[4]; 1164 ti->flags &= ~DO_SYNC; 1165 if (ti->offset == 0) { 1166 } else if (ti->period < sc->sc_minsync || 1167 ti->period > sc->sc_maxsync || 1168 ti->offset > 8) { 1169 ti->period = ti->offset = 0; 1170 aic_sched_msgout(sc, SEND_SDTR); 1171 } else { 1172 aic_update_xfer_mode(sc, 1173 acb->xs->xs_periph->periph_target); 1174 } 1175 aic_setsync(sc, ti); 1176 break; 1177 #endif 1178 1179 #if AIC_USE_WIDE 1180 case MSG_EXT_WDTR: 1181 if (sc->sc_imess[1] != 2) 1182 goto reject; 1183 ti->width = sc->sc_imess[3]; 1184 ti->flags &= ~DO_WIDE; 1185 if (ti->width == 0) { 1186 } else if (ti->width > AIC_MAX_WIDTH) { 1187 ti->width = 0; 1188 aic_sched_msgout(sc, SEND_WDTR); 1189 } else { 1190 aic_update_xfer_mode(sc, 1191 acb->xs->xs_periph->periph_target); 1192 } 1193 break; 1194 #endif 1195 1196 default: 1197 printf("%s: unrecognized MESSAGE EXTENDED; " 1198 "sending REJECT\n", sc->sc_dev.dv_xname); 1199 AIC_BREAK(); 1200 goto reject; 1201 } 1202 break; 1203 1204 default: 1205 printf("%s: unrecognized MESSAGE; sending REJECT\n", 1206 sc->sc_dev.dv_xname); 1207 AIC_BREAK(); 1208 reject: 1209 aic_sched_msgout(sc, SEND_REJECT); 1210 break; 1211 } 1212 break; 1213 1214 case AIC_RESELECTED: 1215 if (!MSG_ISIDENTIFY(sc->sc_imess[0])) { 1216 printf("%s: reselect without IDENTIFY; " 1217 "sending DEVICE RESET\n", sc->sc_dev.dv_xname); 1218 AIC_BREAK(); 1219 goto reset; 1220 } 1221 1222 (void) aic_reselect(sc, sc->sc_imess[0]); 1223 break; 1224 1225 default: 1226 printf("%s: unexpected MESSAGE IN; sending DEVICE RESET\n", 1227 sc->sc_dev.dv_xname); 1228 AIC_BREAK(); 1229 reset: 1230 aic_sched_msgout(sc, SEND_DEV_RESET); 1231 break; 1232 1233 #ifdef notdef 1234 abort: 1235 aic_sched_msgout(sc, SEND_ABORT); 1236 break; 1237 #endif 1238 } 1239 1240 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1241 /* Ack the last message byte. */ 1242 (void) bus_space_read_1(iot, ioh, SCSIDAT); 1243 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1244 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1245 ; 1246 1247 /* Go get the next message, if any. */ 1248 goto nextmsg; 1249 1250 out: 1251 AIC_MISC(("n=%d imess=0x%02x ", n, sc->sc_imess[0])); 1252 } 1253 1254 /* 1255 * Send the highest priority, scheduled message. 1256 */ 1257 static void 1258 aic_msgout(struct aic_softc *sc) 1259 { 1260 bus_space_tag_t iot = sc->sc_iot; 1261 bus_space_handle_t ioh = sc->sc_ioh; 1262 #if AIC_USE_SYNCHRONOUS 1263 struct aic_tinfo *ti; 1264 #endif 1265 u_char sstat1; 1266 int n; 1267 1268 AIC_TRACE(("aic_msgout ")); 1269 1270 /* Reset the FIFO. */ 1271 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1272 /* Enable REQ/ACK protocol. */ 1273 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 1274 1275 if (sc->sc_prevphase == PH_MSGOUT) { 1276 if (sc->sc_omp == sc->sc_omess) { 1277 /* 1278 * This is a retransmission. 1279 * 1280 * We get here if the target stayed in MESSAGE OUT 1281 * phase. Section 5.1.9.2 of the SCSI 2 spec indicates 1282 * that all of the previously transmitted messages must 1283 * be sent again, in the same order. Therefore, we 1284 * requeue all the previously transmitted messages, and 1285 * start again from the top. Our simple priority 1286 * scheme keeps the messages in the right order. 1287 */ 1288 AIC_MISC(("retransmitting ")); 1289 sc->sc_msgpriq |= sc->sc_msgoutq; 1290 /* 1291 * Set ATN. If we're just sending a trivial 1-byte 1292 * message, we'll clear ATN later on anyway. 1293 */ 1294 bus_space_write_1(iot, ioh, SCSISIG, PH_MSGOUT | ATNO); 1295 } else { 1296 /* This is a continuation of the previous message. */ 1297 n = sc->sc_omp - sc->sc_omess; 1298 goto nextbyte; 1299 } 1300 } 1301 1302 /* No messages transmitted so far. */ 1303 sc->sc_msgoutq = 0; 1304 sc->sc_lastmsg = 0; 1305 1306 nextmsg: 1307 /* Pick up highest priority message. */ 1308 sc->sc_currmsg = sc->sc_msgpriq & -sc->sc_msgpriq; 1309 sc->sc_msgpriq &= ~sc->sc_currmsg; 1310 sc->sc_msgoutq |= sc->sc_currmsg; 1311 1312 /* Build the outgoing message data. */ 1313 switch (sc->sc_currmsg) { 1314 case SEND_IDENTIFY: 1315 AIC_ASSERT(sc->sc_nexus != NULL); 1316 sc->sc_omess[0] = 1317 MSG_IDENTIFY(sc->sc_nexus->xs->xs_periph->periph_lun, 1); 1318 n = 1; 1319 break; 1320 1321 #if AIC_USE_SYNCHRONOUS 1322 case SEND_SDTR: 1323 AIC_ASSERT(sc->sc_nexus != NULL); 1324 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1325 sc->sc_omess[4] = MSG_EXTENDED; 1326 sc->sc_omess[3] = 3; 1327 sc->sc_omess[2] = MSG_EXT_SDTR; 1328 sc->sc_omess[1] = ti->period >> 2; 1329 sc->sc_omess[0] = ti->offset; 1330 n = 5; 1331 break; 1332 #endif 1333 1334 #if AIC_USE_WIDE 1335 case SEND_WDTR: 1336 AIC_ASSERT(sc->sc_nexus != NULL); 1337 ti = &sc->sc_tinfo[sc->sc_nexus->xs->xs_periph->periph_target]; 1338 sc->sc_omess[3] = MSG_EXTENDED; 1339 sc->sc_omess[2] = 2; 1340 sc->sc_omess[1] = MSG_EXT_WDTR; 1341 sc->sc_omess[0] = ti->width; 1342 n = 4; 1343 break; 1344 #endif 1345 1346 case SEND_DEV_RESET: 1347 sc->sc_flags |= AIC_ABORTING; 1348 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 1349 n = 1; 1350 break; 1351 1352 case SEND_REJECT: 1353 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 1354 n = 1; 1355 break; 1356 1357 case SEND_PARITY_ERROR: 1358 sc->sc_omess[0] = MSG_PARITY_ERROR; 1359 n = 1; 1360 break; 1361 1362 case SEND_INIT_DET_ERR: 1363 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 1364 n = 1; 1365 break; 1366 1367 case SEND_ABORT: 1368 sc->sc_flags |= AIC_ABORTING; 1369 sc->sc_omess[0] = MSG_ABORT; 1370 n = 1; 1371 break; 1372 1373 default: 1374 printf("%s: unexpected MESSAGE OUT; sending NOOP\n", 1375 sc->sc_dev.dv_xname); 1376 AIC_BREAK(); 1377 sc->sc_omess[0] = MSG_NOOP; 1378 n = 1; 1379 break; 1380 } 1381 sc->sc_omp = &sc->sc_omess[n]; 1382 1383 nextbyte: 1384 /* Send message bytes. */ 1385 for (;;) { 1386 for (;;) { 1387 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1388 if ((sstat1 & (REQINIT | PHASECHG | BUSFREE)) != 0) 1389 break; 1390 /* Wait for REQINIT. XXX Need timeout. */ 1391 } 1392 if ((sstat1 & (PHASECHG | BUSFREE)) != 0) { 1393 /* 1394 * Target left MESSAGE OUT, possibly to reject 1395 * our message. 1396 * 1397 * If this is the last message being sent, then we 1398 * deassert ATN, since either the target is going to 1399 * ignore this message, or it's going to ask for a 1400 * retransmission via MESSAGE PARITY ERROR (in which 1401 * case we reassert ATN anyway). 1402 */ 1403 if (sc->sc_msgpriq == 0) 1404 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1405 goto out; 1406 } 1407 1408 /* Clear ATN before last byte if this is the last message. */ 1409 if (n == 1 && sc->sc_msgpriq == 0) 1410 bus_space_write_1(iot, ioh, CLRSINT1, CLRATNO); 1411 /* Send message byte. */ 1412 bus_space_write_1(iot, ioh, SCSIDAT, *--sc->sc_omp); 1413 --n; 1414 /* Keep track of the last message we've sent any bytes of. */ 1415 sc->sc_lastmsg = sc->sc_currmsg; 1416 /* Wait for ACK to be negated. XXX Need timeout. */ 1417 while ((bus_space_read_1(iot, ioh, SCSISIG) & ACKI) != 0) 1418 ; 1419 1420 if (n == 0) 1421 break; 1422 } 1423 1424 /* We get here only if the entire message has been transmitted. */ 1425 if (sc->sc_msgpriq != 0) { 1426 /* There are more outgoing messages. */ 1427 goto nextmsg; 1428 } 1429 1430 /* 1431 * The last message has been transmitted. We need to remember the last 1432 * message transmitted (in case the target switches to MESSAGE IN phase 1433 * and sends a MESSAGE REJECT), and the list of messages transmitted 1434 * this time around (in case the target stays in MESSAGE OUT phase to 1435 * request a retransmit). 1436 */ 1437 1438 out: 1439 /* Disable REQ/ACK protocol. */ 1440 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1441 } 1442 1443 /* aic_dataout_pio: perform a data transfer using the FIFO datapath in the 1444 * aic6360 1445 * Precondition: The SCSI bus should be in the DOUT phase, with REQ asserted 1446 * and ACK deasserted (i.e. waiting for a data byte) 1447 * This new revision has been optimized (I tried) to make the common case fast, 1448 * and the rarer cases (as a result) somewhat more comlex 1449 */ 1450 static int 1451 aic_dataout_pio(struct aic_softc *sc, u_char *p, int n) 1452 { 1453 bus_space_tag_t iot = sc->sc_iot; 1454 bus_space_handle_t ioh = sc->sc_ioh; 1455 u_char dmastat = 0; 1456 int out = 0; 1457 #define DOUTAMOUNT 128 /* Full FIFO */ 1458 1459 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1460 bus_space_read_1(iot, ioh, SSTAT2))); 1461 1462 /* Clear host FIFO and counter. */ 1463 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO | WRITE); 1464 /* Enable FIFOs. */ 1465 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO | WRITE); 1466 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1467 1468 /* Turn off ENREQINIT for now. */ 1469 bus_space_write_1(iot, ioh, SIMODE1, 1470 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1471 1472 /* I have tried to make the main loop as tight as possible. This 1473 * means that some of the code following the loop is a bit more 1474 * complex than otherwise. 1475 */ 1476 while (n > 0) { 1477 for (;;) { 1478 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1479 if ((dmastat & (DFIFOEMP | INTSTAT)) != 0) 1480 break; 1481 } 1482 1483 if ((dmastat & INTSTAT) != 0) 1484 goto phasechange; 1485 1486 if (n >= DOUTAMOUNT) { 1487 n -= DOUTAMOUNT; 1488 out += DOUTAMOUNT; 1489 1490 #if AIC_USE_DWORDS 1491 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1492 (u_int32_t *) p, DOUTAMOUNT >> 2); 1493 #else 1494 bus_space_write_multi_2(iot, ioh, DMADATA, 1495 (u_int16_t *) p, DOUTAMOUNT >> 1); 1496 #endif 1497 1498 p += DOUTAMOUNT; 1499 } else { 1500 int xfer; 1501 1502 xfer = n; 1503 AIC_MISC(("%d> ", xfer)); 1504 1505 n -= xfer; 1506 out += xfer; 1507 1508 #if AIC_USE_DWORDS 1509 if (xfer >= 12) { 1510 bus_space_write_multi_4(iot, ioh, DMADATALONG, 1511 (u_int32_t *) p, xfer >> 2); 1512 p += xfer & ~3; 1513 xfer &= 3; 1514 } 1515 #else 1516 if (xfer >= 8) { 1517 bus_space_write_multi_2(iot, ioh, DMADATA, 1518 (u_int16_t *) p, xfer >> 1); 1519 p += xfer & ~1; 1520 xfer &= 1; 1521 } 1522 #endif 1523 1524 if (xfer > 0) { 1525 bus_space_write_1(iot, ioh, DMACNTRL0, 1526 ENDMA | B8MODE | WRITE); 1527 bus_space_write_multi_1(iot, ioh, DMADATA, 1528 p, xfer); 1529 p += xfer; 1530 bus_space_write_1(iot, ioh, DMACNTRL0, 1531 ENDMA | DWORDPIO | WRITE); 1532 } 1533 } 1534 } 1535 1536 if (out == 0) { 1537 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1538 for (;;) { 1539 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1540 != 0) 1541 break; 1542 } 1543 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1544 AIC_MISC(("extra data ")); 1545 } else { 1546 /* See the bytes off chip */ 1547 for (;;) { 1548 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1549 if ((dmastat & INTSTAT) != 0) 1550 goto phasechange; 1551 if ((dmastat & DFIFOEMP) != 0 && 1552 (bus_space_read_1(iot, ioh, SSTAT2) & SEMPTY) != 0) 1553 break; 1554 } 1555 } 1556 1557 phasechange: 1558 if ((dmastat & INTSTAT) != 0) { 1559 /* Some sort of phase change. */ 1560 int amount; 1561 1562 /* Stop transfers, do some accounting */ 1563 amount = bus_space_read_1(iot, ioh, FIFOSTAT) 1564 + (bus_space_read_1(iot, ioh, SSTAT2) & 15); 1565 if (amount > 0) { 1566 out -= amount; 1567 bus_space_write_1(iot, ioh, DMACNTRL0, 1568 RSTFIFO | WRITE); 1569 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRCH); 1570 AIC_MISC(("+%d ", amount)); 1571 } 1572 } 1573 1574 /* Turn on ENREQINIT again. */ 1575 bus_space_write_1(iot, ioh, SIMODE1, 1576 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1577 1578 /* Stop the FIFO data path. */ 1579 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1580 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1581 1582 return out; 1583 } 1584 1585 /* aic_datain_pio: perform data transfers using the FIFO datapath in the 1586 * aic6360 1587 * Precondition: The SCSI bus should be in the DIN phase, with REQ asserted 1588 * and ACK deasserted (i.e. at least one byte is ready). 1589 * For now, uses a pretty dumb algorithm, hangs around until all data has been 1590 * transferred. This, is OK for fast targets, but not so smart for slow 1591 * targets which don't disconnect or for huge transfers. 1592 */ 1593 static int 1594 aic_datain_pio(struct aic_softc *sc, u_char *p, int n) 1595 { 1596 bus_space_tag_t iot = sc->sc_iot; 1597 bus_space_handle_t ioh = sc->sc_ioh; 1598 u_char dmastat; 1599 int in = 0; 1600 #define DINAMOUNT 128 /* Full FIFO */ 1601 1602 AIC_MISC(("%02x%02x ", bus_space_read_1(iot, ioh, FIFOSTAT), 1603 bus_space_read_1(iot, ioh, SSTAT2))); 1604 1605 /* Clear host FIFO and counter. */ 1606 bus_space_write_1(iot, ioh, DMACNTRL0, RSTFIFO); 1607 /* Enable FIFOs. */ 1608 bus_space_write_1(iot, ioh, DMACNTRL0, ENDMA | DWORDPIO); 1609 bus_space_write_1(iot, ioh, SXFRCTL0, SCSIEN | DMAEN | CHEN); 1610 1611 /* Turn off ENREQINIT for now. */ 1612 bus_space_write_1(iot, ioh, SIMODE1, 1613 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENPHASECHG); 1614 1615 /* We leave this loop if one or more of the following is true: 1616 * a) phase != PH_DATAIN && FIFOs are empty 1617 * b) SCSIRSTI is set (a reset has occurred) or busfree is detected. 1618 */ 1619 while (n > 0) { 1620 /* Wait for fifo half full or phase mismatch */ 1621 for (;;) { 1622 dmastat = bus_space_read_1(iot, ioh, DMASTAT); 1623 if ((dmastat & (DFIFOFULL | INTSTAT)) != 0) 1624 break; 1625 } 1626 1627 if ((dmastat & DFIFOFULL) != 0) { 1628 n -= DINAMOUNT; 1629 in += DINAMOUNT; 1630 1631 #if AIC_USE_DWORDS 1632 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1633 (u_int32_t *) p, DINAMOUNT >> 2); 1634 #else 1635 bus_space_read_multi_2(iot, ioh, DMADATA, 1636 (u_int16_t *) p, DINAMOUNT >> 1); 1637 #endif 1638 1639 p += DINAMOUNT; 1640 } else { 1641 int xfer; 1642 1643 xfer = min(bus_space_read_1(iot, ioh, FIFOSTAT), n); 1644 AIC_MISC((">%d ", xfer)); 1645 1646 n -= xfer; 1647 in += xfer; 1648 1649 #if AIC_USE_DWORDS 1650 if (xfer >= 12) { 1651 bus_space_read_multi_4(iot, ioh, DMADATALONG, 1652 (u_int32_t *) p, xfer >> 2); 1653 p += xfer & ~3; 1654 xfer &= 3; 1655 } 1656 #else 1657 if (xfer >= 8) { 1658 bus_space_read_multi_2(iot, ioh, DMADATA, 1659 (u_int16_t *) p, xfer >> 1); 1660 p += xfer & ~1; 1661 xfer &= 1; 1662 } 1663 #endif 1664 1665 if (xfer > 0) { 1666 bus_space_write_1(iot, ioh, DMACNTRL0, 1667 ENDMA | B8MODE); 1668 bus_space_read_multi_1(iot, ioh, DMADATA, 1669 p, xfer); 1670 p += xfer; 1671 bus_space_write_1(iot, ioh, DMACNTRL0, 1672 ENDMA | DWORDPIO); 1673 } 1674 } 1675 1676 if ((dmastat & INTSTAT) != 0) 1677 goto phasechange; 1678 } 1679 1680 /* Some SCSI-devices are rude enough to transfer more data than what 1681 * was requested, e.g. 2048 bytes from a CD-ROM instead of the 1682 * requested 512. Test for progress, i.e. real transfers. If no real 1683 * transfers have been performed (n is probably already zero) and the 1684 * FIFO is not empty, waste some bytes.... 1685 */ 1686 if (in == 0) { 1687 bus_space_write_1(iot, ioh, SXFRCTL1, BITBUCKET); 1688 for (;;) { 1689 if ((bus_space_read_1(iot, ioh, DMASTAT) & INTSTAT) 1690 != 0) 1691 break; 1692 } 1693 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1694 AIC_MISC(("extra data ")); 1695 } 1696 1697 phasechange: 1698 /* Turn on ENREQINIT again. */ 1699 bus_space_write_1(iot, ioh, SIMODE1, 1700 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | ENPHASECHG); 1701 1702 /* Stop the FIFO data path. */ 1703 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 1704 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1705 1706 return in; 1707 } 1708 1709 /* 1710 * This is the workhorse routine of the driver. 1711 * Deficiencies (for now): 1712 * 1) always uses programmed I/O 1713 */ 1714 int 1715 aicintr(void *arg) 1716 { 1717 struct aic_softc *sc = arg; 1718 bus_space_tag_t iot = sc->sc_iot; 1719 bus_space_handle_t ioh = sc->sc_ioh; 1720 u_char sstat0, sstat1; 1721 struct aic_acb *acb; 1722 struct scsipi_periph *periph; 1723 struct aic_tinfo *ti; 1724 int n; 1725 1726 if (! device_is_active(&sc->sc_dev)) 1727 return (0); 1728 1729 /* 1730 * Clear INTEN. We enable it again before returning. This makes the 1731 * interrupt esssentially level-triggered. 1732 */ 1733 bus_space_write_1(iot, ioh, DMACNTRL0, 0); 1734 1735 AIC_TRACE(("aicintr ")); 1736 1737 loop: 1738 /* 1739 * First check for abnormal conditions, such as reset. 1740 */ 1741 sstat1 = bus_space_read_1(iot, ioh, SSTAT1); 1742 AIC_MISC(("sstat1:0x%02x ", sstat1)); 1743 1744 if ((sstat1 & SCSIRSTI) != 0) { 1745 printf("%s: SCSI bus reset\n", sc->sc_dev.dv_xname); 1746 goto reset; 1747 } 1748 1749 /* 1750 * Check for less serious errors. 1751 */ 1752 if ((sstat1 & SCSIPERR) != 0) { 1753 printf("%s: SCSI bus parity error\n", sc->sc_dev.dv_xname); 1754 bus_space_write_1(iot, ioh, CLRSINT1, CLRSCSIPERR); 1755 if (sc->sc_prevphase == PH_MSGIN) { 1756 sc->sc_flags |= AIC_DROP_MSGIN; 1757 aic_sched_msgout(sc, SEND_PARITY_ERROR); 1758 } else 1759 aic_sched_msgout(sc, SEND_INIT_DET_ERR); 1760 } 1761 1762 /* 1763 * If we're not already busy doing something test for the following 1764 * conditions: 1765 * 1) We have been reselected by something 1766 * 2) We have selected something successfully 1767 * 3) Our selection process has timed out 1768 * 4) This is really a bus free interrupt just to get a new command 1769 * going? 1770 * 5) Spurious interrupt? 1771 */ 1772 switch (sc->sc_state) { 1773 case AIC_IDLE: 1774 case AIC_SELECTING: 1775 sstat0 = bus_space_read_1(iot, ioh, SSTAT0); 1776 AIC_MISC(("sstat0:0x%02x ", sstat0)); 1777 1778 if ((sstat0 & TARGET) != 0) { 1779 /* 1780 * We don't currently support target mode. 1781 */ 1782 printf("%s: target mode selected; going to BUS FREE\n", 1783 sc->sc_dev.dv_xname); 1784 bus_space_write_1(iot, ioh, SCSISIG, 0); 1785 1786 goto sched; 1787 } else if ((sstat0 & SELDI) != 0) { 1788 AIC_MISC(("reselected ")); 1789 1790 /* 1791 * If we're trying to select a target ourselves, 1792 * push our command back into the ready list. 1793 */ 1794 if (sc->sc_state == AIC_SELECTING) { 1795 AIC_MISC(("backoff selector ")); 1796 AIC_ASSERT(sc->sc_nexus != NULL); 1797 acb = sc->sc_nexus; 1798 sc->sc_nexus = NULL; 1799 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 1800 } 1801 1802 /* Save reselection ID. */ 1803 sc->sc_selid = bus_space_read_1(iot, ioh, SELID); 1804 1805 sc->sc_state = AIC_RESELECTED; 1806 } else if ((sstat0 & SELDO) != 0) { 1807 AIC_MISC(("selected ")); 1808 1809 /* We have selected a target. Things to do: 1810 * a) Determine what message(s) to send. 1811 * b) Verify that we're still selecting the target. 1812 * c) Mark device as busy. 1813 */ 1814 if (sc->sc_state != AIC_SELECTING) { 1815 printf("%s: selection out while idle; " 1816 "resetting\n", sc->sc_dev.dv_xname); 1817 AIC_BREAK(); 1818 goto reset; 1819 } 1820 AIC_ASSERT(sc->sc_nexus != NULL); 1821 acb = sc->sc_nexus; 1822 periph = acb->xs->xs_periph; 1823 ti = &sc->sc_tinfo[periph->periph_target]; 1824 1825 sc->sc_msgpriq = SEND_IDENTIFY; 1826 if (acb->flags & ACB_RESET) 1827 sc->sc_msgpriq |= SEND_DEV_RESET; 1828 else if (acb->flags & ACB_ABORT) 1829 sc->sc_msgpriq |= SEND_ABORT; 1830 else { 1831 #if AIC_USE_SYNCHRONOUS 1832 if ((ti->flags & DO_SYNC) != 0) 1833 sc->sc_msgpriq |= SEND_SDTR; 1834 #endif 1835 #if AIC_USE_WIDE 1836 if ((ti->flags & DO_WIDE) != 0) 1837 sc->sc_msgpriq |= SEND_WDTR; 1838 #endif 1839 } 1840 1841 acb->flags |= ACB_NEXUS; 1842 ti->lubusy |= (1 << periph->periph_lun); 1843 1844 /* Do an implicit RESTORE POINTERS. */ 1845 sc->sc_dp = acb->data_addr; 1846 sc->sc_dleft = acb->data_length; 1847 sc->sc_cp = (u_char *)&acb->scsipi_cmd; 1848 sc->sc_cleft = acb->scsipi_cmd_length; 1849 1850 /* On our first connection, schedule a timeout. */ 1851 if ((acb->xs->xs_control & XS_CTL_POLL) == 0) 1852 callout_reset(&acb->xs->xs_callout, 1853 mstohz(acb->timeout), aic_timeout, acb); 1854 1855 sc->sc_state = AIC_CONNECTED; 1856 } else if ((sstat1 & SELTO) != 0) { 1857 AIC_MISC(("selection timeout ")); 1858 1859 if (sc->sc_state != AIC_SELECTING) { 1860 printf("%s: selection timeout while idle; " 1861 "resetting\n", sc->sc_dev.dv_xname); 1862 AIC_BREAK(); 1863 goto reset; 1864 } 1865 AIC_ASSERT(sc->sc_nexus != NULL); 1866 acb = sc->sc_nexus; 1867 1868 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1869 bus_space_write_1(iot, ioh, SCSISEQ, ENRESELI); 1870 bus_space_write_1(iot, ioh, CLRSINT1, CLRSELTIMO); 1871 delay(250); 1872 1873 acb->xs->error = XS_SELTIMEOUT; 1874 goto finish; 1875 } else { 1876 if (sc->sc_state != AIC_IDLE) { 1877 printf("%s: BUS FREE while not idle; " 1878 "state=%d\n", 1879 sc->sc_dev.dv_xname, sc->sc_state); 1880 AIC_BREAK(); 1881 goto out; 1882 } 1883 1884 goto sched; 1885 } 1886 1887 /* 1888 * Turn off selection stuff, and prepare to catch bus free 1889 * interrupts, parity errors, and phase changes. 1890 */ 1891 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | CLRSTCNT | CLRCH); 1892 bus_space_write_1(iot, ioh, SXFRCTL1, 0); 1893 bus_space_write_1(iot, ioh, SCSISEQ, ENAUTOATNP); 1894 bus_space_write_1(iot, ioh, CLRSINT0, CLRSELDI | CLRSELDO); 1895 bus_space_write_1(iot, ioh, CLRSINT1, 1896 CLRBUSFREE | CLRPHASECHG); 1897 bus_space_write_1(iot, ioh, SIMODE0, 0); 1898 bus_space_write_1(iot, ioh, SIMODE1, 1899 ENSCSIRST | ENSCSIPERR | ENBUSFREE | ENREQINIT | 1900 ENPHASECHG); 1901 1902 sc->sc_flags = 0; 1903 sc->sc_prevphase = PH_INVALID; 1904 goto dophase; 1905 } 1906 1907 if ((sstat1 & BUSFREE) != 0) { 1908 /* We've gone to BUS FREE phase. */ 1909 bus_space_write_1(iot, ioh, CLRSINT1, 1910 CLRBUSFREE | CLRPHASECHG); 1911 1912 switch (sc->sc_state) { 1913 case AIC_RESELECTED: 1914 goto sched; 1915 1916 case AIC_CONNECTED: 1917 AIC_ASSERT(sc->sc_nexus != NULL); 1918 acb = sc->sc_nexus; 1919 1920 #if AIC_USE_SYNCHRONOUS + AIC_USE_WIDE 1921 if (sc->sc_prevphase == PH_MSGOUT) { 1922 /* 1923 * If the target went to BUS FREE phase during 1924 * or immediately after sending a SDTR or WDTR 1925 * message, disable negotiation. 1926 */ 1927 periph = acb->xs->xs_periph; 1928 ti = &sc->sc_tinfo[periph->periph_target]; 1929 switch (sc->sc_lastmsg) { 1930 #if AIC_USE_SYNCHRONOUS 1931 case SEND_SDTR: 1932 ti->flags &= ~DO_SYNC; 1933 ti->period = ti->offset = 0; 1934 break; 1935 #endif 1936 #if AIC_USE_WIDE 1937 case SEND_WDTR: 1938 ti->flags &= ~DO_WIDE; 1939 ti->width = 0; 1940 break; 1941 #endif 1942 } 1943 } 1944 #endif 1945 1946 if ((sc->sc_flags & AIC_ABORTING) == 0) { 1947 /* 1948 * Section 5.1.1 of the SCSI 2 spec suggests 1949 * issuing a REQUEST SENSE following an 1950 * unexpected disconnect. Some devices go into 1951 * a contingent allegiance condition when 1952 * disconnecting, and this is necessary to 1953 * clean up their state. 1954 */ 1955 printf("%s: unexpected disconnect; " 1956 "sending REQUEST SENSE\n", 1957 sc->sc_dev.dv_xname); 1958 AIC_BREAK(); 1959 aic_sense(sc, acb); 1960 goto out; 1961 } 1962 1963 acb->xs->error = XS_DRIVER_STUFFUP; 1964 goto finish; 1965 1966 case AIC_DISCONNECT: 1967 AIC_ASSERT(sc->sc_nexus != NULL); 1968 acb = sc->sc_nexus; 1969 #if 1 /* XXXX */ 1970 acb->data_addr = sc->sc_dp; 1971 acb->data_length = sc->sc_dleft; 1972 #endif 1973 TAILQ_INSERT_HEAD(&sc->nexus_list, acb, chain); 1974 sc->sc_nexus = NULL; 1975 goto sched; 1976 1977 case AIC_CMDCOMPLETE: 1978 AIC_ASSERT(sc->sc_nexus != NULL); 1979 acb = sc->sc_nexus; 1980 goto finish; 1981 } 1982 } 1983 1984 bus_space_write_1(iot, ioh, CLRSINT1, CLRPHASECHG); 1985 1986 dophase: 1987 if ((sstat1 & REQINIT) == 0) { 1988 /* Wait for REQINIT. */ 1989 goto out; 1990 } 1991 1992 sc->sc_phase = bus_space_read_1(iot, ioh, SCSISIG) & PH_MASK; 1993 bus_space_write_1(iot, ioh, SCSISIG, sc->sc_phase); 1994 1995 switch (sc->sc_phase) { 1996 case PH_MSGOUT: 1997 if (sc->sc_state != AIC_CONNECTED && 1998 sc->sc_state != AIC_RESELECTED) 1999 break; 2000 aic_msgout(sc); 2001 sc->sc_prevphase = PH_MSGOUT; 2002 goto loop; 2003 2004 case PH_MSGIN: 2005 if (sc->sc_state != AIC_CONNECTED && 2006 sc->sc_state != AIC_RESELECTED) 2007 break; 2008 aic_msgin(sc); 2009 sc->sc_prevphase = PH_MSGIN; 2010 goto loop; 2011 2012 case PH_CMD: 2013 if (sc->sc_state != AIC_CONNECTED) 2014 break; 2015 #if AIC_DEBUG 2016 if ((aic_debug & AIC_SHOWMISC) != 0) { 2017 AIC_ASSERT(sc->sc_nexus != NULL); 2018 acb = sc->sc_nexus; 2019 printf("cmd=0x%02x+%d ", 2020 acb->scsipi_cmd.opcode, acb->scsipi_cmd_length-1); 2021 } 2022 #endif 2023 n = aic_dataout_pio(sc, sc->sc_cp, sc->sc_cleft); 2024 sc->sc_cp += n; 2025 sc->sc_cleft -= n; 2026 sc->sc_prevphase = PH_CMD; 2027 goto loop; 2028 2029 case PH_DATAOUT: 2030 if (sc->sc_state != AIC_CONNECTED) 2031 break; 2032 AIC_MISC(("dataout %ld ", (long)sc->sc_dleft)); 2033 n = aic_dataout_pio(sc, sc->sc_dp, sc->sc_dleft); 2034 sc->sc_dp += n; 2035 sc->sc_dleft -= n; 2036 sc->sc_prevphase = PH_DATAOUT; 2037 goto loop; 2038 2039 case PH_DATAIN: 2040 if (sc->sc_state != AIC_CONNECTED) 2041 break; 2042 AIC_MISC(("datain %ld ", (long)sc->sc_dleft)); 2043 n = aic_datain_pio(sc, sc->sc_dp, sc->sc_dleft); 2044 sc->sc_dp += n; 2045 sc->sc_dleft -= n; 2046 sc->sc_prevphase = PH_DATAIN; 2047 goto loop; 2048 2049 case PH_STAT: 2050 if (sc->sc_state != AIC_CONNECTED) 2051 break; 2052 AIC_ASSERT(sc->sc_nexus != NULL); 2053 acb = sc->sc_nexus; 2054 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN | SPIOEN); 2055 acb->target_stat = bus_space_read_1(iot, ioh, SCSIDAT); 2056 bus_space_write_1(iot, ioh, SXFRCTL0, CHEN); 2057 AIC_MISC(("target_stat=0x%02x ", acb->target_stat)); 2058 sc->sc_prevphase = PH_STAT; 2059 goto loop; 2060 } 2061 2062 printf("%s: unexpected bus phase; resetting\n", sc->sc_dev.dv_xname); 2063 AIC_BREAK(); 2064 reset: 2065 aic_init(sc, 1); 2066 return 1; 2067 2068 finish: 2069 callout_stop(&acb->xs->xs_callout); 2070 aic_done(sc, acb); 2071 goto out; 2072 2073 sched: 2074 sc->sc_state = AIC_IDLE; 2075 aic_sched(sc); 2076 goto out; 2077 2078 out: 2079 bus_space_write_1(iot, ioh, DMACNTRL0, INTEN); 2080 return 1; 2081 } 2082 2083 static void 2084 aic_abort(struct aic_softc *sc, struct aic_acb *acb) 2085 { 2086 2087 /* 2 secs for the abort */ 2088 acb->timeout = AIC_ABORT_TIMEOUT; 2089 acb->flags |= ACB_ABORT; 2090 2091 if (acb == sc->sc_nexus) { 2092 /* 2093 * If we're still selecting, the message will be scheduled 2094 * after selection is complete. 2095 */ 2096 if (sc->sc_state == AIC_CONNECTED) 2097 aic_sched_msgout(sc, SEND_ABORT); 2098 } else { 2099 aic_dequeue(sc, acb); 2100 TAILQ_INSERT_HEAD(&sc->ready_list, acb, chain); 2101 if (sc->sc_state == AIC_IDLE) 2102 aic_sched(sc); 2103 } 2104 } 2105 2106 static void 2107 aic_timeout(void *arg) 2108 { 2109 struct aic_acb *acb = arg; 2110 struct scsipi_xfer *xs = acb->xs; 2111 struct scsipi_periph *periph = xs->xs_periph; 2112 struct aic_softc *sc = 2113 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2114 int s; 2115 2116 scsipi_printaddr(periph); 2117 printf("timed out"); 2118 2119 s = splbio(); 2120 2121 if (acb->flags & ACB_ABORT) { 2122 /* abort timed out */ 2123 printf(" AGAIN\n"); 2124 /* XXX Must reset! */ 2125 } else { 2126 /* abort the operation that has timed out */ 2127 printf("\n"); 2128 acb->xs->error = XS_TIMEOUT; 2129 aic_abort(sc, acb); 2130 } 2131 2132 splx(s); 2133 } 2134 2135 #ifdef AIC_DEBUG 2136 /* 2137 * The following functions are mostly used for debugging purposes, either 2138 * directly called from the driver or from the kernel debugger. 2139 */ 2140 2141 static void 2142 aic_show_scsi_cmd(struct aic_acb *acb) 2143 { 2144 u_char *b = (u_char *)&acb->scsipi_cmd; 2145 struct scsipi_periph *periph = acb->xs->xs_periph; 2146 int i; 2147 2148 scsipi_printaddr(periph); 2149 if ((acb->xs->xs_control & XS_CTL_RESET) == 0) { 2150 for (i = 0; i < acb->scsipi_cmd_length; i++) { 2151 if (i) 2152 printf(","); 2153 printf("%x", b[i]); 2154 } 2155 printf("\n"); 2156 } else 2157 printf("RESET\n"); 2158 } 2159 2160 static void 2161 aic_print_acb(struct aic_acb *acb) 2162 { 2163 2164 printf("acb@%p xs=%p flags=%x", acb, acb->xs, acb->flags); 2165 printf(" dp=%p dleft=%d target_stat=%x\n", 2166 acb->data_addr, acb->data_length, acb->target_stat); 2167 aic_show_scsi_cmd(acb); 2168 } 2169 2170 void 2171 aic_print_active_acb(void) 2172 { 2173 extern struct cfdriver aic_cd; 2174 struct aic_acb *acb; 2175 struct aic_softc *sc = aic_cd.cd_devs[0]; 2176 2177 printf("ready list:\n"); 2178 for (acb = sc->ready_list.tqh_first; acb != NULL; 2179 acb = acb->chain.tqe_next) 2180 aic_print_acb(acb); 2181 printf("nexus:\n"); 2182 if (sc->sc_nexus != NULL) 2183 aic_print_acb(sc->sc_nexus); 2184 printf("nexus list:\n"); 2185 for (acb = sc->nexus_list.tqh_first; acb != NULL; 2186 acb = acb->chain.tqe_next) 2187 aic_print_acb(acb); 2188 } 2189 2190 void 2191 aic_dump6360(struct aic_softc *sc) 2192 { 2193 bus_space_tag_t iot = sc->sc_iot; 2194 bus_space_handle_t ioh = sc->sc_ioh; 2195 2196 printf("aic6360: SCSISEQ=%x SXFRCTL0=%x SXFRCTL1=%x SCSISIG=%x\n", 2197 bus_space_read_1(iot, ioh, SCSISEQ), 2198 bus_space_read_1(iot, ioh, SXFRCTL0), 2199 bus_space_read_1(iot, ioh, SXFRCTL1), 2200 bus_space_read_1(iot, ioh, SCSISIG)); 2201 printf(" SSTAT0=%x SSTAT1=%x SSTAT2=%x SSTAT3=%x SSTAT4=%x\n", 2202 bus_space_read_1(iot, ioh, SSTAT0), 2203 bus_space_read_1(iot, ioh, SSTAT1), 2204 bus_space_read_1(iot, ioh, SSTAT2), 2205 bus_space_read_1(iot, ioh, SSTAT3), 2206 bus_space_read_1(iot, ioh, SSTAT4)); 2207 printf(" SIMODE0=%x SIMODE1=%x DMACNTRL0=%x DMACNTRL1=%x " 2208 "DMASTAT=%x\n", 2209 bus_space_read_1(iot, ioh, SIMODE0), 2210 bus_space_read_1(iot, ioh, SIMODE1), 2211 bus_space_read_1(iot, ioh, DMACNTRL0), 2212 bus_space_read_1(iot, ioh, DMACNTRL1), 2213 bus_space_read_1(iot, ioh, DMASTAT)); 2214 printf(" FIFOSTAT=%d SCSIBUS=0x%x\n", 2215 bus_space_read_1(iot, ioh, FIFOSTAT), 2216 bus_space_read_1(iot, ioh, SCSIBUS)); 2217 } 2218 2219 void 2220 aic_dump_driver(struct aic_softc *sc) 2221 { 2222 struct aic_tinfo *ti; 2223 int i; 2224 2225 printf("nexus=%p prevphase=%x\n", sc->sc_nexus, sc->sc_prevphase); 2226 printf("state=%x msgin=%x msgpriq=%x msgoutq=%x lastmsg=%x " 2227 "currmsg=%x\n", 2228 sc->sc_state, sc->sc_imess[0], 2229 sc->sc_msgpriq, sc->sc_msgoutq, sc->sc_lastmsg, sc->sc_currmsg); 2230 for (i = 0; i < 7; i++) { 2231 ti = &sc->sc_tinfo[i]; 2232 printf("tinfo%d: %d cmds %d disconnects %d timeouts", 2233 i, ti->cmds, ti->dconns, ti->touts); 2234 printf(" %d senses flags=%x\n", ti->senses, ti->flags); 2235 } 2236 } 2237 #endif
Cache object: f1cc18d395ad1ebeac21bc738ef641f0
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]