FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/aic6915.h
1 /* $OpenBSD: aic6915.h,v 1.5 2022/01/09 05:42:38 jsg Exp $ */
2 /* $NetBSD: aic6915reg.h,v 1.4 2005/12/11 12:21:25 christos Exp $ */
3
4 /*-
5 * Copyright (c) 2001 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #ifndef _DEV_IC_AIC6915_H_
34 #define _DEV_IC_AIC6915_H_
35
36 #include <sys/timeout.h>
37
38 /*
39 * Register description for the Adaptec AIC-6915 (``Starfire'')
40 * 10/100 Ethernet controller.
41 */
42
43 /*
44 * Receive Buffer Descriptor (One-size, 32-bit addressing)
45 */
46 struct sf_rbd32 {
47 uint32_t rbd32_addr; /* address, flags */
48 };
49
50 /*
51 * Receive Buffer Descriptor (One-size, 64-bit addressing)
52 */
53 struct sf_rbd64 {
54 uint32_t rbd64_addr_lo; /* address (LSD), flags */
55 uint32_t rbd64_addr_hi; /* address (MDS) */
56 };
57
58 #define RBD_V (1U << 0) /* valid descriptor */
59 #define RBD_E (1U << 1) /* end of ring */
60
61 /*
62 * Short (Type 0) Completion Descriptor
63 */
64 struct sf_rcd_short {
65 uint32_t rcd_word0; /* length, end index, status1 */
66 };
67
68 /*
69 * Basic (Type 1) Completion Descriptor
70 */
71 struct sf_rcd_basic {
72 uint32_t rcd_word0; /* length, end index, status1 */
73 uint32_t rcd_word1; /* VLAN ID, status2 */
74 };
75
76 /*
77 * Checksum (Type 2) Completion Descriptor
78 */
79 struct sf_rcd_checksum {
80 uint32_t rcd_word0; /* length, end index, status1 */
81 uint32_t rcd_word1; /* partial TCP/UDP checksum, status2 */
82 };
83
84 /*
85 * Full (Type 3) Completion Descriptor
86 */
87 struct sf_rcd_full {
88 uint32_t rcd_word0; /* length, end index, status1 */
89 uint32_t rcd_word1; /* start index, status3, status2 */
90 uint32_t rcd_word2; /* VLAN ID + priority, TCP/UDP csum */
91 uint32_t rcd_timestamp; /* timestamp */
92 };
93
94 #define RCD_W0_ID (1U << 30)
95
96 #define RCD_W0_Length(x) ((x) & 0xffff)
97 #define RCD_W0_EndIndex(x) (((x) >> 16) & 0x7ff)
98 #define RCD_W0_BufferQueue (1U << 27) /* 1 == Queue 2 */
99 #define RCD_W0_FifoFull (1U << 28) /* FIFO full */
100 #define RCD_W0_OK (1U << 29) /* packet is OK */
101
102 /* Status2 field */
103 #define RCD_W1_FrameType (7U << 16)
104 #define RCD_W1_FrameType_Unknown (0 << 16)
105 #define RCD_W1_FrameType_IPv4 (1U << 16)
106 #define RCD_W1_FrameType_IPv6 (2U << 16)
107 #define RCD_W1_FrameType_IPX (3U << 16)
108 #define RCD_W1_FrameType_ICMP (4U << 16)
109 #define RCD_W1_FrameType_Unsupported (5U << 16)
110 #define RCD_W1_UdpFrame (1U << 19)
111 #define RCD_W1_TcpFrame (1U << 20)
112 #define RCD_W1_Fragmented (1U << 21)
113 #define RCD_W1_PartialChecksumValid (1U << 22)
114 #define RCD_W1_ChecksumBad (1U << 23)
115 #define RCD_W1_ChecksumOk (1U << 24)
116 #define RCD_W1_VlanFrame (1U << 25)
117 #define RCD_W1_ReceiveCodeViolation (1U << 26)
118 #define RCD_W1_Dribble (1U << 27)
119 #define RCD_W1_ISLCRCerror (1U << 28)
120 #define RCD_W1_CRCerror (1U << 29)
121 #define RCD_W1_Hash (1U << 30)
122 #define RCD_W1_Perfect (1U << 31)
123
124 #define RCD_W1_VLANID(x) ((x) & 0xffff)
125 #define RCD_W1_TCP_UDP_Checksum(x) ((x) & 0xffff)
126
127 /* Status3 field */
128 #define RCD_W1_Trailer (1U << 11)
129 #define RCD_W1_Header (1U << 12)
130 #define RCD_W1_ControlFrame (1U << 13)
131 #define RCD_W1_PauseFrame (1U << 14)
132 #define RCD_W1_IslFrame (1U << 15)
133
134 #define RCD_W1_StartIndex(x) ((x) & 0x7ff)
135
136 #define RCD_W2_TCP_UDP_Checksum(x) ((x) >> 16)
137 #define RCD_W2_VLANID(x) ((x) & 0xffff)
138
139 /*
140 * Number of transmit buffer fragments we use. This is arbitrary, but
141 * we choose it carefully; see blow.
142 */
143 #define SF_NTXFRAGS 15
144
145 /*
146 * Type 0, 32-bit addressing mode (Frame Descriptor) Transmit Descriptor
147 *
148 * NOTE: The total length of this structure is: 8 + (15 * 8) == 128
149 * This means 16 Tx indices per Type 0 descriptor. This is important later
150 * on; see below.
151 */
152 struct sf_txdesc0 {
153 /* skip field */
154 uint32_t td_word0; /* ID, flags */
155 uint32_t td_word1; /* Tx buffer count */
156 struct {
157 uint32_t fr_addr; /* address */
158 uint32_t fr_len; /* length */
159 } td_frags[SF_NTXFRAGS];
160 };
161
162 #define TD_W1_NTXBUFS (0xff << 0)
163
164 /*
165 * Type 1, 32-bit addressing mode (Buffer Descriptor) Transmit Descriptor
166 */
167 struct sf_txdesc1 {
168 /* skip field */
169 uint32_t td_word0; /* ID, flags */
170 uint32_t td_addr; /* buffer address */
171 };
172
173 #define TD_W0_ID (0xb << 28)
174 #define TD_W0_INTR (1U << 27)
175 #define TD_W0_END (1U << 26)
176 #define TD_W0_CALTCP (1U << 25)
177 #define TD_W0_CRCEN (1U << 24)
178 #define TD_W0_LEN (0xffff << 0)
179 #define TD_W0_NTXBUFS (0xff << 16)
180 #define TD_W0_NTXBUFS_SHIFT 16
181
182 /*
183 * Type 2, 64-bit addressing mode (Buffer Descriptor) Transmit Descriptor
184 */
185 struct sf_txdesc2 {
186 /* skip field */
187 uint32_t td_word0; /* ID, flags */
188 uint32_t td_reserved;
189 uint32_t td_addr_lo; /* buffer address (LSD) */
190 uint32_t td_addr_hi; /* buffer address (MSD) */
191 };
192
193 /*
194 * Transmit Completion Descriptor.
195 */
196 struct sf_tcd {
197 uint32_t tcd_word0; /* index, priority, flags */
198 };
199
200 #define TCD_DMA_ID (0x4 << 29)
201 #define TCD_INDEX(x) ((x) & 0x7fff)
202 #define TCD_PR (1U << 15)
203 #define TCD_TIMESTAMP(x) (((x) >> 16) & 0x1fff)
204
205 #define TCD_TX_ID (0x5 << 29)
206 #define TCD_CRCerror (1U << 16)
207 #define TCD_FieldLengthCkError (1U << 17)
208 #define TCD_FieldLengthRngError (1U << 18)
209 #define TCD_PacketTxOk (1U << 19)
210 #define TCD_Deferred (1U << 20)
211 #define TCD_ExDeferral (1U << 21)
212 #define TCD_ExCollisions (1U << 22)
213 #define TCD_LateCollision (1U << 23)
214 #define TCD_LongFrame (1U << 24)
215 #define TCD_FIFOUnderrun (1U << 25)
216 #define TCD_ControlTx (1U << 26)
217 #define TCD_PauseTx (1U << 27)
218 #define TCD_TxPaused (1U << 28)
219
220 /*
221 * The Tx indices are in units of 8 bytes, and since we are using
222 * Tx descriptors that are 128 bytes long, we need to divide by 16
223 * to get the actual index that we care about.
224 */
225 #define SF_TXDINDEX_TO_HOST(x) ((x) >> 4)
226 #define SF_TXDINDEX_TO_CHIP(x) ((x) << 4)
227
228 /*
229 * To make matters worse, the manual lies about the indices in the
230 * completion queue entries. It claims they are in 8-byte units,
231 * but they're actually *BYTES*, which means we need to divide by
232 * 128 to get the actual index.
233 */
234 #define SF_TCD_INDEX_TO_HOST(x) ((x) >> 7)
235
236 /*
237 * PCI configuration space addresses.
238 */
239 #define SF_PCI_MEMBA (PCI_MAPREG_START + 0x00)
240 #define SF_PCI_IOBA (PCI_MAPREG_START + 0x08)
241
242 #define SF_GENREG_OFFSET 0x50000
243 #define SF_FUNCREG_SIZE 0x100
244
245 /*
246 * PCI functional registers.
247 */
248 #define SF_PciDeviceConfig 0x40
249 #define PDC_EnDpeInt (1U << 31) /* enable DPE PCIint */
250 #define PDC_EnSseInt (1U << 30) /* enable SSE PCIint */
251 #define PDC_EnRmaInt (1U << 29) /* enable RMA PCIint */
252 #define PDC_EnRtaInt (1U << 28) /* enable RTA PCIint */
253 #define PDC_EnStaInt (1U << 27) /* enable STA PCIint */
254 #define PDC_EnDprInt (1U << 24) /* enable DPR PCIint */
255 #define PDC_IntEnable (1U << 23) /* enable PCI_INTA_ */
256 #define PDC_ExternalRegCsWidth (7U << 20) /* external chip-sel width */
257 #define PDC_StopMWrOnCacheLineDis (1U << 19)
258 #define PDC_EpromCsWidth (7U << 16)
259 #define PDC_EnBeLogic (1U << 15)
260 #define PDC_LatencyStopOnCacheLine (1U << 14)
261 #define PDC_PCIMstDmaEn (1U << 13)
262 #define PDC_StopOnCachelineEn (1U << 12)
263 #define PDC_FifoThreshold (0xf << 8)
264 #define PDC_FifoThreshold_SHIFT 8
265 #define PDC_MemRdCmdEn (1U << 7)
266 #define PDC_StopOnPerr (1U << 6)
267 #define PDC_AbortOnAddrParityErr (1U << 5)
268 #define PDC_EnIncrement (1U << 4)
269 #define PDC_System64 (1U << 2)
270 #define PDC_Force64 (1U << 1)
271 #define PDC_SoftReset (1U << 0)
272
273 #define SF_BacControl 0x44
274 #define BC_DescSwapMode (0x3 << 6)
275 #define BC_DataSwapMode (0x3 << 4)
276 #define BC_SingleDmaMode (1U << 3)
277 #define BC_PreferTxDmaReq (1U << 2)
278 #define BC_PreferRxDmaReq (1U << 1)
279 #define BC_BacDmaEn (1U << 0)
280
281 #define SF_PciMonitor1 0x48
282
283 #define SF_PciMonitor2 0x4c
284
285 #define SF_PMC 0x50
286
287 #define SF_PMCSR 0x54
288
289 #define SF_PMEvent 0x58
290
291 #define SF_SerialEpromControl 0x60
292 #define SEC_InitDone (1U << 3)
293 #define SEC_Idle (1U << 2)
294 #define SEC_WriteEnable (1U << 1)
295 #define SEC_WriteDisable (1U << 0)
296
297 #define SF_PciComplianceTesting 0x64
298
299 #define SF_IndirectIoAccess 0x68
300
301 #define SF_IndirectIoDataPort 0x6c
302
303 /*
304 * Ethernet functional registers.
305 */
306 #define SF_GeneralEthernetCtrl 0x70
307 #define GEC_SetSoftInt (1U << 8)
308 #define GEC_TxGfpEn (1U << 5)
309 #define GEC_RxGfpEn (1U << 4)
310 #define GEC_TxDmaEn (1U << 3)
311 #define GEC_RxDmaEn (1U << 2)
312 #define GEC_TransmitEn (1U << 1)
313 #define GEC_ReceiveEn (1U << 0)
314
315 #define SF_TimersControl 0x74
316 #define TC_EarlyRxQ1IntDelayDisable (1U << 31)
317 #define TC_RxQ1DoneIntDelayDisable (1U << 30)
318 #define TC_EarlyRxQ2IntDelayDisable (1U << 29)
319 #define TC_RxQ2DoneIntDelayDisable (1U << 28)
320 #define TC_TimeStampResolution (1U << 26)
321 #define TC_GeneralTimerResolution (1U << 25)
322 #define TC_OneShotMode (1U << 24)
323 #define TC_GeneralTimerInterval (0xff << 16)
324 #define TC_GeneralTimerInterval_SHIFT 16
325 #define TC_TxFrameCompleteIntDelayDisable (1U << 15)
326 #define TC_TxQueueDoneIntDelayDisable (1U << 14)
327 #define TC_TxDmaDoneIntDelayDisable (1U << 13)
328 #define TC_RxHiPrBypass (1U << 12)
329 #define TC_Timer10X (1U << 11)
330 #define TC_SmallRxFrame (3U << 9)
331 #define TC_SmallFrameBypass (1U << 8)
332 #define TC_IntMaskMode (3U << 5)
333 #define TC_IntMaskPeriod (0x1f << 0)
334
335 #define SF_CurrentTime 0x78
336
337 #define SF_InterruptStatus 0x80
338 #define IS_GPIO3 (1U << 31)
339 #define IS_GPIO2 (1U << 30)
340 #define IS_GPIO1 (1U << 29)
341 #define IS_GPIO0 (1U << 28)
342 #define IS_StatisticWrapInt (1U << 27)
343 #define IS_AbnormalInterrupt (1U << 25)
344 #define IS_GeneralTimerInt (1U << 24)
345 #define IS_SoftInt (1U << 23)
346 #define IS_RxCompletionQueue1Int (1U << 22)
347 #define IS_TxCompletionQueueInt (1U << 21)
348 #define IS_PCIInt (1U << 20)
349 #define IS_DmaErrInt (1U << 19)
350 #define IS_TxDataLowInt (1U << 18)
351 #define IS_RxCompletionQueue2Int (1U << 17)
352 #define IS_RxQ1LowBuffersInt (1U << 16)
353 #define IS_NormalInterrupt (1U << 15)
354 #define IS_TxFrameCompleteInt (1U << 14)
355 #define IS_TxDmaDoneInt (1U << 13)
356 #define IS_TxQueueDoneInt (1U << 12)
357 #define IS_EarlyRxQ2Int (1U << 11)
358 #define IS_EarlyRxQ1Int (1U << 10)
359 #define IS_RxQ2DoneInt (1U << 9)
360 #define IS_RxQ1DoneInt (1U << 8)
361 #define IS_RxGfpNoResponseInt (1U << 7)
362 #define IS_RxQ2LowBuffersInt (1U << 6)
363 #define IS_NoTxChecksumInt (1U << 5)
364 #define IS_TxLowPrMismatchInt (1U << 4)
365 #define IS_TxHiPrMismatchInt (1U << 3)
366 #define IS_GfpRxInt (1U << 2)
367 #define IS_GfpTxInt (1U << 1)
368 #define IS_PCIPadInt (1U << 0)
369
370 #define SF_ShadowInterruptStatus 0x84
371
372 #define SF_InterruptEn 0x88
373
374 #define SF_GPIO 0x8c
375 #define GPIOCtrl(x) (1U << (24 + (x)))
376 #define GPIOOutMode(x) (1U << (16 + (x)))
377 #define GPIOInpMode(x, y) ((y) << (8 + ((x) * 2)))
378 #define GPIOData(x) (1U << (x))
379
380 #define SF_TxDescQueueCtrl 0x90
381 #define TDQC_TxHighPriorityFifoThreshold(x) ((x) << 24)
382 #define TDQC_SkipLength(x) ((x) << 16)
383 #define TDQC_TxDmaBurstSize(x) ((x) << 8)
384 #define TDQC_TxDescQueue64bitAddr (1U << 7)
385 #define TDQC_MinFrameSpacing(x) ((x) << 4)
386 #define TDQC_DisableTxDmaCompletion (1U << 3)
387 #define TDQC_TxDescType(x) ((x) << 0)
388
389 #define SF_HiPrTxDescQueueBaseAddr 0x94
390
391 #define SF_LoPrTxDescQueueBaseAddr 0x98
392
393 #define SF_TxDescQueueHighAddr 0x9c
394
395 #define SF_TxDescQueueProducerIndex 0xa0
396 #define TDQPI_HiPrTxProducerIndex(x) ((x) << 16)
397 #define TDQPI_LoPrTxProducerIndex(x) ((x) << 0)
398 #define TDQPI_HiPrTxProducerIndex_get(x) (((x) >> 16) & 0x7ff)
399 #define TDQPI_LoPrTxProducerIndex_get(x) (((x) >> 0) & 0x7ff)
400
401 #define SF_TxDescQueueConsumerIndex 0xa4
402 #define TDQCI_HiPrTxConsumerIndex(x) (((x) >> 16) & 0x7ff)
403 #define TDQCI_LoPrTxConsumerIndex(s) (((x) >> 0) & 0x7ff)
404
405 #define SF_TxDmaStatus1 0xa8
406
407 #define SF_TxDmaStatus2 0xac
408
409 #define SF_TransmitFrameCSR 0xb0
410 #define TFCSR_TxFrameStatus (0xff << 16)
411 #define TFCSR_TxDebugConfigBits (0x7f << 9)
412 #define TFCSR_DmaCompletionAfterTransmitComplete (1U << 8)
413 #define TFCSR_TransmitThreshold(x) ((x) << 0)
414
415 #define SF_CompletionQueueHighAddr 0xb4
416
417 #define SF_TxCompletionQueueCtrl 0xb8
418 #define TCQC_TxCompletionBaseAddress 0xffffff00
419 #define TCQC_TxCompletion64bitAddress (1U << 7)
420 #define TCQC_TxCompletionProducerWe (1U << 6)
421 #define TCQC_TxCompletionSize (1U << 5)
422 #define TCQC_CommonQueueMode (1U << 4)
423 #define TCQC_TxCompletionQueueThreshold ((x) << 0)
424
425 #define SF_RxCompletionQueue1Ctrl 0xbc
426 #define RCQ1C_RxCompletionQ1BaseAddress 0xffffff00
427 #define RCQ1C_RxCompletionQ164bitAddress (1U << 7)
428 #define RCQ1C_RxCompletionQ1ProducerWe (1U << 6)
429 #define RCQ1C_RxCompletionQ1Type(x) ((x) << 4)
430 #define RCQ1C_RxCompletionQ1Threshold(x) ((x) << 0)
431
432 #define SF_RxCompletionQueue2Ctrl 0xc0
433 #define RCQ1C_RxCompletionQ2BaseAddress 0xffffff00
434 #define RCQ1C_RxCompletionQ264bitAddress (1U << 7)
435 #define RCQ1C_RxCompletionQ2ProducerWe (1U << 6)
436 #define RCQ1C_RxCompletionQ2Type(x) ((x) << 4)
437 #define RCQ1C_RxCompletionQ2Threshold(x) ((x) << 0)
438
439 #define SF_CompletionQueueConsumerIndex 0xc4
440 #define CQCI_TxCompletionThresholdMode (1U << 31)
441 #define CQCI_TxCompletionConsumerIndex(x) ((x) << 16)
442 #define CQCI_TxCompletionConsumerIndex_get(x) (((x) >> 16) & 0x7ff)
443 #define CQCI_RxCompletionQ1ThresholdMode (1U << 15)
444 #define CQCI_RxCompletionQ1ConsumerIndex(x) ((x) << 0)
445 #define CQCI_RxCompletionQ1ConsumerIndex_get(x) ((x) & 0x7ff)
446
447 #define SF_CompletionQueueProducerIndex 0xc8
448 #define CQPI_TxCompletionProducerIndex(x) ((x) << 16)
449 #define CQPI_TxCompletionProducerIndex_get(x) (((x) >> 16) & 0x7ff)
450 #define CQPI_RxCompletionQ1ProducerIndex(x) ((x) << 0)
451 #define CQPI_RxCompletionQ1ProducerIndex_get(x) ((x) & 0x7ff)
452
453 #define SF_RxHiPrCompletionPtrs 0xcc
454 #define RHPCP_RxCompletionQ2ProducerIndex(x) ((x) << 16)
455 #define RHPCP_RxCompletionQ2ThresholdMode (1U << 15)
456 #define RHPCP_RxCompletionQ2ConsumerIndex(x) ((x) << 0)
457
458 #define SF_RxDmaCtrl 0xd0
459 #define RDC_RxReportBadFrames (1U << 31)
460 #define RDC_RxDmaShortFrames (1U << 30)
461 #define RDC_RxDmaBadFrames (1U << 29)
462 #define RDC_RxDmaCrcErrorFrames (1U << 28)
463 #define RDC_RxDmaControlFrame (1U << 27)
464 #define RDC_RxDmaPauseFrame (1U << 26)
465 #define RDC_RxChecksumMode(x) ((x) << 24)
466 #define RDC_RxCompletionQ2Enable (1U << 23)
467 #define RDC_RxDmaQueueMode(x) ((x) << 20)
468 #define RDC_RxUseBackupQueue (1U << 19)
469 #define RDC_RxDmaCrc (1U << 18)
470 #define RDC_RxEarlyIntThreshold(x) ((x) << 12)
471 #define RDC_RxHighPriorityThreshold(x) ((x) << 8)
472 #define RDC_RxBurstSize(x) ((x) << 0)
473
474 #define SF_RxDescQueue1Ctrl 0xd4
475 #define RDQ1C_RxQ1BufferLength(x) ((x) << 16)
476 #define RDQ1C_RxPrefetchDescriptorsMode (1U << 15)
477 #define RDQ1C_RxDescQ1Entries (1U << 14)
478 #define RDQ1C_RxVariableSizeQueues (1U << 13)
479 #define RDQ1C_Rx64bitBufferAddresses (1U << 12)
480 #define RDQ1C_Rx64bitDescQueueAddress (1U << 11)
481 #define RDQ1C_RxDescSpacing(x) ((x) << 8)
482 #define RDQ1C_RxQ1ConsumerWe (1U << 7)
483 #define RDQ1C_RxQ1MinDescriptorsThreshold(x) ((x) << 0)
484
485 #define SF_RxDescQueue2Ctrl 0xd8
486 #define RDQ2C_RxQ2BufferLength(x) ((x) << 16)
487 #define RDQ2C_RxDescQ2Entries (1U << 14)
488 #define RDQ2C_RxQ2MinDescriptorsThreshold(x) ((x) << 0)
489
490 #define SF_RxDescQueueHighAddress 0xdc
491
492 #define SF_RxDescQueue1LowAddress 0xe0
493
494 #define SF_RxDescQueue2LowAddress 0xe4
495
496 #define SF_RxDescQueue1Ptrs 0xe8
497 #define RXQ1P_RxDescQ1Consumer(x) ((x) << 16)
498 #define RXQ1P_RxDescQ1Producer(x) ((x) << 0)
499 #define RXQ1P_RxDescQ1Producer_get(x) ((x) & 0x7ff)
500
501 #define SF_RxDescQueue2Ptrs 0xec
502 #define RXQ2P_RxDescQ2Consumer(x) ((x) << 16)
503 #define RXQ2P_RxDescQ2Producer(x) ((x) << 0)
504
505 #define SF_RxDmaStatus 0xf0
506 #define RDS_RxFramesLostCount(x) ((x) & 0xffff)
507
508 #define SF_RxAddressFilteringCtl 0xf4
509 #define RAFC_PerfectAddressPriority(x) (1U << ((x) + 16))
510 #define RAFC_MinVlanPriority(x) ((x) << 13)
511 #define RAFC_PassMulticastExceptBroadcast (1U << 12)
512 #define RAFC_WakeupMode(x) ((x) << 10)
513 #define RAFC_VlanMode(x) ((x) << 8)
514 #define RAFC_PerfectFilteringMode(x) ((x) << 6)
515 #define RAFC_HashFilteringMode(x) ((x) << 4)
516 #define RAFC_HashPriorityEnable (1U << 3)
517 #define RAFC_PassBroadcast (1U << 2)
518 #define RAFC_PassMulticast (1U << 1)
519 #define RAFC_PromiscuousMode (1U << 0)
520
521 #define SF_RxFrameTestOut 0xf8
522
523 /*
524 * Additional PCI registers. To access these registers via I/O space,
525 * indirect access must be used.
526 */
527 #define SF_PciTargetStatus 0x100
528
529 #define SF_PciMasterStatus1 0x104
530
531 #define SF_PciMasterStatus2 0x108
532
533 #define SF_PciDmaLowHostAddr 0x10c
534
535 #define SF_BacDmaDiagnostic0 0x110
536
537 #define SF_BacDmaDiagnostic1 0x114
538
539 #define SF_BacDmaDiagnostic2 0x118
540
541 #define SF_BacDmaDiagnostic3 0x11c
542
543 #define SF_MacAddr1 0x120
544
545 #define SF_MacAddr2 0x124
546
547 #define SF_FunctionEvent 0x130
548
549 #define SF_FunctionEventMask 0x134
550
551 #define SF_FunctionPresentState 0x138
552
553 #define SF_ForceFunction 0x13c
554
555 #define SF_EEPROM_BASE 0x1000
556
557 #define SF_MII_BASE 0x2000
558 #define MiiDataValid (1U << 31)
559 #define MiiBusy (1U << 30)
560 #define MiiRegDataPort(x) ((x) & 0xffff)
561
562 #define SF_MII_PHY_REG(p, r) (SF_MII_BASE + \
563 ((p) * 32 * sizeof(uint32_t)) + \
564 ((r) * sizeof(uint32_t)))
565
566 #define SF_TestMode 0x4000
567
568 #define SF_RxFrameProcessorCtrl 0x4004
569
570 #define SF_TxFrameProcessorCtrl 0x4008
571
572 #define SF_MacConfig1 0x5000
573 #define MC1_SoftRst (1U << 15)
574 #define MC1_MiiLoopBack (1U << 14)
575 #define MC1_TestMode(x) ((x) << 12)
576 #define MC1_TxFlowEn (1U << 11)
577 #define MC1_RxFlowEn (1U << 10)
578 #define MC1_PreambleDetectCount (1U << 9)
579 #define MC1_PassAllRxPackets (1U << 8)
580 #define MC1_PurePreamble (1U << 7)
581 #define MC1_LengthCheck (1U << 6)
582 #define MC1_NoBackoff (1U << 5)
583 #define MC1_DelayCRC (1U << 4)
584 #define MC1_TxHalfDuplexJam (1U << 3)
585 #define MC1_PadEn (1U << 2)
586 #define MC1_FullDuplex (1U << 1)
587 #define MC1_HugeFrame (1U << 0)
588
589 #define SF_MacConfig2 0x5004
590 #define MC2_TxCRCerr (1U << 15)
591 #define MC2_TxIslCRCerr (1U << 14)
592 #define MC2_RxCRCerr (1U << 13)
593 #define MC2_RxIslCRCerr (1U << 12)
594 #define MC2_TXCF (1U << 11)
595 #define MC2_CtlSoftRst (1U << 10)
596 #define MC2_RxSoftRst (1U << 9)
597 #define MC2_TxSoftRst (1U << 8)
598 #define MC2_RxISLEn (1U << 7)
599 #define MC2_BackPressureNoBackOff (1U << 6)
600 #define MC2_AutoVlanPad (1U << 5)
601 #define MC2_MandatoryVLANPad (1U << 4)
602 #define MC2_TxISLAppen (1U << 3)
603 #define MC2_TxISLEn (1U << 2)
604 #define MC2_SimuRst (1U << 1)
605 #define MC2_TxXmtEn (1U << 0)
606
607 #define SF_BkToBkIPG 0x5008
608
609 #define SF_NonBkToBkIPG 0x500c
610
611 #define SF_ColRetry 0x5010
612
613 #define SF_MaxLength 0x5014
614
615 #define SF_TxNibbleCnt 0x5018
616
617 #define SF_TxByteCnt 0x501c
618
619 #define SF_ReTxCnt 0x5020
620
621 #define SF_RandomNumGen 0x5024
622
623 #define SF_MskRandomNum 0x5028
624
625 #define SF_TotalTxCnt 0x5034
626
627 #define SF_RxByteCnt 0x5040
628
629 #define SF_TxPauseTimer 0x5060
630
631 #define SF_VLANType 0x5064
632
633 #define SF_MiiStatus 0x5070
634
635 #define SF_PERFECT_BASE 0x6000
636 #define SF_PERFECT_SIZE 0x100
637
638 #define SF_HASH_BASE 0x6100
639 #define SF_HASH_SIZE 0x200
640
641 #define SF_STATS_BASE 0x7000
642 struct sf_stats {
643 uint32_t TransmitOKFrames;
644 uint32_t SingleCollisionFrames;
645 uint32_t MultipleCollisionFrames;
646 uint32_t TransmitCRCErrors;
647 uint32_t TransmitOKOctets;
648 uint32_t TransmitDeferredFrames;
649 uint32_t TransmitLateCollisionCount;
650 uint32_t TransmitPauseControlFrames;
651 uint32_t TransmitControlFrames;
652 uint32_t TransmitAbortDueToExcessiveCollisions;
653 uint32_t TransmitAbortDueToExcessingDeferral;
654 uint32_t MulticastFramesTransmittedOK;
655 uint32_t BroadcastFramesTransmittedOK;
656 uint32_t FramesLostDueToInternalTransmitErrors;
657 uint32_t ReceiveOKFrames;
658 uint32_t ReceiveCRCErrors;
659 uint32_t AlignmentErrors;
660 uint32_t ReceiveOKOctets;
661 uint32_t PauseFramesReceivedOK;
662 uint32_t ControlFramesReceivedOK;
663 uint32_t ControlFramesReceivedWithUnsupportedOpcode;
664 uint32_t ReceiveFramesTooLong;
665 uint32_t ReceiveFramesTooShort;
666 uint32_t ReceiveFramesJabbersError;
667 uint32_t ReceiveFramesFragments;
668 uint32_t ReceivePackets64Bytes;
669 uint32_t ReceivePackets127Bytes;
670 uint32_t ReceivePackets255Bytes;
671 uint32_t ReceivePackets511Bytes;
672 uint32_t ReceivePackets1023Bytes;
673 uint32_t ReceivePackets1518Bytes;
674 uint32_t FramesLostDueToInternalReceiveErrors;
675 uint32_t TransmitFifoUnderflowCounts;
676 };
677
678 #define SF_TxGfpMem 0x8000
679
680 #define SF_RxGfpMem 0xa000
681
682 /*
683 * Data structure definitions for the Adaptec AIC-6915 (``Starfire'')
684 * PCI 10/100 Ethernet controller driver.
685 */
686
687 /*
688 * Transmit descriptor list size.
689 */
690 #define SF_NTXDESC 256
691 #define SF_NTXDESC_MASK (SF_NTXDESC - 1)
692 #define SF_NEXTTX(x) ((x + 1) & SF_NTXDESC_MASK)
693
694 /*
695 * Transmit completion queue size. 1024 is a hardware requirement.
696 */
697 #define SF_NTCD 1024
698 #define SF_NTCD_MASK (SF_NTCD - 1)
699 #define SF_NEXTTCD(x) ((x + 1) & SF_NTCD_MASK)
700
701 /*
702 * Receive descriptor list size.
703 */
704 #define SF_NRXDESC 256
705 #define SF_NRXDESC_MASK (SF_NRXDESC - 1)
706 #define SF_NEXTRX(x) ((x + 1) & SF_NRXDESC_MASK)
707
708 /*
709 * Receive completion queue size. 1024 is a hardware requirement.
710 */
711 #define SF_NRCD 1024
712 #define SF_NRCD_MASK (SF_NRCD - 1)
713 #define SF_NEXTRCD(x) ((x + 1) & SF_NRCD_MASK)
714
715 /*
716 * Control structures are DMA to the Starfire chip. We allocate them in
717 * a single clump that maps to a single DMA segment to make several things
718 * easier.
719 */
720 struct sf_control_data {
721 /*
722 * The transmit descriptors.
723 */
724 struct sf_txdesc0 scd_txdescs[SF_NTXDESC];
725
726 /*
727 * The transmit completion queue entries.
728 */
729 struct sf_tcd scd_txcomp[SF_NTCD];
730
731 /*
732 * The receive buffer descriptors.
733 */
734 struct sf_rbd32 scd_rxbufdescs[SF_NRXDESC];
735
736 /*
737 * The receive completion queue entries.
738 */
739 struct sf_rcd_full scd_rxcomp[SF_NRCD];
740 };
741
742 #define SF_CDOFF(x) offsetof(struct sf_control_data, x)
743 #define SF_CDTXDOFF(x) SF_CDOFF(scd_txdescs[(x)])
744 #define SF_CDTXCOFF(x) SF_CDOFF(scd_txcomp[(x)])
745 #define SF_CDRXDOFF(x) SF_CDOFF(scd_rxbufdescs[(x)])
746 #define SF_CDRXCOFF(x) SF_CDOFF(scd_rxcomp[(x)])
747
748 /*
749 * Software state for transmit and receive descriptors.
750 */
751 struct sf_descsoft {
752 struct mbuf *ds_mbuf; /* head of mbuf chain */
753 bus_dmamap_t ds_dmamap; /* our DMA map */
754 };
755
756 /*
757 * Software state per device.
758 */
759 struct sf_softc {
760 struct device sc_dev; /* generic device information */
761 bus_space_tag_t sc_st; /* bus space tag */
762 bus_space_handle_t sc_sh; /* bus space handle */
763 bus_space_handle_t sc_sh_func; /* sub-handle for func regs */
764 bus_dma_tag_t sc_dmat; /* bus DMA tag */
765 struct arpcom sc_arpcom; /* ethernet common data */
766 int sc_iomapped; /* are we I/O mapped? */
767 int sc_flags; /* misc. flags */
768
769 struct mii_data sc_mii; /* MII/media information */
770 struct timeout sc_mii_timeout; /* MII callout */
771
772 bus_dmamap_t sc_cddmamap; /* control data DMA map */
773 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
774
775 /*
776 * Software state for transmit and receive descriptors.
777 */
778 struct sf_descsoft sc_txsoft[SF_NTXDESC];
779 struct sf_descsoft sc_rxsoft[SF_NRXDESC];
780
781 /*
782 * Control data structures.
783 */
784 struct sf_control_data *sc_control_data;
785 #define sc_txdescs sc_control_data->scd_txdescs
786 #define sc_txcomp sc_control_data->scd_txcomp
787 #define sc_rxbufdescs sc_control_data->scd_rxbufdescs
788 #define sc_rxcomp sc_control_data->scd_rxcomp
789
790 int sc_txpending; /* number of Tx requests pending */
791
792 uint32_t sc_InterruptEn; /* prototype InterruptEn register */
793
794 uint32_t sc_TransmitFrameCSR; /* prototype TransmitFrameCSR reg */
795 uint32_t sc_TxDescQueueCtrl; /* prototype TxDescQueueCtrl reg */
796 int sc_txthresh; /* current Tx threshold */
797
798 uint32_t sc_MacConfig1; /* prototype MacConfig1 register */
799
800 uint32_t sc_RxAddressFilteringCtl;
801 };
802
803 #define SF_CDTXDADDR(sc, x) ((sc)->sc_cddma + SF_CDTXDOFF((x)))
804 #define SF_CDTXCADDR(sc, x) ((sc)->sc_cddma + SF_CDTXCOFF((x)))
805 #define SF_CDRXDADDR(sc, x) ((sc)->sc_cddma + SF_CDRXDOFF((x)))
806 #define SF_CDRXCADDR(sc, x) ((sc)->sc_cddma + SF_CDRXCOFF((x)))
807
808 #define SF_CDTXDSYNC(sc, x, ops) \
809 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
810 SF_CDTXDOFF((x)), sizeof(struct sf_txdesc0), (ops))
811
812 #define SF_CDTXCSYNC(sc, x, ops) \
813 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
814 SF_CDTXCOFF((x)), sizeof(struct sf_tcd), (ops))
815
816 #define SF_CDRXDSYNC(sc, x, ops) \
817 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
818 SF_CDRXDOFF((x)), sizeof(struct sf_rbd32), (ops))
819
820 #define SF_CDRXCSYNC(sc, x, ops) \
821 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
822 SF_CDRXCOFF((x)), sizeof(struct sf_rcd_full), (ops))
823
824 #define SF_INIT_RXDESC(sc, x) \
825 do { \
826 struct sf_descsoft *__ds = &sc->sc_rxsoft[(x)]; \
827 \
828 (sc)->sc_rxbufdescs[(x)].rbd32_addr = \
829 __ds->ds_dmamap->dm_segs[0].ds_addr | RBD_V; \
830 SF_CDRXDSYNC((sc), (x), BUS_DMASYNC_PREWRITE); \
831 } while (/*CONSTCOND*/0)
832
833 #ifdef _KERNEL
834 void sf_attach(struct sf_softc *);
835 int sf_intr(void *);
836 #endif /* _KERNEL */
837
838 #endif /* _DEV_IC_AIC6915_H_ */
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