aic6915var.h

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    1 /*      $NetBSD: aic6915var.h,v 1.5 2022/05/04 07:32:50 andvar Exp $    */
    2 
    3 /*-
    4  * Copyright (c) 2001 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   29  * POSSIBILITY OF SUCH DAMAGE.
   30  */
   31 
   32 #ifndef _DEV_IC_AIC6915VAR_H_
   33 #define _DEV_IC_AIC6915VAR_H_
   34 
   35 #include <sys/callout.h>
   36 
   37 /*
   38  * Data structure definitions for the Adaptec AIC-6915 (``Starfire'')
   39  * PCI 10/100 Ethernet controller driver.
   40  */
   41 
   42 /*
   43  * Transmit descriptor list size.
   44  */
   45 #define SF_NTXDESC              256
   46 #define SF_NTXDESC_MASK         (SF_NTXDESC - 1)
   47 #define SF_NEXTTX(x)            ((x + 1) & SF_NTXDESC_MASK)
   48 
   49 /*
   50  * Transmit completion queue size.  1024 is a hardware requirement.
   51  */
   52 #define SF_NTCD                 1024
   53 #define SF_NTCD_MASK            (SF_NTCD - 1)
   54 #define SF_NEXTTCD(x)           ((x + 1) & SF_NTCD_MASK)
   55 
   56 /*
   57  * Receive descriptor list size.
   58  */
   59 #define SF_NRXDESC              256
   60 #define SF_NRXDESC_MASK         (SF_NRXDESC - 1)
   61 #define SF_NEXTRX(x)            ((x + 1) & SF_NRXDESC_MASK)
   62 
   63 /*
   64  * Receive completion queue size.  1024 is a hardware requirement.
   65  */
   66 #define SF_NRCD                 1024
   67 #define SF_NRCD_MASK            (SF_NRCD - 1)
   68 #define SF_NEXTRCD(x)           ((x + 1) & SF_NRCD_MASK)
   69 
   70 /*
   71  * Control structures are DMA to the Starfire chip.  We allocate them in
   72  * a single clump that maps to a single DMA segment to make several things
   73  * easier.
   74  */
   75 struct sf_control_data {
   76         /*
   77          * The transmit descriptors.
   78          */
   79         struct sf_txdesc0 scd_txdescs[SF_NTXDESC];
   80 
   81         /*
   82          * The transmit completion queue entries.
   83          */
   84         struct sf_tcd scd_txcomp[SF_NTCD];
   85 
   86         /*
   87          * The receive buffer descriptors.
   88          */
   89         struct sf_rbd32 scd_rxbufdescs[SF_NRXDESC];
   90 
   91         /*
   92          * The receive completion queue entries.
   93          */
   94         struct sf_rcd_full scd_rxcomp[SF_NRCD];
   95 };
   96 
   97 #define SF_CDOFF(x)             offsetof(struct sf_control_data, x)
   98 #define SF_CDTXDOFF(x)          SF_CDOFF(scd_txdescs[(x)])
   99 #define SF_CDTXCOFF(x)          SF_CDOFF(scd_txcomp[(x)])
  100 #define SF_CDRXDOFF(x)          SF_CDOFF(scd_rxbufdescs[(x)])
  101 #define SF_CDRXCOFF(x)          SF_CDOFF(scd_rxcomp[(x)])
  102 
  103 /*
  104  * Software state for transmit and receive descriptors.
  105  */
  106 struct sf_descsoft {
  107         struct mbuf *ds_mbuf;           /* head of mbuf chain */
  108         bus_dmamap_t ds_dmamap;         /* our DMA map */
  109 };
  110 
  111 /*
  112  * Software state per device.
  113  */
  114 struct sf_softc {
  115         device_t sc_dev;                /* generic device information */
  116         bus_space_tag_t sc_st;          /* bus space tag */
  117         bus_space_handle_t sc_sh;       /* bus space handle */
  118         bus_space_handle_t sc_sh_func;  /* sub-handle for func regs */
  119         bus_dma_tag_t sc_dmat;          /* bus DMA tag */
  120         struct ethercom sc_ethercom;    /* ethernet common data */
  121         int sc_iomapped;                /* are we I/O mapped? */
  122 
  123         struct mii_data sc_mii;         /* MII/media information */
  124         struct callout sc_tick_callout; /* MII callout */
  125 
  126         bus_dmamap_t sc_cddmamap;       /* control data DMA map */
  127 #define sc_cddma        sc_cddmamap->dm_segs[0].ds_addr
  128 
  129         /*
  130          * Software state for transmit and receive descriptors.
  131          */
  132         struct sf_descsoft sc_txsoft[SF_NTXDESC];
  133         struct sf_descsoft sc_rxsoft[SF_NRXDESC];
  134 
  135         /*
  136          * Control data structures.
  137          */
  138         struct sf_control_data *sc_control_data;
  139 #define sc_txdescs      sc_control_data->scd_txdescs
  140 #define sc_txcomp       sc_control_data->scd_txcomp
  141 #define sc_rxbufdescs   sc_control_data->scd_rxbufdescs
  142 #define sc_rxcomp       sc_control_data->scd_rxcomp
  143 
  144         int     sc_txpending;           /* number of Tx requests pending */
  145 
  146         uint32_t sc_InterruptEn;        /* prototype InterruptEn register */
  147 
  148         uint32_t sc_TransmitFrameCSR;   /* prototype TransmitFrameCSR reg */
  149         uint32_t sc_TxDescQueueCtrl;    /* prototype TxDescQueueCtrl reg */
  150         int     sc_txthresh;            /* current Tx threshold */
  151 
  152         uint32_t sc_MacConfig1;         /* prototype MacConfig1 register */
  153 
  154         uint32_t sc_RxAddressFilteringCtl;
  155 };
  156 
  157 #define SF_CDTXDADDR(sc, x)     ((sc)->sc_cddma + SF_CDTXDOFF((x)))
  158 #define SF_CDTXCADDR(sc, x)     ((sc)->sc_cddma + SF_CDTXCOFF((x)))
  159 #define SF_CDRXDADDR(sc, x)     ((sc)->sc_cddma + SF_CDRXDOFF((x)))
  160 #define SF_CDRXCADDR(sc, x)     ((sc)->sc_cddma + SF_CDRXCOFF((x)))
  161 
  162 #define SF_CDTXDSYNC(sc, x, ops)                                        \
  163         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  164             SF_CDTXDOFF((x)), sizeof(struct sf_txdesc0), (ops))
  165 
  166 #define SF_CDTXCSYNC(sc, x, ops)                                        \
  167         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  168             SF_CDTXCOFF((x)), sizeof(struct sf_tcd), (ops))
  169 
  170 #define SF_CDRXDSYNC(sc, x, ops)                                        \
  171         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  172             SF_CDRXDOFF((x)), sizeof(struct sf_rbd32), (ops))
  173 
  174 #define SF_CDRXCSYNC(sc, x, ops)                                        \
  175         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  176             SF_CDRXCOFF((x)), sizeof(struct sf_rcd_full), (ops))
  177 
  178 #define SF_INIT_RXDESC(sc, x)                                           \
  179 do {                                                                    \
  180         struct sf_descsoft *__ds = &sc->sc_rxsoft[(x)];                 \
  181                                                                         \
  182         (sc)->sc_rxbufdescs[(x)].rbd32_addr =                           \
  183             __ds->ds_dmamap->dm_segs[0].ds_addr | RBD_V;                \
  184         SF_CDRXDSYNC((sc), (x), BUS_DMASYNC_PREWRITE);                  \
  185 } while (/*CONSTCOND*/0)
  186 
  187 #ifdef _KERNEL
  188 void    sf_attach(struct sf_softc *);
  189 int     sf_intr(void *);
  190 #endif /* _KERNEL */
  191 
  192 #endif /* _DEV_IC_AIC6915VAR_H_ */

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