1 /* $NetBSD: aic7xxx_inline.h,v 1.4.2.1 2005/12/16 20:06:31 jmc Exp $ */
2
3 /*
4 * Inline routines shareable across OS platforms.
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * //depot/aic7xxx/aic7xxx/aic7xxx_inline.h#39 $
43 *
44 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_inline.h,v 1.20 2003/01/20 20:44:55 gibbs Exp $
45 */
46 /*
47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
48 */
49
50 #ifndef _AIC7XXX_INLINE_H_
51 #define _AIC7XXX_INLINE_H_
52
53 /************************* Sequencer Execution Control ************************/
54 static __inline void ahc_pause_bug_fix(struct ahc_softc *ahc);
55 static __inline int ahc_is_paused(struct ahc_softc *ahc);
56 static __inline void ahc_pause(struct ahc_softc *ahc);
57 static __inline void ahc_unpause(struct ahc_softc *ahc);
58
59 /*
60 * Work around any chip bugs related to halting sequencer execution.
61 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by
62 * reading a register that will set this signal and deassert it.
63 * Without this workaround, if the chip is paused, by an interrupt or
64 * manual pause while accessing scb ram, accesses to certain registers
65 * will hang the system (infinite pci retries).
66 */
67 static __inline void
68 ahc_pause_bug_fix(struct ahc_softc *ahc)
69 {
70 if ((ahc->features & AHC_ULTRA2) != 0)
71 (void)ahc_inb(ahc, CCSCBCTL);
72 }
73
74 /*
75 * Determine whether the sequencer has halted code execution.
76 * Returns non-zero status if the sequencer is stopped.
77 */
78 static __inline int
79 ahc_is_paused(struct ahc_softc *ahc)
80 {
81 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0);
82 }
83
84 /*
85 * Request that the sequencer stop and wait, indefinitely, for it
86 * to stop. The sequencer will only acknowledge that it is paused
87 * once it has reached an instruction boundary and PAUSEDIS is
88 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS
89 * for critical sections.
90 */
91 static __inline void
92 ahc_pause(struct ahc_softc *ahc)
93 {
94 ahc_outb(ahc, HCNTRL, ahc->pause);
95
96 /*
97 * Since the sequencer can disable pausing in a critical section, we
98 * must loop until it actually stops.
99 */
100 while (ahc_is_paused(ahc) == 0)
101 ;
102
103 ahc_pause_bug_fix(ahc);
104 }
105
106 /*
107 * Allow the sequencer to continue program execution.
108 * We check here to ensure that no additional interrupt
109 * sources that would cause the sequencer to halt have been
110 * asserted. If, for example, a SCSI bus reset is detected
111 * while we are fielding a different, pausing, interrupt type,
112 * we don't want to release the sequencer before going back
113 * into our interrupt handler and dealing with this new
114 * condition.
115 */
116 static __inline void
117 ahc_unpause(struct ahc_softc *ahc)
118 {
119 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0)
120 ahc_outb(ahc, HCNTRL, ahc->unpause);
121 }
122
123 /*********************** Untagged Transaction Routines ************************/
124 static __inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc);
125 static __inline void ahc_release_untagged_queues(struct ahc_softc *ahc);
126
127 /*
128 * Block our completion routine from starting the next untagged
129 * transaction for this target or target lun.
130 */
131 static __inline void
132 ahc_freeze_untagged_queues(struct ahc_softc *ahc)
133 {
134 if ((ahc->flags & AHC_SCB_BTT) == 0)
135 ahc->untagged_queue_lock++;
136 }
137
138 /*
139 * Allow the next untagged transaction for this target or target lun
140 * to be executed. We use a counting semaphore to allow the lock
141 * to be acquired recursively. Once the count drops to zero, the
142 * transaction queues will be run.
143 */
144 static __inline void
145 ahc_release_untagged_queues(struct ahc_softc *ahc)
146 {
147 if ((ahc->flags & AHC_SCB_BTT) == 0) {
148 ahc->untagged_queue_lock--;
149 if (ahc->untagged_queue_lock == 0)
150 ahc_run_untagged_queues(ahc);
151 }
152 }
153
154 /************************** Memory mapping routines ***************************/
155 static __inline struct ahc_dma_seg *
156 ahc_sg_bus_to_virt(struct scb *scb,
157 uint32_t sg_busaddr);
158 static __inline uint32_t
159 ahc_sg_virt_to_bus(struct scb *scb,
160 struct ahc_dma_seg *sg);
161 static __inline uint32_t
162 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index);
163 static __inline void ahc_sync_scb(struct ahc_softc *ahc,
164 struct scb *scb, int op);
165 static __inline void ahc_sync_sglist(struct ahc_softc *ahc,
166 struct scb *scb, int op);
167 static __inline uint32_t
168 ahc_targetcmd_offset(struct ahc_softc *ahc,
169 u_int index);
170
171 static __inline struct ahc_dma_seg *
172 ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr)
173 {
174 int sg_index;
175
176 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg);
177 /* sg_list_phys points to entry 1, not 0 */
178 sg_index++;
179
180 return (&scb->sg_list[sg_index]);
181 }
182
183 static __inline uint32_t
184 ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg)
185 {
186 int sg_index;
187
188 /* sg_list_phys points to entry 1, not 0 */
189 sg_index = sg - &scb->sg_list[1];
190
191 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list)));
192 }
193
194 static __inline uint32_t
195 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index)
196 {
197 return (ahc->scb_data->hscb_busaddr
198 + (sizeof(struct hardware_scb) * index));
199 }
200
201 static __inline void
202 ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op)
203 {
204 ahc_dmamap_sync(ahc, ahc->parent_dmat,
205 ahc->scb_data->hscb_dmamap,
206 /*offset*/(scb->hscb - ahc->scb_data->hscbs) * sizeof(*scb->hscb),
207 /*len*/sizeof(*scb->hscb), op);
208 }
209
210 static __inline void
211 ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op)
212 {
213 if (scb->sg_count == 0)
214 return;
215
216 ahc_dmamap_sync(ahc, ahc->parent_dmat, scb->sg_map->sg_dmamap,
217 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr)
218 * sizeof(struct ahc_dma_seg),
219 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op);
220 }
221
222 static __inline uint32_t
223 ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index)
224 {
225 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo);
226 }
227
228 /******************************** Debugging ***********************************/
229 static __inline char *ahc_name(struct ahc_softc *ahc);
230
231 static __inline char *
232 ahc_name(struct ahc_softc *ahc)
233 {
234 return (ahc->name);
235 }
236
237 /*********************** Miscellaneous Support Functions ***********************/
238
239 static __inline void ahc_update_residual(struct ahc_softc *ahc,
240 struct scb *scb);
241 static __inline struct ahc_initiator_tinfo *
242 ahc_fetch_transinfo(struct ahc_softc *ahc,
243 char channel, u_int our_id,
244 u_int remote_id,
245 struct ahc_tmode_tstate **tstate);
246 static __inline uint16_t
247 ahc_inw(struct ahc_softc *ahc, u_int port);
248 static __inline void ahc_outw(struct ahc_softc *ahc, u_int port,
249 u_int value);
250 static __inline uint32_t
251 ahc_inl(struct ahc_softc *ahc, u_int port);
252 static __inline void ahc_outl(struct ahc_softc *ahc, u_int port,
253 uint32_t value);
254 static __inline uint64_t
255 ahc_inq(struct ahc_softc *ahc, u_int port);
256 static __inline void ahc_outq(struct ahc_softc *ahc, u_int port,
257 uint64_t value);
258 static __inline struct scb*
259 ahc_get_scb(struct ahc_softc *ahc);
260 static __inline void ahc_free_scb(struct ahc_softc *ahc, struct scb *scb);
261 static __inline void ahc_swap_with_next_hscb(struct ahc_softc *ahc,
262 struct scb *scb);
263 static __inline void ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb);
264 static __inline struct scsipi_sense_data *
265 ahc_get_sense_buf(struct ahc_softc *ahc,
266 struct scb *scb);
267 static __inline uint32_t
268 ahc_get_sense_bufaddr(struct ahc_softc *ahc,
269 struct scb *scb);
270
271 /*
272 * Determine whether the sequencer reported a residual
273 * for this SCB/transaction.
274 */
275 static __inline void
276 ahc_update_residual(struct ahc_softc *ahc, struct scb *scb)
277 {
278 uint32_t sgptr;
279
280 sgptr = ahc_le32toh(scb->hscb->sgptr);
281 if ((sgptr & SG_RESID_VALID) != 0)
282 ahc_calc_residual(ahc, scb);
283 }
284
285 /*
286 * Return pointers to the transfer negotiation information
287 * for the specified our_id/remote_id pair.
288 */
289 static __inline struct ahc_initiator_tinfo *
290 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id,
291 u_int remote_id, struct ahc_tmode_tstate **tstate)
292 {
293 /*
294 * Transfer data structures are stored from the perspective
295 * of the target role. Since the parameters for a connection
296 * in the initiator role to a given target are the same as
297 * when the roles are reversed, we pretend we are the target.
298 */
299 /*if (channel == 'B')
300 our_id += 8;*/
301 *tstate = ahc->enabled_targets[our_id];
302 return (&(*tstate)->transinfo[remote_id]);
303 }
304
305 static __inline uint16_t
306 ahc_inw(struct ahc_softc *ahc, u_int port)
307 {
308 return ((ahc_inb(ahc, port+1) << 8) | ahc_inb(ahc, port));
309 }
310
311 static __inline void
312 ahc_outw(struct ahc_softc *ahc, u_int port, u_int value)
313 {
314 ahc_outb(ahc, port, value & 0xFF);
315 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
316 }
317
318 static __inline uint32_t
319 ahc_inl(struct ahc_softc *ahc, u_int port)
320 {
321 return ((ahc_inb(ahc, port))
322 | (ahc_inb(ahc, port+1) << 8)
323 | (ahc_inb(ahc, port+2) << 16)
324 | (ahc_inb(ahc, port+3) << 24));
325 }
326
327 static __inline void
328 ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value)
329 {
330 ahc_outb(ahc, port, (value) & 0xFF);
331 ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF);
332 ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF);
333 ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF);
334 }
335
336 static __inline uint64_t
337 ahc_inq(struct ahc_softc *ahc, u_int port)
338 {
339 return ((ahc_inb(ahc, port))
340 | (ahc_inb(ahc, port+1) << 8)
341 | (ahc_inb(ahc, port+2) << 16)
342 | (ahc_inb(ahc, port+3) << 24)
343 | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
344 | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
345 | (((uint64_t)ahc_inb(ahc, port+6)) << 48)
346 | (((uint64_t)ahc_inb(ahc, port+7)) << 56));
347 }
348
349 static __inline void
350 ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value)
351 {
352 ahc_outb(ahc, port, value & 0xFF);
353 ahc_outb(ahc, port+1, (value >> 8) & 0xFF);
354 ahc_outb(ahc, port+2, (value >> 16) & 0xFF);
355 ahc_outb(ahc, port+3, (value >> 24) & 0xFF);
356 ahc_outb(ahc, port+4, (value >> 32) & 0xFF);
357 ahc_outb(ahc, port+5, (value >> 40) & 0xFF);
358 ahc_outb(ahc, port+6, (value >> 48) & 0xFF);
359 ahc_outb(ahc, port+7, (value >> 56) & 0xFF);
360 }
361
362 /*
363 * Get a free scb. If there are none, see if we can allocate a new SCB.
364 */
365 static __inline struct scb *
366 ahc_get_scb(struct ahc_softc *ahc)
367 {
368 struct scb *scb;
369
370 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL)
371 return (NULL);
372 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle);
373 return (scb);
374 }
375
376 /*
377 * Return an SCB resource to the free list.
378 */
379 static __inline void
380 ahc_free_scb(struct ahc_softc *ahc, struct scb *scb)
381 {
382 struct hardware_scb *hscb;
383
384 hscb = scb->hscb;
385 /* Clean up for the next user */
386 ahc->scb_data->scbindex[hscb->tag] = NULL;
387 scb->flags = SCB_FREE;
388 hscb->control = 0;
389
390 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle);
391
392 /* Notify the OSM that a resource is now available. */
393 ahc_platform_scb_free(ahc, scb);
394 }
395
396 static __inline struct scb *
397 ahc_lookup_scb(struct ahc_softc *ahc, u_int tag)
398 {
399 struct scb* scb;
400
401 scb = ahc->scb_data->scbindex[tag];
402 if (scb != NULL)
403 ahc_sync_scb(ahc, scb,
404 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
405 return (scb);
406 }
407
408 static __inline void
409 ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb)
410 {
411 struct hardware_scb *q_hscb;
412 u_int saved_tag;
413
414 /*
415 * Our queuing method is a bit tricky. The card
416 * knows in advance which HSCB to download, and we
417 * can't disappoint it. To achieve this, the next
418 * SCB to download is saved off in ahc->next_queued_scb.
419 * When we are called to queue "an arbitrary scb",
420 * we copy the contents of the incoming HSCB to the one
421 * the sequencer knows about, swap HSCB pointers and
422 * finally assign the SCB to the tag indexed location
423 * in the scb_array. This makes sure that we can still
424 * locate the correct SCB by SCB_TAG.
425 */
426 q_hscb = ahc->next_queued_scb->hscb;
427 saved_tag = q_hscb->tag;
428 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb));
429 if ((scb->flags & SCB_CDB32_PTR) != 0) {
430 q_hscb->shared_data.cdb_ptr =
431 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag)
432 + offsetof(struct hardware_scb, cdb32));
433 }
434 q_hscb->tag = saved_tag;
435 q_hscb->next = scb->hscb->tag;
436
437 /* Now swap HSCB pointers. */
438 ahc->next_queued_scb->hscb = scb->hscb;
439 scb->hscb = q_hscb;
440
441 /* Now define the mapping from tag to SCB in the scbindex */
442 ahc->scb_data->scbindex[scb->hscb->tag] = scb;
443 }
444
445 /*
446 * Tell the sequencer about a new transaction to execute.
447 */
448 static __inline void
449 ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb)
450 {
451 ahc_swap_with_next_hscb(ahc, scb);
452
453 if (scb->hscb->tag == SCB_LIST_NULL
454 || scb->hscb->next == SCB_LIST_NULL)
455 panic("Attempt to queue invalid SCB tag %x:%x\n",
456 scb->hscb->tag, scb->hscb->next);
457 /*
458 * Keep a history of SCBs we've downloaded in the qinfifo.
459 */
460 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
461
462 /*
463 * Make sure our data is consistent from the
464 * perspective of the adapter.
465 */
466 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
467
468 /* Tell the adapter about the newly queued SCB */
469 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
470 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
471 } else {
472 if ((ahc->features & AHC_AUTOPAUSE) == 0)
473 ahc_pause(ahc);
474 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
475 if ((ahc->features & AHC_AUTOPAUSE) == 0)
476 ahc_unpause(ahc);
477 }
478 }
479
480 static __inline struct scsipi_sense_data *
481 ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb)
482 {
483 int offset;
484
485 offset = scb - ahc->scb_data->scbarray;
486 return (&ahc->scb_data->sense[offset]);
487 }
488
489 static __inline uint32_t
490 ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb)
491 {
492 int offset;
493
494 offset = scb - ahc->scb_data->scbarray;
495 return (ahc->scb_data->sense_busaddr
496 + (offset * sizeof(struct scsipi_sense_data)));
497 }
498
499 /************************** Interrupt Processing ******************************/
500 static __inline void ahc_sync_qoutfifo(struct ahc_softc *ahc, int op);
501 static __inline void ahc_sync_tqinfifo(struct ahc_softc *ahc, int op);
502 static __inline u_int ahc_check_cmdcmpltqueues(struct ahc_softc *ahc);
503 static __inline int ahc_intr(void *arg);
504 static __inline void ahc_minphys(struct buf *bp);
505
506 static __inline void
507 ahc_minphys(bp)
508 struct buf *bp;
509 {
510 /*
511 * Even though the card can transfer up to 16megs per command
512 * we are limited by the number of segments in the DMA segment
513 * list that we can hold. The worst case is that all pages are
514 * discontinuous physically, hence the "page per segment" limit
515 * enforced here.
516 */
517 if (bp->b_bcount > AHC_MAXTRANSFER_SIZE) {
518 bp->b_bcount = AHC_MAXTRANSFER_SIZE;
519 }
520 minphys(bp);
521 }
522
523 static __inline void
524 ahc_sync_qoutfifo(struct ahc_softc *ahc, int op)
525 {
526 ahc_dmamap_sync(ahc, ahc->parent_dmat, ahc->shared_data_dmamap,
527 /*offset*/0, /*len*/256, op);
528 }
529
530 static __inline void
531 ahc_sync_tqinfifo(struct ahc_softc *ahc, int op)
532 {
533 #ifdef AHC_TARGET_MODE
534 if ((ahc->flags & AHC_TARGETROLE) != 0) {
535 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
536 ahc->shared_data_dmamap,
537 ahc_targetcmd_offset(ahc, 0),
538 sizeof(struct target_cmd) * AHC_TMODE_CMDS,
539 op);
540 }
541 #endif
542 }
543
544 /*
545 * See if the firmware has posted any completed commands
546 * into our in-core command complete fifos.
547 */
548 #define AHC_RUN_QOUTFIFO 0x1
549 #define AHC_RUN_TQINFIFO 0x2
550 static __inline u_int
551 ahc_check_cmdcmpltqueues(struct ahc_softc *ahc)
552 {
553 u_int retval;
554
555 retval = 0;
556 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/, ahc->shared_data_dmamap,
557 /*offset*/ahc->qoutfifonext, /*len*/1,
558 BUS_DMASYNC_POSTREAD);
559 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL)
560 retval |= AHC_RUN_QOUTFIFO;
561 #ifdef AHC_TARGET_MODE
562 if ((ahc->flags & AHC_TARGETROLE) != 0
563 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) {
564 ahc_dmamap_sync(ahc, ahc->parent_dmat /*shared_data_dmat*/,
565 ahc->shared_data_dmamap,
566 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
567 /*len*/sizeof(struct target_cmd),
568 BUS_DMASYNC_POSTREAD);
569 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0)
570 retval |= AHC_RUN_TQINFIFO;
571 }
572 #endif
573 return (retval);
574 }
575
576 /*
577 * Catch an interrupt from the adapter
578 */
579 static __inline int
580 ahc_intr(void *arg)
581 {
582 struct ahc_softc *ahc = (struct ahc_softc*)arg;
583 u_int intstat;
584
585 if ((ahc->pause & INTEN) == 0) {
586 /*
587 * Our interrupt is not enabled on the chip
588 * and may be disabled for re-entrancy reasons,
589 * so just return. This is likely just a shared
590 * interrupt.
591 */
592 return 1;
593 }
594 /*
595 * Instead of directly reading the interrupt status register,
596 * infer the cause of the interrupt by checking our in-core
597 * completion queues. This avoids a costly PCI bus read in
598 * most cases.
599 */
600 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0
601 && (ahc_check_cmdcmpltqueues(ahc) != 0))
602 intstat = CMDCMPLT;
603 else {
604 intstat = ahc_inb(ahc, INTSTAT);
605 }
606
607 if (intstat & CMDCMPLT) {
608 ahc_outb(ahc, CLRINT, CLRCMDINT);
609 /*
610 * Ensure that the chip sees that we've cleared
611 * this interrupt before we walk the output fifo.
612 * Otherwise, we may, due to posted bus writes,
613 * clear the interrupt after we finish the scan,
614 * and after the sequencer has added new entries
615 * and asserted the interrupt again.
616 */
617 ahc_flush_device_writes(ahc);
618 scsipi_channel_freeze(ahc->channel == 'A' ? &ahc->sc_channel : &ahc->sc_channel_b, 1);
619 ahc_run_qoutfifo(ahc);
620 scsipi_channel_thaw(ahc->channel == 'A' ? &ahc->sc_channel : &ahc->sc_channel_b, 1);
621 #ifdef AHC_TARGET_MODE
622 if ((ahc->flags & AHC_TARGETROLE) != 0)
623 ahc_run_tqinfifo(ahc, /*paused*/FALSE);
624 #endif
625 }
626
627 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0)
628 /* Hot eject */
629 return 1;
630
631 if ((intstat & INT_PEND) == 0) {
632 #if AHC_PCI_CONFIG > 0
633 if (ahc->unsolicited_ints > 500) {
634 ahc->unsolicited_ints = 0;
635 if ((ahc->chip & AHC_PCI) != 0
636 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0)
637 ahc->bus_intr(ahc);
638 }
639 #endif
640 ahc->unsolicited_ints++;
641 return 1;
642 }
643 ahc->unsolicited_ints = 0;
644
645 if (intstat & BRKADRINT) {
646 ahc_handle_brkadrint(ahc);
647 /* Fatal error, no more interrupts to handle. */
648 return 1;
649 }
650
651 if ((intstat & (SEQINT|SCSIINT)) != 0)
652 ahc_pause_bug_fix(ahc);
653
654 if ((intstat & SEQINT) != 0)
655 ahc_handle_seqint(ahc, intstat);
656
657 if ((intstat & SCSIINT) != 0)
658 ahc_handle_scsiint(ahc, intstat);
659
660 return 1;
661 }
662
663 #endif /* _AIC7XXX_INLINE_H_ */
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