1 /*
2 * Core definitions and data structures shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: aic7xxxvar.h,v 1.43.2.1 2005/12/16 20:06:01 jmc Exp $
41 *
42 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.h,v 1.44 2003/01/20 20:44:55 gibbs Exp $
43 */
44 /*
45 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
46 */
47
48 #ifndef _AIC7XXXVAR_H_
49 #define _AIC7XXXVAR_H_
50
51 #undef AHC_DEBUG
52
53 /* Register Definitions */
54 #include <dev/microcode/aic7xxx/aic7xxx_reg.h>
55
56 #include <dev/ic/aic7xxx_cam.h>
57
58 #define AIC_OP_OR 0x0
59 #define AIC_OP_AND 0x1
60 #define AIC_OP_XOR 0x2
61 #define AIC_OP_ADD 0x3
62 #define AIC_OP_ADC 0x4
63 #define AIC_OP_ROL 0x5
64 #define AIC_OP_BMOV 0x6
65
66 #define AIC_OP_JMP 0x8
67 #define AIC_OP_JC 0x9
68 #define AIC_OP_JNC 0xa
69 #define AIC_OP_CALL 0xb
70 #define AIC_OP_JNE 0xc
71 #define AIC_OP_JNZ 0xd
72 #define AIC_OP_JE 0xe
73 #define AIC_OP_JZ 0xf
74
75 /* Pseudo Ops */
76 #define AIC_OP_SHL 0x10
77 #define AIC_OP_SHR 0x20
78 #define AIC_OP_ROR 0x30
79
80 struct ins_format1 {
81 #if BYTE_ORDER == LITTLE_ENDIAN
82 uint32_t immediate : 8,
83 source : 9,
84 destination : 9,
85 ret : 1,
86 opcode : 4,
87 parity : 1;
88 #else
89 uint32_t parity : 1,
90 opcode : 4,
91 ret : 1,
92 destination : 9,
93 source : 9,
94 immediate : 8;
95 #endif
96 };
97
98 struct ins_format2 {
99 #if BYTE_ORDER == LITTLE_ENDIAN
100 uint32_t shift_control : 8,
101 source : 9,
102 destination : 9,
103 ret : 1,
104 opcode : 4,
105 parity : 1;
106 #else
107 uint32_t parity : 1,
108 opcode : 4,
109 ret : 1,
110 destination : 9,
111 source : 9,
112 shift_control : 8;
113 #endif
114 };
115
116 struct ins_format3 {
117 #if BYTE_ORDER == LITTLE_ENDIAN
118 uint32_t immediate : 8,
119 source : 9,
120 address : 10,
121 opcode : 4,
122 parity : 1;
123 #else
124 uint32_t parity : 1,
125 opcode : 4,
126 address : 10,
127 source : 9,
128 immediate : 8;
129 #endif
130 };
131
132 union ins_formats {
133 struct ins_format1 format1;
134 struct ins_format2 format2;
135 struct ins_format3 format3;
136 uint8_t bytes[4];
137 uint32_t integer;
138 };
139
140 /************************* Forward Declarations *******************************/
141 struct ahc_platform_data;
142 struct scb_platform_data;
143 struct seeprom_descriptor;
144
145 /****************************** Useful Macros *********************************/
146 #ifndef MAX
147 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
148 #endif
149
150 #ifndef MIN
151 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
152 #endif
153
154 #ifndef TRUE
155 #define TRUE 1
156 #endif
157 #ifndef FALSE
158 #define FALSE 0
159 #endif
160
161 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
162
163 #define ALL_CHANNELS '\0'
164 #define ALL_TARGETS_MASK 0xFFFF
165 #define INITIATOR_WILDCARD (~0)
166
167 #define SCSIID_TARGET(ahc, scsiid) \
168 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
169 >> TID_SHIFT)
170 #define SCSIID_OUR_ID(scsiid) \
171 ((scsiid) & OID)
172 #define SCSIID_CHANNEL(ahc, scsiid) \
173 ((((ahc)->features & AHC_TWIN) != 0) \
174 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
175 : 'A')
176 #define SCB_IS_SCSIBUS_B(ahc, scb) \
177 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
178 #define SCB_GET_OUR_ID(scb) \
179 SCSIID_OUR_ID((scb)->hscb->scsiid)
180 #define SCB_GET_TARGET(ahc, scb) \
181 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
182 #define SCB_GET_CHANNEL(ahc, scb) \
183 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
184 #define SCB_GET_LUN(scb) \
185 ((scb)->hscb->lun)
186 #define SCB_GET_TARGET_OFFSET(ahc, scb) \
187 (SCB_GET_TARGET(ahc, scb))
188 #define SCB_GET_TARGET_MASK(ahc, scb) \
189 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
190 #ifdef AHC_DEBUG
191 #define SCB_IS_SILENT(scb) \
192 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
193 && (((scb)->flags & SCB_SILENT) != 0))
194 #else
195 #define SCB_IS_SILENT(scb) \
196 (((scb)->flags & SCB_SILENT) != 0)
197 #endif
198 #define TCL_TARGET_OFFSET(tcl) \
199 ((((tcl) >> 4) & TID) >> 4)
200 #define TCL_LUN(tcl) \
201 (tcl & (AHC_NUM_LUNS - 1))
202 #define BUILD_TCL(scsiid, lun) \
203 ((lun) | (((scsiid) & TID) << 4))
204
205 #ifndef AHC_TARGET_MODE
206 #undef AHC_TMODE_ENABLE
207 #define AHC_TMODE_ENABLE 0
208 #endif
209
210 /**************************** Driver Constants ********************************/
211 /*
212 * The maximum number of supported targets.
213 */
214 #define AHC_NUM_TARGETS 16
215
216 /*
217 * The maximum number of supported luns.
218 * The identify message only supports 64 luns in SPI3.
219 * You can have 2^64 luns when information unit transfers are enabled,
220 * but it is doubtful this driver will ever support IUTs.
221 */
222 #define AHC_NUM_LUNS 64
223
224 /*
225 * The maximum transfer per S/G segment.
226 * Limited by MAXPHYS or a 24-bit counter.
227 */
228 #define AHC_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff)
229
230 /*
231 * The maximum amount of SCB storage in hardware on a controller.
232 * This value represents an upper bound. Controllers vary in the number
233 * they actually support.
234 */
235 #define AHC_SCB_MAX 255
236
237 /*
238 * The maximum number of concurrent transactions supported per driver instance.
239 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
240 * the space for SCBs on the host adapter varies by model, the driver will
241 * page the SCBs between host and controller memory as needed. We are limited
242 * to 253 because:
243 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
244 * 2) We reserve one value, 255, to represent the invalid element.
245 * 3) Our input queue scheme requires one SCB to always be reserved
246 * in advance of queuing any SCBs. This takes us down to 254.
247 * 4) To handle our output queue correctly on machines that only
248 * support 32bit stores, we must clear the array 4 bytes at a
249 * time. To avoid colliding with a DMA write from the sequencer,
250 * we must be sure that 4 slots are empty when we write to clear
251 * the queue. This reduces us to 253 SCBs: 1 that just completed
252 * and the known three additional empty slots in the queue that
253 * precede it.
254 */
255 #define AHC_MAX_QUEUE 253
256
257 /*
258 * The maximum amount of SCB storage we allocate in host memory. This
259 * number should reflect the 1 additional SCB we require to handle our
260 * qinfifo mechanism.
261 */
262 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
263
264 /*
265 * Ring Buffer of incoming target commands.
266 * We allocate 256 to simplify the logic in the sequencer
267 * by using the natural wrap point of an 8bit counter.
268 */
269 #define AHC_TMODE_CMDS 256
270
271 /* Reset line assertion time in us */
272 #define AHC_BUSRESET_DELAY 25
273
274 /******************* Chip Characteristics/Operating Settings *****************/
275 /*
276 * Chip Type
277 * The chip order is from least sophisticated to most sophisticated.
278 */
279 typedef enum {
280 AHC_NONE = 0x0000,
281 AHC_CHIPID_MASK = 0x00FF,
282 AHC_AIC7770 = 0x0001,
283 AHC_AIC7850 = 0x0002,
284 AHC_AIC7855 = 0x0003,
285 AHC_AIC7859 = 0x0004,
286 AHC_AIC7860 = 0x0005,
287 AHC_AIC7870 = 0x0006,
288 AHC_AIC7880 = 0x0007,
289 AHC_AIC7895 = 0x0008,
290 AHC_AIC7895C = 0x0009,
291 AHC_AIC7890 = 0x000a,
292 AHC_AIC7896 = 0x000b,
293 AHC_AIC7892 = 0x000c,
294 AHC_AIC7899 = 0x000d,
295 AHC_VL = 0x0100, /* Bus type VL */
296 AHC_EISA = 0x0200, /* Bus type EISA */
297 AHC_PCI = 0x0400, /* Bus type PCI */
298 AHC_BUS_MASK = 0x0F00
299 } ahc_chip;
300
301 /*
302 * Features available in each chip type.
303 */
304 typedef enum {
305 AHC_FENONE = 0x00000,
306 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
307 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
308 AHC_WIDE = 0x00004, /* Wide Channel */
309 AHC_TWIN = 0x00008, /* Twin Channel */
310 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
311 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
312 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
313 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
314 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
315 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
316 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
317 AHC_DT = 0x00800, /* Double Transition transfers */
318 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
319 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
320 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
321 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
322 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
323 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
324 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
325 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
326 AHC_AIC7770_FE = AHC_FENONE,
327 /*
328 * The real 7850 does not support Ultra modes, but there are
329 * several cards that use the generic 7850 PCI ID even though
330 * they are using an Ultra capable chip (7859/7860). We start
331 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
332 * register to determine if the capability is really present.
333 */
334 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
335 AHC_AIC7860_FE = AHC_AIC7850_FE,
336 AHC_AIC7870_FE = AHC_TARGETMODE,
337 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
338 /*
339 * Although we have space for both the initiator and
340 * target roles on ULTRA2 chips, we currently disable
341 * the initiator role to allow multi-scsi-id target mode
342 * configurations. We can only respond on the same SCSI
343 * ID as our initiator role if we allow initiator operation.
344 * At some point, we should add a configuration knob to
345 * allow both roles to be loaded.
346 */
347 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
348 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
349 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
350 |AHC_TARGETMODE,
351 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
352 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
353 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
354 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
355 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
356 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
357 } ahc_feature;
358
359 /*
360 * Bugs in the silicon that we work around in software.
361 */
362 typedef enum {
363 AHC_BUGNONE = 0x00,
364 /*
365 * On all chips prior to the U2 product line,
366 * the WIDEODD S/G segment feature does not
367 * work during scsi->HostBus transfers.
368 */
369 AHC_TMODE_WIDEODD_BUG = 0x01,
370 /*
371 * On the aic7890/91 Rev 0 chips, the autoflush
372 * feature does not work. A manual flush of
373 * the DMA FIFO is required.
374 */
375 AHC_AUTOFLUSH_BUG = 0x02,
376 /*
377 * On many chips, cacheline streaming does not work.
378 */
379 AHC_CACHETHEN_BUG = 0x04,
380 /*
381 * On the aic7896/97 chips, cacheline
382 * streaming must be enabled.
383 */
384 AHC_CACHETHEN_DIS_BUG = 0x08,
385 /*
386 * PCI 2.1 Retry failure on non-empty data fifo.
387 */
388 AHC_PCI_2_1_RETRY_BUG = 0x10,
389 /*
390 * Controller does not handle cacheline residuals
391 * properly on S/G segments if PCI MWI instructions
392 * are allowed.
393 */
394 AHC_PCI_MWI_BUG = 0x20,
395 /*
396 * An SCB upload using the SCB channel's
397 * auto array entry copy feature may
398 * corrupt data. This appears to only
399 * occur on 66MHz systems.
400 */
401 AHC_SCBCHAN_UPLOAD_BUG = 0x40
402 } ahc_bug;
403
404 /*
405 * Configuration specific settings.
406 * The driver determines these settings by probing the
407 * chip/controller's configuration.
408 */
409 typedef enum {
410 AHC_FNONE = 0x000,
411 AHC_PRIMARY_CHANNEL = 0x003, /*
412 * The channel that should
413 * be probed first.
414 */
415 AHC_USEDEFAULTS = 0x004, /*
416 * For cards without an seeprom
417 * or a BIOS to initialize the chip's
418 * SRAM, we use the default target
419 * settings.
420 */
421 AHC_SEQUENCER_DEBUG = 0x008,
422 AHC_SHARED_SRAM = 0x010,
423 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
424 AHC_RESET_BUS_A = 0x040,
425 AHC_RESET_BUS_B = 0x080,
426 AHC_EXTENDED_TRANS_A = 0x100,
427 AHC_EXTENDED_TRANS_B = 0x200,
428 AHC_TERM_ENB_A = 0x400,
429 AHC_TERM_ENB_B = 0x800,
430 AHC_INITIATORROLE = 0x1000, /*
431 * Allow initiator operations on
432 * this controller.
433 */
434 AHC_TARGETROLE = 0x2000, /*
435 * Allow target operations on this
436 * controller.
437 */
438 AHC_NEWEEPROM_FMT = 0x4000,
439 AHC_RESOURCE_SHORTAGE = 0x8000,
440 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
441 AHC_INT50_SPEEDFLEX = 0x20000, /*
442 * Internal 50pin connector
443 * sits behind an aic3860
444 */
445 AHC_SCB_BTT = 0x40000, /*
446 * The busy targets table is
447 * stored in SCB space rather
448 * than SRAM.
449 */
450 AHC_BIOS_ENABLED = 0x80000,
451 AHC_ALL_INTERRUPTS = 0x100000,
452 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
453 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
454 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
455 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
456 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
457 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
458 AHC_DISABLE_PCI_PERR = 0x10000000
459 } ahc_flag;
460
461 /************************* Hardware SCB Definition ***************************/
462
463 /*
464 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
465 * consists of a "hardware SCB" mirroring the fields available on the card
466 * and additional information the kernel stores for each transaction.
467 *
468 * To minimize space utilization, a portion of the hardware scb stores
469 * different data during different portions of a SCSI transaction.
470 * As initialized by the host driver for the initiator role, this area
471 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
472 * the cdb has been presented to the target, this area serves to store
473 * residual transfer information and the SCSI status byte.
474 * For the target role, the contents of this area do not change, but
475 * still serve a different purpose than for the initiator role. See
476 * struct target_data for details.
477 */
478
479 /*
480 * Status information embedded in the shared portion of
481 * an SCB after passing the cdb to the target. The kernel
482 * driver will only read this data for transactions that
483 * complete abnormally (non-zero status byte).
484 */
485 struct status_pkt {
486 uint32_t residual_datacnt; /* Residual in the current S/G seg */
487 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
488 uint8_t scsi_status; /* Standard SCSI status byte */
489 };
490
491 /*
492 * Target mode version of the shared data SCB segment.
493 */
494 struct target_data {
495 uint32_t residual_datacnt; /* Residual in the current S/G seg */
496 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
497 uint8_t scsi_status; /* SCSI status to give to initiator */
498 uint8_t target_phases; /* Bitmap of phases to execute */
499 uint8_t data_phase; /* Data-In or Data-Out */
500 uint8_t initiator_tag; /* Initiator's transaction tag */
501 };
502
503 struct hardware_scb {
504 /**/ union {
505 /*
506 * If the cdb is 12 bytes or less, we embed it directly
507 * in the SCB. For longer cdbs, we embed the address
508 * of the cdb payload as seen by the chip and a DMA
509 * is used to pull it in.
510 */
511 uint8_t cdb[12];
512 uint32_t cdb_ptr;
513 struct status_pkt status;
514 struct target_data tdata;
515 } shared_data;
516 /*
517 * A word about residuals.
518 * The scb is presented to the sequencer with the dataptr and datacnt
519 * fields initialized to the contents of the first S/G element to
520 * transfer. The sgptr field is initialized to the bus address for
521 * the S/G element that follows the first in the in core S/G array
522 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
523 * S/G entry for this transfer (single S/G element transfer with the
524 * first elements address and length preloaded in the dataptr/datacnt
525 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
526 * The SG_FULL_RESID flag ensures that the residual will be correctly
527 * noted even if no data transfers occur. Once the data phase is entered,
528 * the residual sgptr and datacnt are loaded from the sgptr and the
529 * datacnt fields. After each S/G element's dataptr and length are
530 * loaded into the hardware, the residual sgptr is advanced. After
531 * each S/G element is expired, its datacnt field is checked to see
532 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
533 * residual sg ptr and the transfer is considered complete. If the
534 * sequencer determines that there is a residual in the transfer, it
535 * will set the SG_RESID_VALID flag in sgptr and DMA the scb back into
536 * host memory. To summarize:
537 *
538 * Sequencer:
539 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
540 * or residual_sgptr does not have SG_LIST_NULL set.
541 *
542 * o We are transfering the last segment if residual_datacnt has
543 * the SG_LAST_SEG flag set.
544 *
545 * Host:
546 * o A residual has occurred if a completed scb has the
547 * SG_RESID_VALID flag set.
548 *
549 * o residual_sgptr and sgptr refer to the "next" sg entry
550 * and so may point beyond the last valid sg entry for the
551 * transfer.
552 */
553 /*12*/ uint32_t dataptr;
554 /*16*/ uint32_t datacnt; /*
555 * Byte 3 (numbered from 0) of
556 * the datacnt is really the
557 * 4th byte in that data address.
558 */
559 /*20*/ uint32_t sgptr;
560 #define SG_PTR_MASK 0xFFFFFFF8
561 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
562 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
563 /*26*/ uint8_t lun;
564 /*27*/ uint8_t tag; /*
565 * Index into our kernel SCB array.
566 * Also used as the tag for tagged I/O
567 */
568 /*28*/ uint8_t cdb_len;
569 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
570 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
571 /*31*/ uint8_t next; /*
572 * Used for threading SCBs in the
573 * "Waiting for Selection" and
574 * "Disconnected SCB" lists down
575 * in the sequencer.
576 */
577 /*32*/ uint8_t cdb32[32]; /*
578 * CDB storage for cdbs of size
579 * 13->32. We store them here
580 * because hardware scbs are
581 * allocated from DMA safe
582 * memory so we are guaranteed
583 * the controller can access
584 * this data.
585 */
586 };
587
588 /************************ Kernel SCB Definitions ******************************/
589 /*
590 * Some fields of the SCB are OS dependent. Here we collect the
591 * definitions for elements that all OS platforms need to include
592 * in there SCB definition.
593 */
594
595 /*
596 * Definition of a scatter/gather element as transferred to the controller.
597 * The aic7xxx chips only support a 24bit length. We use the top byte of
598 * the length to store additional address bits and a flag to indicate
599 * that a given segment terminates the transfer. This gives us an
600 * addressable range of 512GB on machines with 64bit PCI or with chips
601 * that can support dual address cycles on 32bit PCI busses.
602 */
603 struct ahc_dma_seg {
604 uint32_t addr;
605 uint32_t len;
606 #define AHC_DMA_LAST_SEG 0x80000000
607 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000
608 #define AHC_SG_LEN_MASK 0x00FFFFFF
609 };
610
611 struct sg_map_node {
612 bus_dmamap_t sg_dmamap;
613 bus_addr_t sg_physaddr;
614 bus_dma_segment_t sg_dmasegs;
615 int sg_nseg;
616 struct ahc_dma_seg* sg_vaddr;
617 SLIST_ENTRY(sg_map_node) links;
618 };
619
620 struct ahc_pci_busdata {
621 pci_chipset_tag_t pc;
622 pcitag_t tag;
623 u_int dev;
624 u_int func;
625 pcireg_t class;
626 };
627
628 /*
629 * The current state of this SCB.
630 */
631 typedef enum {
632 SCB_FREE = 0x0000,
633 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
634 * Another device was active
635 * during the first timeout for
636 * this SCB so we gave ourselves
637 * an additional timeout period
638 * in case it was hogging the
639 * bus.
640 */
641 SCB_DEVICE_RESET = 0x0004,
642 SCB_SENSE = 0x0008,
643 SCB_CDB32_PTR = 0x0010,
644 SCB_RECOVERY_SCB = 0x0020,
645 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
646 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
647 SCB_ABORT = 0x0100,
648 SCB_UNTAGGEDQ = 0x0200,
649 SCB_ACTIVE = 0x0400,
650 SCB_TARGET_IMMEDIATE = 0x0800,
651 SCB_TRANSMISSION_ERROR = 0x1000,/*
652 * We detected a parity or CRC
653 * error that has effected the
654 * payload of the command. This
655 * flag is checked when normal
656 * status is returned to catch
657 * the case of a target not
658 * responding to our attempt
659 * to report the error.
660 */
661 SCB_TARGET_SCB = 0x2000,
662 SCB_SILENT = 0x4000,/*
663 * Be quiet about transmission type
664 * errors. They are expected and we
665 * don't want to upset the user. This
666 * flag is typically used during DV.
667 */
668 SCB_FREEZE_QUEUE = 0x8000
669 } scb_flag;
670
671 struct scb {
672 struct hardware_scb *hscb;
673 union {
674 SLIST_ENTRY(scb) sle;
675 TAILQ_ENTRY(scb) tqe;
676 } links;
677 LIST_ENTRY(scb) pending_links;
678
679 struct scsipi_xfer *xs;
680 struct ahc_softc *ahc_softc;
681 scb_flag flags;
682 #ifndef __linux__
683 bus_dmamap_t dmamap;
684 #endif
685 struct scb_platform_data *platform_data;
686 struct sg_map_node *sg_map;
687 struct ahc_dma_seg *sg_list;
688 bus_addr_t sg_list_phys;
689 u_int sg_count;/* How full ahc_dma_seg is */
690 };
691
692 struct scb_data {
693 SLIST_HEAD(, scb) free_scbs; /*
694 * Pool of SCBs ready to be assigned
695 * commands to execute.
696 */
697 struct scb *scbindex[256]; /*
698 * Mapping from tag to SCB.
699 * As tag identifiers are an
700 * 8bit value, we provide space
701 * for all possible tag values.
702 * Any lookups to entries at or
703 * above AHC_SCB_MAX_ALLOC will
704 * always fail.
705 */
706 struct hardware_scb *hscbs; /* Array of hardware SCBs */
707 struct scb *scbarray; /* Array of kernel SCBs */
708 struct scsipi_sense_data *sense; /* Per SCB sense data */
709
710 /*
711 * "Bus" addresses of our data structures.
712 */
713 bus_dmamap_t hscb_dmamap;
714 bus_addr_t hscb_busaddr;
715 bus_dma_segment_t hscb_seg;
716 int hscb_nseg;
717 int hscb_size;
718
719 bus_dmamap_t sense_dmamap;
720 bus_addr_t sense_busaddr;
721 bus_dma_segment_t sense_seg;
722 int sense_nseg;
723 int sense_size;
724
725 SLIST_HEAD(, sg_map_node) sg_maps;
726 uint8_t numscbs;
727 uint8_t maxhscbs; /* Number of SCBs on the card */
728 uint8_t init_level; /*
729 * How far we've initialized
730 * this structure.
731 */
732 };
733
734 /************************ Target Mode Definitions *****************************/
735
736 /*
737 * Connection desciptor for select-in requests in target mode.
738 */
739 struct target_cmd {
740 uint8_t scsiid; /* Our ID and the initiator's ID */
741 uint8_t identify; /* Identify message */
742 uint8_t bytes[22]; /*
743 * Bytes contains any additional message
744 * bytes terminated by 0xFF. The remainder
745 * is the cdb to execute.
746 */
747 uint8_t cmd_valid; /*
748 * When a command is complete, the firmware
749 * will set cmd_valid to all bits set.
750 * After the host has seen the command,
751 * the bits are cleared. This allows us
752 * to just peek at host memory to determine
753 * if more work is complete. cmd_valid is on
754 * an 8 byte boundary to simplify setting
755 * it on aic7880 hardware which only has
756 * limited direct access to the DMA FIFO.
757 */
758 uint8_t pad[7];
759 };
760
761 /*
762 * Number of events we can buffer up if we run out
763 * of immediate notify ccbs.
764 */
765 #define AHC_TMODE_EVENT_BUFFER_SIZE 8
766 struct ahc_tmode_event {
767 uint8_t initiator_id;
768 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
769 #define EVENT_TYPE_BUS_RESET 0xFF
770 uint8_t event_arg;
771 };
772
773 /*
774 * Per enabled lun target mode state.
775 * As this state is directly influenced by the host OS'es target mode
776 * environment, we let the OS module define it. Forward declare the
777 * structure here so we can store arrays of them, etc. in OS neutral
778 * data structures.
779 */
780 #ifdef AHC_TARGET_MODE
781 struct ahc_tmode_lstate {
782 #if 0
783 struct cam_path *path;
784 struct ccb_hdr_slist accept_tios;
785 struct ccb_hdr_slist immed_notifies;
786 #endif
787 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
788 uint8_t event_r_idx;
789 uint8_t event_w_idx;
790 };
791 #else
792 struct ahc_tmode_lstate;
793 #endif
794
795 /******************** Transfer Negotiation Datastructures *********************/
796 #define AHC_TRANS_CUR 0x01 /* Modify current negotiation status */
797 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
798 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
799 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
800
801 #define AHC_WIDTH_UNKNOWN 0xFF
802 #define AHC_PERIOD_UNKNOWN 0xFF
803 #define AHC_OFFSET_UNKNOWN 0x0
804 #define AHC_PPR_OPTS_UNKNOWN 0xFF
805
806 /*
807 * Transfer Negotiation Information.
808 */
809 struct ahc_transinfo {
810 uint8_t protocol_version; /* SCSI Revision level */
811 uint8_t transport_version; /* SPI Revision level */
812 uint8_t width; /* Bus width */
813 uint8_t period; /* Sync rate factor */
814 uint8_t offset; /* Sync offset */
815 uint8_t ppr_options; /* Parallel Protocol Request options */
816 };
817
818 /*
819 * Per-initiator current, goal and user transfer negotiation information. */
820 struct ahc_initiator_tinfo {
821 uint8_t scsirate; /* Computed value for SCSIRATE reg */
822 struct ahc_transinfo curr;
823 struct ahc_transinfo goal;
824 struct ahc_transinfo user;
825 };
826
827 /*
828 * Per enabled target ID state.
829 * Pointers to lun target state as well as sync/wide negotiation information
830 * for each initiator<->target mapping. For the initiator role we pretend
831 * that we are the target and the targets are the initiators since the
832 * negotiation is the same regardless of role.
833 */
834 struct ahc_tmode_tstate {
835 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
836 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
837
838 /*
839 * Per initiator state bitmasks.
840 */
841 uint16_t auto_negotiate;/* Auto Negotiation Required */
842 uint16_t ultraenb; /* Using ultra sync rate */
843 uint16_t discenable; /* Disconnection allowed */
844 uint16_t tagenable; /* Tagged Queuing allowed */
845 };
846
847 /*
848 * Data structure for our table of allowed synchronous transfer rates.
849 */
850 struct ahc_syncrate {
851 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
852 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
853 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
854 #define ST_SXFR 0x010 /* Rate Single Transition Only */
855 #define DT_SXFR 0x040 /* Rate Double Transition Only */
856 uint8_t period; /* Period to send to SCSI target */
857 char *rate;
858 };
859
860 /* Safe and valid period for async negotiations. */
861 #define AHC_ASYNC_XFER_PERIOD 0x45
862 #define AHC_ULTRA2_XFER_PERIOD 0x0a
863
864 /*
865 * Indexes into our table of syncronous transfer rates.
866 */
867 #define AHC_SYNCRATE_DT 0
868 #define AHC_SYNCRATE_ULTRA2 1
869 #define AHC_SYNCRATE_ULTRA 3
870 #define AHC_SYNCRATE_FAST 6
871 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
872 #define AHC_SYNCRATE_MIN 13
873
874 /***************************** Lookup Tables **********************************/
875 /*
876 * Phase -> name and message out response
877 * to parity errors in each phase table.
878 */
879 struct ahc_phase_table_entry {
880 uint8_t phase;
881 uint8_t mesg_out; /* Message response to parity errors */
882 char *phasemsg;
883 };
884
885 /************************** Serial EEPROM Format ******************************/
886
887 struct seeprom_config {
888 /*
889 * Per SCSI ID Configuration Flags
890 */
891 uint16_t device_flags[16]; /* words 0-15 */
892 #define CFXFER 0x0007 /* synchronous transfer rate */
893 #define CFSYNCH 0x0008 /* enable synchronous transfer */
894 #define CFDISC 0x0010 /* enable disconnection */
895 #define CFWIDEB 0x0020 /* wide bus device */
896 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
897 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
898 #define CFSTART 0x0100 /* send start unit SCSI command */
899 #define CFINCBIOS 0x0200 /* include in BIOS scan */
900 #define CFRNFOUND 0x0400 /* report even if not found */
901 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
902 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
903 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
904
905 /*
906 * BIOS Control Bits
907 */
908 uint16_t bios_control; /* word 16 */
909 #define CFSUPREM 0x0001 /* support all removeable drives */
910 #define CFSUPREMB 0x0002 /* support removeable boot drives */
911 #define CFBIOSEN 0x0004 /* BIOS enabled */
912 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
913 #define CFSM2DRV 0x0010 /* support more than two drives */
914 #define CFSTPWLEVEL 0x0010 /* Termination level control */
915 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
916 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
917 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
918 #define CFEXTEND 0x0080 /* extended translation enabled */
919 #define CFSCAMEN 0x0100 /* SCAM enable */
920 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
921 #define CFMSG_VERBOSE 0x0000
922 #define CFMSG_SILENT 0x0200
923 #define CFMSG_DIAG 0x0400
924 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
925 /* UNUSED 0xff00 */
926
927 /*
928 * Host Adapter Control Bits
929 */
930 uint16_t adapter_control; /* word 17 */
931 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
932 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
933 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
934 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
935 #define CFSTERM 0x0004 /* SCSI low byte termination */
936 #define CFWSTERM 0x0008 /* SCSI high byte termination */
937 #define CFSPARITY 0x0010 /* SCSI parity */
938 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
939 #define CFMULTILUN 0x0020
940 #define CFRESETB 0x0040 /* reset SCSI bus at boot */
941 #define CFCLUSTERENB 0x0080 /* Cluster Enable */
942 #define CFBOOTCHAN 0x0300 /* probe this channel first */
943 #define CFBOOTCHANSHIFT 8
944 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
945 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
946 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
947 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/
948
949 /*
950 * Bus Release Time, Host Adapter ID
951 */
952 uint16_t brtime_id; /* word 18 */
953 #define CFSCSIID 0x000f /* host adapter SCSI ID */
954 /* UNUSED 0x00f0 */
955 #define CFBRTIME 0xff00 /* bus release time */
956
957 /*
958 * Maximum targets
959 */
960 uint16_t max_targets; /* word 19 */
961 #define CFMAXTARG 0x00ff /* maximum targets */
962 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
963 #define CFBOOTID 0xf000 /* Target to boot from */
964 uint16_t res_1[10]; /* words 20-29 */
965 uint16_t signature; /* Signature == 0x250 */
966 #define CFSIGNATURE 0x250
967 #define CFSIGNATURE2 0x300
968 uint16_t checksum; /* word 31 */
969 };
970
971 /**************************** Message Buffer *********************************/
972 typedef enum {
973 MSG_TYPE_NONE = 0x00,
974 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
975 MSG_TYPE_INITIATOR_MSGIN = 0x02,
976 MSG_TYPE_TARGET_MSGOUT = 0x03,
977 MSG_TYPE_TARGET_MSGIN = 0x04
978 } ahc_msg_type;
979
980 typedef enum {
981 MSGLOOP_IN_PROG,
982 MSGLOOP_MSGCOMPLETE,
983 MSGLOOP_TERMINATED
984 } msg_loop_stat;
985
986 /*********************** Software Configuration Structure *********************/
987 TAILQ_HEAD(scb_tailq, scb);
988
989 struct ahc_suspend_channel_state {
990 uint8_t scsiseq;
991 uint8_t sxfrctl0;
992 uint8_t sxfrctl1;
993 uint8_t simode0;
994 uint8_t simode1;
995 uint8_t seltimer;
996 uint8_t seqctl;
997 };
998
999 struct ahc_suspend_state {
1000 struct ahc_suspend_channel_state channel[2];
1001 uint8_t optionmode;
1002 uint8_t dscommand0;
1003 uint8_t dspcistatus;
1004 /* hsmailbox */
1005 uint8_t crccontrol1;
1006 uint8_t scbbaddr;
1007 /* Host and sequencer SCB counts */
1008 uint8_t dff_thrsh;
1009 uint8_t *scratch_ram;
1010 uint8_t *btt;
1011 };
1012
1013 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
1014 typedef void ahc_callback_t (void *);
1015
1016 struct ahc_softc {
1017 struct device sc_dev;
1018
1019 struct scsipi_channel sc_channel;
1020 struct scsipi_channel sc_channel_b;
1021 struct device * sc_child;
1022 struct device * sc_child_b;
1023 struct scsipi_adapter sc_adapter;
1024
1025 bus_space_tag_t tag;
1026 bus_space_handle_t bsh;
1027
1028 #ifndef __linux__
1029 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1030 #endif
1031 struct scb_data *scb_data;
1032
1033 struct scb *next_queued_scb;
1034
1035 /*
1036 * SCBs that have been sent to the controller
1037 */
1038 LIST_HEAD(, scb) pending_scbs;
1039
1040 /*
1041 * Counting lock for deferring the release of additional
1042 * untagged transactions from the untagged_queues. When
1043 * the lock is decremented to 0, all queues in the
1044 * untagged_queues array are run.
1045 */
1046 u_int untagged_queue_lock;
1047
1048 /*
1049 * Per-target queue of untagged-transactions. The
1050 * transaction at the head of the queue is the
1051 * currently pending untagged transaction for the
1052 * target. The driver only allows a single untagged
1053 * transaction per target.
1054 */
1055 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
1056
1057 /*
1058 * Platform specific data.
1059 */
1060 struct ahc_platform_data *platform_data;
1061
1062 /*
1063 * Platform specific device information.
1064 */
1065 /* ahc_dev_softc_t dev_softc; */
1066
1067 /*
1068 * Bus specific device information.
1069 */
1070 ahc_bus_intr_t bus_intr;
1071
1072 /*
1073 * Target mode related state kept on a per enabled lun basis.
1074 * Targets that are not enabled will have null entries.
1075 * As an initiator, we keep one target entry for our initiator
1076 * ID to store our sync/wide transfer settings.
1077 */
1078 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
1079
1080 char inited_target[AHC_NUM_TARGETS];
1081
1082 /*
1083 * The black hole device responsible for handling requests for
1084 * disabled luns on enabled targets.
1085 */
1086 struct ahc_tmode_lstate *black_hole;
1087
1088 /*
1089 * Device instance currently on the bus awaiting a continue TIO
1090 * for a command that was not given the disconnect priviledge.
1091 */
1092 struct ahc_tmode_lstate *pending_device;
1093
1094 /*
1095 * Card characteristics
1096 */
1097 ahc_chip chip;
1098 ahc_feature features;
1099 ahc_bug bugs;
1100 ahc_flag flags;
1101 struct seeprom_config *seep_config;
1102
1103 /* Values to store in the SEQCTL register for pause and unpause */
1104 uint8_t unpause;
1105 uint8_t pause;
1106
1107 /* Command Queues */
1108 uint8_t qoutfifonext;
1109 uint8_t qinfifonext;
1110 uint8_t *qoutfifo;
1111 uint8_t *qinfifo;
1112
1113 /* Critical Section Data */
1114 struct cs *critical_sections;
1115 u_int num_critical_sections;
1116
1117 /* Links for chaining softcs */
1118 TAILQ_ENTRY(ahc_softc) links;
1119
1120 /* Channel Names ('A', 'B', etc.) */
1121 char channel;
1122
1123 /* Initiator Bus ID */
1124 uint8_t our_id;
1125 uint8_t our_id_b;
1126
1127 /*
1128 * PCI error detection.
1129 */
1130 int unsolicited_ints;
1131
1132 /*
1133 * Target incoming command FIFO.
1134 */
1135 struct target_cmd *targetcmds;
1136 uint8_t tqinfifonext;
1137
1138 /*
1139 * Incoming and outgoing message handling.
1140 */
1141 uint8_t send_msg_perror;
1142 ahc_msg_type msg_type;
1143 uint8_t msgout_buf[12];/* Message we are sending */
1144 uint8_t msgin_buf[12];/* Message we are receiving */
1145 u_int msgout_len; /* Length of message to send */
1146 u_int msgout_index; /* Current index in msgout */
1147 u_int msgin_index; /* Current index in msgin */
1148
1149 /* Interrupt routine */
1150 void *ih;
1151
1152 /*
1153 * Mapping information for data structures shared
1154 * between the sequencer and kernel.
1155 */
1156 bus_dma_tag_t parent_dmat;
1157 bus_dmamap_t shared_data_dmamap;
1158 bus_addr_t shared_data_busaddr;
1159
1160 bus_dma_segment_t shared_data_seg;
1161 int shared_data_nseg;
1162 int shared_data_size;
1163 int sc_dmaflags;
1164
1165 /*
1166 * Bus address of the one byte buffer used to
1167 * work-around a DMA bug for chips <= aic7880
1168 * in target mode.
1169 */
1170 bus_addr_t dma_bug_buf;
1171
1172 /* Information saved through suspend/resume cycles */
1173 struct ahc_suspend_state suspend_state;
1174
1175 /* Number of enabled target mode device on this card */
1176 u_int enabled_luns;
1177
1178 /* Initialization level of this data structure */
1179 u_int init_level;
1180
1181 /* PCI cacheline size. */
1182 u_int pci_cachesize;
1183
1184 u_int stack_size;
1185
1186 /* Per-Unit descriptive information */
1187 const char *description;
1188 char *name;
1189 int unit;
1190
1191 /* Selection Timer settings */
1192 int seltime;
1193 int seltime_b;
1194
1195 uint16_t user_discenable;/* Disconnection allowed */
1196 uint16_t user_tagenable;/* Tagged Queuing allowed */
1197
1198 struct ahc_pci_busdata *bd;
1199
1200 void *shutdown_hook;
1201 };
1202
1203 TAILQ_HEAD(ahc_softc_tailq, ahc_softc);
1204 extern struct ahc_softc_tailq ahc_tailq;
1205
1206 /************************ Active Device Information ***************************/
1207 typedef enum {
1208 ROLE_UNKNOWN,
1209 ROLE_INITIATOR,
1210 ROLE_TARGET
1211 } role_t;
1212
1213 struct ahc_devinfo {
1214 int our_scsiid;
1215 int target_offset;
1216 uint16_t target_mask;
1217 u_int target;
1218 u_int lun;
1219 char channel;
1220 role_t role; /*
1221 * Only guaranteed to be correct if not
1222 * in the busfree state.
1223 */
1224 };
1225
1226 /****************************** PCI Structures ********************************/
1227 typedef int (ahc_device_setup_t)(struct ahc_softc *);
1228
1229 struct ahc_pci_identity {
1230 uint64_t full_id;
1231 uint64_t id_mask;
1232 char *name;
1233 ahc_device_setup_t *setup;
1234 };
1235 extern struct ahc_pci_identity ahc_pci_ident_table [];
1236 extern const u_int ahc_num_pci_devs;
1237
1238 /***************************** VL/EISA Declarations ***************************/
1239 struct aic7770_identity {
1240 uint32_t full_id;
1241 uint32_t id_mask;
1242 char *name;
1243 ahc_device_setup_t *setup;
1244 };
1245 extern struct aic7770_identity aic7770_ident_table [];
1246 extern const int ahc_num_aic7770_devs;
1247
1248 #define AHC_EISA_SLOT_OFFSET 0xc00
1249 #define AHC_EISA_IOSIZE 0x100
1250
1251 /*************************** Function Declarations ****************************/
1252 /******************************************************************************/
1253 u_int ahc_index_busy_tcl(struct ahc_softc *, u_int);
1254 void ahc_unbusy_tcl(struct ahc_softc *, u_int);
1255 void ahc_busy_tcl(struct ahc_softc *, u_int, u_int);
1256
1257 /***************************** PCI Front End *********************************/
1258 const struct ahc_pci_identity *ahc_find_pci_device(pcireg_t, pcireg_t, u_int);
1259 int ahc_pci_config(struct ahc_softc *,
1260 struct ahc_pci_identity *);
1261 int ahc_pci_test_register_access(struct ahc_softc *);
1262
1263 /*************************** EISA/VL Front End ********************************/
1264 struct aic7770_identity *aic7770_find_device(uint32_t);
1265 int aic7770_config(struct ahc_softc *,
1266 struct aic7770_identity *, u_int);
1267
1268 /************************** SCB and SCB queue management **********************/
1269 int ahc_probe_scbs(struct ahc_softc *);
1270 void ahc_run_untagged_queues(struct ahc_softc *);
1271 void ahc_run_untagged_queue(struct ahc_softc *, struct scb_tailq *);
1272 void ahc_qinfifo_requeue_tail(struct ahc_softc *, struct scb *);
1273 int ahc_match_scb(struct ahc_softc *, struct scb *,
1274 int, char, int, u_int, role_t);
1275
1276 /****************************** Initialization ********************************/
1277 int ahc_softc_init(struct ahc_softc *);
1278 void ahc_controller_info(struct ahc_softc *, char *);
1279 int ahc_init(struct ahc_softc *);
1280 void ahc_intr_enable(struct ahc_softc *, int);
1281 void ahc_pause_and_flushwork(struct ahc_softc *);
1282 int ahc_suspend(struct ahc_softc *);
1283 int ahc_resume(struct ahc_softc *);
1284 void ahc_softc_insert(struct ahc_softc *);
1285 struct ahc_softc *ahc_find_softc(struct ahc_softc *);
1286 void ahc_set_unit(struct ahc_softc *, int);
1287 void ahc_set_name(struct ahc_softc *, char *);
1288 int ahc_alloc_scbs(struct ahc_softc *);
1289 void ahc_free(struct ahc_softc *);
1290 int ahc_reset(struct ahc_softc *);
1291 void ahc_shutdown(void *);
1292
1293 /*************************** Interrupt Services *******************************/
1294 void ahc_pci_intr(struct ahc_softc *);
1295 void ahc_clear_intstat(struct ahc_softc *);
1296 void ahc_run_qoutfifo(struct ahc_softc *);
1297 #ifdef AHC_TARGET_MODE
1298 void ahc_run_tqinfifo(struct ahc_softc *, int);
1299 #endif
1300 void ahc_handle_brkadrint(struct ahc_softc *);
1301 void ahc_handle_seqint(struct ahc_softc *, u_int);
1302 void ahc_handle_scsiint(struct ahc_softc *, u_int);
1303 void ahc_clear_critical_section(struct ahc_softc *);
1304
1305 /***************************** Error Recovery *********************************/
1306 typedef enum {
1307 SEARCH_COMPLETE,
1308 SEARCH_COUNT,
1309 SEARCH_REMOVE
1310 } ahc_search_action;
1311 int ahc_search_qinfifo(struct ahc_softc *, int, char,
1312 int, u_int, role_t, uint32_t, ahc_search_action);
1313 int ahc_search_untagged_queues(struct ahc_softc *,
1314 struct scsipi_xfer *, int, char, int, uint32_t,
1315 ahc_search_action);
1316 int ahc_search_disc_list(struct ahc_softc *, int, char,
1317 int, u_int, int, int, int);
1318 void ahc_freeze_devq(struct ahc_softc *, struct scb *);
1319 int ahc_reset_channel(struct ahc_softc *, char, int);
1320 int ahc_abort_scbs(struct ahc_softc *, int, char, int,
1321 u_int, role_t, uint32_t);
1322 void ahc_restart(struct ahc_softc *);
1323 void ahc_calc_residual(struct ahc_softc *, struct scb *);
1324 /*************************** Utility Functions ********************************/
1325 struct ahc_phase_table_entry*
1326 ahc_lookup_phase_entry(int);
1327 void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int,
1328 u_int, char, role_t);
1329 /************************** Transfer Negotiation ******************************/
1330 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *, u_int *,
1331 u_int *, u_int);
1332 u_int ahc_find_period(struct ahc_softc *, u_int, u_int);
1333 void ahc_validate_offset(struct ahc_softc *,
1334 struct ahc_initiator_tinfo *, struct ahc_syncrate *,
1335 u_int *, int, role_t);
1336 void ahc_validate_width(struct ahc_softc *,
1337 struct ahc_initiator_tinfo *, u_int *, role_t);
1338 /*
1339 * Negotiation types. These are used to qualify if we should renegotiate
1340 * even if our goal and current transport parameters are identical.
1341 */
1342 typedef enum {
1343 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1344 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1345 AHC_NEG_ALWAYS /* Renegotiat even if goal is async. */
1346 } ahc_neg_type;
1347 int ahc_update_neg_request(struct ahc_softc *,
1348 struct ahc_devinfo *, struct ahc_tmode_tstate *,
1349 struct ahc_initiator_tinfo*, ahc_neg_type);
1350 void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *,
1351 u_int, u_int, int);
1352 void ahc_set_syncrate(struct ahc_softc *,
1353 struct ahc_devinfo *, struct ahc_syncrate *,
1354 u_int, u_int, u_int, u_int, int);
1355 typedef enum {
1356 AHC_QUEUE_NONE,
1357 AHC_QUEUE_BASIC,
1358 AHC_QUEUE_TAGGED
1359 } ahc_queue_alg;
1360
1361 void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *,
1362 ahc_queue_alg);
1363
1364 /**************************** Target Mode *************************************/
1365 #ifdef AHC_TARGET_MODE
1366 void ahc_send_lstate_events(struct ahc_softc *,
1367 struct ahc_tmode_lstate *);
1368 void ahc_handle_en_lun(struct ahc_softc *, struct scsipi_xfer *);
1369 cam_status ahc_find_tmode_devs(struct ahc_softc *,
1370 struct ahc_tmode_tstate **, struct ahc_tmode_lstate **,
1371 int);
1372 #ifndef AHC_TMODE_ENABLE
1373 #define AHC_TMODE_ENABLE 0
1374 #endif
1375 #endif
1376 /******************************* Debug ***************************************/
1377 #ifdef AHC_DEBUG
1378 extern uint32_t ahc_debug;
1379 #define AHC_SHOW_MISC 0x0001
1380 #define AHC_SHOW_SENSE 0x0002
1381 #define AHC_DUMP_SEEPROM 0x0004
1382 #define AHC_SHOW_TERMCTL 0x0008
1383 #define AHC_SHOW_MEMORY 0x0010
1384 #define AHC_SHOW_MESSAGES 0x0020
1385 #define AHC_SHOW_DV 0x0040
1386 #define AHC_SHOW_SELTO 0x0080
1387 #define AHC_SHOW_QFULL 0x0200
1388 #define AHC_SHOW_QUEUE 0x0400
1389 #define AHC_SHOW_TQIN 0x0800
1390 #define AHC_SHOW_MASKED_ERRORS 0x1000
1391 #define AHC_DEBUG_SEQUENCER 0x2000
1392 #endif
1393 void ahc_print_scb(struct scb *);
1394 void ahc_print_devinfo(struct ahc_softc *,
1395 struct ahc_devinfo *);
1396 void ahc_dump_card_state(struct ahc_softc *);
1397 int ahc_print_register(ahc_reg_parse_entry_t *, u_int,
1398 const char *, u_int, u_int, u_int *, u_int);
1399 /******************************* SEEPROM *************************************/
1400 int ahc_acquire_seeprom(struct ahc_softc *,
1401 struct seeprom_descriptor *);
1402 void ahc_release_seeprom(struct seeprom_descriptor *);
1403
1404 void ahc_check_extport(struct ahc_softc *, u_int *);
1405 #endif /* _AIC7XXXVAR_H_ */
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