1 /* $NetBSD: aic7xxxvar.h,v 1.58 2021/08/22 19:56:15 andvar Exp $ */
2
3 /*
4 * Core definitions and data structures sharable across OS platforms.
5 *
6 * Copyright (c) 1994-2001 Justin T. Gibbs.
7 * Copyright (c) 2000-2001 Adaptec Inc.
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * substantially similar to the "NO WARRANTY" disclaimer below
18 * ("Disclaimer") and any redistribution must be conditioned upon
19 * including a substantially similar Disclaimer requirement for further
20 * binary redistribution.
21 * 3. Neither the names of the above-listed copyright holders nor the names
22 * of any contributors may be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * Alternatively, this software may be distributed under the terms of the
26 * GNU General Public License ("GPL") version 2 as published by the Free
27 * Software Foundation.
28 *
29 * NO WARRANTY
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40 * POSSIBILITY OF SUCH DAMAGES.
41 *
42 * $Id: aic7xxxvar.h,v 1.58 2021/08/22 19:56:15 andvar Exp $
43 *
44 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx.h,v 1.44 2003/01/20 20:44:55 gibbs Exp $
45 */
46 /*
47 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
48 */
49
50 #ifndef _AIC7XXXVAR_H_
51 #define _AIC7XXXVAR_H_
52
53 #undef AHC_DEBUG
54
55 /* Register Definitions */
56 #include <dev/microcode/aic7xxx/aic7xxx_reg.h>
57
58 #include <dev/ic/aic7xxx_cam.h>
59
60 #define AIC_OP_OR 0x0
61 #define AIC_OP_AND 0x1
62 #define AIC_OP_XOR 0x2
63 #define AIC_OP_ADD 0x3
64 #define AIC_OP_ADC 0x4
65 #define AIC_OP_ROL 0x5
66 #define AIC_OP_BMOV 0x6
67
68 #define AIC_OP_JMP 0x8
69 #define AIC_OP_JC 0x9
70 #define AIC_OP_JNC 0xa
71 #define AIC_OP_CALL 0xb
72 #define AIC_OP_JNE 0xc
73 #define AIC_OP_JNZ 0xd
74 #define AIC_OP_JE 0xe
75 #define AIC_OP_JZ 0xf
76
77 /* Pseudo Ops */
78 #define AIC_OP_SHL 0x10
79 #define AIC_OP_SHR 0x20
80 #define AIC_OP_ROR 0x30
81
82 struct ins_format1 {
83 #if BYTE_ORDER == LITTLE_ENDIAN
84 uint32_t immediate : 8,
85 source : 9,
86 destination : 9,
87 ret : 1,
88 opcode : 4,
89 parity : 1;
90 #else
91 uint32_t parity : 1,
92 opcode : 4,
93 ret : 1,
94 destination : 9,
95 source : 9,
96 immediate : 8;
97 #endif
98 };
99
100 struct ins_format2 {
101 #if BYTE_ORDER == LITTLE_ENDIAN
102 uint32_t shift_control : 8,
103 source : 9,
104 destination : 9,
105 ret : 1,
106 opcode : 4,
107 parity : 1;
108 #else
109 uint32_t parity : 1,
110 opcode : 4,
111 ret : 1,
112 destination : 9,
113 source : 9,
114 shift_control : 8;
115 #endif
116 };
117
118 struct ins_format3 {
119 #if BYTE_ORDER == LITTLE_ENDIAN
120 uint32_t immediate : 8,
121 source : 9,
122 address : 10,
123 opcode : 4,
124 parity : 1;
125 #else
126 uint32_t parity : 1,
127 opcode : 4,
128 address : 10,
129 source : 9,
130 immediate : 8;
131 #endif
132 };
133
134 union ins_formats {
135 struct ins_format1 format1;
136 struct ins_format2 format2;
137 struct ins_format3 format3;
138 uint8_t bytes[4];
139 uint32_t integer;
140 };
141
142 /************************* Forward Declarations *******************************/
143 struct ahc_platform_data;
144 struct scb_platform_data;
145 struct seeprom_descriptor;
146
147 /****************************** Useful Macros *********************************/
148 #ifndef MAX
149 #define MAX(a,b) (((a) > (b)) ? (a) : (b))
150 #endif
151
152 #ifndef MIN
153 #define MIN(a,b) (((a) < (b)) ? (a) : (b))
154 #endif
155
156 #ifndef TRUE
157 #define TRUE 1
158 #endif
159 #ifndef FALSE
160 #define FALSE 0
161 #endif
162
163 #define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array))
164
165 #define ALL_CHANNELS '\0'
166 #define ALL_TARGETS_MASK 0xFFFF
167 #define INITIATOR_WILDCARD (~0)
168
169 #define SCSIID_TARGET(ahc, scsiid) \
170 (((scsiid) & ((((ahc)->features & AHC_TWIN) != 0) ? TWIN_TID : TID)) \
171 >> TID_SHIFT)
172 #define SCSIID_OUR_ID(scsiid) \
173 ((scsiid) & OID)
174 #define SCSIID_CHANNEL(ahc, scsiid) \
175 ((((ahc)->features & AHC_TWIN) != 0) \
176 ? ((((scsiid) & TWIN_CHNLB) != 0) ? 'B' : 'A') \
177 : 'A')
178 #define SCB_IS_SCSIBUS_B(ahc, scb) \
179 (SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid) == 'B')
180 #define SCB_GET_OUR_ID(scb) \
181 SCSIID_OUR_ID((scb)->hscb->scsiid)
182 #define SCB_GET_TARGET(ahc, scb) \
183 SCSIID_TARGET((ahc), (scb)->hscb->scsiid)
184 #define SCB_GET_CHANNEL(ahc, scb) \
185 SCSIID_CHANNEL(ahc, (scb)->hscb->scsiid)
186 #define SCB_GET_LUN(scb) \
187 ((scb)->hscb->lun)
188 #define SCB_GET_TARGET_OFFSET(ahc, scb) \
189 (SCB_GET_TARGET(ahc, scb))
190 #define SCB_GET_TARGET_MASK(ahc, scb) \
191 (0x01 << (SCB_GET_TARGET_OFFSET(ahc, scb)))
192 #ifdef AHC_DEBUG
193 #define SCB_IS_SILENT(scb) \
194 ((ahc_debug & AHC_SHOW_MASKED_ERRORS) == 0 \
195 && (((scb)->flags & SCB_SILENT) != 0))
196 #else
197 #define SCB_IS_SILENT(scb) \
198 (((scb)->flags & SCB_SILENT) != 0)
199 #endif
200 #define TCL_TARGET_OFFSET(tcl) \
201 ((((tcl) >> 4) & TID) >> 4)
202 #define TCL_LUN(tcl) \
203 (tcl & (AHC_NUM_LUNS - 1))
204 #define BUILD_TCL(scsiid, lun) \
205 ((lun) | (((scsiid) & TID) << 4))
206
207 #ifndef AHC_TARGET_MODE
208 #undef AHC_TMODE_ENABLE
209 #define AHC_TMODE_ENABLE 0
210 #endif
211
212 /**************************** Driver Constants ********************************/
213 /*
214 * The maximum number of supported targets.
215 */
216 #define AHC_NUM_TARGETS 16
217
218 /*
219 * The maximum number of supported luns.
220 * The identify message only supports 64 luns in SPI3.
221 * You can have 2^64 luns when information unit transfers are enabled,
222 * but it is doubtful this driver will ever support IUTs.
223 */
224 #define AHC_NUM_LUNS 64
225
226 /*
227 * The maximum transfer per S/G segment.
228 * Limited by MAXPHYS or a 24-bit counter.
229 */
230 #define AHC_MAXTRANSFER_SIZE MIN(MAXPHYS,0x00ffffff)
231
232 /*
233 * The maximum amount of SCB storage in hardware on a controller.
234 * This value represents an upper bound. Controllers vary in the number
235 * they actually support.
236 */
237 #define AHC_SCB_MAX 255
238
239 /*
240 * The maximum number of concurrent transactions supported per driver instance.
241 * Sequencer Control Blocks (SCBs) store per-transaction information. Although
242 * the space for SCBs on the host adapter varies by model, the driver will
243 * page the SCBs between host and controller memory as needed. We are limited
244 * to 253 because:
245 * 1) The 8bit nature of the RISC engine holds us to an 8bit value.
246 * 2) We reserve one value, 255, to represent the invalid element.
247 * 3) Our input queue scheme requires one SCB to always be reserved
248 * in advance of queuing any SCBs. This takes us down to 254.
249 * 4) To handle our output queue correctly on machines that only
250 * support 32bit stores, we must clear the array 4 bytes at a
251 * time. To avoid colliding with a DMA write from the sequencer,
252 * we must be sure that 4 slots are empty when we write to clear
253 * the queue. This reduces us to 253 SCBs: 1 that just completed
254 * and the known three additional empty slots in the queue that
255 * precede it.
256 */
257 #define AHC_MAX_QUEUE 253
258
259 /*
260 * The maximum amount of SCB storage we allocate in host memory. This
261 * number should reflect the 1 additional SCB we require to handle our
262 * qinfifo mechanism.
263 */
264 #define AHC_SCB_MAX_ALLOC (AHC_MAX_QUEUE+1)
265
266 /*
267 * Ring Buffer of incoming target commands.
268 * We allocate 256 to simplify the logic in the sequencer
269 * by using the natural wrap point of an 8bit counter.
270 */
271 #define AHC_TMODE_CMDS 256
272
273 /* Reset line assertion time in us */
274 #define AHC_BUSRESET_DELAY 25
275
276 /******************* Chip Characteristics/Operating Settings *****************/
277 /*
278 * Chip Type
279 * The chip order is from least sophisticated to most sophisticated.
280 */
281 typedef enum {
282 AHC_NONE = 0x0000,
283 AHC_CHIPID_MASK = 0x00FF,
284 AHC_AIC7770 = 0x0001,
285 AHC_AIC7850 = 0x0002,
286 AHC_AIC7855 = 0x0003,
287 AHC_AIC7859 = 0x0004,
288 AHC_AIC7860 = 0x0005,
289 AHC_AIC7870 = 0x0006,
290 AHC_AIC7880 = 0x0007,
291 AHC_AIC7895 = 0x0008,
292 AHC_AIC7895C = 0x0009,
293 AHC_AIC7890 = 0x000a,
294 AHC_AIC7896 = 0x000b,
295 AHC_AIC7892 = 0x000c,
296 AHC_AIC7899 = 0x000d,
297 AHC_VL = 0x0100, /* Bus type VL */
298 AHC_EISA = 0x0200, /* Bus type EISA */
299 AHC_PCI = 0x0400, /* Bus type PCI */
300 AHC_BUS_MASK = 0x0F00
301 } ahc_chip;
302
303 /*
304 * Features available in each chip type.
305 */
306 typedef enum {
307 AHC_FENONE = 0x00000,
308 AHC_ULTRA = 0x00001, /* Supports 20MHz Transfers */
309 AHC_ULTRA2 = 0x00002, /* Supports 40MHz Transfers */
310 AHC_WIDE = 0x00004, /* Wide Channel */
311 AHC_TWIN = 0x00008, /* Twin Channel */
312 AHC_MORE_SRAM = 0x00010, /* 80 bytes instead of 64 */
313 AHC_CMD_CHAN = 0x00020, /* Has a Command DMA Channel */
314 AHC_QUEUE_REGS = 0x00040, /* Has Queue management registers */
315 AHC_SG_PRELOAD = 0x00080, /* Can perform auto-SG preload */
316 AHC_SPIOCAP = 0x00100, /* Has a Serial Port I/O Cap Register */
317 AHC_MULTI_TID = 0x00200, /* Has bitmask of TIDs for select-in */
318 AHC_HS_MAILBOX = 0x00400, /* Has HS_MAILBOX register */
319 AHC_DT = 0x00800, /* Double Transition transfers */
320 AHC_NEW_TERMCTL = 0x01000, /* Newer termination scheme */
321 AHC_MULTI_FUNC = 0x02000, /* Multi-Function Twin Channel Device */
322 AHC_LARGE_SCBS = 0x04000, /* 64byte SCBs */
323 AHC_AUTORATE = 0x08000, /* Automatic update of SCSIRATE/OFFSET*/
324 AHC_AUTOPAUSE = 0x10000, /* Automatic pause on register access */
325 AHC_TARGETMODE = 0x20000, /* Has tested target mode support */
326 AHC_MULTIROLE = 0x40000, /* Space for two roles at a time */
327 AHC_REMOVABLE = 0x80000, /* Hot-Swap supported */
328 AHC_AIC7770_FE = AHC_FENONE,
329 /*
330 * The real 7850 does not support Ultra modes, but there are
331 * several cards that use the generic 7850 PCI ID even though
332 * they are using an Ultra capable chip (7859/7860). We start
333 * out with the AHC_ULTRA feature set and then check the DEVSTATUS
334 * register to determine if the capability is really present.
335 */
336 AHC_AIC7850_FE = AHC_SPIOCAP|AHC_AUTOPAUSE|AHC_TARGETMODE|AHC_ULTRA,
337 AHC_AIC7860_FE = AHC_AIC7850_FE,
338 AHC_AIC7870_FE = AHC_TARGETMODE,
339 AHC_AIC7880_FE = AHC_AIC7870_FE|AHC_ULTRA,
340 /*
341 * Although we have space for both the initiator and
342 * target roles on ULTRA2 chips, we currently disable
343 * the initiator role to allow multi-scsi-id target mode
344 * configurations. We can only respond on the same SCSI
345 * ID as our initiator role if we allow initiator operation.
346 * At some point, we should add a configuration knob to
347 * allow both roles to be loaded.
348 */
349 AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2
350 |AHC_QUEUE_REGS|AHC_SG_PRELOAD|AHC_MULTI_TID
351 |AHC_HS_MAILBOX|AHC_NEW_TERMCTL|AHC_LARGE_SCBS
352 |AHC_TARGETMODE,
353 AHC_AIC7892_FE = AHC_AIC7890_FE|AHC_DT|AHC_AUTORATE|AHC_AUTOPAUSE,
354 AHC_AIC7895_FE = AHC_AIC7880_FE|AHC_MORE_SRAM|AHC_AUTOPAUSE
355 |AHC_CMD_CHAN|AHC_MULTI_FUNC|AHC_LARGE_SCBS,
356 AHC_AIC7895C_FE = AHC_AIC7895_FE|AHC_MULTI_TID,
357 AHC_AIC7896_FE = AHC_AIC7890_FE|AHC_MULTI_FUNC,
358 AHC_AIC7899_FE = AHC_AIC7892_FE|AHC_MULTI_FUNC
359 } ahc_feature;
360
361 /*
362 * Bugs in the silicon that we work around in software.
363 */
364 typedef enum {
365 AHC_BUGNONE = 0x00,
366 /*
367 * On all chips prior to the U2 product line,
368 * the WIDEODD S/G segment feature does not
369 * work during scsi->HostBus transfers.
370 */
371 AHC_TMODE_WIDEODD_BUG = 0x01,
372 /*
373 * On the aic7890/91 Rev 0 chips, the autoflush
374 * feature does not work. A manual flush of
375 * the DMA FIFO is required.
376 */
377 AHC_AUTOFLUSH_BUG = 0x02,
378 /*
379 * On many chips, cacheline streaming does not work.
380 */
381 AHC_CACHETHEN_BUG = 0x04,
382 /*
383 * On the aic7896/97 chips, cacheline
384 * streaming must be enabled.
385 */
386 AHC_CACHETHEN_DIS_BUG = 0x08,
387 /*
388 * PCI 2.1 Retry failure on non-empty data fifo.
389 */
390 AHC_PCI_2_1_RETRY_BUG = 0x10,
391 /*
392 * Controller does not handle cacheline residuals
393 * properly on S/G segments if PCI MWI instructions
394 * are allowed.
395 */
396 AHC_PCI_MWI_BUG = 0x20,
397 /*
398 * An SCB upload using the SCB channel's
399 * auto array entry copy feature may
400 * corrupt data. This appears to only
401 * occur on 66MHz systems.
402 */
403 AHC_SCBCHAN_UPLOAD_BUG = 0x40
404 } ahc_bug;
405
406 /*
407 * Configuration specific settings.
408 * The driver determines these settings by probing the
409 * chip/controller's configuration.
410 */
411 typedef enum {
412 AHC_FNONE = 0x000,
413 AHC_PRIMARY_CHANNEL = 0x003, /*
414 * The channel that should
415 * be probed first.
416 */
417 AHC_USEDEFAULTS = 0x004, /*
418 * For cards without an seeprom
419 * or a BIOS to initialize the chip's
420 * SRAM, we use the default settings.
421 */
422 AHC_SEQUENCER_DEBUG = 0x008,
423 AHC_SHARED_SRAM = 0x010,
424 AHC_LARGE_SEEPROM = 0x020, /* Uses C56_66 not C46 */
425 AHC_RESET_BUS_A = 0x040,
426 AHC_RESET_BUS_B = 0x080,
427 AHC_EXTENDED_TRANS_A = 0x100,
428 AHC_EXTENDED_TRANS_B = 0x200,
429 AHC_TERM_ENB_A = 0x400,
430 AHC_TERM_ENB_B = 0x800,
431 AHC_INITIATORROLE = 0x1000, /*
432 * Allow initiator operations on
433 * this controller.
434 */
435 AHC_TARGETROLE = 0x2000, /*
436 * Allow target operations on this
437 * controller.
438 */
439 AHC_NEWEEPROM_FMT = 0x4000,
440 AHC_RESOURCE_SHORTAGE = 0x8000,
441 AHC_TQINFIFO_BLOCKED = 0x10000, /* Blocked waiting for ATIOs */
442 AHC_INT50_SPEEDFLEX = 0x20000, /*
443 * Internal 50pin connector
444 * sits behind an aic3860
445 */
446 AHC_SCB_BTT = 0x40000, /*
447 * The busy targets table is
448 * stored in SCB space rather
449 * than SRAM.
450 */
451 AHC_BIOS_ENABLED = 0x80000,
452 AHC_ALL_INTERRUPTS = 0x100000,
453 AHC_PAGESCBS = 0x400000, /* Enable SCB paging */
454 AHC_EDGE_INTERRUPT = 0x800000, /* Device uses edge triggered ints */
455 AHC_39BIT_ADDRESSING = 0x1000000, /* Use 39 bit addressing scheme. */
456 AHC_LSCBS_ENABLED = 0x2000000, /* 64Byte SCBs enabled */
457 AHC_SCB_CONFIG_USED = 0x4000000, /* No SEEPROM but SCB2 had info. */
458 AHC_NO_BIOS_INIT = 0x8000000, /* No BIOS left over settings. */
459 AHC_DISABLE_PCI_PERR = 0x10000000,
460 AHC_USETARGETDEFAULTS = 0x20000000 /*
461 * For cards without an seeprom but
462 * with BIOS which initializes chip's
463 * SRAM with some conservative target
464 * settings, we use the default
465 * SCSI target settings.
466 */
467 } ahc_flag;
468
469 /************************* Hardware SCB Definition ***************************/
470
471 /*
472 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
473 * consists of a "hardware SCB" mirroring the fields available on the card
474 * and additional information the kernel stores for each transaction.
475 *
476 * To minimize space utilization, a portion of the hardware scb stores
477 * different data during different portions of a SCSI transaction.
478 * As initialized by the host driver for the initiator role, this area
479 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After
480 * the cdb has been presented to the target, this area serves to store
481 * residual transfer information and the SCSI status byte.
482 * For the target role, the contents of this area do not change, but
483 * still serve a different purpose than for the initiator role. See
484 * struct target_data for details.
485 */
486
487 /*
488 * Status information embedded in the shared portion of
489 * an SCB after passing the cdb to the target. The kernel
490 * driver will only read this data for transactions that
491 * complete abnormally (non-zero status byte).
492 */
493 struct status_pkt {
494 uint32_t residual_datacnt; /* Residual in the current S/G seg */
495 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
496 uint8_t scsi_status; /* Standard SCSI status byte */
497 };
498
499 /*
500 * Target mode version of the shared data SCB segment.
501 */
502 struct target_data {
503 uint32_t residual_datacnt; /* Residual in the current S/G seg */
504 uint32_t residual_sg_ptr; /* The next S/G for this transfer */
505 uint8_t scsi_status; /* SCSI status to give to initiator */
506 uint8_t target_phases; /* Bitmap of phases to execute */
507 uint8_t data_phase; /* Data-In or Data-Out */
508 uint8_t initiator_tag; /* Initiator's transaction tag */
509 };
510
511 struct hardware_scb {
512 /**/ union {
513 /*
514 * If the cdb is 12 bytes or less, we embed it directly
515 * in the SCB. For longer cdbs, we embed the address
516 * of the cdb payload as seen by the chip and a DMA
517 * is used to pull it in.
518 */
519 uint8_t cdb[12];
520 uint32_t cdb_ptr;
521 struct status_pkt status;
522 struct target_data tdata;
523 } shared_data;
524 /*
525 * A word about residuals.
526 * The scb is presented to the sequencer with the dataptr and datacnt
527 * fields initialized to the contents of the first S/G element to
528 * transfer. The sgptr field is initialized to the bus address for
529 * the S/G element that follows the first in the in core S/G array
530 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid
531 * S/G entry for this transfer (single S/G element transfer with the
532 * first elements address and length preloaded in the dataptr/datacnt
533 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL.
534 * The SG_FULL_RESID flag ensures that the residual will be correctly
535 * noted even if no data transfers occur. Once the data phase is entered,
536 * the residual sgptr and datacnt are loaded from the sgptr and the
537 * datacnt fields. After each S/G element's dataptr and length are
538 * loaded into the hardware, the residual sgptr is advanced. After
539 * each S/G element is expired, its datacnt field is checked to see
540 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the
541 * residual sg ptr and the transfer is considered complete. If the
542 * sequencer determines that there is a residual in the transfer, it
543 * will set the SG_RESID_VALID flag in sgptr and DMA the scb back into
544 * host memory. To summarize:
545 *
546 * Sequencer:
547 * o A residual has occurred if SG_FULL_RESID is set in sgptr,
548 * or residual_sgptr does not have SG_LIST_NULL set.
549 *
550 * o We are transferring the last segment if residual_datacnt has
551 * the SG_LAST_SEG flag set.
552 *
553 * Host:
554 * o A residual has occurred if a completed scb has the
555 * SG_RESID_VALID flag set.
556 *
557 * o residual_sgptr and sgptr refer to the "next" sg entry
558 * and so may point beyond the last valid sg entry for the
559 * transfer.
560 */
561 /*12*/ uint32_t dataptr;
562 /*16*/ uint32_t datacnt; /*
563 * Byte 3 (numbered from 0) of
564 * the datacnt is really the
565 * 4th byte in that data address.
566 */
567 /*20*/ uint32_t sgptr;
568 #define SG_PTR_MASK 0xFFFFFFF8
569 /*24*/ uint8_t control; /* See SCB_CONTROL in aic7xxx.reg for details */
570 /*25*/ uint8_t scsiid; /* what to load in the SCSIID register */
571 /*26*/ uint8_t lun;
572 /*27*/ uint8_t tag; /*
573 * Index into our kernel SCB array.
574 * Also used as the tag for tagged I/O
575 */
576 /*28*/ uint8_t cdb_len;
577 /*29*/ uint8_t scsirate; /* Value for SCSIRATE register */
578 /*30*/ uint8_t scsioffset; /* Value for SCSIOFFSET register */
579 /*31*/ uint8_t next; /*
580 * Used for threading SCBs in the
581 * "Waiting for Selection" and
582 * "Disconnected SCB" lists down
583 * in the sequencer.
584 */
585 /*32*/ uint8_t cdb32[32]; /*
586 * CDB storage for cdbs of size
587 * 13->32. We store them here
588 * because hardware scbs are
589 * allocated from DMA safe
590 * memory so we are guaranteed
591 * the controller can access
592 * this data.
593 */
594 };
595
596 /************************ Kernel SCB Definitions ******************************/
597 /*
598 * Some fields of the SCB are OS dependent. Here we collect the
599 * definitions for elements that all OS platforms need to include
600 * in there SCB definition.
601 */
602
603 /*
604 * Definition of a scatter/gather element as transferred to the controller.
605 * The aic7xxx chips only support a 24bit length. We use the top byte of
606 * the length to store additional address bits and a flag to indicate
607 * that a given segment terminates the transfer. This gives us an
608 * addressable range of 512GB on machines with 64bit PCI or with chips
609 * that can support dual address cycles on 32bit PCI buses.
610 */
611 struct ahc_dma_seg {
612 uint32_t addr;
613 uint32_t len;
614 #define AHC_DMA_LAST_SEG 0x80000000
615 #define AHC_SG_HIGH_ADDR_MASK 0x7F000000
616 #define AHC_SG_LEN_MASK 0x00FFFFFF
617 };
618
619 struct sg_map_node {
620 bus_dmamap_t sg_dmamap;
621 bus_addr_t sg_physaddr;
622 bus_dma_segment_t sg_dmasegs;
623 int sg_nseg;
624 struct ahc_dma_seg* sg_vaddr;
625 SLIST_ENTRY(sg_map_node) links;
626 };
627
628 struct ahc_pci_busdata {
629 pci_chipset_tag_t pc;
630 pcitag_t tag;
631 u_int dev;
632 u_int func;
633 pcireg_t class;
634 };
635
636 /*
637 * The current state of this SCB.
638 */
639 typedef enum {
640 SCB_FREE = 0x0000,
641 SCB_OTHERTCL_TIMEOUT = 0x0002,/*
642 * Another device was active
643 * during the first timeout for
644 * this SCB so we gave ourselves
645 * an additional timeout period
646 * in case it was hogging the
647 * bus.
648 */
649 SCB_DEVICE_RESET = 0x0004,
650 SCB_SENSE = 0x0008,
651 SCB_CDB32_PTR = 0x0010,
652 SCB_RECOVERY_SCB = 0x0020,
653 SCB_AUTO_NEGOTIATE = 0x0040,/* Negotiate to achieve goal. */
654 SCB_NEGOTIATE = 0x0080,/* Negotiation forced for command. */
655 SCB_ABORT = 0x0100,
656 SCB_UNTAGGEDQ = 0x0200,
657 SCB_ACTIVE = 0x0400,
658 SCB_TARGET_IMMEDIATE = 0x0800,
659 SCB_TRANSMISSION_ERROR = 0x1000,/*
660 * We detected a parity or CRC
661 * error that has effected the
662 * payload of the command. This
663 * flag is checked when normal
664 * status is returned to catch
665 * the case of a target not
666 * responding to our attempt
667 * to report the error.
668 */
669 SCB_TARGET_SCB = 0x2000,
670 SCB_SILENT = 0x4000,/*
671 * Be quiet about transmission type
672 * errors. They are expected and we
673 * don't want to upset the user. This
674 * flag is typically used during DV.
675 */
676 SCB_FREEZE_QUEUE = 0x8000
677 } scb_flag;
678
679 struct scb {
680 struct hardware_scb *hscb;
681 union {
682 SLIST_ENTRY(scb) sle;
683 TAILQ_ENTRY(scb) tqe;
684 } links;
685 LIST_ENTRY(scb) pending_links;
686
687 struct scsipi_xfer *xs;
688 struct ahc_softc *ahc_softc;
689 scb_flag flags;
690 #ifndef __linux__
691 bus_dmamap_t dmamap;
692 #endif
693 struct scb_platform_data *platform_data;
694 struct sg_map_node *sg_map;
695 struct ahc_dma_seg *sg_list;
696 bus_addr_t sg_list_phys;
697 u_int sg_count;/* How full ahc_dma_seg is */
698 };
699
700 struct scb_data {
701 SLIST_HEAD(, scb) free_scbs; /*
702 * Pool of SCBs ready to be assigned
703 * commands to execute.
704 */
705 struct scb *scbindex[256]; /*
706 * Mapping from tag to SCB.
707 * As tag identifiers are an
708 * 8bit value, we provide space
709 * for all possible tag values.
710 * Any lookups to entries at or
711 * above AHC_SCB_MAX_ALLOC will
712 * always fail.
713 */
714 struct hardware_scb *hscbs; /* Array of hardware SCBs */
715 struct scb *scbarray; /* Array of kernel SCBs */
716 struct scsi_sense_data *sense; /* Per SCB sense data */
717
718 /*
719 * "Bus" addresses of our data structures.
720 */
721 bus_dmamap_t hscb_dmamap;
722 bus_addr_t hscb_busaddr;
723 bus_dma_segment_t hscb_seg;
724 int hscb_nseg;
725 int hscb_size;
726
727 bus_dmamap_t sense_dmamap;
728 bus_addr_t sense_busaddr;
729 bus_dma_segment_t sense_seg;
730 int sense_nseg;
731 int sense_size;
732
733 SLIST_HEAD(, sg_map_node) sg_maps;
734 uint8_t numscbs;
735 uint8_t maxhscbs; /* Number of SCBs on the card */
736 uint8_t init_level; /*
737 * How far we've initialized
738 * this structure.
739 */
740 };
741
742 /************************ Target Mode Definitions *****************************/
743
744 /*
745 * Connection descriptor for select-in requests in target mode.
746 */
747 struct target_cmd {
748 uint8_t scsiid; /* Our ID and the initiator's ID */
749 uint8_t identify; /* Identify message */
750 uint8_t bytes[22]; /*
751 * Bytes contains any additional message
752 * bytes terminated by 0xFF. The remainder
753 * is the cdb to execute.
754 */
755 uint8_t cmd_valid; /*
756 * When a command is complete, the firmware
757 * will set cmd_valid to all bits set.
758 * After the host has seen the command,
759 * the bits are cleared. This allows us
760 * to just peek at host memory to determine
761 * if more work is complete. cmd_valid is on
762 * an 8 byte boundary to simplify setting
763 * it on aic7880 hardware which only has
764 * limited direct access to the DMA FIFO.
765 */
766 uint8_t pad[7];
767 };
768
769 /*
770 * Number of events we can buffer up if we run out
771 * of immediate notify ccbs.
772 */
773 #define AHC_TMODE_EVENT_BUFFER_SIZE 8
774 struct ahc_tmode_event {
775 uint8_t initiator_id;
776 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
777 #define EVENT_TYPE_BUS_RESET 0xFF
778 uint8_t event_arg;
779 };
780
781 /*
782 * Per enabled lun target mode state.
783 * As this state is directly influenced by the host OS'es target mode
784 * environment, we let the OS module define it. Forward declare the
785 * structure here so we can store arrays of them, etc. in OS neutral
786 * data structures.
787 */
788 #ifdef AHC_TARGET_MODE
789 struct ahc_tmode_lstate {
790 #if 0
791 struct cam_path *path;
792 struct ccb_hdr_slist accept_tios;
793 struct ccb_hdr_slist immed_notifies;
794 #endif
795 struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
796 uint8_t event_r_idx;
797 uint8_t event_w_idx;
798 };
799 #else
800 struct ahc_tmode_lstate;
801 #endif
802
803 /******************** Transfer Negotiation Datastructures *********************/
804 #define AHC_TRANS_CUR 0x01 /* Modify current negotiation status */
805 #define AHC_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */
806 #define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
807 #define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
808
809 #define AHC_WIDTH_UNKNOWN 0xFF
810 #define AHC_PERIOD_UNKNOWN 0xFF
811 #define AHC_OFFSET_UNKNOWN 0x0
812 #define AHC_PPR_OPTS_UNKNOWN 0xFF
813
814 /*
815 * Transfer Negotiation Information.
816 */
817 struct ahc_transinfo {
818 uint8_t protocol_version; /* SCSI Revision level */
819 uint8_t transport_version; /* SPI Revision level */
820 uint8_t width; /* Bus width */
821 uint8_t period; /* Sync rate factor */
822 uint8_t offset; /* Sync offset */
823 uint8_t ppr_options; /* Parallel Protocol Request options */
824 };
825
826 /*
827 * Per-initiator current, goal and user transfer negotiation information. */
828 struct ahc_initiator_tinfo {
829 uint8_t scsirate; /* Computed value for SCSIRATE reg */
830 struct ahc_transinfo curr;
831 struct ahc_transinfo goal;
832 struct ahc_transinfo user;
833 };
834
835 /*
836 * Per enabled target ID state.
837 * Pointers to lun target state as well as sync/wide negotiation information
838 * for each initiator<->target mapping. For the initiator role we pretend
839 * that we are the target and the targets are the initiators since the
840 * negotiation is the same regardless of role.
841 */
842 struct ahc_tmode_tstate {
843 struct ahc_tmode_lstate* enabled_luns[AHC_NUM_LUNS];
844 struct ahc_initiator_tinfo transinfo[AHC_NUM_TARGETS];
845
846 /*
847 * Per initiator state bitmasks.
848 */
849 uint16_t auto_negotiate;/* Auto Negotiation Required */
850 uint16_t ultraenb; /* Using ultra sync rate */
851 uint16_t discenable; /* Disconnection allowed */
852 uint16_t tagenable; /* Tagged Queuing allowed */
853 };
854
855 /*
856 * Data structure for our table of allowed synchronous transfer rates.
857 */
858 struct ahc_syncrate {
859 u_int sxfr_u2; /* Value of the SXFR parameter for Ultra2+ Chips */
860 u_int sxfr; /* Value of the SXFR parameter for <= Ultra Chips */
861 #define ULTRA_SXFR 0x100 /* Rate Requires Ultra Mode set */
862 #define ST_SXFR 0x010 /* Rate Single Transition Only */
863 #define DT_SXFR 0x040 /* Rate Double Transition Only */
864 uint8_t period; /* Period to send to SCSI target */
865 const char *rate;
866 };
867
868 /* Safe and valid period for async negotiations. */
869 #define AHC_ASYNC_XFER_PERIOD 0x45
870 #define AHC_ULTRA2_XFER_PERIOD 0x0a
871
872 /*
873 * Indexes into our table of synchronous transfer rates.
874 */
875 #define AHC_SYNCRATE_DT 0
876 #define AHC_SYNCRATE_ULTRA2 1
877 #define AHC_SYNCRATE_ULTRA 3
878 #define AHC_SYNCRATE_FAST 6
879 #define AHC_SYNCRATE_MAX AHC_SYNCRATE_DT
880 #define AHC_SYNCRATE_MIN 13
881
882 /***************************** Lookup Tables **********************************/
883 /*
884 * Phase -> name and message out response
885 * to parity errors in each phase table.
886 */
887 struct ahc_phase_table_entry {
888 uint8_t phase;
889 uint8_t mesg_out; /* Message response to parity errors */
890 const char *phasemsg;
891 };
892
893 /************************** Serial EEPROM Format ******************************/
894
895 struct seeprom_config {
896 /*
897 * Per SCSI ID Configuration Flags
898 */
899 uint16_t device_flags[16]; /* words 0-15 */
900 #define CFXFER 0x0007 /* synchronous transfer rate */
901 #define CFSYNCH 0x0008 /* enable synchronous transfer */
902 #define CFDISC 0x0010 /* enable disconnection */
903 #define CFWIDEB 0x0020 /* wide bus device */
904 #define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
905 #define CFSYNCSINGLE 0x0080 /* Single-Transition signalling */
906 #define CFSTART 0x0100 /* send start unit SCSI command */
907 #define CFINCBIOS 0x0200 /* include in BIOS scan */
908 #define CFRNFOUND 0x0400 /* report even if not found */
909 #define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */
910 #define CFWBCACHEENB 0x4000 /* Enable W-Behind Cache on disks */
911 #define CFWBCACHENOP 0xc000 /* Don't touch W-Behind Cache */
912
913 /*
914 * BIOS Control Bits
915 */
916 uint16_t bios_control; /* word 16 */
917 #define CFSUPREM 0x0001 /* support all removable drives */
918 #define CFSUPREMB 0x0002 /* support removable boot drives */
919 #define CFBIOSEN 0x0004 /* BIOS enabled */
920 #define CFBIOS_BUSSCAN 0x0008 /* Have the BIOS Scan the Bus */
921 #define CFSM2DRV 0x0010 /* support more than two drives */
922 #define CFSTPWLEVEL 0x0010 /* Termination level control */
923 #define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
924 #define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */
925 #define CFTERM_MENU 0x0040 /* BIOS displays termination menu */
926 #define CFEXTEND 0x0080 /* extended translation enabled */
927 #define CFSCAMEN 0x0100 /* SCAM enable */
928 #define CFMSG_LEVEL 0x0600 /* BIOS Message Level */
929 #define CFMSG_VERBOSE 0x0000
930 #define CFMSG_SILENT 0x0200
931 #define CFMSG_DIAG 0x0400
932 #define CFBOOTCD 0x0800 /* Support Bootable CD-ROM */
933 /* UNUSED 0xff00 */
934
935 /*
936 * Host Adapter Control Bits
937 */
938 uint16_t adapter_control; /* word 17 */
939 #define CFAUTOTERM 0x0001 /* Perform Auto termination */
940 #define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
941 #define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
942 #define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
943 #define CFSTERM 0x0004 /* SCSI low byte termination */
944 #define CFWSTERM 0x0008 /* SCSI high byte termination */
945 #define CFSPARITY 0x0010 /* SCSI parity */
946 #define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
947 #define CFMULTILUN 0x0020
948 #define CFRESETB 0x0040 /* reset SCSI bus at boot */
949 #define CFCLUSTERENB 0x0080 /* Cluster Enable */
950 #define CFBOOTCHAN 0x0300 /* probe this channel first */
951 #define CFBOOTCHANSHIFT 8
952 #define CFSEAUTOTERM 0x0400 /* Ultra2 Perform secondary Auto Term*/
953 #define CFSELOWTERM 0x0800 /* Ultra2 secondary low term */
954 #define CFSEHIGHTERM 0x1000 /* Ultra2 secondary high term */
955 #define CFENABLEDV 0x4000 /* Perform Domain Validation*/
956
957 /*
958 * Bus Release Time, Host Adapter ID
959 */
960 uint16_t brtime_id; /* word 18 */
961 #define CFSCSIID 0x000f /* host adapter SCSI ID */
962 /* UNUSED 0x00f0 */
963 #define CFBRTIME 0xff00 /* bus release time */
964
965 /*
966 * Maximum targets
967 */
968 uint16_t max_targets; /* word 19 */
969 #define CFMAXTARG 0x00ff /* maximum targets */
970 #define CFBOOTLUN 0x0f00 /* Lun to boot from */
971 #define CFBOOTID 0xf000 /* Target to boot from */
972 uint16_t res_1[10]; /* words 20-29 */
973 uint16_t signature; /* Signature == 0x250 */
974 #define CFSIGNATURE 0x250
975 #define CFSIGNATURE2 0x300
976 uint16_t checksum; /* word 31 */
977 };
978
979 /**************************** Message Buffer *********************************/
980 typedef enum {
981 MSG_TYPE_NONE = 0x00,
982 MSG_TYPE_INITIATOR_MSGOUT = 0x01,
983 MSG_TYPE_INITIATOR_MSGIN = 0x02,
984 MSG_TYPE_TARGET_MSGOUT = 0x03,
985 MSG_TYPE_TARGET_MSGIN = 0x04
986 } ahc_msg_type;
987
988 typedef enum {
989 MSGLOOP_IN_PROG,
990 MSGLOOP_MSGCOMPLETE,
991 MSGLOOP_TERMINATED
992 } msg_loop_stat;
993
994 /*********************** Software Configuration Structure *********************/
995 TAILQ_HEAD(scb_tailq, scb);
996
997 struct ahc_suspend_channel_state {
998 uint8_t scsiseq;
999 uint8_t sxfrctl0;
1000 uint8_t sxfrctl1;
1001 uint8_t simode0;
1002 uint8_t simode1;
1003 uint8_t seltimer;
1004 uint8_t seqctl;
1005 };
1006
1007 struct ahc_suspend_state {
1008 struct ahc_suspend_channel_state channel[2];
1009 uint8_t optionmode;
1010 uint8_t dscommand0;
1011 uint8_t dspcistatus;
1012 /* hsmailbox */
1013 uint8_t crccontrol1;
1014 uint8_t scbbaddr;
1015 /* Host and sequencer SCB counts */
1016 uint8_t dff_thrsh;
1017 uint8_t *scratch_ram;
1018 uint8_t *btt;
1019 };
1020
1021 typedef void (*ahc_bus_intr_t)(struct ahc_softc *);
1022 typedef void ahc_callback_t (void *);
1023
1024 struct ahc_softc {
1025 device_t sc_dev;
1026
1027 struct scsipi_channel sc_channel;
1028 struct scsipi_channel sc_channel_b;
1029 device_t sc_child;
1030 device_t sc_child_b;
1031 struct scsipi_adapter sc_adapter;
1032
1033 bus_space_tag_t tag;
1034 bus_space_handle_t bsh;
1035
1036 #ifndef __linux__
1037 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
1038 #endif
1039 struct scb_data *scb_data;
1040
1041 struct scb *next_queued_scb;
1042
1043 /*
1044 * SCBs that have been sent to the controller
1045 */
1046 LIST_HEAD(, scb) pending_scbs;
1047
1048 /*
1049 * Counting lock for deferring the release of additional
1050 * untagged transactions from the untagged_queues. When
1051 * the lock is decremented to 0, all queues in the
1052 * untagged_queues array are run.
1053 */
1054 u_int untagged_queue_lock;
1055
1056 /*
1057 * Per-target queue of untagged-transactions. The
1058 * transaction at the head of the queue is the
1059 * currently pending untagged transaction for the
1060 * target. The driver only allows a single untagged
1061 * transaction per target.
1062 */
1063 struct scb_tailq untagged_queues[AHC_NUM_TARGETS];
1064
1065 /*
1066 * Platform specific data.
1067 */
1068 struct ahc_platform_data *platform_data;
1069
1070 /*
1071 * Platform specific device information.
1072 */
1073 /* ahc_dev_softc_t dev_softc; */
1074
1075 /*
1076 * Bus specific device information.
1077 */
1078 ahc_bus_intr_t bus_intr;
1079
1080 /*
1081 * Target mode related state kept on a per enabled lun basis.
1082 * Targets that are not enabled will have null entries.
1083 * As an initiator, we keep one target entry for our initiator
1084 * ID to store our sync/wide transfer settings.
1085 */
1086 struct ahc_tmode_tstate *enabled_targets[AHC_NUM_TARGETS];
1087
1088 char inited_target[AHC_NUM_TARGETS];
1089
1090 /*
1091 * The black hole device responsible for handling requests for
1092 * disabled luns on enabled targets.
1093 */
1094 struct ahc_tmode_lstate *black_hole;
1095
1096 /*
1097 * Device instance currently on the bus awaiting a continue TIO
1098 * for a command that was not given the disconnect privilege.
1099 */
1100 struct ahc_tmode_lstate *pending_device;
1101
1102 /*
1103 * Card characteristics
1104 */
1105 ahc_chip chip;
1106 ahc_feature features;
1107 ahc_bug bugs;
1108 ahc_flag flags;
1109 struct seeprom_config *seep_config;
1110
1111 /* Values to store in the SEQCTL register for pause and unpause */
1112 uint8_t unpause;
1113 uint8_t pause;
1114
1115 /* Command Queues */
1116 uint8_t qoutfifonext;
1117 uint8_t qinfifonext;
1118 uint8_t *qoutfifo;
1119 uint8_t *qinfifo;
1120
1121 /* Critical Section Data */
1122 struct cs *critical_sections;
1123 u_int num_critical_sections;
1124
1125 /* Links for chaining softcs */
1126 TAILQ_ENTRY(ahc_softc) links;
1127
1128 /* Channel Names ('A', 'B', etc.) */
1129 char channel;
1130
1131 /* Initiator Bus ID */
1132 uint8_t our_id;
1133 uint8_t our_id_b;
1134
1135 /*
1136 * PCI error detection.
1137 */
1138 int unsolicited_ints;
1139
1140 /*
1141 * Target incoming command FIFO.
1142 */
1143 struct target_cmd *targetcmds;
1144 uint8_t tqinfifonext;
1145
1146 /*
1147 * Incoming and outgoing message handling.
1148 */
1149 uint8_t send_msg_perror;
1150 ahc_msg_type msg_type;
1151 uint8_t msgout_buf[12];/* Message we are sending */
1152 uint8_t msgin_buf[12];/* Message we are receiving */
1153 u_int msgout_len; /* Length of message to send */
1154 u_int msgout_index; /* Current index in msgout */
1155 u_int msgin_index; /* Current index in msgin */
1156
1157 /* Interrupt routine */
1158 void *ih;
1159
1160 /*
1161 * Mapping information for data structures shared
1162 * between the sequencer and kernel.
1163 */
1164 bus_dma_tag_t parent_dmat;
1165 bus_dmamap_t shared_data_dmamap;
1166 bus_addr_t shared_data_busaddr;
1167
1168 bus_dma_segment_t shared_data_seg;
1169 int shared_data_nseg;
1170 int shared_data_size;
1171 int sc_dmaflags;
1172
1173 /*
1174 * Bus address of the one byte buffer used to
1175 * work-around a DMA bug for chips <= aic7880
1176 * in target mode.
1177 */
1178 bus_addr_t dma_bug_buf;
1179
1180 /* Information saved through suspend/resume cycles */
1181 struct ahc_suspend_state suspend_state;
1182
1183 /* Number of enabled target mode device on this card */
1184 u_int enabled_luns;
1185
1186 /* Initialization level of this data structure */
1187 u_int init_level;
1188
1189 /* PCI cacheline size. */
1190 u_int pci_cachesize;
1191
1192 u_int stack_size;
1193
1194 /* Per-Unit descriptive information */
1195 const char *description;
1196 const char *name;
1197 int unit;
1198
1199 /* Selection Timer settings */
1200 int seltime;
1201 int seltime_b;
1202
1203 uint16_t user_discenable;/* Disconnection allowed */
1204 uint16_t user_tagenable;/* Tagged Queuing allowed */
1205
1206 struct ahc_pci_busdata *bd;
1207 };
1208
1209 TAILQ_HEAD(ahc_softc_tailq, ahc_softc);
1210 extern struct ahc_softc_tailq ahc_tailq;
1211
1212 /************************ Active Device Information ***************************/
1213 typedef enum {
1214 ROLE_UNKNOWN,
1215 ROLE_INITIATOR,
1216 ROLE_TARGET
1217 } role_t;
1218
1219 struct ahc_devinfo {
1220 int our_scsiid;
1221 int target_offset;
1222 uint16_t target_mask;
1223 u_int target;
1224 u_int lun;
1225 char channel;
1226 role_t role; /*
1227 * Only guaranteed to be correct if not
1228 * in the busfree state.
1229 */
1230 };
1231
1232 /****************************** PCI Structures ********************************/
1233 typedef int (ahc_device_setup_t)(struct ahc_softc *);
1234
1235 struct ahc_pci_identity {
1236 uint64_t full_id;
1237 uint64_t id_mask;
1238 const char *name;
1239 ahc_device_setup_t *setup;
1240 };
1241
1242 /***************************** VL/EISA Declarations ***************************/
1243 struct aic7770_identity {
1244 uint32_t full_id;
1245 uint32_t id_mask;
1246 char *name;
1247 ahc_device_setup_t *setup;
1248 };
1249 extern struct aic7770_identity aic7770_ident_table [];
1250 extern const int ahc_num_aic7770_devs;
1251
1252 #define AHC_EISA_SLOT_OFFSET 0xc00
1253 #define AHC_EISA_IOSIZE 0x100
1254
1255 /*************************** Function Declarations ****************************/
1256 /******************************************************************************/
1257 u_int ahc_index_busy_tcl(struct ahc_softc *, u_int);
1258 void ahc_unbusy_tcl(struct ahc_softc *, u_int);
1259 void ahc_busy_tcl(struct ahc_softc *, u_int, u_int);
1260
1261 /*************************** EISA/VL Front End ********************************/
1262 struct aic7770_identity *aic7770_find_device(uint32_t);
1263 int aic7770_config(struct ahc_softc *,
1264 struct aic7770_identity *, u_int);
1265
1266 /************************** SCB and SCB queue management **********************/
1267 int ahc_probe_scbs(struct ahc_softc *);
1268 void ahc_run_untagged_queues(struct ahc_softc *);
1269 void ahc_run_untagged_queue(struct ahc_softc *, struct scb_tailq *);
1270 void ahc_qinfifo_requeue_tail(struct ahc_softc *, struct scb *);
1271 int ahc_match_scb(struct ahc_softc *, struct scb *,
1272 int, char, int, u_int, role_t);
1273
1274 /****************************** Initialization ********************************/
1275 int ahc_softc_init(struct ahc_softc *);
1276 void ahc_controller_info(struct ahc_softc *, char *, size_t);
1277 int ahc_init(struct ahc_softc *);
1278 void ahc_intr_enable(struct ahc_softc *, int);
1279 void ahc_pause_and_flushwork(struct ahc_softc *);
1280 int ahc_suspend(struct ahc_softc *);
1281 int ahc_resume(struct ahc_softc *);
1282 void ahc_softc_insert(struct ahc_softc *);
1283 struct ahc_softc *ahc_find_softc(struct ahc_softc *);
1284 void ahc_set_unit(struct ahc_softc *, int);
1285 void ahc_set_name(struct ahc_softc *, const char *);
1286 int ahc_alloc_scbs(struct ahc_softc *);
1287 void ahc_free(struct ahc_softc *);
1288 int ahc_reset(struct ahc_softc *);
1289 void ahc_shutdown(void *);
1290
1291 /*************************** Interrupt Services *******************************/
1292 void ahc_clear_intstat(struct ahc_softc *);
1293 void ahc_run_qoutfifo(struct ahc_softc *);
1294 #ifdef AHC_TARGET_MODE
1295 void ahc_run_tqinfifo(struct ahc_softc *, int);
1296 #endif
1297 void ahc_handle_brkadrint(struct ahc_softc *);
1298 void ahc_handle_seqint(struct ahc_softc *, u_int);
1299 void ahc_handle_scsiint(struct ahc_softc *, u_int);
1300 void ahc_clear_critical_section(struct ahc_softc *);
1301
1302 /***************************** Error Recovery *********************************/
1303 typedef enum {
1304 SEARCH_COMPLETE,
1305 SEARCH_COUNT,
1306 SEARCH_REMOVE
1307 } ahc_search_action;
1308 int ahc_search_qinfifo(struct ahc_softc *, int, char,
1309 int, u_int, role_t, uint32_t, ahc_search_action);
1310 int ahc_search_untagged_queues(struct ahc_softc *,
1311 struct scsipi_xfer *, int, char, int, uint32_t,
1312 ahc_search_action);
1313 int ahc_search_disc_list(struct ahc_softc *, int, char,
1314 int, u_int, int, int, int);
1315 void ahc_freeze_devq(struct ahc_softc *, struct scb *);
1316 int ahc_reset_channel(struct ahc_softc *, char, int);
1317 int ahc_abort_scbs(struct ahc_softc *, int, char, int,
1318 u_int, role_t, uint32_t);
1319 void ahc_restart(struct ahc_softc *);
1320 void ahc_calc_residual(struct ahc_softc *, struct scb *);
1321 /*************************** Utility Functions ********************************/
1322 struct ahc_phase_table_entry*
1323 ahc_lookup_phase_entry(int);
1324 void ahc_compile_devinfo(struct ahc_devinfo *, u_int, u_int,
1325 u_int, char, role_t);
1326 /************************** Transfer Negotiation ******************************/
1327 struct ahc_syncrate* ahc_find_syncrate(struct ahc_softc *, u_int *,
1328 u_int *, u_int);
1329 u_int ahc_find_period(struct ahc_softc *, u_int, u_int);
1330 void ahc_validate_offset(struct ahc_softc *,
1331 struct ahc_initiator_tinfo *, struct ahc_syncrate *,
1332 u_int *, int, role_t);
1333 void ahc_validate_width(struct ahc_softc *,
1334 struct ahc_initiator_tinfo *, u_int *, role_t);
1335 /*
1336 * Negotiation types. These are used to qualify if we should renegotiate
1337 * even if our goal and current transport parameters are identical.
1338 */
1339 typedef enum {
1340 AHC_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */
1341 AHC_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */
1342 AHC_NEG_ALWAYS /* Renegotiate even if goal is async. */
1343 } ahc_neg_type;
1344 int ahc_update_neg_request(struct ahc_softc *,
1345 struct ahc_devinfo *, struct ahc_tmode_tstate *,
1346 struct ahc_initiator_tinfo*, ahc_neg_type);
1347 void ahc_set_width(struct ahc_softc *, struct ahc_devinfo *,
1348 u_int, u_int, int);
1349 void ahc_set_syncrate(struct ahc_softc *,
1350 struct ahc_devinfo *, struct ahc_syncrate *,
1351 u_int, u_int, u_int, u_int, int);
1352 typedef enum {
1353 AHC_QUEUE_NONE,
1354 AHC_QUEUE_BASIC,
1355 AHC_QUEUE_TAGGED
1356 } ahc_queue_alg;
1357
1358 void ahc_set_tags(struct ahc_softc *, struct ahc_devinfo *,
1359 ahc_queue_alg);
1360
1361 /**************************** Target Mode *************************************/
1362 #ifdef AHC_TARGET_MODE
1363 void ahc_send_lstate_events(struct ahc_softc *,
1364 struct ahc_tmode_lstate *);
1365 void ahc_handle_en_lun(struct ahc_softc *, struct scsipi_xfer *);
1366 cam_status ahc_find_tmode_devs(struct ahc_softc *,
1367 struct ahc_tmode_tstate **, struct ahc_tmode_lstate **,
1368 int);
1369 #ifndef AHC_TMODE_ENABLE
1370 #define AHC_TMODE_ENABLE 0
1371 #endif
1372 #endif
1373 /******************************* Debug ***************************************/
1374 #ifdef AHC_DEBUG
1375 extern uint32_t ahc_debug;
1376 #define AHC_SHOW_MISC 0x0001
1377 #define AHC_SHOW_SENSE 0x0002
1378 #define AHC_DUMP_SEEPROM 0x0004
1379 #define AHC_SHOW_TERMCTL 0x0008
1380 #define AHC_SHOW_MEMORY 0x0010
1381 #define AHC_SHOW_MESSAGES 0x0020
1382 #define AHC_SHOW_DV 0x0040
1383 #define AHC_SHOW_SELTO 0x0080
1384 #define AHC_SHOW_QFULL 0x0200
1385 #define AHC_SHOW_QUEUE 0x0400
1386 #define AHC_SHOW_TQIN 0x0800
1387 #define AHC_SHOW_MASKED_ERRORS 0x1000
1388 #define AHC_DEBUG_SEQUENCER 0x2000
1389 #endif
1390 void ahc_print_scb(struct scb *);
1391 void ahc_print_devinfo(struct ahc_softc *,
1392 struct ahc_devinfo *);
1393 void ahc_dump_card_state(struct ahc_softc *);
1394 int ahc_print_register(ahc_reg_parse_entry_t *, u_int,
1395 const char *, u_int, u_int, u_int *, u_int);
1396 /******************************* SEEPROM *************************************/
1397 int ahc_acquire_seeprom(struct ahc_softc *,
1398 struct seeprom_descriptor *);
1399 void ahc_release_seeprom(struct seeprom_descriptor *);
1400
1401 void ahc_check_extport(struct ahc_softc *, u_int *);
1402 #endif /* _AIC7XXXVAR_H_ */
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