The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/al2210reg.h

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    1 /* $NetBSD: al2210reg.h,v 1.5 2009/10/19 23:19:39 rmind Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2004 David Young.  All rights reserved.
    5  *
    6  * This code was written by David Young.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
   18  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
   19  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
   20  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
   21  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
   22  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   23  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   25  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   26  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
   28  * OF SUCH DAMAGE.
   29  */
   30 
   31 #ifndef _DEV_IC_AL2210REG_H_
   32 #define _DEV_IC_AL2210REG_H_
   33 
   34 /*
   35  * Register definitions for the Airoha AL2210 2.4GHz 802.11b
   36  * transceiver.
   37  */
   38 
   39 /* NOTE WELL: These register definitions, in spite of being derived
   40  * from an "official" Airoha AL2210 datasheet, contain a lot of
   41  * "magic." Comparing with the magic in this header file with a
   42  * reference driver that also contains AL2210 magic, the magic does
   43  * not match!
   44  */
   45 
   46 /*
   47  * Serial bus format for Airoha AL2210 2.4GHz transceiver.
   48  */
   49 #define AL2210_TWI_DATA_MASK    __BITS(23, 4)
   50 #define AL2210_TWI_ADDR_MASK    __BITS(3, 0)
   51 
   52 /*
   53  * Registers for Airoha AL2210.
   54  */
   55 
   56 /* The synthesizer magic should be decipherable, but I'm not going
   57  * to waste my time right now.
   58  */
   59 #define AL2210_CHANNEL          0x0
   60 #define         AL2210_CHANNEL_B_MASK           __BITS(10, 5)   /* Counter B */
   61 #define         AL2210_CHANNEL_B_2412MHZ        0x396
   62 #define         AL2210_CHANNEL_B_2417MHZ        0x396
   63 #define         AL2210_CHANNEL_B_2422MHZ        0x396
   64 #define         AL2210_CHANNEL_B_2427MHZ        0x396
   65 #define         AL2210_CHANNEL_B_2432MHZ        0x398
   66 #define         AL2210_CHANNEL_B_2437MHZ        0x398
   67 #define         AL2210_CHANNEL_B_2442MHZ        0x398
   68 #define         AL2210_CHANNEL_B_2447MHZ        0x398
   69 #define         AL2210_CHANNEL_B_2452MHZ        0x398
   70 #define         AL2210_CHANNEL_B_2457MHZ        0x398
   71 #define         AL2210_CHANNEL_B_2462MHZ        0x398
   72 #define         AL2210_CHANNEL_B_2467MHZ        0x39a
   73 #define         AL2210_CHANNEL_B_2472MHZ        0x39a
   74 #define         AL2210_CHANNEL_B_2484MHZ        0x39b
   75 #define         AL2210_CHANNEL_A_MASK           __BITS(4, 0)    /* Counter A */
   76 #define         AL2210_CHANNEL_A_2412MHZ        0x0c
   77 #define         AL2210_CHANNEL_A_2417MHZ        0x11
   78 #define         AL2210_CHANNEL_A_2422MHZ        0x16
   79 #define         AL2210_CHANNEL_A_2427MHZ        0x1b
   80 #define         AL2210_CHANNEL_A_2432MHZ        0x00
   81 #define         AL2210_CHANNEL_A_2437MHZ        0x05
   82 #define         AL2210_CHANNEL_A_2442MHZ        0x0a
   83 #define         AL2210_CHANNEL_A_2447MHZ        0x0f
   84 #define         AL2210_CHANNEL_A_2452MHZ        0x14
   85 #define         AL2210_CHANNEL_A_2457MHZ        0x10
   86 #define         AL2210_CHANNEL_A_2462MHZ        0x1e
   87 #define         AL2210_CHANNEL_A_2467MHZ        0x03
   88 #define         AL2210_CHANNEL_A_2472MHZ        0x08
   89 #define         AL2210_CHANNEL_A_2484MHZ        0x14
   90 
   91 #define AL2210_SYNTHESIZER      0x1
   92 #define         AL2210_SYNTHESIZER_R_MASK       __BITS(4, 0)    /* Reference
   93                                                                  * divider
   94                                                                  */
   95 #define AL2210_RECEIVER         0x2
   96 /* Rx VAGC Detector Negative Edge Threshold */
   97 #define         AL2210_RECEIVER_AGCDET_P_MASK   __BITS(16, 15)
   98 #define         AL2210_RECEIVER_AGCDET_P_0_4V   0       /* 0.4V */
   99 #define         AL2210_RECEIVER_AGCDET_P_0_3V   1       /* 0.3V */
  100 #define         AL2210_RECEIVER_AGCDET_P_0_2V   2       /* 0.2V */
  101 #define         AL2210_RECEIVER_AGCDET_P_RSVD   3       /* reserved */
  102 /* Rx VAGC Detector Negative Edge Threshold */
  103 #define         AL2210_RECEIVER_AGCDET_N_MASK   __BITS(14, 13)
  104 #define         AL2210_RECEIVER_AGCDET_N_0_4V   0       /* 0.4V */
  105 #define         AL2210_RECEIVER_AGCDET_N_0_3V   1       /* 0.3V */
  106 #define         AL2210_RECEIVER_AGCDET_N_0_2V   2       /* 0.2V */
  107 #define         AL2210_RECEIVER_AGCDET_N_RSVD   3       /* reserved */
  108 /* AGC detector control, 1: enable, 0: disable. */
  109 #define         AL2210_RECEIVER_AGCDETENA       __BIT(11)
  110 /* Rx filter bandwidth select */
  111 #define         AL2210_RECEIVER_BW_SEL_MASK     __BITS(4, 2)
  112 #define         AL2210_RECEIVER_BW_SEL_9_5MHZ   0
  113 #define         AL2210_RECEIVER_BW_SEL_9MHZ     1
  114 #define         AL2210_RECEIVER_BW_SEL_8_5MHZ   2
  115 #define         AL2210_RECEIVER_BW_SEL_8MHZ     3
  116 #define         AL2210_RECEIVER_BW_SEL_7_5MHZ   4
  117 #define         AL2210_RECEIVER_BW_SEL_7MHZ     5
  118 #define         AL2210_RECEIVER_BW_SEL_6_5MHZ   6
  119 #define         AL2210_RECEIVER_BW_SEL_6MHZ     7
  120 
  121 #define AL2210_TRANSMITTER      0x3
  122 /* 2nd-stage power amplifier current control.  Units of 20uA.
  123  * "Full scale" current is 300uA.  (Is full-scale at PABIAS2 = 0 or
  124  * at PABIAS2 = 15?)
  125  */
  126 #define         AL2210_TRANSMITTER_PABIAS2_MASK __BITS(7, 4)
  127 /* 1st-stage power amplifier current control.  Units of 20uA.
  128  * "Full scale" current is 300uA.  (Is full-scale at PABIAS2 = 0 or
  129  * at PABIAS2 = 15?)
  130  */
  131 #define         AL2210_TRANSMITTER_PABIAS1_MASK __BITS(3, 0)
  132 
  133 #define AL2210_CONFIG1          0x4
  134 
  135 #define AL2210_CONFIG2          0x5
  136 /* Regulator power.  0: on, 1: off. */
  137 #define         AL2210_CONFIG2_REGPD_MASK       __BIT(19)
  138 /* XO clock setting.   0: 44MHz, 1: 22MHz. */
  139 #define         AL2210_CONFIG2_XTAL_SC_MASK     __BIT(10)
  140 
  141 /* DC Offset Calibration (DCOC) */
  142 #define AL2210_CONFIG3          0x6
  143 /* Select 1MHz DCOC timing. */
  144 #define         AL2210_CONFIG3_AGC_DET_PATT_1MHZ        __BIT(17)
  145 /* Select 100kHz DCOC timing. */
  146 #define         AL2210_CONFIG3_AGC_DET_PATT_100KHZ      __BIT(16)
  147 #define         AL2210_CONFIG3_LNA_GAIN_PATT_1MHZ       __BITS(15)
  148 #define         AL2210_CONFIG3_LNA_GAIN_PATT_100KHZ     __BITS(14)
  149 #define         AL2210_CONFIG3_RXON_PATT_1MHZ           __BITS(13)
  150 #define         AL2210_CONFIG3_RXON_PATT_1OOKHZ         __BITS(12)
  151 /* 1MHz DCOC duration?  Microseconds. */
  152 #define         AL2210_CONFIG3_CNT_1M_AGC_MASK          __BITS(11, 8)
  153 #define         AL2210_CONFIG3_CNT_1M_LNA_MASK          __BITS(7, 4)
  154 #define         AL2210_CONFIG3_CNT_1M_RXON_MASK         __BITS(3, 0)
  155 
  156 #define AL2210_CONFIG4          0x7
  157 /* 100kHz DCOC duration?  Microseconds. */
  158 #define         AL2210_CONFIG4_CNT_100K_AGC_MASK        __BITS(11, 8)
  159 #define         AL2210_CONFIG4_CNT_100K_LNA_MASK        __BITS(7, 4)
  160 #define         AL2210_CONFIG4_CNT_100K_RXON_MASK       __BITS(3, 0)
  161 
  162 #define AL2210_CONFIG5          0x8
  163 #define         AL2210_CONFIG5_TXF_BW_MASK              __BITS(9, 8)
  164 #define         AL2210_CONFIG5_TXF_BW_12MHZ             3
  165 #define         AL2210_CONFIG5_TXF_BW_11MHZ             2
  166 #define         AL2210_CONFIG5_TXF_BW_10MHZ             1
  167 #define         AL2210_CONFIG5_TXF_BW_9MHZ              0
  168 
  169 #define AL2210_CONFIG6          0x9
  170 #define AL2210_CONFIG6_DEFAULT  0x2c0009        /* magic */
  171 
  172 #define AL2210_CONFIG7          0xa
  173 #define AL2210_CONFIG7_DEFAULT  0x001c0a        /* magic */
  174 
  175 #define AL2210_CONFIG8          0xb
  176 #define AL2210_CONFIG8_DEFAULT  0x01000b        /* magic */
  177 
  178 #endif /* _DEV_IC_AL2210REG_H_ */

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