Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/am7930reg.h
Version:
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1 /* $NetBSD: am7930reg.h,v 1.7 2005/12/11 12:21:25 christos Exp $ */ 2 3 /* 4 * Am79C30A direct registers 5 */ 6 7 #define AM7930_DREG_CR 0 /* command register (wo) */ 8 #define AM7930_DREG_IR 0 /* interrupt register (ro) */ 9 #define AM7930_IR_DTTHRSH 0x01 /* D-channel TX empty */ 10 #define AM7930_IR_DRTHRSH 0x02 /* D-channel RX avail */ 11 #define AM7930_IR_DSRI 0x04 /* D-channel packet status */ 12 #define AM7930_IR_DERI 0x08 /* D-channel error */ 13 #define AM7930_IR_BBUFF 0x10 /* Bb or Bc byte avail/empty */ 14 #define AM7930_IR_LSRI 0x20 /* LIU status */ 15 #define AM7930_IR_DSR2I 0x40 /* D-channel buffer status */ 16 #define AM7930_IR_PPMF 0x80 /* Multiframe or PP */ 17 #define AM7930_DREG_DR 1 /* data register (rw) */ 18 #define AM7930_DREG_DSR1 2 /* D-channel status register 1 (ro) */ 19 #define AM7930_DREG_DER 3 /* D-channel error register (ro) */ 20 #define AM7930_DREG_DCTB 4 /* D-channel transmit register (wo) */ 21 #define AM7930_DREG_DCRB 4 /* D-channel receive register (ro) */ 22 #define AM7930_DREG_BBTB 5 /* Bb-channel transmit register (wo) */ 23 #define AM7930_DREG_BBRB 5 /* Bb-channel receive register (ro) */ 24 #define AM7930_DREG_BCTB 6 /* Bc-channel transmit register (wo) */ 25 #define AM7930_DREG_BCRB 6 /* Bc-channel receive register (ro) */ 26 #define AM7930_DREG_DSR2 7 /* D-channel status register 2 (ro) */ 27 28 #define AM7930_DREG_SIZE 8 29 30 /* 31 * Am79C30A indirect registers 32 */ 33 34 /* Initialisation registers */ 35 36 #define AM7930_IREG_INIT 0x21 37 #define AM7930_IREG_INIT2 0x20 38 /* power mode selection */ 39 #define AM7930_INIT_PMS_IDLE 0x00 40 #define AM7930_INIT_PMS_ACTIVE 0x01 41 #define AM7930_INIT_PMS_ACTIVE_DATA 0x02 42 #define AM7930_INIT_PMS_MASK 0x03 43 /* interrupt selection */ 44 #define AM7930_INIT_INT_ENABLE 0x00 45 #define AM7930_INIT_INT_DISABLE 0x04 46 #define AM7930_INIT_INT_MASK 0x04 47 /* clock divider selection */ 48 #define AM7930_INIT_CDS_DIV2 0x00 49 #define AM7930_INIT_CDS_DIV1 0x08 50 #define AM7930_INIT_CDS_DIV4 0x10 51 #define AM7930_INIT_CDS_DIV3 0x20 52 #define AM7930_INIT_CDS_MASK 0x38 53 /* abort selection */ 54 #define AM7930_INIT_AS_RX 0x40 55 #define AM7930_INIT_AS_NRX 0x00 56 #define AM7930_INIT_AS_TX 0x80 57 #define AM7930_INIT_AS_NTX 0x00 58 #define AM7930_INIT_AS_MASK 0xc0 59 60 /* Line Interface Unit registers */ 61 62 #define AM7930_IREG_LIU_LSR 0xa1 /* LIU status (ro) */ 63 #define AM7930_IREG_LIU_LPR 0xa2 /* LIU priority (rw) */ 64 #define AM7930_IREG_LIU_LMR1 0xa3 /* LIU mode register 1 (rw) */ 65 #define AM7930_IREG_LIU_LMR2 0xa4 /* LIU mode register 2 (rw) */ 66 #define AM7930_IREG_LIU_2_4 0xa5 67 #define AM7930_IREG_LIU_MF 0xa6 /* Multiframe (rw) */ 68 #define AM7930_IREG_LIU_MFSB 0xa7 /* Multiframe S-bit/status (ro) */ 69 #define AM7930_IREG_LIU_MFQB 0xa8 /* Multiframe Q-bit buffer (wo) */ 70 71 /* Multiplexer registers */ 72 73 #define AM7930_IREG_MUX_MCR1 0x41 /* MUX command register 1 (rw) */ 74 #define AM7930_IREG_MUX_MCR2 0x42 /* MUX command register 2 (rw) */ 75 #define AM7930_IREG_MUX_MCR3 0x43 /* MUX command register 3 (rw) */ 76 #define AM7930_MCRCHAN_NC 0x00 77 #define AM7930_MCRCHAN_B1 0x01 78 #define AM7930_MCRCHAN_B2 0x02 79 #define AM7930_MCRCHAN_BA 0x03 80 #define AM7930_MCRCHAN_BB 0x04 81 #define AM7930_MCRCHAN_BC 0x05 82 #define AM7930_MCRCHAN_BD 0x06 83 #define AM7930_MCRCHAN_BE 0x07 84 #define AM7930_MCRCHAN_BF 0x08 85 #define AM7930_IREG_MUX_MCR4 0x44 /* MUX command register 4 (rw) */ 86 #define AM7930_MCR4_INT_ENABLE (1 << 3) 87 #define AM7930_MCR4_SWAPBB (1 << 4) 88 #define AM7930_MCR4_SWAPBC (1 << 5) 89 #define AM7930_IREG_MUX_1_4 0x45 90 91 /* Main Audio Processor registers */ 92 93 #define AM7930_IREG_MAP_X 0x61 /* X filter coefficient (rw) */ 94 #define AM7930_IREG_MAP_R 0x62 /* R filter coefficient (rw) */ 95 #define AM7930_IREG_MAP_GX 0x63 /* GX gain coefficient (rw) */ 96 #define AM7930_IREG_MAP_GR 0x64 /* GR gain coefficient (rw) */ 97 #define AM7930_IREG_MAP_GER 0x65 /* GER gain coefficient (rw) */ 98 #define AM7930_IREG_MAP_STG 0x66 /* Sidetone gain coefficient (rw) */ 99 #define AM7930_IREG_MAP_FTGR 0x67 /* Frequency tone generator 1,2 (rw) */ 100 #define AM7930_IREG_MAP_ATGR 0x68 /* Amplitude tone generator 1,2 (rw) */ 101 #define AM7930_IREG_MAP_MMR1 0x69 /* MAP mode register 1 (rw) */ 102 #define AM7930_MMR1_ALAW 0x01 103 #define AM7930_MMR1_GX 0x02 104 #define AM7930_MMR1_GR 0x04 105 #define AM7930_MMR1_GER 0x08 106 #define AM7930_MMR1_X 0x10 107 #define AM7930_MMR1_R 0x20 108 #define AM7930_MMR1_STG 0x40 109 #define AM7930_MMR1_LOOP 0x80 110 #define AM7930_IREG_MAP_MMR2 0x6a /* MAP mode register 2 (rw) */ 111 #define AM7930_MMR2_AINB 0x01 112 #define AM7930_MMR2_LS 0x02 113 #define AM7930_MMR2_DTMF 0x04 114 #define AM7930_MMR2_GEN 0x08 115 #define AM7930_MMR2_RNG 0x10 116 #define AM7930_MMR2_DIS_HPF 0x20 117 #define AM7930_MMR2_DIS_AZ 0x40 118 #define AM7930_IREG_MAP_1_10 0x6b 119 #define AM7930_IREG_MAP_MMR3 0x6c /* MAP mode register 3 (rw) */ 120 #define AM7930_MMR3_BOTH 0x02 121 #define AM7930_MMR3_MBZ 0x01 122 #define AM7930_MMR3_GA 0x70 123 #define AM7930_MMR3_GA0 0x00 124 #define AM7930_MMR3_GA6 0x10 125 #define AM7930_MMR3_GA12 0x20 126 #define AM7930_MMR3_GA18 0x30 127 #define AM7930_MMR3_GA24 0x40 128 #define AM7930_MMR3_MUTE 0x08 129 #define AM7930_MMR3_STR 0x01 130 #define AM7930_IREG_MAP_STRA 0x6d /* Second tone ringer amplitude (rw) */ 131 #define AM7930_IREG_MAP_STRF 0x6e /* Second tone ringer frequency (rw) */ 132 133 /* Data Link Controller registers */ 134 135 #define AM7930_IREG_DLC_FRAR123 0x81 /* First rcvd byte address 123 (rw) */ 136 #define AM7930_IREG_DLC_SRAR123 0x82 /* Second rcvd byte address 123 (rw) */ 137 #define AM7930_IREG_DLC_TAR 0x83 /* Transmit address (rw) */ 138 #define AM7930_IREG_DLC_DRLR 0x84 /* D-channel receive byte limit (rw) */ 139 #define AM7930_IREG_DLC_DTCR 0x85 /* D-channel transmit byte count (rw)*/ 140 #define AM7930_IREG_DLC_DMR1 0x86 /* D-channel mode register 1 (rw) */ 141 #define AM7930_IREG_DLC_DMR2 0x87 /* D-channel mode register 2 (rw) */ 142 #define AM7930_IREG_DLC_1_7 0x88 143 #define AM7930_IREG_DLC_DRCR 0x89 /* D-channel receive byte count (ro) */ 144 #define AM7930_IREG_DLC_RNGR1 0x8a /* Random number generator LSB (rw) */ 145 #define AM7930_IREG_DLC_RNGR2 0x8b /* Random number generator MSB (rw) */ 146 #define AM7930_IREG_DLC_FRAR4 0x8c /* First rcvd byte address 4 (rw) */ 147 #define AM7930_IREG_DLC_SRAR4 0x8d /* Second rcvd byte address 4 (rw) */ 148 #define AM7930_IREG_DLC_DMR3 0x8e /* D-channel mode register 3 (rw) */ 149 #define AM7930_IREG_DLC_DMR4 0x8f /* D-channel mode register 4 (rw) */ 150 #define AM7930_IREG_DLC_12_15 0x90 151 #define AM7930_IREG_DLC_ASR 0x91 /* Address status register (ro) */ 152 #define AM7930_IREG_DLC_EFCR 0x92 /* Extended FIFO control (rw) */ 153 154 /* Peripheral Port registers */ 155 156 #define AM7930_IREG_PP_PPCR1 0xc0 /* Peripheral port control 1 (rw) */ 157 #define AM7930_PPCR1_DISABLE 0x00 158 #define AM7930_PPCR1_SBP 0x01 159 #define AM7930_PPCR1_IOM2SL 0x10 160 #define AM7930_PPCR1_IOM2MA 0x11 161 #define AM7930_IREG_PP_PPSR 0xc1 /* Peripheral port control 2 (ro) */ 162 #define AM7930_IREG_PP_PPIER 0xc2 /* Peripheral port intr enable (rw) */ 163 #define AM7930_IREG_PP_MTDR 0xc3 /* monitor transmit data (wo) */ 164 #define AM7930_IREG_PP_MRDR 0xc3 /* monitor receive data (ro) */ 165 #define AM7930_IREG_PP_CITDR0 0xc4 /* C/I transmit data register 0 (wo) */ 166 #define AM7930_IREG_PP_CIRDR0 0xc4 /* C/I receive data register 0 (ro) */ 167 #define AM7930_IREG_PP_CITDR1 0xc5 /* C/I transmit data register 1 (wo) */ 168 #define AM7930_IREG_PP_CIRDR1 0xc5 /* C/I receive data register 1 (ro) */ 169 #define AM7930_IREG_PP_PPCR2 0xc8 /* Peripheral port control 2 (rw) */
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