The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/ic/anreg.h

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    1 /*      $NetBSD: anreg.h,v 1.10 2004/01/28 15:07:52 onoe Exp $  */
    2 /*
    3  * Copyright (c) 1997, 1998, 1999
    4  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Bill Paul.
   17  * 4. Neither the name of the author nor the names of any co-contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  * $FreeBSD: src/sys/dev/an/if_anreg.h,v 1.3 2000/11/13 23:04:12 wpaul Exp $
   34  */
   35 
   36 #ifndef _DEV_IC_ANREG_H
   37 #define _DEV_IC_ANREG_H
   38 
   39 /*
   40  * Size of Aironet I/O space.
   41  */
   42 #define AN_IOSIZ                0x40
   43 
   44 /*
   45  * Hermes register definitions and what little I know about them.
   46  */
   47 
   48 /* Hermes command/status registers. */
   49 #define AN_COMMAND              0x00
   50 #define AN_PARAM0               0x02
   51 #define AN_PARAM1               0x04
   52 #define AN_PARAM2               0x06
   53 #define AN_STATUS               0x08
   54 #define AN_RESP0                0x0A
   55 #define AN_RESP1                0x0C
   56 #define AN_RESP2                0x0E
   57 #define AN_LINKSTAT             0x10
   58 
   59 /* Command register */
   60 #define AN_CMD_BUSY             0x8000 /* busy bit */
   61 #define AN_CMD_NO_ACK           0x0080 /* don't acknowledge command */
   62 #define AN_CMD_CODE_MASK        0x003F
   63 #define AN_CMD_QUAL_MASK        0x7F00
   64 
   65 /* Command codes */
   66 #define AN_CMD_NOOP             0x0000 /* no-op */
   67 #define AN_CMD_ENABLE           0x0001 /* enable */
   68 #define AN_CMD_DISABLE          0x0002 /* disable */
   69 #define AN_CMD_FORCE_SYNCLOSS   0x0003 /* force loss of sync */
   70 #define AN_CMD_FW_RESTART       0x0004 /* firmware resrart */
   71 #define AN_CMD_HOST_SLEEP       0x0005
   72 #define AN_CMD_MAGIC_PKT        0x0006
   73 #define AN_CMD_READCFG          0x0008
   74 #define AN_CMD_SET_MODE         0x0009
   75 #define AN_CMD_ALLOC_MEM        0x000A /* allocate NIC memory */
   76 #define AN_CMD_TX               0x000B /* transmit */
   77 #define AN_CMD_DEALLOC_MEM      0x000C
   78 #define AN_CMD_NOOP2            0x0010
   79 #define AN_CMD_ACCESS           0x0021
   80 #define AN_CMD_ALLOC_BUF        0x0028
   81 #define AN_CMD_PSP_NODES        0x0030
   82 #define AN_CMD_SET_PHYREG       0x003E
   83 #define AN_CMD_TX_TEST          0x003F
   84 #define AN_CMD_SLEEP            0x0085
   85 #define AN_CMD_SAVECFG          0x0108
   86 
   87 /*
   88  * Reclaim qualifier bit, applicable to the
   89  * TX command.
   90  */
   91 #define AN_RECLAIM              0x0100 /* reclaim NIC memory */
   92 
   93 /*
   94  * ACCESS command qualifier bits.
   95  */
   96 #define AN_ACCESS_READ          0x0000
   97 #define AN_ACCESS_WRITE         0x0100
   98 
   99 /*
  100  * PROGRAM command qualifier bits.
  101  */
  102 #define AN_PROGRAM_DISABLE      0x0000
  103 #define AN_PROGRAM_ENABLE_RAM   0x0100
  104 #define AN_PROGRAM_ENABLE_NVRAM 0x0200
  105 #define AN_PROGRAM_NVRAM        0x0300
  106 
  107 /* Status register values */
  108 #define AN_STAT_CMD_CODE        0x003F
  109 #define AN_STAT_CMD_RESULT      0x7F00
  110 
  111 /* Linkstat register */
  112 #define AN_LINKSTAT_ASSOCIATED          0x0400
  113 #define AN_LINKSTAT_AUTHFAIL            0x0300
  114 #define AN_LINKSTAT_ASSOC_FAIL          0x8400
  115 #define AN_LINKSTAT_DISASSOC            0x8200
  116 #define AN_LINKSTAT_DEAUTH              0x8100
  117 #define AN_LINKSTAT_SYNCLOST_TSF        0x8004
  118 #define AN_LINKSTAT_SYNCLOST_HOSTREQ    0x8003
  119 #define AN_LINKSTAT_SYNCLOST_AVGRETRY   0x8002
  120 #define AN_LINKSTAT_SYNCLOST_MAXRETRY   0x8001
  121 #define AN_LINKSTAT_SYNCLOST_MISSBEACON 0x8000
  122 
  123 /* memory handle management registers */
  124 #define AN_RX_FID               0x20
  125 #define AN_ALLOC_FID            0x22
  126 #define AN_TX_CMP_FID           0x24
  127 
  128 /*
  129  * Buffer Access Path (BAP) registers.
  130  * These are I/O channels. I believe you can use each one for
  131  * any desired purpose independently of the other. In general
  132  * though, we use BAP1 for reading and writing LTV records and
  133  * reading received data frames, and BAP0 for writing transmit
  134  * frames. This is a convention though, not a rule.
  135  */
  136 #define AN_SEL0                 0x18
  137 #define AN_SEL1                 0x1A
  138 #define AN_OFF0                 0x1C
  139 #define AN_OFF1                 0x1E
  140 #define AN_DATA0                0x36
  141 #define AN_DATA1                0x38
  142 #define AN_BAP0                 AN_DATA0
  143 #define AN_BAP1                 AN_DATA1
  144 
  145 #define AN_OFF_BUSY             0x8000
  146 #define AN_OFF_ERR              0x4000
  147 #define AN_OFF_DONE             0x2000
  148 #define AN_OFF_DATAOFF          0x0FFF
  149 
  150 /* Event registers */
  151 #define AN_EVENT_STAT           0x30    /* Event status */
  152 #define AN_INT_EN               0x32    /* Interrupt enable/disable */
  153 #define AN_EVENT_ACK            0x34    /* Ack event */
  154 
  155 /* Events */
  156 #define AN_EV_CLR_STUCK_BUSY    0x4000  /* clear stuck busy bit */
  157 #define AN_EV_WAKEREQUEST       0x2000  /* awaken from PSP mode */
  158 #define AN_EV_MIC               0x1000  /* Message Integrity Check*/
  159 #define AN_EV_TX_CPY            0x0400
  160 #define AN_EV_AWAKE             0x0100  /* station woke up from PSP mode*/
  161 #define AN_EV_LINKSTAT          0x0080  /* link status available */
  162 #define AN_EV_CMD               0x0010  /* command completed */
  163 #define AN_EV_ALLOC             0x0008  /* async alloc/reclaim completed */
  164 #define AN_EV_TX_EXC            0x0004  /* async xmit completed with failure */
  165 #define AN_EV_TX                0x0002  /* async xmit completed successfully */
  166 #define AN_EV_RX                0x0001  /* async rx completed */
  167 
  168 /* Host software registers */
  169 #define AN_SW0                  0x28
  170 #define AN_SW1                  0x2A
  171 #define AN_SW2                  0x2C
  172 #define AN_SW3                  0x2E
  173 
  174 #define AN_CNTL                 0x14
  175 
  176 #define AN_CNTL_AUX_ENA         0xC000
  177 #define AN_CNTL_AUX_ENA_STAT    0xC000
  178 #define AN_CNTL_AUX_DIS_STAT    0x0000
  179 #define AN_CNTL_AUX_ENA_CNTL    0x8000
  180 #define AN_CNTL_AUX_DIS_CNTL    0x4000
  181 
  182 #define AN_AUX_PAGE             0x3A
  183 #define AN_AUX_OFFSET           0x3C
  184 #define AN_AUX_DATA             0x3E
  185 
  186 /*
  187  * General configuration information.
  188  */
  189 #define AN_RID_GENCONFIG        0xFF10
  190 struct an_rid_genconfig {
  191         /* General configuration. */
  192         u_int16_t               an_opmode;              /* 0x02 */
  193         u_int16_t               an_rxmode;              /* 0x04 */
  194         u_int16_t               an_fragthresh;          /* 0x06 */
  195         u_int16_t               an_rtsthresh;           /* 0x08 */
  196         u_int8_t                an_macaddr[6];          /* 0x0A */
  197         u_int8_t                an_rates[8];            /* 0x10 */
  198         u_int16_t               an_shortretry_limit;    /* 0x18 */
  199         u_int16_t               an_longretry_limit;     /* 0x1A */
  200         u_int16_t               an_tx_msdu_lifetime;    /* 0x1C */
  201         u_int16_t               an_rx_msdu_lifetime;    /* 0x1E */
  202         u_int16_t               an_stationary;          /* 0x20 */
  203         u_int16_t               an_ordering;            /* 0x22 */
  204         u_int16_t               an_devtype;             /* 0x24 */
  205         u_int16_t               an_rsvd0[5];            /* 0x26 */
  206         /* Scanning associating. */
  207         u_int16_t               an_scanmode;            /* 0x30 */
  208         u_int16_t               an_probedelay;          /* 0x32 */
  209         u_int16_t               an_probe_energy_timeout;/* 0x34 */
  210         u_int16_t               an_probe_response_timeout;/*0x36 */
  211         u_int16_t               an_beacon_listen_timeout;/*0x38 */
  212         u_int16_t               an_ibss_join_net_timeout;/*0x3A */
  213         u_int16_t               an_auth_timeout;        /* 0x3C */
  214         u_int16_t               an_authtype;            /* 0x3E */
  215         u_int16_t               an_assoc_timeout;       /* 0x40 */
  216         u_int16_t               an_specified_ap_timeout;/* 0x42 */
  217         u_int16_t               an_offline_scan_interval;/*0x44 */
  218         u_int16_t               an_offline_scan_duration;/*0x46 */
  219         u_int16_t               an_link_loss_delay;     /* 0x48 */
  220         u_int16_t               an_max_beacon_lost_time;/* 0x4A */
  221         u_int16_t               an_refresh_interval;    /* 0x4C */
  222         u_int16_t               an_rsvd1;               /* 0x4E */
  223         /* Power save operation */
  224         u_int16_t               an_psave_mode;          /* 0x50 */
  225         u_int16_t               an_sleep_for_dtims;     /* 0x52 */
  226         u_int16_t               an_listen_interval;     /* 0x54 */
  227         u_int16_t               an_fast_listen_interval;/* 0x56 */
  228         u_int16_t               an_listen_decay;        /* 0x58 */
  229         u_int16_t               an_fast_listen_decay;   /* 0x5A */
  230         u_int16_t               an_rsvd2[2];            /* 0x5C */
  231         /* Ad-hoc (or AP) operation. */
  232         u_int16_t               an_beacon_period;       /* 0x60 */
  233         u_int16_t               an_atim_duration;       /* 0x62 */
  234         u_int16_t               an_rsvd3;               /* 0x64 */
  235         u_int16_t               an_ds_channel;          /* 0x66 */
  236         u_int16_t               an_rsvd4;               /* 0x68 */
  237         u_int16_t               an_dtim_period;         /* 0x6A */
  238         u_int16_t               an_rsvd5[2];            /* 0x6C */
  239         /* Radio operation. */
  240         u_int16_t               an_radiotype;           /* 0x70 */
  241         u_int16_t               an_diversity;           /* 0x72 */
  242         u_int16_t               an_tx_power;            /* 0x74 */
  243         u_int16_t               an_rss_thresh;          /* 0x76 */
  244         u_int16_t               an_modulation_type;     /* 0x78 */
  245         u_int16_t               an_short_preamble;      /* 0x7A */
  246         u_int16_t               an_home_product;        /* 0x7C */
  247         u_int16_t               an_rsvd6;               /* 0x7E */
  248         /* Aironet extensions. */
  249         u_int8_t                an_nodename[16];        /* 0x80 */
  250         u_int16_t               an_arl_thresh;          /* 0x90 */
  251         u_int16_t               an_arl_decay;           /* 0x92 */
  252         u_int16_t               an_arl_delay;           /* 0x94 */
  253         u_int8_t                an_rsvd7;               /* 0x96 */
  254         u_int8_t                an_rsvd8;               /* 0x97 */
  255         u_int8_t                an_magic_packet_action; /* 0x98 */
  256         u_int8_t                an_magic_packet_ctl;    /* 0x99 */
  257         u_int16_t               an_rsvd9;
  258         u_int16_t               an_spare[16];
  259 } __attribute__((__packed__));
  260 
  261 #define AN_OPMODE_IBSS_ADHOC                    0x0000
  262 #define AN_OPMODE_INFRASTRUCTURE_STATION        0x0001
  263 #define AN_OPMODE_AP                            0x0002
  264 #define AN_OPMODE_AP_REPEATER                   0x0003
  265 #define AN_OPMODE_UNMODIFIED_PAYLOAD            0x0100
  266 #define AN_OPMODE_AIRONET_EXTENSIONS            0x0200
  267 #define AN_OPMODE_AP_EXTENSIONS                 0x0400
  268 #define AN_OPMODE_ANTENNA_ALIGN                 0x0800
  269 #define AN_OPMODE_ETHER_LLC                     0x1000
  270 #define AN_OPMODE_LEAF_NODE                     0x2000
  271 #define AN_OPMODE_CF_POLLABLE                   0x4000
  272 #define AN_OPMODE_MIC                           0x8000
  273 
  274 #define AN_RXMODE_BC_MC_ADDR                    0x0000
  275 #define AN_RXMODE_BC_ADDR                       0x0001
  276 #define AN_RXMODE_ADDR                          0x0002
  277 #define AN_RXMODE_80211_MONITOR_CURBSS          0x0003
  278 #define AN_RXMODE_80211_MONITOR_ANYBSS          0x0004
  279 #define AN_RXMODE_LAN_MONITOR_CURBSS            0x0005
  280 #define AN_RXMODE_NO_8023_HEADER                0x0100
  281 #define AN_RXMODE_NORMALIZED_RSSI               0x0200
  282 
  283 #define AN_RATE_1MBPS                           0x0002
  284 #define AN_RATE_2MBPS                           0x0004
  285 #define AN_RATE_5_5MBPS                         0x000B
  286 #define AN_RATE_11MBPS                          0x0016
  287 
  288 #define AN_DEVTYPE_PC4500                       0x0065
  289 #define AN_DEVTYPE_PC4800                       0x006D
  290 
  291 #define AN_SCANMODE_ACTIVE                      0x0000
  292 #define AN_SCANMODE_PASSIVE                     0x0001
  293 #define AN_SCANMODE_AIRONET_ACTIVE              0x0002
  294 
  295 #define AN_AUTHTYPE_NONE                        0x0000
  296 #define AN_AUTHTYPE_OPEN                        0x0001
  297 #define AN_AUTHTYPE_SHAREDKEY                   0x0002
  298 #define AN_AUTHTYPE_MASK                        0x00ff
  299 #define AN_AUTHTYPE_PRIVACY_IN_USE              0x0100
  300 #define AN_AUTHTYPE_ALLOW_UNENCRYPTED           0x0200
  301 #define AN_AUTHTYPE_LEAP                        0x1000
  302 
  303 #define AN_PSAVE_CAM                            0x0000
  304 #define AN_PSAVE_PSP                            0x0001
  305 #define AN_PSAVE_PSP_CAM                        0x0002
  306 
  307 #define AN_RADIOTYPE_80211_FH                   0x0001
  308 #define AN_RADIOTYPE_80211_DS                   0x0002
  309 #define AN_RADIOTYPE_LM2000_DS                  0x0004
  310 
  311 #define AN_DIVERSITY_FACTORY_DEFAULT            0x0000
  312 #define AN_DIVERSITY_ANTENNA_1_ONLY             0x0001
  313 #define AN_DIVERSITY_ANTENNA_2_ONLY             0x0002
  314 #define AN_DIVERSITY_ANTENNA_1_AND_2            0x0003
  315 
  316 #define AN_TXPOWER_FACTORY_DEFAULT              0x0000
  317 #define AN_TXPOWER_50MW                         50
  318 #define AN_TXPOWER_100MW                        100
  319 #define AN_TXPOWER_250MW                        250
  320 
  321 /*
  322  * Valid SSID list. You can specify up to three SSIDs denoting
  323  * the service sets that you want to join. The first SSID always
  324  * defaults to "tsunami" which is a handy way to detect the
  325  * card.
  326  */
  327 #define AN_RID_SSIDLIST         0xFF11
  328 struct an_rid_ssidlist {
  329         struct an_rid_ssid_entry {
  330                 u_int16_t       an_ssid_len;
  331                 char            an_ssid[32];
  332         } __attribute__((__packed__)) an_entry[3];      /* 25 for fwver.5 */
  333 } __attribute__((__packed__));
  334 
  335 /*
  336  * Valid AP list.
  337  */
  338 #define AN_RID_APLIST           0xFF12
  339 struct an_rid_aplist {
  340         u_int8_t                an_ap1[8];
  341         u_int8_t                an_ap2[8];
  342         u_int8_t                an_ap3[8];
  343         u_int8_t                an_ap4[8];
  344 } __attribute__((__packed__));
  345 
  346 /*
  347  * Driver name.
  348  */
  349 #define AN_RID_DRVNAME          0xFF13
  350 struct an_rid_drvname {
  351         u_int8_t                an_drvname[16];
  352 } __attribute__((__packed__));
  353 
  354 /*
  355  * Frame encapsulation.
  356  */
  357 #define AN_RID_ENCAP            0xFF14
  358 #define AN_ENCAP_NENTS          8
  359 struct an_rid_encap {
  360         struct an_rid_encap_entry {
  361                 u_int16_t       an_ethertype;
  362                 u_int16_t       an_action;
  363         } __attribute__((__packed__)) an_entry[AN_ENCAP_NENTS];
  364 } __attribute__((__packed__));
  365 
  366 #define AN_ENCAP_ACTION_RX      0x0001
  367 #define AN_ENCAP_ACTION_TX      0x0002
  368 
  369 #define AN_RXENCAP_NONE         0x0000
  370 #define AN_RXENCAP_RFC1024      0x0001
  371 
  372 #define AN_TXENCAP_RFC1024      0x0000
  373 #define AN_TXENCAP_80211        0x0002
  374 
  375 /*
  376  * Actual config, same structure as general config (read only).
  377  */
  378 #define AN_RID_ACTUALCFG        0xFF20
  379 
  380 /*
  381  * Card capabilities (read only).
  382  */
  383 #define AN_RID_CAPABILITIES     0xFF00
  384 struct an_rid_caps {
  385         u_int8_t                an_oui[3];              /* 0x02 */
  386         u_int8_t                an_rsvd0;               /* 0x05 */
  387         u_int16_t               an_prodnum;             /* 0x06 */
  388         u_int8_t                an_manufname[32];       /* 0x08 */
  389         u_int8_t                an_prodname[16];        /* 0x28 */
  390         u_int8_t                an_prodvers[8];         /* 0x38 */
  391         u_int8_t                an_oemaddr[6];          /* 0x40 */
  392         u_int8_t                an_aironetaddr[6];      /* 0x46 */
  393         u_int16_t               an_radiotype;           /* 0x4C */
  394         u_int16_t               an_regdomain;           /* 0x4E */
  395         u_int8_t                an_callid[6];           /* 0x50 */
  396         u_int8_t                an_rates[8];            /* 0x56 */
  397         u_int8_t                an_rx_diversity;        /* 0x5E */
  398         u_int8_t                an_tx_diversity;        /* 0x5F */
  399         u_int16_t               an_tx_powerlevels[8];   /* 0x60 */
  400         u_int16_t               an_hwrev;               /* 0x70 */
  401         u_int16_t               an_hwcaps;              /* 0x72 */
  402         u_int16_t               an_temprange;           /* 0x74 */
  403         u_int16_t               an_fwrev;               /* 0x76 */
  404         u_int16_t               an_fwsubrev;            /* 0x78 */
  405         u_int16_t               an_ifacerev;            /* 0x7A */
  406         u_int16_t               an_softcaps;            /* 0x7C */
  407         u_int16_t               an_bootblockrev;        /* 0x7E */
  408         u_int16_t               an_req_hw_support;      /* 0x80 */
  409         /* extended capabilities */
  410         u_int16_t               an_ext_softcaps;        /* 0x82 */
  411         u_int16_t               an_spare[34];
  412 } __attribute__((__packed__));
  413 
  414 #define AN_REGDOMAIN_USA        0
  415 #define AN_REGDOMAIN_EUROPE     1
  416 #define AN_REGDOMAIN_JAPAN      2
  417 #define AN_REGDOMAIN_SPAIN      3
  418 #define AN_REGDOMAIN_FRANCE     4
  419 #define AN_REGDOMAIN_BELGIUM    5
  420 #define AN_REGDOMAIN_ISRAEL     6
  421 #define AN_REGDOMAIN_CANADA     7
  422 #define AN_REGDOMAIN_AUSTRALIA  8
  423 #define AN_REGDOMAIN_JAPANWIDE  9
  424 
  425 #define AN_SOFTCAPS_WEP         0x0002
  426 #define AN_SOFTCAPS_RSSIMAP     0x0008
  427 #define AN_SOFTCAPS_WEP128      0x0100
  428 
  429 #define AN_EXT_SOFTCAPS_MIC     0x0001
  430 
  431 /*
  432  * Access point (read only)
  433  */
  434 #define AN_RID_APINFO           0xFF01
  435 struct an_rid_apinfo {
  436         u_int16_t               an_tim_addr;
  437         u_int16_t               an_airo_addr;
  438 } __attribute__((__packed__));
  439 
  440 /*
  441  * Radio info (read only).
  442  */
  443 #define AN_RID_RADIOINFO        0xFF02
  444 
  445 /*
  446  * Status (read only). Note: the manual claims this RID is 108 bytes
  447  * long (0x6A is the last datum, which is 2 bytes long) however when
  448  * this RID is read from the NIC, it returns a length of 110 or 112.
  449  * To be on the safe side, this structure is padded with 4 extra 16-bit
  450  * words. (There is a misprint in the manual which says the macaddr
  451  * field is 8 bytes long.)
  452  *
  453  * Also, the channel_set and current_channel fields appear to be
  454  * reversed. Either that, or the hop_period field is unused.
  455  */
  456 #define AN_RID_STATUS           0xFF50
  457 struct an_rid_status {
  458         u_int8_t                an_macaddr[6];          /* 0x02 */
  459         u_int16_t               an_opmode;              /* 0x08 */
  460         u_int16_t               an_errcode;             /* 0x0A */
  461         u_int16_t               an_cur_signal_strength; /* 0x0C */
  462         u_int16_t               an_ssidlen;             /* 0x0E */
  463         u_int8_t                an_ssid[32];            /* 0x10 */
  464         u_int8_t                an_ap_name[16];         /* 0x30 */
  465         u_int8_t                an_cur_bssid[6];        /* 0x40 */
  466         u_int8_t                an_prev_bssid1[6];      /* 0x46 */
  467         u_int8_t                an_prev_bssid2[6];      /* 0x4C */
  468         u_int8_t                an_prev_bssid3[6];      /* 0x52 */
  469         u_int16_t               an_beacon_period;       /* 0x58 */
  470         u_int16_t               an_dtim_period;         /* 0x5A */
  471         u_int16_t               an_atim_duration;       /* 0x5C */
  472         u_int16_t               an_hop_period;          /* 0x5E */
  473         u_int16_t               an_cur_channel;         /* 0x62 */
  474         u_int16_t               an_channel_set;         /* 0x60 */
  475         u_int16_t               an_hops_to_backbone;    /* 0x64 */
  476         u_int16_t               an_ap_total_load;       /* 0x66 */
  477         u_int16_t               an_our_generated_load;  /* 0x68 */
  478         u_int16_t               an_accumulated_arl;     /* 0x6A */
  479         u_int16_t               an_cur_signal_quality;  /* 0x6C */
  480         u_int16_t               an_current_tx_rate;     /* 0x6E */
  481         u_int16_t               an_ap_device;           /* 0x70 */
  482         u_int16_t               an_normalized_rssi;     /* 0x72 */
  483         u_int16_t               an_short_pre_in_use;    /* 0x74 */
  484         u_int8_t                an_ap_ip_addr[4];       /* 0x76 */
  485         u_int16_t               an_max_noise_prev_sec;  /* 0x7A */
  486         u_int16_t               an_avg_noise_prev_min;  /* 0x7C */
  487         u_int16_t               an_max_noise_prev_min;  /* 0x7E */
  488         u_int16_t               an_spare[11];
  489 } __attribute__((__packed__));
  490 
  491 #define AN_STATUS_OPMODE_CONFIGURED             0x0001
  492 #define AN_STATUS_OPMODE_MAC_ENABLED            0x0002
  493 #define AN_STATUS_OPMODE_RX_ENABLED             0x0004
  494 #define AN_STATUS_OPMODE_IN_SYNC                0x0010
  495 #define AN_STATUS_OPMODE_ASSOCIATED             0x0020
  496 #define AN_STATUS_OPMODE_ERROR                  0x8000
  497 
  498 /*
  499  * Statistics
  500  */
  501 #define AN_RID_16BITS_CUM       0xFF60  /* Cumulative 16-bit stats counters */
  502 #define AN_RID_16BITS_DELTA     0xFF61  /* 16-bit stats (since last clear) */
  503 #define AN_RID_16BITS_DELTACLR  0xFF62  /* 16-bit stats, clear on read */
  504 #define AN_RID_32BITS_CUM       0xFF68  /* Cumulative 32-bit stats counters */
  505 #define AN_RID_32BITS_DELTA     0xFF69  /* 32-bit stats (since last clear) */
  506 #define AN_RID_32BITS_DELTACLR  0xFF6A  /* 32-bit stats, clear on read */
  507 
  508 /*
  509  * Grrr. The manual says the statistics record is 384 bytes in length,
  510  * but the card says the record is 404 bytes. There's some padding left
  511  * at the end of this structure to account for any discrepancies.
  512  */
  513 struct an_rid_stats {
  514         u_int16_t               an_spacer;              /* 0x02 */
  515         u_int32_t               an_rx_overruns;         /* 0x04 */
  516         u_int32_t               an_rx_plcp_csum_errs;   /* 0x08 */
  517         u_int32_t               an_rx_plcp_format_errs; /* 0x0C */
  518         u_int32_t               an_rx_plcp_len_errs;    /* 0x10 */
  519         u_int32_t               an_rx_mac_crc_errs;     /* 0x14 */
  520         u_int32_t               an_rx_mac_crc_ok;       /* 0x18 */
  521         u_int32_t               an_rx_wep_errs;         /* 0x1C */
  522         u_int32_t               an_rx_wep_ok;           /* 0x20 */
  523         u_int32_t               an_retry_long;          /* 0x24 */
  524         u_int32_t               an_retry_short;         /* 0x28 */
  525         u_int32_t               an_retry_max;           /* 0x2C */
  526         u_int32_t               an_no_ack;              /* 0x30 */
  527         u_int32_t               an_no_cts;              /* 0x34 */
  528         u_int32_t               an_rx_ack_ok;           /* 0x38 */
  529         u_int32_t               an_rx_cts_ok;           /* 0x3C */
  530         u_int32_t               an_tx_ack_ok;           /* 0x40 */
  531         u_int32_t               an_tx_rts_ok;           /* 0x44 */
  532         u_int32_t               an_tx_cts_ok;           /* 0x48 */
  533         u_int32_t               an_tx_lmac_mcasts;      /* 0x4C */
  534         u_int32_t               an_tx_lmac_bcasts;      /* 0x50 */
  535         u_int32_t               an_tx_lmac_ucast_frags; /* 0x54 */
  536         u_int32_t               an_tx_lmac_ucasts;      /* 0x58 */
  537         u_int32_t               an_tx_beacons;          /* 0x5C */
  538         u_int32_t               an_rx_beacons;          /* 0x60 */
  539         u_int32_t               an_tx_single_cols;      /* 0x64 */
  540         u_int32_t               an_tx_multi_cols;       /* 0x68 */
  541         u_int32_t               an_tx_defers_no;        /* 0x6C */
  542         u_int32_t               an_tx_defers_prot;      /* 0x70 */
  543         u_int32_t               an_tx_defers_energy;    /* 0x74 */
  544         u_int32_t               an_rx_dups;             /* 0x78 */
  545         u_int32_t               an_rx_partial;          /* 0x7C */
  546         u_int32_t               an_tx_too_old;          /* 0x80 */
  547         u_int32_t               an_rx_too_old;          /* 0x84 */
  548         u_int32_t               an_lostsync_max_retries;/* 0x88 */
  549         u_int32_t               an_lostsync_missed_beacons;/* 0x8C */
  550         u_int32_t               an_lostsync_arl_exceeded;/*0x90 */
  551         u_int32_t               an_lostsync_deauthed;   /* 0x94 */
  552         u_int32_t               an_lostsync_disassociated;/*0x98 */
  553         u_int32_t               an_lostsync_tsf_timing; /* 0x9C */
  554         u_int32_t               an_tx_host_mcasts;      /* 0xA0 */
  555         u_int32_t               an_tx_host_bcasts;      /* 0xA4 */
  556         u_int32_t               an_tx_host_ucasts;      /* 0xA8 */
  557         u_int32_t               an_tx_host_failed;      /* 0xAC */
  558         u_int32_t               an_rx_host_mcasts;      /* 0xB0 */
  559         u_int32_t               an_rx_host_bcasts;      /* 0xB4 */
  560         u_int32_t               an_rx_host_ucasts;      /* 0xB8 */
  561         u_int32_t               an_rx_host_discarded;   /* 0xBC */
  562         u_int32_t               an_tx_hmac_mcasts;      /* 0xC0 */
  563         u_int32_t               an_tx_hmac_bcasts;      /* 0xC4 */
  564         u_int32_t               an_tx_hmac_ucasts;      /* 0xC8 */
  565         u_int32_t               an_tx_hmac_failed;      /* 0xCC */
  566         u_int32_t               an_rx_hmac_mcasts;      /* 0xD0 */
  567         u_int32_t               an_rx_hmac_bcasts;      /* 0xD4 */
  568         u_int32_t               an_rx_hmac_ucasts;      /* 0xD8 */
  569         u_int32_t               an_rx_hmac_discarded;   /* 0xDC */
  570         u_int32_t               an_tx_hmac_accepted;    /* 0xE0 */
  571         u_int32_t               an_ssid_mismatches;     /* 0xE4 */
  572         u_int32_t               an_ap_mismatches;       /* 0xE8 */
  573         u_int32_t               an_rates_mismatches;    /* 0xEC */
  574         u_int32_t               an_auth_rejects;        /* 0xF0 */
  575         u_int32_t               an_auth_timeouts;       /* 0xF4 */
  576         u_int32_t               an_assoc_rejects;       /* 0xF8 */
  577         u_int32_t               an_assoc_timeouts;      /* 0xFC */
  578         u_int32_t               an_reason_outside_table;/* 0x100 */
  579         u_int32_t               an_reason1;             /* 0x104 */
  580         u_int32_t               an_reason2;             /* 0x108 */
  581         u_int32_t               an_reason3;             /* 0x10C */
  582         u_int32_t               an_reason4;             /* 0x110 */
  583         u_int32_t               an_reason5;             /* 0x114 */
  584         u_int32_t               an_reason6;             /* 0x118 */
  585         u_int32_t               an_reason7;             /* 0x11C */
  586         u_int32_t               an_reason8;             /* 0x120 */
  587         u_int32_t               an_reason9;             /* 0x124 */
  588         u_int32_t               an_reason10;            /* 0x128 */
  589         u_int32_t               an_reason11;            /* 0x12C */
  590         u_int32_t               an_reason12;            /* 0x130 */
  591         u_int32_t               an_reason13;            /* 0x134 */
  592         u_int32_t               an_reason14;            /* 0x138 */
  593         u_int32_t               an_reason15;            /* 0x13C */
  594         u_int32_t               an_reason16;            /* 0x140 */
  595         u_int32_t               an_reason17;            /* 0x144 */
  596         u_int32_t               an_reason18;            /* 0x148 */
  597         u_int32_t               an_reason19;            /* 0x14C */
  598         u_int32_t               an_rx_mgmt_pkts;        /* 0x150 */
  599         u_int32_t               an_tx_mgmt_pkts;        /* 0x154 */
  600         u_int32_t               an_rx_refresh_pkts;     /* 0x158 */
  601         u_int32_t               an_tx_refresh_pkts;     /* 0x15C */
  602         u_int32_t               an_rx_poll_pkts;        /* 0x160 */
  603         u_int32_t               an_tx_poll_pkts;        /* 0x164 */
  604         u_int32_t               an_host_retries;        /* 0x168 */
  605         u_int32_t               an_lostsync_hostreq;    /* 0x16C */
  606         u_int32_t               an_host_tx_bytes;       /* 0x170 */
  607         u_int32_t               an_host_rx_bytes;       /* 0x174 */
  608         u_int32_t               an_uptime_usecs;        /* 0x178 */
  609         u_int32_t               an_uptime_secs;         /* 0x17C */
  610         u_int32_t               an_lostsync_better_ap;  /* 0x180 */
  611         u_int32_t               an_rsvd[10];
  612 } __attribute__((__packed__));
  613 
  614 /*
  615  * Volatile WEP Key
  616  */
  617 #define AN_RID_WEP_VOLATILE     0xFF15  /* Volatile WEP Key */
  618 struct an_rid_wepkey {
  619         u_int16_t               an_key_index;           /* 0x02 */
  620         u_int8_t                an_mac_addr[6];         /* 0x04 */
  621         u_int16_t               an_key_len;             /* 0x0A */
  622         u_int8_t                an_key[16];             /* 0x0C */
  623 } __attribute__((__packed__));
  624 
  625 /*
  626  * Persistent WEP Key
  627  */
  628 #define AN_RID_WEP_PERSISTENT   0xFF16  /* Persistent WEP Key */
  629 
  630 /*
  631  * LEAP Key
  632  */
  633 #define AN_RID_LEAP_USER        0xFF23  /* User Name for LEAP */
  634 #define AN_RID_LEAP_PASS        0xFF24  /* Password for LEAP */
  635 struct an_rid_leapkey {
  636         u_int16_t               an_key_len;             /* 0x02 */
  637         u_int8_t                an_key[32];             /* 0x04 */
  638 } __attribute__((__packed__));
  639 
  640 /*
  641  * MIC
  642  */
  643 #define AN_RID_MIC              0xFF57  /* Message Integrity Check */
  644 struct an_rid_mic {
  645         u_int16_t               an_mic_state;           /* 0x02 */
  646         u_int16_t               an_mic_mcast_valid;     /* 0x04 */
  647         u_int8_t                an_mic_mcast[16];       /* 0x06 */
  648         u_int16_t               an_mic_ucast_valid;     /* 0x16 */
  649         u_int8_t                an_mic_ucast[16];       /* 0x18 */
  650 } __attribute__((__packed__));
  651 
  652 /*
  653  * Receive frame structure.
  654  */
  655 struct an_rxframe {
  656         u_int32_t               an_rx_time;             /* 0x00 */
  657         u_int16_t               an_rx_status;           /* 0x04 */
  658         u_int16_t               an_rx_payload_len;      /* 0x06 */
  659         u_int8_t                an_rsvd0;               /* 0x08 */
  660         u_int8_t                an_rx_signal_strength;  /* 0x09 */
  661         u_int8_t                an_rx_rate;             /* 0x0A */
  662         u_int8_t                an_rx_chan;             /* 0x0B */
  663         u_int8_t                an_rx_assoc_cnt;        /* 0x0C */
  664         u_int8_t                an_rsvd1[3];            /* 0x0D */
  665         u_int8_t                an_plcp_hdr[4];         /* 0x10 */
  666         struct ieee80211_frame_addr4    an_whdr;
  667         u_int16_t               an_gaplen;              /* 0x32 */
  668 } __attribute__((__packed__));
  669 #define AN_RXGAP_MAX    8
  670 
  671 /*
  672  * Transmit frame structure.
  673  */
  674 struct an_txframe {
  675         u_int32_t               an_tx_sw;               /* 0x00 */
  676         u_int16_t               an_tx_status;           /* 0x04 */
  677         u_int16_t               an_tx_payload_len;      /* 0x06 */
  678         u_int16_t               an_tx_ctl;              /* 0x08 */
  679         u_int16_t               an_tx_assoc_id;         /* 0x0A */
  680         u_int16_t               an_tx_retry;            /* 0x0C */
  681         u_int8_t                an_tx_assoc_cnt;        /* 0x0E */
  682         u_int8_t                an_tx_rate;             /* 0x0F */
  683         u_int8_t                an_tx_max_long_retries; /* 0x10 */
  684         u_int8_t                an_tx_max_short_retries; /*0x11 */
  685         u_int8_t                an_rsvd0[2];            /* 0x12 */
  686         struct ieee80211_frame_addr4    an_whdr;
  687         u_int16_t               an_gaplen;              /* 0x32 */
  688 } __attribute__((__packed__));
  689 
  690 #define AN_TXGAP_802_3  0
  691 #define AN_TXGAP_802_11 6
  692 
  693 struct an_802_3_hdr {
  694         u_int16_t               an_802_3_status;
  695         u_int16_t               an_802_3_payload_len;
  696         u_int8_t                an_dst_addr[6];
  697         u_int8_t                an_src_addr[6];
  698 } __attribute__((__packed__));
  699 
  700 #define AN_TXSTAT_EXCESS_RETRY  0x0002
  701 #define AN_TXSTAT_LIFE_EXCEEDED 0x0004
  702 #define AN_TXSTAT_AID_FAIL      0x0008
  703 #define AN_TXSTAT_MAC_DISABLED  0x0010
  704 #define AN_TXSTAT_ASSOC_LOST    0x0020
  705 
  706 #define AN_TXCTL_RSVD           0x0001
  707 #define AN_TXCTL_TXOK_INTR      0x0002
  708 #define AN_TXCTL_TXERR_INTR     0x0004
  709 #define AN_TXCTL_HEADER_TYPE    0x0008
  710 #define AN_TXCTL_PAYLOAD_TYPE   0x0010
  711 #define AN_TXCTL_NORELEASE      0x0020
  712 #define AN_TXCTL_NORETRIES      0x0040
  713 #define AN_TXCTL_CLEAR_AID      0x0080
  714 #define AN_TXCTL_STRICT_ORDER   0x0100
  715 #define AN_TXCTL_USE_RTS        0x0200
  716 
  717 #define AN_HEADERTYPE_8023      0x0000
  718 #define AN_HEADERTYPE_80211     0x0008
  719 
  720 #define AN_PAYLOADTYPE_ETHER    0x0000
  721 #define AN_PAYLOADTYPE_LLC      0x0010
  722 
  723 #define AN_TXCTL_80211  \
  724         (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_80211|    \
  725         AN_PAYLOADTYPE_LLC|AN_TXCTL_NORELEASE)
  726 
  727 #define AN_TXCTL_8023   \
  728         (AN_TXCTL_TXOK_INTR|AN_TXCTL_TXERR_INTR|AN_HEADERTYPE_8023|     \
  729         AN_PAYLOADTYPE_ETHER|AN_TXCTL_NORELEASE)
  730 
  731 #define AN_STAT_BADCRC          0x0001
  732 #define AN_STAT_UNDECRYPTABLE   0x0002
  733 #define AN_STAT_ERRSTAT         0x0003
  734 #define AN_STAT_MAC_PORT        0x0700
  735 #define AN_STAT_1042            0x2000  /* RFC1042 encoded */
  736 #define AN_STAT_TUNNEL          0x4000  /* Bridge-tunnel encoded */
  737 #define AN_STAT_WMP_MSG         0x6000  /* WaveLAN-II management protocol */
  738 #define AN_RXSTAT_MSG_TYPE      0xE000
  739 
  740 #define AN_ENC_TX_802_3         0x00
  741 #define AN_ENC_TX_802_11        0x11
  742 #define AN_ENC_TX_E_II          0x0E
  743 
  744 #define AN_ENC_TX_1042          0x00
  745 #define AN_ENC_TX_TUNNEL        0xF8
  746 
  747 #define AN_TXCNTL_MACPORT       0x00FF
  748 #define AN_TXCNTL_STRUCTTYPE    0xFF00
  749 
  750 #endif  /* _DEV_IC_ANREG_H */

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