FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/ar5210reg.h
1 /* $OpenBSD: ar5210reg.h,v 1.14 2022/01/09 05:42:38 jsg Exp $ */
2
3 /*
4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * Known registers of the Atheros AR5000 Wireless LAN chipset
21 * (AR5210 + AR5110).
22 */
23
24 #ifndef _AR5K_AR5210_REG_H
25 #define _AR5K_AR5210_REG_H
26
27 /*
28 * First transmit queue descriptor pointer register ("data queue")
29 */
30 #define AR5K_AR5210_TXDP0 0x0000
31
32 /*
33 * Second transmit queue descriptor pointer register ("beacon queue")
34 */
35 #define AR5K_AR5210_TXDP1 0x0004
36
37 /*
38 * Command register
39 */
40 #define AR5K_AR5210_CR 0x0008
41 #define AR5K_AR5210_CR_TXE0 0x00000001
42 #define AR5K_AR5210_CR_TXE1 0x00000002
43 #define AR5K_AR5210_CR_RXE 0x00000004
44 #define AR5K_AR5210_CR_TXD0 0x00000008
45 #define AR5K_AR5210_CR_TXD1 0x00000010
46 #define AR5K_AR5210_CR_RXD 0x00000020
47 #define AR5K_AR5210_CR_SWI 0x00000040
48
49 /*
50 * Receive queue descriptor pointer register
51 */
52 #define AR5K_AR5210_RXDP 0x000c
53
54 /*
55 * Configuration and status register
56 */
57 #define AR5K_AR5210_CFG 0x0014
58 #define AR5K_AR5210_CFG_SWTD 0x00000001
59 #define AR5K_AR5210_CFG_SWTB 0x00000002
60 #define AR5K_AR5210_CFG_SWRD 0x00000004
61 #define AR5K_AR5210_CFG_SWRB 0x00000008
62 #define AR5K_AR5210_CFG_SWRG 0x00000010
63 #define AR5K_AR5210_CFG_EEBS 0x00000200
64 #define AR5K_AR5210_CFG_TXCNT 0x00007800
65 #define AR5K_AR5210_CFG_TXCNT_S 11
66 #define AR5K_AR5210_CFG_TXFSTAT 0x00008000
67 #define AR5K_AR5210_CFG_TXFSTRT 0x00010000
68
69 /*
70 * Interrupt service register
71 */
72 #define AR5K_AR5210_ISR 0x001c
73 #define AR5K_AR5210_ISR_RXOK 0x00000001
74 #define AR5K_AR5210_ISR_RXDESC 0x00000002
75 #define AR5K_AR5210_ISR_RXERR 0x00000004
76 #define AR5K_AR5210_ISR_RXNOFRM 0x00000008
77 #define AR5K_AR5210_ISR_RXEOL 0x00000010
78 #define AR5K_AR5210_ISR_RXORN 0x00000020
79 #define AR5K_AR5210_ISR_TXOK 0x00000040
80 #define AR5K_AR5210_ISR_TXDESC 0x00000080
81 #define AR5K_AR5210_ISR_TXERR 0x00000100
82 #define AR5K_AR5210_ISR_TXNOFRM 0x00000200
83 #define AR5K_AR5210_ISR_TXEOL 0x00000400
84 #define AR5K_AR5210_ISR_TXURN 0x00000800
85 #define AR5K_AR5210_ISR_MIB 0x00001000
86 #define AR5K_AR5210_ISR_SWI 0x00002000
87 #define AR5K_AR5210_ISR_RXPHY 0x00004000
88 #define AR5K_AR5210_ISR_RXKCM 0x00008000
89 #define AR5K_AR5210_ISR_SWBA 0x00010000
90 #define AR5K_AR5210_ISR_BRSSI 0x00020000
91 #define AR5K_AR5210_ISR_BMISS 0x00040000
92 #define AR5K_AR5210_ISR_MCABT 0x00100000
93 #define AR5K_AR5210_ISR_SSERR 0x00200000
94 #define AR5K_AR5210_ISR_DPERR 0x00400000
95 #define AR5K_AR5210_ISR_GPIO 0x01000000
96 #define AR5K_AR5210_ISR_FATAL ( \
97 AR5K_AR5210_ISR_MCABT | AR5K_AR5210_ISR_SSERR | \
98 AR5K_AR5210_ISR_DPERR | AR5K_AR5210_ISR_RXORN \
99 )
100
101 /*
102 * Interrupt mask register
103 */
104 #define AR5K_AR5210_IMR 0x0020
105 #define AR5K_AR5210_IMR_RXOK 0x00000001
106 #define AR5K_AR5210_IMR_RXDESC 0x00000002
107 #define AR5K_AR5210_IMR_RXERR 0x00000004
108 #define AR5K_AR5210_IMR_RXNOFRM 0x00000008
109 #define AR5K_AR5210_IMR_RXEOL 0x00000010
110 #define AR5K_AR5210_IMR_RXORN 0x00000020
111 #define AR5K_AR5210_IMR_TXOK 0x00000040
112 #define AR5K_AR5210_IMR_TXDESC 0x00000080
113 #define AR5K_AR5210_IMR_TXERR 0x00000100
114 #define AR5K_AR5210_IMR_TXNOFRM 0x00000200
115 #define AR5K_AR5210_IMR_TXEOL 0x00000400
116 #define AR5K_AR5210_IMR_TXURN 0x00000800
117 #define AR5K_AR5210_IMR_MIB 0x00001000
118 #define AR5K_AR5210_IMR_SWI 0x00002000
119 #define AR5K_AR5210_IMR_RXPHY 0x00004000
120 #define AR5K_AR5210_IMR_RXKCM 0x00008000
121 #define AR5K_AR5210_IMR_SWBA 0x00010000
122 #define AR5K_AR5210_IMR_BRSSI 0x00020000
123 #define AR5K_AR5210_IMR_BMISS 0x00040000
124 #define AR5K_AR5210_IMR_MCABT 0x00100000
125 #define AR5K_AR5210_IMR_SSERR 0x00200000
126 #define AR5K_AR5210_IMR_DPERR 0x00400000
127 #define AR5K_AR5210_IMR_GPIO 0x01000000
128
129 /*
130 * Interrupt enable register
131 */
132 #define AR5K_AR5210_IER 0x0024
133 #define AR5K_AR5210_IER_DISABLE 0x00000000
134 #define AR5K_AR5210_IER_ENABLE 0x00000001
135
136 /*
137 * Beacon control register
138 */
139 #define AR5K_AR5210_BCR 0x0028
140 #define AR5K_AR5210_BCR_AP 0x00000000
141 #define AR5K_AR5210_BCR_ADHOC 0x00000001
142 #define AR5K_AR5210_BCR_BDMAE 0x00000002
143 #define AR5K_AR5210_BCR_TQ1FV 0x00000004
144 #define AR5K_AR5210_BCR_TQ1V 0x00000008
145 #define AR5K_AR5210_BCR_BCGET 0x00000010
146
147 /*
148 * Beacon status register
149 */
150 #define AR5K_AR5210_BSR 0x002c
151 #define AR5K_AR5210_BSR_BDLYSW 0x00000001
152 #define AR5K_AR5210_BSR_BDLYDMA 0x00000002
153 #define AR5K_AR5210_BSR_TXQ1F 0x00000004
154 #define AR5K_AR5210_BSR_ATIMDLY 0x00000008
155 #define AR5K_AR5210_BSR_SNPBCMD 0x00000100
156 #define AR5K_AR5210_BSR_SNPBDMAE 0x00000200
157 #define AR5K_AR5210_BSR_SNPTQ1FV 0x00000400
158 #define AR5K_AR5210_BSR_SNPTQ1V 0x00000800
159 #define AR5K_AR5210_BSR_SNAPPEDBCRVALID 0x00001000
160 #define AR5K_AR5210_BSR_SWBA_CNT 0x00ff0000
161
162 /*
163 * DMA size definitions
164 */
165 typedef enum {
166 AR5K_AR5210_DMASIZE_4B = 0,
167 AR5K_AR5210_DMASIZE_8B,
168 AR5K_AR5210_DMASIZE_16B,
169 AR5K_AR5210_DMASIZE_32B,
170 AR5K_AR5210_DMASIZE_64B,
171 AR5K_AR5210_DMASIZE_128B,
172 AR5K_AR5210_DMASIZE_256B,
173 AR5K_AR5210_DMASIZE_512B
174 } ar5k_ar5210_dmasize_t;
175
176 /*
177 * Transmit configuration register
178 */
179 #define AR5K_AR5210_TXCFG 0x0030
180 #define AR5K_AR5210_TXCFG_SDMAMR 0x00000007
181 #define AR5K_AR5210_TXCFG_TXFSTP 0x00000008
182 #define AR5K_AR5210_TXCFG_TXFULL 0x00000070
183 #define AR5K_AR5210_TXCFG_TXCONT_EN 0x00000080
184
185 /*
186 * Receive configuration register
187 */
188 #define AR5K_AR5210_RXCFG 0x0034
189 #define AR5K_AR5210_RXCFG_SDMAMW 0x00000007
190 #define AR5K_AR5210_RXCFG_ZLFDMA 0x00000010
191
192 /*
193 * MIB control register
194 */
195 #define AR5K_AR5210_MIBC 0x0040
196 #define AR5K_AR5210_MIBC_COW 0x00000001
197 #define AR5K_AR5210_MIBC_FMC 0x00000002
198 #define AR5K_AR5210_MIBC_CMC 0x00000004
199 #define AR5K_AR5210_MIBC_MCS 0x00000008
200
201 /*
202 * Timeout prescale register
203 */
204 #define AR5K_AR5210_TOPS 0x0044
205
206 /*
207 * Receive timeout register (no frame received)
208 */
209 #define AR5K_AR5210_RXNOFRM 0x0048
210
211 /*
212 * Transmit timeout register (no frame sent)
213 */
214 #define AR5K_AR5210_TXNOFRM 0x004c
215
216 /*
217 * Receive frame gap timeout register
218 */
219 #define AR5K_AR5210_RPGTO 0x0050
220
221 /*
222 * Receive frame count limit register
223 */
224 #define AR5K_AR5210_RFCNT 0x0054
225 #define AR5K_AR5210_RFCNT_RFCL 0x0000000f
226
227 /*
228 * Misc settings/status register
229 */
230 #define AR5K_AR5210_MISC 0x0058
231 #define AR5K_AR5210_MISC_LED_DECAY 0x001c0000
232 #define AR5K_AR5210_MISC_LED_BLINK 0x00e00000
233
234 /*
235 * Reset control register
236 */
237 #define AR5K_AR5210_RC 0x4000
238 #define AR5K_AR5210_RC_PCU 0x00000001
239 #define AR5K_AR5210_RC_DMA 0x00000002
240 #define AR5K_AR5210_RC_MAC 0x00000004
241 #define AR5K_AR5210_RC_PHY 0x00000008
242 #define AR5K_AR5210_RC_PCI 0x00000010
243 #define AR5K_AR5210_RC_CHIP ( \
244 AR5K_AR5210_RC_PCU | AR5K_AR5210_RC_DMA | \
245 AR5K_AR5210_RC_MAC | AR5K_AR5210_RC_PHY \
246 )
247
248 /*
249 * Sleep control register
250 */
251 #define AR5K_AR5210_SCR 0x4004
252 #define AR5K_AR5210_SCR_SLDUR 0x0000ffff
253 #define AR5K_AR5210_SCR_SLE 0x00030000
254 #define AR5K_AR5210_SCR_SLE_WAKE 0x00000000
255 #define AR5K_AR5210_SCR_SLE_SLP 0x00010000
256 #define AR5K_AR5210_SCR_SLE_ALLOW 0x00020000
257
258 /*
259 * Interrupt pending register
260 */
261 #define AR5K_AR5210_INTPEND 0x4008
262 #define AR5K_AR5210_INTPEND_IP 0x00000001
263
264 /*
265 * Sleep force register
266 */
267 #define AR5K_AR5210_SFR 0x400c
268 #define AR5K_AR5210_SFR_SF 0x00000001
269
270 /*
271 * PCI configuration register
272 */
273 #define AR5K_AR5210_PCICFG 0x4010
274 #define AR5K_AR5210_PCICFG_EEAE 0x00000001
275 #define AR5K_AR5210_PCICFG_CLKRUNEN 0x00000004
276 #define AR5K_AR5210_PCICFG_LED_PEND 0x00000020
277 #define AR5K_AR5210_PCICFG_LED_ACT 0x00000040
278 #define AR5K_AR5210_PCICFG_SL_INTEN 0x00000800
279 #define AR5K_AR5210_PCICFG_LED_BCTL 0x00001000
280 #define AR5K_AR5210_PCICFG_SL_INPEN 0x00002800
281 #define AR5K_AR5210_PCICFG_SPWR_DN 0x00010000
282
283 /*
284 * "General Purpose Input/Output" (GPIO) control register
285 */
286 #define AR5K_AR5210_GPIOCR 0x4014
287 #define AR5K_AR5210_GPIOCR_INT_ENA 0x00008000
288 #define AR5K_AR5210_GPIOCR_INT_SELL 0x00000000
289 #define AR5K_AR5210_GPIOCR_INT_SELH 0x00010000
290 #define AR5K_AR5210_GPIOCR_IN(n) (0 << ((n) * 2))
291 #define AR5K_AR5210_GPIOCR_OUT0(n) (1 << ((n) * 2))
292 #define AR5K_AR5210_GPIOCR_OUT1(n) (2 << ((n) * 2))
293 #define AR5K_AR5210_GPIOCR_OUT(n) (3 << ((n) * 2))
294 #define AR5K_AR5210_GPIOCR_ALL(n) (3<< ((n) * 2))
295 #define AR5K_AR5210_GPIOCR_INT_SEL(n) ((n) << 12)
296
297 #define AR5K_AR5210_NUM_GPIO 6
298
299 /*
300 * "General Purpose Input/Output" (GPIO) data output register
301 */
302 #define AR5K_AR5210_GPIODO 0x4018
303
304 /*
305 * "General Purpose Input/Output" (GPIO) data input register
306 */
307 #define AR5K_AR5210_GPIODI 0x401c
308 #define AR5K_AR5210_GPIOD_MASK 0x0000002f
309
310 /*
311 * Silicon revision register
312 */
313 #define AR5K_AR5210_SREV 0x4020
314 #define AR5K_AR5210_SREV_REV 0x0000000f
315 #define AR5K_AR5210_SREV_REV_S 0
316 #define AR5K_AR5210_SREV_VER 0x000000ff
317 #define AR5K_AR5210_SREV_VER_S 4
318
319 /*
320 * EEPROM access registers
321 */
322 #define AR5K_AR5210_EEPROM_BASE 0x6000
323 #define AR5K_AR5210_EEPROM_RDATA 0x6800
324 #define AR5K_AR5210_EEPROM_STATUS 0x6c00
325 #define AR5K_AR5210_EEPROM_STAT_RDERR 0x0001
326 #define AR5K_AR5210_EEPROM_STAT_RDDONE 0x0002
327 #define AR5K_AR5210_EEPROM_STAT_WRERR 0x0004
328 #define AR5K_AR5210_EEPROM_STAT_WRDONE 0x0008
329
330 /*
331 * PCU registers
332 */
333
334 #define AR5K_AR5210_PCU_MIN 0x8000
335 #define AR5K_AR5210_PCU_MAX 0x8fff
336
337 /*
338 * First station id register (MAC address in lower 32 bits)
339 */
340 #define AR5K_AR5210_STA_ID0 0x8000
341
342 /*
343 * Second station id register (MAC address in upper 16 bits)
344 */
345 #define AR5K_AR5210_STA_ID1 0x8004
346 #define AR5K_AR5210_STA_ID1_AP 0x00010000
347 #define AR5K_AR5210_STA_ID1_ADHOC 0x00020000
348 #define AR5K_AR5210_STA_ID1_PWR_SV 0x00040000
349 #define AR5K_AR5210_STA_ID1_NO_KEYSRCH 0x00080000
350 #define AR5K_AR5210_STA_ID1_NO_PSPOLL 0x00100000
351 #define AR5K_AR5210_STA_ID1_PCF 0x00200000
352 #define AR5K_AR5210_STA_ID1_DESC_ANTENNA 0x00400000
353 #define AR5K_AR5210_STA_ID1_DEFAULT_ANTENNA 0x00800000
354 #define AR5K_AR5210_STA_ID1_ACKCTS_6MB 0x01000000
355
356 /*
357 * First BSSID register (MAC address, lower 32bits)
358 */
359 #define AR5K_AR5210_BSS_ID0 0x8008
360
361 /*
362 * Second BSSID register (MAC address in upper 16 bits)
363 *
364 * AID: Association ID
365 */
366 #define AR5K_AR5210_BSS_ID1 0x800c
367 #define AR5K_AR5210_BSS_ID1_AID 0xffff0000
368 #define AR5K_AR5210_BSS_ID1_AID_S 16
369
370 /*
371 * Backoff slot time register
372 */
373 #define AR5K_AR5210_SLOT_TIME 0x8010
374
375 /*
376 * ACK/CTS timeout register
377 */
378 #define AR5K_AR5210_TIME_OUT 0x8014
379 #define AR5K_AR5210_TIME_OUT_ACK 0x00001fff
380 #define AR5K_AR5210_TIME_OUT_ACK_S 0
381 #define AR5K_AR5210_TIME_OUT_CTS 0x1fff0000
382 #define AR5K_AR5210_TIME_OUT_CTS_S 16
383
384 /*
385 * RSSI threshold register
386 */
387 #define AR5K_AR5210_RSSI_THR 0x8018
388 #define AR5K_AR5210_RSSI_THR_BM_THR 0x00000700
389 #define AR5K_AR5210_RSSI_THR_BM_THR_S 8
390
391 /*
392 * Retry limit register
393 */
394 #define AR5K_AR5210_RETRY_LMT 0x801c
395 #define AR5K_AR5210_RETRY_LMT_SH_RETRY 0x0000000f
396 #define AR5K_AR5210_RETRY_LMT_SH_RETRY_S 0
397 #define AR5K_AR5210_RETRY_LMT_LG_RETRY 0x000000f0
398 #define AR5K_AR5210_RETRY_LMT_LG_RETRY_S 4
399 #define AR5K_AR5210_RETRY_LMT_SSH_RETRY 0x00003f00
400 #define AR5K_AR5210_RETRY_LMT_SSH_RETRY_S 8
401 #define AR5K_AR5210_RETRY_LMT_SLG_RETRY 0x000fc000
402 #define AR5K_AR5210_RETRY_LMT_SLG_RETRY_S 14
403 #define AR5K_AR5210_RETRY_LMT_CW_MIN 0x3ff00000
404 #define AR5K_AR5210_RETRY_LMT_CW_MIN_S 20
405
406 /*
407 * Transmit latency register
408 */
409 #define AR5K_AR5210_USEC 0x8020
410 #define AR5K_AR5210_USEC_1 0x0000007f
411 #define AR5K_AR5210_USEC_1_S 0
412 #define AR5K_AR5210_USEC_32 0x00003f80
413 #define AR5K_AR5210_USEC_32_S 7
414 #define AR5K_AR5210_USEC_TX_LATENCY 0x000fc000
415 #define AR5K_AR5210_USEC_TX_LATENCY_S 14
416 #define AR5K_AR5210_USEC_RX_LATENCY 0x03f00000
417 #define AR5K_AR5210_USEC_RX_LATENCY_S 20
418
419 /*
420 * PCU beacon control register
421 */
422 #define AR5K_AR5210_BEACON 0x8024
423 #define AR5K_AR5210_BEACON_PERIOD 0x0000ffff
424 #define AR5K_AR5210_BEACON_PERIOD_S 0
425 #define AR5K_AR5210_BEACON_TIM 0x007f0000
426 #define AR5K_AR5210_BEACON_TIM_S 16
427 #define AR5K_AR5210_BEACON_EN 0x00800000
428 #define AR5K_AR5210_BEACON_RESET_TSF 0x01000000
429
430 /*
431 * CFP period register
432 */
433 #define AR5K_AR5210_CFP_PERIOD 0x8028
434
435 /*
436 * Next beacon time register
437 */
438 #define AR5K_AR5210_TIMER0 0x802c
439
440 /*
441 * Next DMA beacon alert register
442 */
443 #define AR5K_AR5210_TIMER1 0x8030
444
445 /*
446 * Next software beacon alert register
447 */
448 #define AR5K_AR5210_TIMER2 0x8034
449
450 /*
451 * Next ATIM window time register
452 */
453 #define AR5K_AR5210_TIMER3 0x8038
454
455 /*
456 * First inter frame spacing register (IFS)
457 */
458 #define AR5K_AR5210_IFS0 0x8040
459 #define AR5K_AR5210_IFS0_SIFS 0x000007ff
460 #define AR5K_AR5210_IFS0_SIFS_S 0
461 #define AR5K_AR5210_IFS0_DIFS 0x007ff800
462 #define AR5K_AR5210_IFS0_DIFS_S 11
463
464 /*
465 * Second inter frame spacing register (IFS)
466 */
467 #define AR5K_AR5210_IFS1 0x8044
468 #define AR5K_AR5210_IFS1_PIFS 0x00000fff
469 #define AR5K_AR5210_IFS1_PIFS_S 0
470 #define AR5K_AR5210_IFS1_EIFS 0x03fff000
471 #define AR5K_AR5210_IFS1_EIFS_S 12
472 #define AR5K_AR5210_IFS1_CS_EN 0x04000000
473
474 /*
475 * CFP duration register
476 */
477 #define AR5K_AR5210_CFP_DUR 0x8048
478
479 /*
480 * Receive filter register
481 */
482 #define AR5K_AR5210_RX_FILTER 0x804c
483 #define AR5K_AR5210_RX_FILTER_UNICAST 0x00000001
484 #define AR5K_AR5210_RX_FILTER_MULTICAST 0x00000002
485 #define AR5K_AR5210_RX_FILTER_BROADCAST 0x00000004
486 #define AR5K_AR5210_RX_FILTER_CONTROL 0x00000008
487 #define AR5K_AR5210_RX_FILTER_BEACON 0x00000010
488 #define AR5K_AR5210_RX_FILTER_PROMISC 0x00000020
489
490 /*
491 * Multicast filter register (lower 32 bits)
492 */
493 #define AR5K_AR5210_MCAST_FIL0 0x8050
494
495 /*
496 * Multicast filter register (higher 16 bits)
497 */
498 #define AR5K_AR5210_MCAST_FIL1 0x8054
499
500 /*
501 * Transmit mask register (lower 32 bits)
502 */
503 #define AR5K_AR5210_TX_MASK0 0x8058
504
505 /*
506 * Transmit mask register (higher 16 bits)
507 */
508 #define AR5K_AR5210_TX_MASK1 0x805c
509
510 /*
511 * Clear transmit mask
512 */
513 #define AR5K_AR5210_CLR_TMASK 0x8060
514
515 /*
516 * Trigger level register (before transmission)
517 */
518 #define AR5K_AR5210_TRIG_LVL 0x8064
519
520 /*
521 * PCU control register
522 */
523 #define AR5K_AR5210_DIAG_SW 0x8068
524 #define AR5K_AR5210_DIAG_SW_DIS_WEP_ACK 0x00000001
525 #define AR5K_AR5210_DIAG_SW_DIS_ACK 0x00000002
526 #define AR5K_AR5210_DIAG_SW_DIS_CTS 0x00000004
527 #define AR5K_AR5210_DIAG_SW_DIS_ENC 0x00000008
528 #define AR5K_AR5210_DIAG_SW_DIS_DEC 0x00000010
529 #define AR5K_AR5210_DIAG_SW_DIS_TX 0x00000020
530 #define AR5K_AR5210_DIAG_SW_DIS_RX 0x00000040
531 #define AR5K_AR5210_DIAG_SW_LOOP_BACK 0x00000080
532 #define AR5K_AR5210_DIAG_SW_CORR_FCS 0x00000100
533 #define AR5K_AR5210_DIAG_SW_CHAN_INFO 0x00000200
534 #define AR5K_AR5210_DIAG_SW_EN_SCRAM_SEED 0x00000400
535 #define AR5K_AR5210_DIAG_SW_SCVRAM_SEED 0x0003f800
536 #define AR5K_AR5210_DIAG_SW_DIS_SEQ_INC 0x00040000
537 #define AR5K_AR5210_DIAG_SW_FRAME_NV0 0x00080000
538
539 /*
540 * TSF (clock) register (lower 32 bits)
541 */
542 #define AR5K_AR5210_TSF_L32 0x806c
543
544 /*
545 * TSF (clock) register (higher 32 bits)
546 */
547 #define AR5K_AR5210_TSF_U32 0x8070
548
549 /*
550 * Last beacon timestamp register
551 */
552 #define AR5K_AR5210_LAST_TSTP 0x8080
553
554 /*
555 * Retry count register
556 */
557 #define AR5K_AR5210_RETRY_CNT 0x8084
558 #define AR5K_AR5210_RETRY_CNT_SSH 0x0000003f
559 #define AR5K_AR5210_RETRY_CNT_SLG 0x00000fc0
560
561 /*
562 * Back-off status register
563 */
564 #define AR5K_AR5210_BACKOFF 0x8088
565 #define AR5K_AR5210_BACKOFF_CW 0x000003ff
566 #define AR5K_AR5210_BACKOFF_CNT 0x03ff0000
567
568 /*
569 * NAV register (current)
570 */
571 #define AR5K_AR5210_NAV 0x808c
572
573 /*
574 * RTS success register
575 */
576 #define AR5K_AR5210_RTS_OK 0x8090
577
578 /*
579 * RTS failure register
580 */
581 #define AR5K_AR5210_RTS_FAIL 0x8094
582
583 /*
584 * ACK failure register
585 */
586 #define AR5K_AR5210_ACK_FAIL 0x8098
587
588 /*
589 * FCS failure register
590 */
591 #define AR5K_AR5210_FCS_FAIL 0x809c
592
593 /*
594 * Beacon count register
595 */
596 #define AR5K_AR5210_BEACON_CNT 0x80a0
597
598 /*
599 * Key table (WEP) register
600 */
601 #define AR5K_AR5210_KEYTABLE_0 0x9000
602 #define AR5K_AR5210_KEYTABLE(n) (AR5K_AR5210_KEYTABLE_0 + ((n) << 5))
603 #define AR5K_AR5210_KEYTABLE_OFF(_n, x) (AR5K_AR5210_KEYTABLE(_n) + (x << 2))
604 #define AR5K_AR5210_KEYTABLE_TYPE(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 5)
605 #define AR5K_AR5210_KEYTABLE_TYPE_40 0x00000000
606 #define AR5K_AR5210_KEYTABLE_TYPE_104 0x00000001
607 #define AR5K_AR5210_KEYTABLE_TYPE_128 0x00000003
608 #define AR5K_AR5210_KEYTABLE_MAC0(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 6)
609 #define AR5K_AR5210_KEYTABLE_MAC1(_n) AR5K_AR5210_KEYTABLE_OFF(_n, 7)
610 #define AR5K_AR5210_KEYTABLE_VALID 0x00008000
611
612 #define AR5K_AR5210_KEYTABLE_SIZE 64
613 #define AR5K_AR5210_KEYCACHE_SIZE 8
614
615 /*
616 * PHY register
617 */
618 #define AR5K_AR5210_PHY(_n) (0x9800 + ((_n) << 2))
619
620 /*
621 * PHY frame control register
622 */
623 #define AR5K_AR5210_PHY_FC 0x9804
624 #define AR5K_AR5210_PHY_FC_TURBO_MODE 0x00000001
625 #define AR5K_AR5210_PHY_FC_TURBO_SHORT 0x00000002
626 #define AR5K_AR5210_PHY_FC_TIMING_ERR 0x01000000
627 #define AR5K_AR5210_PHY_FC_PARITY_ERR 0x02000000
628 #define AR5K_AR5210_PHY_FC_ILLRATE_ERR 0x04000000
629 #define AR5K_AR5210_PHY_FC_ILLLEN_ERR 0x08000000
630 #define AR5K_AR5210_PHY_FC_SERVICE_ERR 0x20000000
631 #define AR5K_AR5210_PHY_FC_TXURN_ERR 0x40000000
632
633 /*
634 * PHY agility command register
635 */
636 #define AR5K_AR5210_PHY_AGC 0x9808
637 #define AR5K_AR5210_PHY_AGC_DISABLE 0x08000000
638
639 /*
640 * PHY chip revision register
641 */
642 #define AR5K_AR5210_PHY_CHIP_ID 0x9818
643
644 /*
645 * PHY activation register
646 */
647 #define AR5K_AR5210_PHY_ACTIVE 0x981c
648 #define AR5K_AR5210_PHY_ENABLE 0x00000001
649 #define AR5K_AR5210_PHY_DISABLE 0x00000002
650
651 /*
652 * PHY signal register
653 */
654 #define AR5K_AR5210_PHY_SIG 0x9858
655 #define AR5K_AR5210_PHY_SIG_FIRSTEP 0x0003f000
656 #define AR5K_AR5210_PHY_SIG_FIRSTEP_S 12
657 #define AR5K_AR5210_PHY_SIG_FIRPWR 0x03fc0000
658 #define AR5K_AR5210_PHY_SIG_FIRPWR_S 18
659
660 /*
661 * PHY coarse agility control register
662 */
663 #define AR5K_AR5210_PHY_AGCCOARSE 0x985c
664 #define AR5K_AR5210_PHY_AGCCOARSE_LO 0x00007f80
665 #define AR5K_AR5210_PHY_AGCCOARSE_LO_S 7
666 #define AR5K_AR5210_PHY_AGCCOARSE_HI 0x003f8000
667 #define AR5K_AR5210_PHY_AGCCOARSE_HI_S 15
668
669 /*
670 * PHY agility control register
671 */
672 #define AR5K_AR5210_PHY_AGCCTL 0x9860
673 #define AR5K_AR5210_PHY_AGCCTL_CAL 0x00000001
674 #define AR5K_AR5210_PHY_AGCCTL_NF 0x00000002
675
676 /*
677 * PHY noise floor status register
678 */
679 #define AR5K_AR5210_PHY_NF 0x9864
680 #define AR5K_AR5210_PHY_NF_M 0x000001ff
681 #define AR5K_AR5210_PHY_NF_ACTIVE 0x00000100
682 #define AR5K_AR5210_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5K_AR5210_PHY_NF_M)
683 #define AR5K_AR5210_PHY_NF_AVAL(_n) (-((_n) ^ AR5K_AR5210_PHY_NF_M) + 1)
684
685 /*
686 * PHY ADC saturation register
687 */
688 #define AR5K_AR5210_PHY_ADCSAT 0x9868
689 #define AR5K_AR5210_PHY_ADCSAT_ICNT 0x0001f800
690 #define AR5K_AR5210_PHY_ADCSAT_ICNT_S 11
691 #define AR5K_AR5210_PHY_ADCSAT_THR 0x000007e0
692 #define AR5K_AR5210_PHY_ADCSAT_THR_S 5
693
694 /*
695 * PHY RF stage register
696 */
697 #define AR5K_AR5210_PHY_RFSTG 0x98d4
698 #define AR5K_AR5210_PHY_RFSTG_DISABLE 0x00000021
699
700 /*
701 * Misc PHY/radio registers
702 */
703 #define AR5K_AR5210_BB_GAIN(_n) (0x9b00 + ((_n) << 2))
704 #define AR5K_AR5210_RF_GAIN(_n) (0x9a00 + ((_n) << 2))
705
706 #endif
Cache object: 23b73b9c115cbd7450e393f9e85f82af
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