Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/ar5210var.h
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1 /* $OpenBSD: ar5210var.h,v 1.16 2022/01/09 05:42:38 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Specific definitions for the Atheros AR5000 Wireless LAN chipset 21 * (AR5210 + AR5110). 22 */ 23 24 #ifndef _AR5K_AR5210_VAR_H 25 #define _AR5K_AR5210_VAR_H 26 27 #include <dev/ic/ar5xxx.h> 28 29 /* 30 * Define a "magic" code for the AR5210 (the HAL layer wants it) 31 */ 32 33 #define AR5K_AR5210_MAGIC 0x0000145a /* 5210 */ 34 #define AR5K_AR5210_TX_NUM_QUEUES 2 35 36 #if BYTE_ORDER == BIG_ENDIAN 37 #define AR5K_AR5210_INIT_CFG ( \ 38 AR5K_AR5210_CFG_SWTD | AR5K_AR5210_CFG_SWRD \ 39 ) 40 #else 41 #define AR5K_AR5210_INIT_CFG 0x00000000 42 #endif 43 44 /* 45 * Internal RX/TX descriptor structures 46 * (rX: reserved fields possibly used by future versions of the ar5k chipset) 47 */ 48 49 struct ar5k_ar5210_rx_desc { 50 /* 51 * RX control word 0 52 */ 53 u_int32_t rx_control_0; 54 55 #define AR5K_AR5210_DESC_RX_CTL0 0x00000000 56 57 /* 58 * RX control word 1 59 */ 60 u_int32_t rx_control_1; 61 62 #define AR5K_AR5210_DESC_RX_CTL1_BUF_LEN 0x00000fff 63 #define AR5K_AR5210_DESC_RX_CTL1_INTREQ 0x00002000 64 } __packed; 65 66 struct ar5k_ar5210_rx_status { 67 /* 68 * RX status word 0 69 */ 70 u_int32_t rx_status_0; 71 72 #define AR5K_AR5210_DESC_RX_STATUS0_DATA_LEN 0x00000fff 73 #define AR5K_AR5210_DESC_RX_STATUS0_MORE 0x00001000 74 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_ANTENNA 0x00004000 75 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE 0x00078000 76 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_RATE_S 15 77 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL 0x07f80000 78 #define AR5K_AR5210_DESC_RX_STATUS0_RECEIVE_SIGNAL_S 19 79 80 /* 81 * RX status word 1 82 */ 83 u_int32_t rx_status_1; 84 85 #define AR5K_AR5210_DESC_RX_STATUS1_DONE 0x00000001 86 #define AR5K_AR5210_DESC_RX_STATUS1_FRAME_RECEIVE_OK 0x00000002 87 #define AR5K_AR5210_DESC_RX_STATUS1_CRC_ERROR 0x00000004 88 #define AR5K_AR5210_DESC_RX_STATUS1_FIFO_OVERRUN 0x00000008 89 #define AR5K_AR5210_DESC_RX_STATUS1_DECRYPT_CRC_ERROR 0x00000010 90 #define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR 0x000000e0 91 #define AR5K_AR5210_DESC_RX_STATUS1_PHY_ERROR_S 5 92 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_VALID 0x00000100 93 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX 0x00007e00 94 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_INDEX_S 9 95 #define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 96 #define AR5K_AR5210_DESC_RX_STATUS1_RECEIVE_TIMESTAMP_S 15 97 #define AR5K_AR5210_DESC_RX_STATUS1_KEY_CACHE_MISS 0x10000000 98 } __packed; 99 100 #define AR5K_AR5210_DESC_RX_PHY_ERROR_NONE 0x00 101 #define AR5K_AR5210_DESC_RX_PHY_ERROR_TIMING 0x20 102 #define AR5K_AR5210_DESC_RX_PHY_ERROR_PARITY 0x40 103 #define AR5K_AR5210_DESC_RX_PHY_ERROR_RATE 0x60 104 #define AR5K_AR5210_DESC_RX_PHY_ERROR_LENGTH 0x80 105 #define AR5K_AR5210_DESC_RX_PHY_ERROR_64QAM 0xa0 106 #define AR5K_AR5210_DESC_RX_PHY_ERROR_SERVICE 0xc0 107 #define AR5K_AR5210_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 108 109 struct ar5k_ar5210_tx_desc { 110 /* 111 * TX control word 0 112 */ 113 u_int32_t tx_control_0; 114 115 #define AR5K_AR5210_DESC_TX_CTL0_FRAME_LEN 0x00000fff 116 #define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN 0x0003f000 117 #define AR5K_AR5210_DESC_TX_CTL0_HEADER_LEN_S 12 118 #define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE 0x003c0000 119 #define AR5K_AR5210_DESC_TX_CTL0_XMIT_RATE_S 18 120 #define AR5K_AR5210_DESC_TX_CTL0_RTSENA 0x00400000 121 #define AR5K_AR5210_DESC_TX_CTL0_LONG_PACKET 0x00800000 122 #define AR5K_AR5210_DESC_TX_CTL0_CLRDMASK 0x01000000 123 #define AR5K_AR5210_DESC_TX_CTL0_ANT_MODE_XMIT 0x02000000 124 #define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE 0x1c000000 125 #define AR5K_AR5210_DESC_TX_CTL0_FRAME_TYPE_S 26 126 #define AR5K_AR5210_DESC_TX_CTL0_INTREQ 0x20000000 127 #define AR5K_AR5210_DESC_TX_CTL0_ENCRYPT_KEY_VALID 0x40000000 128 129 /* 130 * TX control word 1 131 */ 132 u_int32_t tx_control_1; 133 134 #define AR5K_AR5210_DESC_TX_CTL1_BUF_LEN 0x00000fff 135 #define AR5K_AR5210_DESC_TX_CTL1_MORE 0x00001000 136 #define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX 0x0007e000 137 #define AR5K_AR5210_DESC_TX_CTL1_ENCRYPT_KEY_INDEX_S 13 138 #define AR5K_AR5210_DESC_TX_CTL1_RTS_DURATION 0xfff80000 139 } __packed; 140 141 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_NORMAL 0x00 142 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_ATIM 0x04 143 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_PSPOLL 0x08 144 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_NO_DELAY 0x0c 145 #define AR5K_AR5210_DESC_TX_FRAME_TYPE_PIFS 0x10 146 147 struct ar5k_ar5210_tx_status { 148 /* 149 * TX status word 0 150 */ 151 u_int32_t tx_status_0; 152 153 #define AR5K_AR5210_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 154 #define AR5K_AR5210_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 155 #define AR5K_AR5210_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 156 #define AR5K_AR5210_DESC_TX_STATUS0_FILTERED 0x00000008 157 #define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 158 #define AR5K_AR5210_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 159 #define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 160 #define AR5K_AR5210_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 161 #define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 162 #define AR5K_AR5210_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 163 164 /* 165 * TX status word 1 166 */ 167 u_int32_t tx_status_1; 168 169 #define AR5K_AR5210_DESC_TX_STATUS1_DONE 0x00000001 170 #define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe 171 #define AR5K_AR5210_DESC_TX_STATUS1_SEQ_NUM_S 1 172 #define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 173 #define AR5K_AR5210_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 174 } __packed; 175 176 /* 177 * Public function prototypes 178 */ 179 extern ar5k_attach_t ar5k_ar5210_attach; 180 181 /* 182 * Initial mode settings ("Base Mode" or "Turbo Mode") 183 */ 184 185 #define AR5K_AR5210_INI_MODE(_aifs) { \ 186 { AR5K_AR5210_SLOT_TIME, \ 187 AR5K_INIT_SLOT_TIME }, \ 188 { AR5K_AR5210_SLOT_TIME, \ 189 AR5K_INIT_ACK_CTS_TIMEOUT }, \ 190 { AR5K_AR5210_USEC, \ 191 AR5K_INIT_TRANSMIT_LATENCY }, \ 192 { AR5K_AR5210_IFS0, \ 193 ((AR5K_INIT_SIFS + (_aifs) * AR5K_INIT_SLOT_TIME) \ 194 << AR5K_AR5210_IFS0_DIFS_S) | AR5K_INIT_SIFS }, \ 195 { AR5K_AR5210_IFS1, \ 196 AR5K_INIT_PROTO_TIME_CNTRL }, \ 197 { AR5K_AR5210_PHY(17), \ 198 (AR5K_REG_READ(AR5K_AR5210_PHY(17)) & ~0x7F) | 0x1C }, \ 199 { AR5K_AR5210_PHY_FC, \ 200 AR5K_AR5210_PHY_FC_SERVICE_ERR | \ 201 AR5K_AR5210_PHY_FC_TXURN_ERR | \ 202 AR5K_AR5210_PHY_FC_ILLLEN_ERR | \ 203 AR5K_AR5210_PHY_FC_ILLRATE_ERR | \ 204 AR5K_AR5210_PHY_FC_PARITY_ERR | \ 205 AR5K_AR5210_PHY_FC_TIMING_ERR | 0x1020 }, \ 206 } 207 208 /* 209 * Initial register values which have to be loaded into the 210 * card at boot time and after each reset. 211 */ 212 213 #define AR5K_AR5210_INI { \ 214 /* PCU and MAC registers */ \ 215 { AR5K_AR5210_TXDP0, 0 }, \ 216 { AR5K_AR5210_TXDP1, 0 }, \ 217 { AR5K_AR5210_RXDP, 0 }, \ 218 { AR5K_AR5210_CR, 0 }, \ 219 { AR5K_AR5210_ISR, 0, AR5K_INI_READ }, \ 220 { AR5K_AR5210_IMR, 0 }, \ 221 { AR5K_AR5210_IER, AR5K_AR5210_IER_DISABLE }, \ 222 { AR5K_AR5210_BSR, 0, AR5K_INI_READ }, \ 223 { AR5K_AR5210_TXCFG, AR5K_AR5210_DMASIZE_128B }, \ 224 { AR5K_AR5210_RXCFG, AR5K_AR5210_DMASIZE_128B }, \ 225 { AR5K_AR5210_CFG, AR5K_AR5210_INIT_CFG }, \ 226 { AR5K_AR5210_TOPS, AR5K_INIT_TOPS }, \ 227 { AR5K_AR5210_RXNOFRM, AR5K_INIT_RXNOFRM }, \ 228 { AR5K_AR5210_RPGTO, AR5K_INIT_RPGTO }, \ 229 { AR5K_AR5210_TXNOFRM, AR5K_INIT_TXNOFRM }, \ 230 { AR5K_AR5210_SFR, 0 }, \ 231 { AR5K_AR5210_MIBC, 0 }, \ 232 { AR5K_AR5210_MISC, 0 }, \ 233 { AR5K_AR5210_RX_FILTER, 0 }, \ 234 { AR5K_AR5210_MCAST_FIL0, 0 }, \ 235 { AR5K_AR5210_MCAST_FIL1, 0 }, \ 236 { AR5K_AR5210_TX_MASK0, 0 }, \ 237 { AR5K_AR5210_TX_MASK1, 0 }, \ 238 { AR5K_AR5210_CLR_TMASK, 0 }, \ 239 { AR5K_AR5210_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \ 240 { AR5K_AR5210_DIAG_SW, 0 }, \ 241 { AR5K_AR5210_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \ 242 { AR5K_AR5210_TSF_L32, 0 }, \ 243 { AR5K_AR5210_TIMER0, 0 }, \ 244 { AR5K_AR5210_TIMER1, 0xffffffff }, \ 245 { AR5K_AR5210_TIMER2, 0xffffffff }, \ 246 { AR5K_AR5210_TIMER3, 1 }, \ 247 { AR5K_AR5210_CFP_DUR, 0 }, \ 248 { AR5K_AR5210_CFP_PERIOD, 0 }, \ 249 /* PHY registers */ \ 250 { AR5K_AR5210_PHY(0), 0x00000047 }, \ 251 { AR5K_AR5210_PHY_AGC, 0x00000000 }, \ 252 { AR5K_AR5210_PHY(3), 0x09848ea6 }, \ 253 { AR5K_AR5210_PHY(4), 0x3d32e000 }, \ 254 { AR5K_AR5210_PHY(5), 0x0000076b }, \ 255 { AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_DISABLE }, \ 256 { AR5K_AR5210_PHY(8), 0x02020200 }, \ 257 { AR5K_AR5210_PHY(9), 0x00000e0e }, \ 258 { AR5K_AR5210_PHY(10), 0x0a020201 }, \ 259 { AR5K_AR5210_PHY(11), 0x00036ffc }, \ 260 { AR5K_AR5210_PHY(12), 0x00000000 }, \ 261 { AR5K_AR5210_PHY(13), 0x00000e0e }, \ 262 { AR5K_AR5210_PHY(14), 0x00000007 }, \ 263 { AR5K_AR5210_PHY(15), 0x00020100 }, \ 264 { AR5K_AR5210_PHY(16), 0x89630000 }, \ 265 { AR5K_AR5210_PHY(17), 0x1372169c }, \ 266 { AR5K_AR5210_PHY(18), 0x0018b633 }, \ 267 { AR5K_AR5210_PHY(19), 0x1284613c }, \ 268 { AR5K_AR5210_PHY(20), 0x0de8b8e0 }, \ 269 { AR5K_AR5210_PHY(21), 0x00074859 }, \ 270 { AR5K_AR5210_PHY(22), 0x7e80beba }, \ 271 { AR5K_AR5210_PHY(23), 0x313a665e }, \ 272 { AR5K_AR5210_PHY_AGCCTL, 0x00001d08 }, \ 273 { AR5K_AR5210_PHY(25), 0x0001ce00 }, \ 274 { AR5K_AR5210_PHY(26), 0x409a4190 }, \ 275 { AR5K_AR5210_PHY(28), 0x0000000f }, \ 276 { AR5K_AR5210_PHY(29), 0x00000080 }, \ 277 { AR5K_AR5210_PHY(30), 0x00000004 }, \ 278 { AR5K_AR5210_PHY(31), 0x00000018 }, /* 0x987c */ \ 279 { AR5K_AR5210_PHY(64), 0x00000000 }, /* 0x9900 */ \ 280 { AR5K_AR5210_PHY(65), 0x00000000 }, \ 281 { AR5K_AR5210_PHY(66), 0x00000000 }, \ 282 { AR5K_AR5210_PHY(67), 0x00800000 }, \ 283 { AR5K_AR5210_PHY(68), 0x00000003 }, \ 284 /* BB gain table (64bytes) */ \ 285 { AR5K_AR5210_BB_GAIN(0), 0x00000000 }, \ 286 { AR5K_AR5210_BB_GAIN(0x01), 0x00000020 }, \ 287 { AR5K_AR5210_BB_GAIN(0x02), 0x00000010 }, \ 288 { AR5K_AR5210_BB_GAIN(0x03), 0x00000030 }, \ 289 { AR5K_AR5210_BB_GAIN(0x04), 0x00000008 }, \ 290 { AR5K_AR5210_BB_GAIN(0x05), 0x00000028 }, \ 291 { AR5K_AR5210_BB_GAIN(0x06), 0x00000028 }, \ 292 { AR5K_AR5210_BB_GAIN(0x07), 0x00000004 }, \ 293 { AR5K_AR5210_BB_GAIN(0x08), 0x00000024 }, \ 294 { AR5K_AR5210_BB_GAIN(0x09), 0x00000014 }, \ 295 { AR5K_AR5210_BB_GAIN(0x0a), 0x00000034 }, \ 296 { AR5K_AR5210_BB_GAIN(0x0b), 0x0000000c }, \ 297 { AR5K_AR5210_BB_GAIN(0x0c), 0x0000002c }, \ 298 { AR5K_AR5210_BB_GAIN(0x0d), 0x00000002 }, \ 299 { AR5K_AR5210_BB_GAIN(0x0e), 0x00000022 }, \ 300 { AR5K_AR5210_BB_GAIN(0x0f), 0x00000012 }, \ 301 { AR5K_AR5210_BB_GAIN(0x10), 0x00000032 }, \ 302 { AR5K_AR5210_BB_GAIN(0x11), 0x0000000a }, \ 303 { AR5K_AR5210_BB_GAIN(0x12), 0x0000002a }, \ 304 { AR5K_AR5210_BB_GAIN(0x13), 0x00000001 }, \ 305 { AR5K_AR5210_BB_GAIN(0x14), 0x00000021 }, \ 306 { AR5K_AR5210_BB_GAIN(0x15), 0x00000011 }, \ 307 { AR5K_AR5210_BB_GAIN(0x16), 0x00000031 }, \ 308 { AR5K_AR5210_BB_GAIN(0x17), 0x00000009 }, \ 309 { AR5K_AR5210_BB_GAIN(0x18), 0x00000029 }, \ 310 { AR5K_AR5210_BB_GAIN(0x19), 0x00000005 }, \ 311 { AR5K_AR5210_BB_GAIN(0x1a), 0x00000025 }, \ 312 { AR5K_AR5210_BB_GAIN(0x1b), 0x00000015 }, \ 313 { AR5K_AR5210_BB_GAIN(0x1c), 0x00000035 }, \ 314 { AR5K_AR5210_BB_GAIN(0x1d), 0x0000000d }, \ 315 { AR5K_AR5210_BB_GAIN(0x1e), 0x0000002d }, \ 316 { AR5K_AR5210_BB_GAIN(0x1f), 0x00000003 }, \ 317 { AR5K_AR5210_BB_GAIN(0x20), 0x00000023 }, \ 318 { AR5K_AR5210_BB_GAIN(0x21), 0x00000013 }, \ 319 { AR5K_AR5210_BB_GAIN(0x22), 0x00000033 }, \ 320 { AR5K_AR5210_BB_GAIN(0x23), 0x0000000b }, \ 321 { AR5K_AR5210_BB_GAIN(0x24), 0x0000002b }, \ 322 { AR5K_AR5210_BB_GAIN(0x25), 0x00000007 }, \ 323 { AR5K_AR5210_BB_GAIN(0x26), 0x00000027 }, \ 324 { AR5K_AR5210_BB_GAIN(0x27), 0x00000017 }, \ 325 { AR5K_AR5210_BB_GAIN(0x28), 0x00000037 }, \ 326 { AR5K_AR5210_BB_GAIN(0x29), 0x0000000f }, \ 327 { AR5K_AR5210_BB_GAIN(0x2a), 0x0000002f }, \ 328 { AR5K_AR5210_BB_GAIN(0x2b), 0x0000002f }, \ 329 { AR5K_AR5210_BB_GAIN(0x2c), 0x0000002f }, \ 330 { AR5K_AR5210_BB_GAIN(0x2d), 0x0000002f }, \ 331 { AR5K_AR5210_BB_GAIN(0x2e), 0x0000002f }, \ 332 { AR5K_AR5210_BB_GAIN(0x2f), 0x0000002f }, \ 333 { AR5K_AR5210_BB_GAIN(0x30), 0x0000002f }, \ 334 { AR5K_AR5210_BB_GAIN(0x31), 0x0000002f }, \ 335 { AR5K_AR5210_BB_GAIN(0x32), 0x0000002f }, \ 336 { AR5K_AR5210_BB_GAIN(0x33), 0x0000002f }, \ 337 { AR5K_AR5210_BB_GAIN(0x34), 0x0000002f }, \ 338 { AR5K_AR5210_BB_GAIN(0x35), 0x0000002f }, \ 339 { AR5K_AR5210_BB_GAIN(0x36), 0x0000002f }, \ 340 { AR5K_AR5210_BB_GAIN(0x37), 0x0000002f }, \ 341 { AR5K_AR5210_BB_GAIN(0x38), 0x0000002f }, \ 342 { AR5K_AR5210_BB_GAIN(0x39), 0x0000002f }, \ 343 { AR5K_AR5210_BB_GAIN(0x3a), 0x0000002f }, \ 344 { AR5K_AR5210_BB_GAIN(0x3b), 0x0000002f }, \ 345 { AR5K_AR5210_BB_GAIN(0x3c), 0x0000002f }, \ 346 { AR5K_AR5210_BB_GAIN(0x3d), 0x0000002f }, \ 347 { AR5K_AR5210_BB_GAIN(0x3e), 0x0000002f }, \ 348 { AR5K_AR5210_BB_GAIN(0x3f), 0x0000002f }, \ 349 /* RF gain table (64bytes) */ \ 350 { AR5K_AR5210_RF_GAIN(0), 0x0000001d }, \ 351 { AR5K_AR5210_RF_GAIN(0x01), 0x0000005d }, \ 352 { AR5K_AR5210_RF_GAIN(0x02), 0x0000009d }, \ 353 { AR5K_AR5210_RF_GAIN(0x03), 0x000000dd }, \ 354 { AR5K_AR5210_RF_GAIN(0x04), 0x0000011d }, \ 355 { AR5K_AR5210_RF_GAIN(0x05), 0x00000021 }, \ 356 { AR5K_AR5210_RF_GAIN(0x06), 0x00000061 }, \ 357 { AR5K_AR5210_RF_GAIN(0x07), 0x000000a1 }, \ 358 { AR5K_AR5210_RF_GAIN(0x08), 0x000000e1 }, \ 359 { AR5K_AR5210_RF_GAIN(0x09), 0x00000031 }, \ 360 { AR5K_AR5210_RF_GAIN(0x0a), 0x00000071 }, \ 361 { AR5K_AR5210_RF_GAIN(0x0b), 0x000000b1 }, \ 362 { AR5K_AR5210_RF_GAIN(0x0c), 0x0000001c }, \ 363 { AR5K_AR5210_RF_GAIN(0x0d), 0x0000005c }, \ 364 { AR5K_AR5210_RF_GAIN(0x0e), 0x00000029 }, \ 365 { AR5K_AR5210_RF_GAIN(0x0f), 0x00000069 }, \ 366 { AR5K_AR5210_RF_GAIN(0x10), 0x000000a9 }, \ 367 { AR5K_AR5210_RF_GAIN(0x11), 0x00000020 }, \ 368 { AR5K_AR5210_RF_GAIN(0x12), 0x00000019 }, \ 369 { AR5K_AR5210_RF_GAIN(0x13), 0x00000059 }, \ 370 { AR5K_AR5210_RF_GAIN(0x14), 0x00000099 }, \ 371 { AR5K_AR5210_RF_GAIN(0x15), 0x00000030 }, \ 372 { AR5K_AR5210_RF_GAIN(0x16), 0x00000005 }, \ 373 { AR5K_AR5210_RF_GAIN(0x17), 0x00000025 }, \ 374 { AR5K_AR5210_RF_GAIN(0x18), 0x00000065 }, \ 375 { AR5K_AR5210_RF_GAIN(0x19), 0x000000a5 }, \ 376 { AR5K_AR5210_RF_GAIN(0x1a), 0x00000028 }, \ 377 { AR5K_AR5210_RF_GAIN(0x1b), 0x00000068 }, \ 378 { AR5K_AR5210_RF_GAIN(0x1c), 0x0000001f }, \ 379 { AR5K_AR5210_RF_GAIN(0x1d), 0x0000001e }, \ 380 { AR5K_AR5210_RF_GAIN(0x1e), 0x00000018 }, \ 381 { AR5K_AR5210_RF_GAIN(0x1f), 0x00000058 }, \ 382 { AR5K_AR5210_RF_GAIN(0x20), 0x00000098 }, \ 383 { AR5K_AR5210_RF_GAIN(0x21), 0x00000003 }, \ 384 { AR5K_AR5210_RF_GAIN(0x22), 0x00000004 }, \ 385 { AR5K_AR5210_RF_GAIN(0x23), 0x00000044 }, \ 386 { AR5K_AR5210_RF_GAIN(0x24), 0x00000084 }, \ 387 { AR5K_AR5210_RF_GAIN(0x25), 0x00000013 }, \ 388 { AR5K_AR5210_RF_GAIN(0x26), 0x00000012 }, \ 389 { AR5K_AR5210_RF_GAIN(0x27), 0x00000052 }, \ 390 { AR5K_AR5210_RF_GAIN(0x28), 0x00000092 }, \ 391 { AR5K_AR5210_RF_GAIN(0x29), 0x000000d2 }, \ 392 { AR5K_AR5210_RF_GAIN(0x2a), 0x0000002b }, \ 393 { AR5K_AR5210_RF_GAIN(0x2b), 0x0000002a }, \ 394 { AR5K_AR5210_RF_GAIN(0x2c), 0x0000006a }, \ 395 { AR5K_AR5210_RF_GAIN(0x2d), 0x000000aa }, \ 396 { AR5K_AR5210_RF_GAIN(0x2e), 0x0000001b }, \ 397 { AR5K_AR5210_RF_GAIN(0x2f), 0x0000001a }, \ 398 { AR5K_AR5210_RF_GAIN(0x30), 0x0000005a }, \ 399 { AR5K_AR5210_RF_GAIN(0x31), 0x0000009a }, \ 400 { AR5K_AR5210_RF_GAIN(0x32), 0x000000da }, \ 401 { AR5K_AR5210_RF_GAIN(0x33), 0x00000006 }, \ 402 { AR5K_AR5210_RF_GAIN(0x34), 0x00000006 }, \ 403 { AR5K_AR5210_RF_GAIN(0x35), 0x00000006 }, \ 404 { AR5K_AR5210_RF_GAIN(0x36), 0x00000006 }, \ 405 { AR5K_AR5210_RF_GAIN(0x37), 0x00000006 }, \ 406 { AR5K_AR5210_RF_GAIN(0x38), 0x00000006 }, \ 407 { AR5K_AR5210_RF_GAIN(0x39), 0x00000006 }, \ 408 { AR5K_AR5210_RF_GAIN(0x3a), 0x00000006 }, \ 409 { AR5K_AR5210_RF_GAIN(0x3b), 0x00000006 }, \ 410 { AR5K_AR5210_RF_GAIN(0x3c), 0x00000006 }, \ 411 { AR5K_AR5210_RF_GAIN(0x3d), 0x00000006 }, \ 412 { AR5K_AR5210_RF_GAIN(0x3e), 0x00000006 }, \ 413 { AR5K_AR5210_RF_GAIN(0x3f), 0x00000006 }, \ 414 /* PHY activation */ \ 415 { AR5K_AR5210_PHY(53), 0x00000020 }, \ 416 { AR5K_AR5210_PHY(51), 0x00000004 }, \ 417 { AR5K_AR5210_PHY(50), 0x00060106 }, \ 418 { AR5K_AR5210_PHY(39), 0x0000006d }, \ 419 { AR5K_AR5210_PHY(48), 0x00000000 }, \ 420 { AR5K_AR5210_PHY(52), 0x00000014 }, \ 421 { AR5K_AR5210_PHY_ACTIVE, AR5K_AR5210_PHY_ENABLE }, \ 422 } 423 424 #endif /* _AR5K_AR5210_VAR_H */
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