FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/ar5xxx.h
1 /* $OpenBSD: ar5xxx.h,v 1.60 2017/08/25 12:17:27 tb Exp $ */
2
3 /*
4 * Copyright (c) 2004, 2005, 2006, 2007 Reyk Floeter <reyk@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * HAL interface for Atheros Wireless LAN devices.
21 *
22 * ar5k is a free replacement of the binary-only HAL used by some drivers
23 * for Atheros chipsets. While using a different ABI, it tries to be
24 * source-compatible with the original (non-free) HAL interface.
25 *
26 * Many thanks to various contributors who supported the development of
27 * ar5k with hard work and useful information. And, of course, for all the
28 * people who encouraged me to continue this work which has been based
29 * on my initial approach found on http://team.vantronix.net/ar5k/.
30 */
31
32 #ifndef _AR5K_H
33 #define _AR5K_H
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/kernel.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/errno.h>
43 #include <sys/endian.h>
44
45 #include <machine/bus.h>
46
47 #include <net/if.h>
48 #include <net/if_media.h>
49
50 #include <netinet/in.h>
51 #include <netinet/if_ether.h>
52
53 #include <net80211/ieee80211_var.h>
54 #include <net80211/ieee80211_radiotap.h>
55 #include <net80211/ieee80211_regdomain.h>
56
57 /*
58 * Possible chipsets (could appear in different combinations)
59 */
60
61 enum ar5k_version {
62 AR5K_AR5210 = 0,
63 AR5K_AR5211 = 1,
64 AR5K_AR5212 = 2,
65 };
66
67 enum ar5k_radio {
68 AR5K_AR5110 = 0,
69 AR5K_AR5111 = 1,
70 AR5K_AR5112 = 2,
71 AR5K_AR2413 = 3,
72 AR5K_AR5413 = 4,
73 AR5K_AR2425 = 5
74 };
75
76 /*
77 * Generic definitions
78 */
79
80 typedef enum {
81 AH_FALSE = 0,
82 AH_TRUE,
83 } HAL_BOOL;
84
85 typedef enum {
86 HAL_MODE_11A = 0x001,
87 HAL_MODE_TURBO = 0x002,
88 HAL_MODE_11B = 0x004,
89 HAL_MODE_PUREG = 0x008,
90 HAL_MODE_11G = 0x010,
91 HAL_MODE_108G = 0x020,
92 HAL_MODE_XR = 0x040,
93 HAL_MODE_ALL = 0xfff
94 } HAL_MODE;
95
96 typedef enum {
97 HAL_ANT_VARIABLE = 0,
98 HAL_ANT_FIXED_A = 1,
99 HAL_ANT_FIXED_B = 2,
100 HAL_ANT_MAX = 3,
101 } HAL_ANT_SETTING;
102
103 typedef enum ieee80211_opmode HAL_OPMODE;
104
105 #define HAL_M_STA IEEE80211_M_STA
106 #define HAL_M_IBSS IEEE80211_M_IBSS
107 #define HAL_M_HOSTAP IEEE80211_M_HOSTAP
108 #define HAL_M_MONITOR IEEE80211_M_MONITOR
109
110 typedef int HAL_STATUS;
111
112 #define HAL_OK 0
113 #define HAL_EINPROGRESS EINPROGRESS
114
115 #define AR5K_MAX_RSSI 64
116
117 /*
118 * TX queues
119 */
120
121 typedef enum {
122 HAL_TX_QUEUE_INACTIVE = 0,
123 HAL_TX_QUEUE_DATA,
124 HAL_TX_QUEUE_BEACON,
125 HAL_TX_QUEUE_CAB,
126 HAL_TX_QUEUE_PSPOLL,
127 } HAL_TX_QUEUE;
128
129 #define HAL_NUM_TX_QUEUES 10
130
131 typedef enum {
132 HAL_TX_QUEUE_ID_DATA_MIN = 0,
133 HAL_TX_QUEUE_ID_DATA_MAX = 6,
134 HAL_TX_QUEUE_ID_PSPOLL = 7,
135 HAL_TX_QUEUE_ID_BEACON = 8,
136 HAL_TX_QUEUE_ID_CAB = 9,
137 } HAL_TX_QUEUE_ID;
138
139 typedef enum {
140 HAL_WME_AC_BK = 0,
141 HAL_WME_AC_BE = 1,
142 HAL_WME_AC_VI = 2,
143 HAL_WME_AC_VO = 3,
144 HAL_WME_UPSD = 4,
145 } HAL_TX_QUEUE_SUBTYPE;
146
147 #define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001
148 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002
149 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0004
150 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x0008
151 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0010
152 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0020
153 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x0040
154
155 typedef struct {
156 u_int32_t tqi_ver;
157 HAL_TX_QUEUE tqi_type;
158 HAL_TX_QUEUE_SUBTYPE tqi_subtype;
159 u_int16_t tqi_flags;
160 u_int32_t tqi_priority;
161 u_int32_t tqi_aifs;
162 int32_t tqi_cw_min;
163 int32_t tqi_cw_max;
164 u_int32_t tqi_cbr_period;
165 u_int32_t tqi_cbr_overflow_limit;
166 u_int32_t tqi_burst_time;
167 u_int32_t tqi_ready_time;
168 } HAL_TXQ_INFO;
169
170 typedef enum {
171 HAL_PKT_TYPE_NORMAL = 0,
172 HAL_PKT_TYPE_ATIM = 1,
173 HAL_PKT_TYPE_PSPOLL = 2,
174 HAL_PKT_TYPE_BEACON = 3,
175 HAL_PKT_TYPE_PROBE_RESP = 4,
176 HAL_PKT_TYPE_PIFS = 5,
177 } HAL_PKT_TYPE;
178
179 /*
180 * Used to compute TX times
181 */
182
183 #define AR5K_CCK_SIFS_TIME 10
184 #define AR5K_CCK_PREAMBLE_BITS 144
185 #define AR5K_CCK_PLCP_BITS 48
186 #define AR5K_CCK_NUM_BITS(_frmlen) (_frmlen << 3)
187 #define AR5K_CCK_PHY_TIME(_sp) (_sp ? \
188 ((AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS) >> 1) : \
189 (AR5K_CCK_PREAMBLE_BITS + AR5K_CCK_PLCP_BITS))
190 #define AR5K_CCK_TX_TIME(_kbps, _frmlen, _sp) \
191 AR5K_CCK_PHY_TIME(_sp) + \
192 ((AR5K_CCK_NUM_BITS(_frmlen) * 1000) / _kbps) + \
193 AR5K_CCK_SIFS_TIME
194
195 #define AR5K_OFDM_SIFS_TIME 16
196 #define AR5K_OFDM_PREAMBLE_TIME 20
197 #define AR5K_OFDM_PLCP_BITS 22
198 #define AR5K_OFDM_SYMBOL_TIME 4
199 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
200 #define AR5K_OFDM_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
201 AR5K_OFDM_SYMBOL_TIME) / 1000)
202 #define AR5K_OFDM_NUM_BITS(_frmlen) (AR5K_OFDM_PLCP_BITS + (_frmlen << 3))
203 #define AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) \
204 howmany(AR5K_OFDM_NUM_BITS(_frmlen), AR5K_OFDM_NUM_BITS_PER_SYM(_kbps))
205 #define AR5K_OFDM_TX_TIME(_kbps, _frmlen) \
206 AR5K_OFDM_PREAMBLE_TIME + AR5K_OFDM_SIFS_TIME + \
207 (AR5K_OFDM_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_OFDM_SYMBOL_TIME)
208
209 #define AR5K_TURBO_SIFS_TIME 8
210 #define AR5K_TURBO_PREAMBLE_TIME 14
211 #define AR5K_TURBO_PLCP_BITS 22
212 #define AR5K_TURBO_SYMBOL_TIME 4
213 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
214 #define AR5K_TURBO_NUM_BITS_PER_SYM(_kbps) (((_kbps << 1) * \
215 AR5K_TURBO_SYMBOL_TIME) / 1000)
216 #define AR5K_TURBO_NUM_BITS(_frmlen) (AR5K_TURBO_PLCP_BITS + (_frmlen << 3))
217 #define AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) \
218 howmany(AR5K_TURBO_NUM_BITS(_frmlen), \
219 AR5K_TURBO_NUM_BITS_PER_SYM(_kbps))
220 #define AR5K_TURBO_TX_TIME(_kbps, _frmlen) \
221 AR5K_TURBO_PREAMBLE_TIME + AR5K_TURBO_SIFS_TIME + \
222 (AR5K_TURBO_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_TURBO_SYMBOL_TIME)
223
224 #define AR5K_XR_SIFS_TIME 16
225 #define AR5K_XR_PLCP_BITS 22
226 #define AR5K_XR_SYMBOL_TIME 4
227 #define AR5K_XR_PREAMBLE_TIME(_kbps) (((_kbps) < 1000) ? 173 : 76)
228 #define AR5K_XR_NUM_BITS_PER_SYM(_kbps) ((_kbps * \
229 AR5K_XR_SYMBOL_TIME) / 1000)
230 #define AR5K_XR_NUM_BITS(_frmlen) (AR5K_XR_PLCP_BITS + (_frmlen << 3))
231 #define AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) \
232 howmany(AR5K_XR_NUM_BITS(_frmlen), AR5K_XR_NUM_BITS_PER_SYM(_kbps))
233 #define AR5K_XR_TX_TIME(_kbps, _frmlen) \
234 AR5K_XR_PREAMBLE_TIME(_kbps) + AR5K_XR_SIFS_TIME + \
235 (AR5K_XR_NUM_SYMBOLS(_kbps, _frmlen) * AR5K_XR_SYMBOL_TIME)
236
237 /*
238 * RX definitions
239 */
240
241 #define HAL_RX_FILTER_UCAST 0x00000001
242 #define HAL_RX_FILTER_MCAST 0x00000002
243 #define HAL_RX_FILTER_BCAST 0x00000004
244 #define HAL_RX_FILTER_CONTROL 0x00000008
245 #define HAL_RX_FILTER_BEACON 0x00000010
246 #define HAL_RX_FILTER_PROM 0x00000020
247 #define HAL_RX_FILTER_PROBEREQ 0x00000080
248 #define HAL_RX_FILTER_PHYERR 0x00000100
249 #define HAL_RX_FILTER_PHYRADAR 0x00000200
250
251 typedef struct {
252 u_int32_t ackrcv_bad;
253 u_int32_t rts_bad;
254 u_int32_t rts_good;
255 u_int32_t fcs_bad;
256 u_int32_t beacons;
257 } HAL_MIB_STATS;
258
259 /*
260 * Beacon/AP definitions
261 */
262
263 #define HAL_BEACON_PERIOD 0x0000ffff
264 #define HAL_BEACON_ENA 0x00800000
265 #define HAL_BEACON_RESET_TSF 0x01000000
266
267 typedef struct {
268 u_int32_t bs_next_beacon;
269 u_int32_t bs_next_dtim;
270 u_int32_t bs_interval;
271 u_int8_t bs_dtim_period;
272 u_int8_t bs_cfp_period;
273 u_int16_t bs_cfp_max_duration;
274 u_int16_t bs_cfp_du_remain;
275 u_int16_t bs_tim_offset;
276 u_int16_t bs_sleep_duration;
277 u_int16_t bs_bmiss_threshold;
278
279 #define bs_nexttbtt bs_next_beacon
280 #define bs_intval bs_interval
281 #define bs_nextdtim bs_next_dtim
282 #define bs_bmissthreshold bs_bmiss_threshold
283 #define bs_sleepduration bs_sleep_duration
284 #define bs_dtimperiod bs_dtim_period
285
286 } HAL_BEACON_STATE;
287
288 /*
289 * Power management
290 */
291
292 typedef enum {
293 HAL_PM_UNDEFINED = 0,
294 HAL_PM_AUTO,
295 HAL_PM_AWAKE,
296 HAL_PM_FULL_SLEEP,
297 HAL_PM_NETWORK_SLEEP,
298 } HAL_POWER_MODE;
299
300 /*
301 * Weak wireless crypto definitions (use IPsec/WLSec/...)
302 */
303
304 typedef enum {
305 HAL_CIPHER_WEP = 0,
306 HAL_CIPHER_AES_CCM,
307 HAL_CIPHER_CKIP,
308 } HAL_CIPHER;
309
310 #define AR5K_KEYVAL_LENGTH_40 5
311 #define AR5K_KEYVAL_LENGTH_104 13
312 #define AR5K_KEYVAL_LENGTH_128 16
313 #define AR5K_KEYVAL_LENGTH_MAX AR5K_KEYVAL_LENGTH_128
314
315 typedef struct {
316 int wk_len;
317 u_int8_t wk_key[AR5K_KEYVAL_LENGTH_MAX];
318 } HAL_KEYVAL;
319
320 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
321 if (_e >= _s) \
322 return (AH_FALSE); \
323 } while (0)
324
325 /*
326 * PHY
327 */
328
329 #define AR5K_MAX_RATES 32
330
331 typedef struct {
332 u_int8_t valid;
333 u_int8_t phy;
334 u_int16_t rateKbps;
335 u_int8_t rateCode;
336 u_int8_t shortPreamble;
337 u_int8_t dot11Rate;
338 u_int8_t controlRate;
339
340 #define r_valid valid
341 #define r_phy phy
342 #define r_rate_kbps rateKbps
343 #define r_rate_code rateCode
344 #define r_short_preamble shortPreamble
345 #define r_dot11_rate dot11Rate
346 #define r_control_rate controlRate
347
348 } HAL_RATE;
349
350 typedef struct {
351 u_int16_t rateCount;
352 u_int8_t rateCodeToIndex[AR5K_MAX_RATES];
353 HAL_RATE info[AR5K_MAX_RATES];
354
355 #define rt_rate_count rateCount
356 #define rt_rate_code_index rateCodeToIndex
357 #define rt_info info
358
359 } HAL_RATE_TABLE;
360
361 #define AR5K_RATES_11A { 8, { \
362 255, 255, 255, 255, 255, 255, 255, 255, 6, 4, 2, 0, \
363 7, 5, 3, 1, 255, 255, 255, 255, 255, 255, 255, 255, \
364 255, 255, 255, 255, 255, 255, 255, 255 }, { \
365 { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 0 }, \
366 { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 0 }, \
367 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 2 }, \
368 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 2 }, \
369 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 4 }, \
370 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 4 }, \
371 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 4 }, \
372 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 4 } } \
373 }
374
375 #define AR5K_RATES_11B { 4, { \
376 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
377 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, \
378 3, 2, 1, 0, 255, 255, 255, 255 }, { \
379 { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 }, \
380 { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 132, 1 }, \
381 { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 139, 1 }, \
382 { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 150, 1 } } \
383 }
384
385 #define AR5K_RATES_11G { 12, { \
386 255, 255, 255, 255, 255, 255, 255, 255, 10, 8, 6, 4, \
387 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
388 3, 2, 1, 0, 255, 255, 255, 255 }, { \
389 { 1, IEEE80211_T_CCK, 1000, 27, 0x00, 130, 0 }, \
390 { 1, IEEE80211_T_CCK, 2000, 26, 0x04, 132, 1 }, \
391 { 1, IEEE80211_T_CCK, 5500, 25, 0x04, 139, 2 }, \
392 { 1, IEEE80211_T_CCK, 11000, 24, 0x04, 150, 3 }, \
393 { 0, IEEE80211_T_OFDM, 6000, 11, 0, 12, 4 }, \
394 { 0, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \
395 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 24, 6 }, \
396 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \
397 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 48, 8 }, \
398 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \
399 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \
400 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \
401 }
402
403 #define AR5K_RATES_XR { 12, { \
404 255, 3, 1, 255, 255, 255, 2, 0, 10, 8, 6, 4, \
405 11, 9, 7, 5, 255, 255, 255, 255, 255, 255, 255, 255, \
406 255, 255, 255, 255, 255, 255, 255, 255 }, { \
407 { 1, IEEE80211_T_XR, 500, 7, 0, 129, 0 }, \
408 { 1, IEEE80211_T_XR, 1000, 2, 0, 139, 1 }, \
409 { 1, IEEE80211_T_XR, 2000, 6, 0, 150, 2 }, \
410 { 1, IEEE80211_T_XR, 3000, 1, 0, 150, 3 }, \
411 { 1, IEEE80211_T_OFDM, 6000, 11, 0, 140, 4 }, \
412 { 1, IEEE80211_T_OFDM, 9000, 15, 0, 18, 4 }, \
413 { 1, IEEE80211_T_OFDM, 12000, 10, 0, 152, 6 }, \
414 { 1, IEEE80211_T_OFDM, 18000, 14, 0, 36, 6 }, \
415 { 1, IEEE80211_T_OFDM, 24000, 9, 0, 176, 8 }, \
416 { 1, IEEE80211_T_OFDM, 36000, 13, 0, 72, 8 }, \
417 { 1, IEEE80211_T_OFDM, 48000, 8, 0, 96, 8 }, \
418 { 1, IEEE80211_T_OFDM, 54000, 12, 0, 108, 8 } } \
419 }
420
421 typedef enum {
422 HAL_RFGAIN_INACTIVE = 0,
423 HAL_RFGAIN_READ_REQUESTED,
424 HAL_RFGAIN_NEED_CHANGE,
425 } HAL_RFGAIN;
426
427 typedef struct {
428 u_int16_t channel; /* MHz */
429 u_int16_t channelFlags;
430
431 #define c_channel channel
432 #define c_channel_flags channelFlags
433
434 } HAL_CHANNEL;
435
436 #define HAL_SLOT_TIME_9 396
437 #define HAL_SLOT_TIME_20 880
438 #define HAL_SLOT_TIME_MAX 0xffff
439
440 #define CHANNEL_A (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
441 #define CHANNEL_B (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK)
442 #define CHANNEL_G (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN)
443 #define CHANNEL_PUREG (IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM)
444 #define CHANNEL_XR (CHANNEL_A | IEEE80211_CHAN_XR)
445 #define CHANNEL_MODES \
446 (CHANNEL_A | CHANNEL_B | CHANNEL_G | CHANNEL_PUREG | CHANNEL_XR)
447
448 typedef enum {
449 HAL_CHIP_5GHZ = IEEE80211_CHAN_5GHZ,
450 HAL_CHIP_2GHZ = IEEE80211_CHAN_2GHZ
451 } HAL_CHIP;
452
453 /*
454 * The following structure will be used to map 2GHz channels to
455 * 5GHz Atheros channels.
456 */
457
458 struct ar5k_athchan_2ghz {
459 u_int32_t a2_flags;
460 u_int16_t a2_athchan;
461 };
462
463 /*
464 * Regulation stuff
465 */
466
467 typedef enum ieee80211_countrycode HAL_CTRY_CODE;
468
469 /*
470 * HAL interrupt abstraction
471 */
472
473 #define HAL_INT_RX 0x00000001
474 #define HAL_INT_RXDESC 0x00000002
475 #define HAL_INT_RXNOFRM 0x00000008
476 #define HAL_INT_RXEOL 0x00000010
477 #define HAL_INT_RXORN 0x00000020
478 #define HAL_INT_TX 0x00000040
479 #define HAL_INT_TXDESC 0x00000080
480 #define HAL_INT_TXURN 0x00000800
481 #define HAL_INT_MIB 0x00001000
482 #define HAL_INT_RXPHY 0x00004000
483 #define HAL_INT_RXKCM 0x00008000
484 #define HAL_INT_SWBA 0x00010000
485 #define HAL_INT_BMISS 0x00040000
486 #define HAL_INT_BNR 0x00100000
487 #define HAL_INT_GPIO 0x01000000
488 #define HAL_INT_FATAL 0x40000000
489 #define HAL_INT_GLOBAL 0x80000000
490 #define HAL_INT_NOCARD 0xffffffff
491 #define HAL_INT_COMMON ( \
492 HAL_INT_RXNOFRM | HAL_INT_RXDESC | HAL_INT_RXEOL | \
493 HAL_INT_RXORN | HAL_INT_TXURN | HAL_INT_TXDESC | \
494 HAL_INT_MIB | HAL_INT_RXPHY | HAL_INT_RXKCM | \
495 HAL_INT_SWBA | HAL_INT_BMISS | HAL_INT_GPIO \
496 )
497
498 typedef u_int32_t HAL_INT;
499
500 /*
501 * LED states
502 */
503
504 typedef enum ieee80211_state HAL_LED_STATE;
505
506 #define HAL_LED_INIT IEEE80211_S_INIT
507 #define HAL_LED_SCAN IEEE80211_S_SCAN
508 #define HAL_LED_AUTH IEEE80211_S_AUTH
509 #define HAL_LED_ASSOC IEEE80211_S_ASSOC
510 #define HAL_LED_RUN IEEE80211_S_RUN
511
512 /* GPIO-controlled software LED */
513 #define AR5K_SOFTLED_PIN 0
514 #define AR5K_SOFTLED_ON 0
515 #define AR5K_SOFTLED_OFF 1
516
517 /*
518 * Gain settings
519 */
520
521 #define AR5K_GAIN_CRN_FIX_BITS_5111 4
522 #define AR5K_GAIN_CRN_FIX_BITS_5112 7
523 #define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
524 #define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
525 #define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
526 #define AR5K_GAIN_CCK_PROBE_CORR 5
527 #define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
528 #define AR5K_GAIN_STEP_COUNT 10
529 #define AR5K_GAIN_PARAM_TX_CLIP 0
530 #define AR5K_GAIN_PARAM_PD_90 1
531 #define AR5K_GAIN_PARAM_PD_84 2
532 #define AR5K_GAIN_PARAM_GAIN_SEL 3
533 #define AR5K_GAIN_PARAM_MIX_ORN 0
534 #define AR5K_GAIN_PARAM_PD_138 1
535 #define AR5K_GAIN_PARAM_PD_137 2
536 #define AR5K_GAIN_PARAM_PD_136 3
537 #define AR5K_GAIN_PARAM_PD_132 4
538 #define AR5K_GAIN_PARAM_PD_131 5
539 #define AR5K_GAIN_PARAM_PD_130 6
540 #define AR5K_GAIN_CHECK_ADJUST(_g) \
541 ((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
542
543 struct ar5k_gain_opt_step {
544 int16_t gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
545 int32_t gos_gain;
546 };
547
548 struct ar5k_gain_opt {
549 u_int32_t go_default;
550 u_int32_t go_steps_count;
551 const struct ar5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
552 };
553
554 struct ar5k_gain {
555 u_int32_t g_step_idx;
556 u_int32_t g_current;
557 u_int32_t g_target;
558 u_int32_t g_low;
559 u_int32_t g_high;
560 u_int32_t g_f_corr;
561 u_int32_t g_active;
562 const struct ar5k_gain_opt_step *g_step;
563 };
564
565 #define AR5K_AR5111_GAIN_OPT { \
566 4, \
567 9, \
568 { \
569 { { 4, 1, 1, 1 }, 6 }, \
570 { { 4, 0, 1, 1 }, 4 }, \
571 { { 3, 1, 1, 1 }, 3 }, \
572 { { 4, 0, 0, 1 }, 1 }, \
573 { { 4, 1, 1, 0 }, 0 }, \
574 { { 4, 0, 1, 0 }, -2 }, \
575 { { 3, 1, 1, 0 }, -3 }, \
576 { { 4, 0, 0, 0 }, -4 }, \
577 { { 2, 1, 1, 0 }, -6 } \
578 } \
579 }
580
581 #define AR5K_AR5112_GAIN_OPT { \
582 1, \
583 8, \
584 { \
585 { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \
586 { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \
587 { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \
588 { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \
589 { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \
590 { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \
591 { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \
592 { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \
593 } \
594 }
595
596 /*
597 * Common ar5xxx EEPROM data registers
598 */
599
600 #define AR5K_EEPROM_MAGIC 0x003d
601 #define AR5K_EEPROM_MAGIC_VALUE 0x5aa5
602 #define AR5K_EEPROM_PROTECT 0x003f
603 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001
604 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002
605 #define AR5K_EEPROM_PROTECT_RD_32_63 0x0004
606 #define AR5K_EEPROM_PROTECT_WR_32_63 0x0008
607 #define AR5K_EEPROM_PROTECT_RD_64_127 0x0010
608 #define AR5K_EEPROM_PROTECT_WR_64_127 0x0020
609 #define AR5K_EEPROM_PROTECT_RD_128_191 0x0040
610 #define AR5K_EEPROM_PROTECT_WR_128_191 0x0080
611 #define AR5K_EEPROM_PROTECT_RD_192_207 0x0100
612 #define AR5K_EEPROM_PROTECT_WR_192_207 0x0200
613 #define AR5K_EEPROM_PROTECT_RD_208_223 0x0400
614 #define AR5K_EEPROM_PROTECT_WR_208_223 0x0800
615 #define AR5K_EEPROM_PROTECT_RD_224_239 0x1000
616 #define AR5K_EEPROM_PROTECT_WR_224_239 0x2000
617 #define AR5K_EEPROM_PROTECT_RD_240_255 0x4000
618 #define AR5K_EEPROM_PROTECT_WR_240_255 0x8000
619 #define AR5K_EEPROM_REG_DOMAIN 0x00bf
620 #define AR5K_EEPROM_INFO_BASE 0x00c0
621 #define AR5K_EEPROM_INFO_MAX \
622 (0x400 - AR5K_EEPROM_INFO_BASE)
623 #define AR5K_EEPROM_INFO_CKSUM 0xffff
624 #define AR5K_EEPROM_INFO(_n) (AR5K_EEPROM_INFO_BASE + (_n))
625
626 #define AR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1)
627 #define AR5K_EEPROM_VERSION_3_0 0x3000
628 #define AR5K_EEPROM_VERSION_3_1 0x3001
629 #define AR5K_EEPROM_VERSION_3_2 0x3002
630 #define AR5K_EEPROM_VERSION_3_3 0x3003
631 #define AR5K_EEPROM_VERSION_3_4 0x3004
632 #define AR5K_EEPROM_VERSION_4_0 0x4000
633 #define AR5K_EEPROM_VERSION_4_1 0x4001
634 #define AR5K_EEPROM_VERSION_4_2 0x4002
635 #define AR5K_EEPROM_VERSION_4_3 0x4003
636 #define AR5K_EEPROM_VERSION_4_6 0x4006
637 #define AR5K_EEPROM_VERSION_4_7 0x3007
638
639 #define AR5K_EEPROM_MODE_11A 0
640 #define AR5K_EEPROM_MODE_11B 1
641 #define AR5K_EEPROM_MODE_11G 2
642
643 #define AR5K_EEPROM_HDR AR5K_EEPROM_INFO(2)
644 #define AR5K_EEPROM_HDR_11A(_v) (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
645 #define AR5K_EEPROM_HDR_11B(_v) (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
646 #define AR5K_EEPROM_HDR_11G(_v) (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
647 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1)
648 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f)
649 #define AR5K_EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
650 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1)
651 #define AR5K_EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1)
652
653 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
654 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S 2
655 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
656 #define AR5K_EEPROM_RFKILL_POLARITY_S 1
657
658 /* Newer EEPROMs are using a different offset */
659 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
660 (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
661
662 #define AR5K_EEPROM_ANT_GAIN(_v) AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
663 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
664 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
665
666 #define AR5K_EEPROM_MODES_11A(_v) AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
667 #define AR5K_EEPROM_MODES_11B(_v) AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
668 #define AR5K_EEPROM_MODES_11G(_v) AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
669 #define AR5K_EEPROM_CTL(_v) AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)
670
671 /* Since 3.1 */
672 #define AR5K_EEPROM_OBDB0_2GHZ 0x00ec
673 #define AR5K_EEPROM_OBDB1_2GHZ 0x00ed
674
675 /* Misc values available since EEPROM 4.0 */
676 #define AR5K_EEPROM_MISC0 0x00c4
677 #define AR5K_EEPROM_EARSTART(_v) ((_v) & 0xfff)
678 #define AR5K_EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
679 #define AR5K_EEPROM_MISC1 0x00c5
680 #define AR5K_EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
681 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
682
683 /* Some EEPROM defines */
684 #define AR5K_EEPROM_EEP_SCALE 100
685 #define AR5K_EEPROM_EEP_DELTA 10
686 #define AR5K_EEPROM_N_MODES 3
687 #define AR5K_EEPROM_N_5GHZ_CHAN 10
688 #define AR5K_EEPROM_N_2GHZ_CHAN 3
689 #define AR5K_EEPROM_MAX_CHAN 10
690 #define AR5K_EEPROM_N_PCDAC 11
691 #define AR5K_EEPROM_N_TEST_FREQ 8
692 #define AR5K_EEPROM_N_EDGES 8
693 #define AR5K_EEPROM_N_INTERCEPTS 11
694 #define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
695 #define AR5K_EEPROM_PCDAC_M 0x3f
696 #define AR5K_EEPROM_PCDAC_START 1
697 #define AR5K_EEPROM_PCDAC_STOP 63
698 #define AR5K_EEPROM_PCDAC_STEP 1
699 #define AR5K_EEPROM_NON_EDGE_M 0x40
700 #define AR5K_EEPROM_CHANNEL_POWER 8
701 #define AR5K_EEPROM_N_OBDB 4
702 #define AR5K_EEPROM_OBDB_DIS 0xffff
703 #define AR5K_EEPROM_CHANNEL_DIS 0xff
704 #define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
705 #define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
706 #define AR5K_EEPROM_MAX_CTLS 32
707 #define AR5K_EEPROM_N_XPD_PER_CHANNEL 4
708 #define AR5K_EEPROM_N_XPD0_POINTS 4
709 #define AR5K_EEPROM_N_XPD3_POINTS 3
710 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
711 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
712 #define AR5K_EEPROM_POWER_M 0x3f
713 #define AR5K_EEPROM_POWER_MIN 0
714 #define AR5K_EEPROM_POWER_MAX 3150
715 #define AR5K_EEPROM_POWER_STEP 50
716 #define AR5K_EEPROM_POWER_TABLE_SIZE 64
717 #define AR5K_EEPROM_N_POWER_LOC_11B 4
718 #define AR5K_EEPROM_N_POWER_LOC_11G 6
719 #define AR5K_EEPROM_I_GAIN 10
720 #define AR5K_EEPROM_CCK_OFDM_DELTA 15
721 #define AR5K_EEPROM_N_IQ_CAL 2
722
723 struct ar5k_eeprom_info {
724 u_int16_t ee_magic;
725 u_int16_t ee_protect;
726 u_int16_t ee_regdomain;
727 u_int16_t ee_version;
728 u_int16_t ee_header;
729 u_int16_t ee_ant_gain;
730 u_int16_t ee_misc0;
731 u_int16_t ee_misc1;
732 u_int16_t ee_cck_ofdm_gain_delta;
733 u_int16_t ee_cck_ofdm_power_delta;
734 u_int16_t ee_scaled_cck_delta;
735 u_int16_t ee_tx_clip;
736 u_int16_t ee_pwd_84;
737 u_int16_t ee_pwd_90;
738 u_int16_t ee_gain_select;
739
740 u_int16_t ee_i_cal[AR5K_EEPROM_N_MODES];
741 u_int16_t ee_q_cal[AR5K_EEPROM_N_MODES];
742 u_int16_t ee_fixed_bias[AR5K_EEPROM_N_MODES];
743 u_int16_t ee_xr_power[AR5K_EEPROM_N_MODES];
744 u_int16_t ee_switch_settling[AR5K_EEPROM_N_MODES];
745 u_int16_t ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
746 u_int16_t ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
747 u_int16_t ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
748 u_int16_t ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
749 u_int16_t ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
750 u_int16_t ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
751 u_int16_t ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
752 u_int16_t ee_thr_62[AR5K_EEPROM_N_MODES];
753 u_int16_t ee_xlna_gain[AR5K_EEPROM_N_MODES];
754 u_int16_t ee_xpd[AR5K_EEPROM_N_MODES];
755 u_int16_t ee_x_gain[AR5K_EEPROM_N_MODES];
756 u_int16_t ee_i_gain[AR5K_EEPROM_N_MODES];
757 u_int16_t ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
758 u_int16_t ee_false_detect[AR5K_EEPROM_N_MODES];
759 u_int16_t ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN];
760 u_int16_t ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN];
761
762 u_int16_t ee_ctls;
763 u_int16_t ee_ctl[AR5K_EEPROM_MAX_CTLS];
764
765 int16_t ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
766 int8_t ee_adc_desired_size[AR5K_EEPROM_N_MODES];
767 int8_t ee_pga_desired_size[AR5K_EEPROM_N_MODES];
768 };
769
770 /*
771 * Chipset capabilities
772 */
773
774 typedef struct {
775 /*
776 * Supported PHY modes
777 * (ie. IEEE80211_CHAN_A, IEEE80211_CHAN_B, ...)
778 */
779 u_int16_t cap_mode;
780
781 /*
782 * Frequency range (without regulation restrictions)
783 */
784 struct {
785 u_int16_t range_2ghz_min;
786 u_int16_t range_2ghz_max;
787 u_int16_t range_5ghz_min;
788 u_int16_t range_5ghz_max;
789 } cap_range;
790
791 /*
792 * Active regulation domain settings
793 */
794 struct {
795 ieee80211_regdomain_t reg_current;
796 ieee80211_regdomain_t reg_hw;
797 } cap_regdomain;
798
799 /*
800 * Values stored in the EEPROM (some of them...)
801 */
802 struct ar5k_eeprom_info cap_eeprom;
803
804 /*
805 * Queue information
806 */
807 struct {
808 u_int8_t q_tx_num;
809 } cap_queues;
810 } ar5k_capabilities_t;
811
812 /*
813 * TX power and TPC settings
814 */
815
816 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
817 ((0 & 1) << ((_v) + 6)) | \
818 (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
819 )
820
821 #define AR5K_TXPOWER_CCK(_r, _v) ( \
822 (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
823 )
824
825 /*
826 * Atheros descriptor definitions
827 */
828
829 struct ath_tx_status {
830 u_int16_t ts_seqnum;
831 u_int16_t ts_tstamp;
832 u_int8_t ts_status;
833 u_int8_t ts_rate;
834 int8_t ts_rssi;
835 u_int8_t ts_shortretry;
836 u_int8_t ts_longretry;
837 u_int8_t ts_virtcol;
838 u_int8_t ts_antenna;
839 };
840
841 #define HAL_TXSTAT_ALTRATE 0x80
842 #define HAL_TXERR_XRETRY 0x01
843 #define HAL_TXERR_FILT 0x02
844 #define HAL_TXERR_FIFO 0x04
845
846 struct ath_rx_status {
847 u_int16_t rs_datalen;
848 u_int16_t rs_tstamp;
849 u_int8_t rs_status;
850 u_int8_t rs_phyerr;
851 int8_t rs_rssi;
852 u_int8_t rs_keyix;
853 u_int8_t rs_rate;
854 u_int8_t rs_antenna;
855 u_int8_t rs_more;
856 };
857
858 #define HAL_RXERR_CRC 0x01
859 #define HAL_RXERR_PHY 0x02
860 #define HAL_RXERR_FIFO 0x04
861 #define HAL_RXERR_DECRYPT 0x08
862 #define HAL_RXERR_MIC 0x10
863 #define HAL_RXKEYIX_INVALID ((u_int8_t) - 1)
864 #define HAL_TXKEYIX_INVALID ((u_int32_t) - 1)
865
866 #define HAL_PHYERR_UNDERRUN 0x00
867 #define HAL_PHYERR_TIMING 0x01
868 #define HAL_PHYERR_PARITY 0x02
869 #define HAL_PHYERR_RATE 0x03
870 #define HAL_PHYERR_LENGTH 0x04
871 #define HAL_PHYERR_RADAR 0x05
872 #define HAL_PHYERR_SERVICE 0x06
873 #define HAL_PHYERR_TOR 0x07
874 #define HAL_PHYERR_OFDM_TIMING 0x11
875 #define HAL_PHYERR_OFDM_SIGNAL_PARITY 0x12
876 #define HAL_PHYERR_OFDM_RATE_ILLEGAL 0x13
877 #define HAL_PHYERR_OFDM_LENGTH_ILLEGAL 0x14
878 #define HAL_PHYERR_OFDM_POWER_DROP 0x15
879 #define HAL_PHYERR_OFDM_SERVICE 0x16
880 #define HAL_PHYERR_OFDM_RESTART 0x17
881 #define HAL_PHYERR_CCK_TIMING 0x19
882 #define HAL_PHYERR_CCK_HEADER_CRC 0x1a
883 #define HAL_PHYERR_CCK_RATE_ILLEGAL 0x1b
884 #define HAL_PHYERR_CCK_SERVICE 0x1e
885 #define HAL_PHYERR_CCK_RESTART 0x1f
886
887 struct ath_desc {
888 u_int32_t ds_link;
889 u_int32_t ds_data;
890 u_int32_t ds_ctl0;
891 u_int32_t ds_ctl1;
892 u_int32_t ds_hw[4];
893
894 union {
895 struct ath_rx_status rx;
896 struct ath_tx_status tx;
897 } ds_us;
898
899 #define ds_rxstat ds_us.rx
900 #define ds_txstat ds_us.tx
901
902 } __packed;
903
904 #define HAL_RXDESC_INTREQ 0x0020
905
906 #define HAL_TXDESC_CLRDMASK 0x0001
907 #define HAL_TXDESC_NOACK 0x0002
908 #define HAL_TXDESC_RTSENA 0x0004
909 #define HAL_TXDESC_CTSENA 0x0008
910 #define HAL_TXDESC_INTREQ 0x0010
911 #define HAL_TXDESC_VEOL 0x0020
912
913 /*
914 * Hardware abstraction layer structure
915 */
916
917 #define AR5K_HAL_FUNCTION(_hal, _n, _f) (_hal)->ah_##_f = ar5k_##_n##_##_f
918 #define AR5K_HAL_FUNCTIONS(_t, _n, _a) \
919 _t const HAL_RATE_TABLE *(_a _n##_get_rate_table)(struct ath_hal *, \
920 u_int mode); \
921 _t void (_a _n##_detach)(struct ath_hal *); \
922 /* Reset functions */ \
923 _t HAL_BOOL (_a _n##_reset)(struct ath_hal *, HAL_OPMODE, \
924 HAL_CHANNEL *, HAL_BOOL change_channel, HAL_STATUS *status); \
925 _t void (_a _n##_set_opmode)(struct ath_hal *); \
926 _t HAL_BOOL (_a _n##_calibrate)(struct ath_hal*, \
927 HAL_CHANNEL *); \
928 /* Transmit functions */ \
929 _t HAL_BOOL (_a _n##_update_tx_triglevel)(struct ath_hal*, \
930 HAL_BOOL level); \
931 _t int (_a _n##_setup_tx_queue)(struct ath_hal *, HAL_TX_QUEUE, \
932 const HAL_TXQ_INFO *); \
933 _t HAL_BOOL (_a _n##_setup_tx_queueprops)(struct ath_hal *, int queue, \
934 const HAL_TXQ_INFO *); \
935 _t HAL_BOOL (_a _n##_release_tx_queue)(struct ath_hal *, u_int queue); \
936 _t HAL_BOOL (_a _n##_reset_tx_queue)(struct ath_hal *, u_int queue); \
937 _t u_int32_t (_a _n##_get_tx_buf)(struct ath_hal *, u_int queue); \
938 _t HAL_BOOL (_a _n##_put_tx_buf)(struct ath_hal *, u_int, \
939 u_int32_t phys_addr); \
940 _t HAL_BOOL (_a _n##_tx_start)(struct ath_hal *, u_int queue); \
941 _t HAL_BOOL (_a _n##_stop_tx_dma)(struct ath_hal *, u_int queue); \
942 _t HAL_BOOL (_a _n##_setup_tx_desc)(struct ath_hal *, \
943 struct ath_desc *, \
944 u_int packet_length, u_int header_length, HAL_PKT_TYPE type, \
945 u_int txPower, u_int tx_rate0, u_int tx_tries0, u_int key_index, \
946 u_int antenna_mode, u_int flags, u_int rtscts_rate, \
947 u_int rtscts_duration); \
948 _t HAL_BOOL (_a _n##_setup_xtx_desc)(struct ath_hal *, \
949 struct ath_desc *, \
950 u_int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2, \
951 u_int tx_rate3, u_int tx_tries3); \
952 _t HAL_BOOL (_a _n##_fill_tx_desc)(struct ath_hal *, \
953 struct ath_desc *, \
954 u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg); \
955 _t HAL_STATUS (_a _n##_proc_tx_desc)(struct ath_hal *, \
956 struct ath_desc *); \
957 _t HAL_BOOL (_a _n##_has_veol)(struct ath_hal *); \
958 /* Receive Functions */ \
959 _t u_int32_t (_a _n##_get_rx_buf)(struct ath_hal*); \
960 _t void (_a _n##_put_rx_buf)(struct ath_hal*, u_int32_t rxdp); \
961 _t void (_a _n##_start_rx)(struct ath_hal*); \
962 _t HAL_BOOL (_a _n##_stop_rx_dma)(struct ath_hal*); \
963 _t void (_a _n##_start_rx_pcu)(struct ath_hal*); \
964 _t void (_a _n##_stop_pcu_recv)(struct ath_hal*); \
965 _t void (_a _n##_set_mcast_filter)(struct ath_hal*, \
966 u_int32_t filter0, u_int32_t filter1); \
967 _t HAL_BOOL (_a _n##_set_mcast_filterindex)(struct ath_hal*, \
968 u_int32_t index); \
969 _t HAL_BOOL (_a _n##_clear_mcast_filter_idx)(struct ath_hal*, \
970 u_int32_t index); \
971 _t u_int32_t (_a _n##_get_rx_filter)(struct ath_hal*); \
972 _t void (_a _n##_set_rx_filter)(struct ath_hal*, u_int32_t); \
973 _t HAL_BOOL (_a _n##_setup_rx_desc)(struct ath_hal *, \
974 struct ath_desc *, u_int32_t size, u_int flags); \
975 _t HAL_STATUS (_a _n##_proc_rx_desc)(struct ath_hal *, \
976 struct ath_desc *, u_int32_t phyAddr, struct ath_desc *next); \
977 _t void (_a _n##_set_rx_signal)(struct ath_hal *); \
978 /* Misc Functions */ \
979 _t void (_a _n##_dump_state)(struct ath_hal *); \
980 _t HAL_BOOL (_a _n##_get_diag_state)(struct ath_hal *, int, void **, \
981 u_int *); \
982 _t void (_a _n##_get_lladdr)(struct ath_hal *, u_int8_t *); \
983 _t HAL_BOOL (_a _n##_set_lladdr)(struct ath_hal *, \
984 const u_int8_t*); \
985 _t HAL_BOOL (_a _n##_set_regdomain)(struct ath_hal*, \
986 u_int16_t, HAL_STATUS *); \
987 _t void (_a _n##_set_ledstate)(struct ath_hal*, HAL_LED_STATE); \
988 _t void (_a _n##_set_associd)(struct ath_hal*, \
989 const u_int8_t *bssid, u_int16_t assocId, u_int16_t timOffset); \
990 _t HAL_BOOL (_a _n##_set_gpio_output)(struct ath_hal *, \
991 u_int32_t gpio); \
992 _t HAL_BOOL (_a _n##_set_gpio_input)(struct ath_hal *, \
993 u_int32_t gpio); \
994 _t u_int32_t (_a _n##_get_gpio)(struct ath_hal *, u_int32_t gpio); \
995 _t HAL_BOOL (_a _n##_set_gpio)(struct ath_hal *, u_int32_t gpio, \
996 u_int32_t val); \
997 _t void (_a _n##_set_gpio_intr)(struct ath_hal*, u_int, u_int32_t); \
998 _t u_int32_t (_a _n##_get_tsf32)(struct ath_hal*); \
999 _t u_int64_t (_a _n##_get_tsf64)(struct ath_hal*); \
1000 _t void (_a _n##_reset_tsf)(struct ath_hal*); \
1001 _t u_int16_t (_a _n##_get_regdomain)(struct ath_hal*); \
1002 _t HAL_BOOL (_a _n##_detect_card_present)(struct ath_hal*); \
1003 _t void (_a _n##_update_mib_counters)(struct ath_hal*, \
1004 HAL_MIB_STATS*); \
1005 _t HAL_BOOL (_a _n##_is_cipher_supported)(struct ath_hal*, \
1006 HAL_CIPHER); \
1007 _t HAL_RFGAIN (_a _n##_get_rf_gain)(struct ath_hal*); \
1008 _t HAL_BOOL (_a _n##_set_slot_time)(struct ath_hal*, u_int); \
1009 _t u_int (_a _n##_get_slot_time)(struct ath_hal*); \
1010 _t HAL_BOOL (_a _n##_set_ack_timeout)(struct ath_hal *, u_int); \
1011 _t u_int (_a _n##_get_ack_timeout)(struct ath_hal*); \
1012 _t HAL_BOOL (_a _n##_set_cts_timeout)(struct ath_hal*, u_int); \
1013 _t u_int (_a _n##_get_cts_timeout)(struct ath_hal*); \
1014 /* Key Cache Functions */ \
1015 _t u_int32_t (_a _n##_get_keycache_size)(struct ath_hal*); \
1016 _t HAL_BOOL (_a _n##_reset_key)(struct ath_hal*, \
1017 u_int16_t); \
1018 _t HAL_BOOL (_a _n##_is_key_valid)(struct ath_hal *, \
1019 u_int16_t); \
1020 _t HAL_BOOL (_a _n##_set_key)(struct ath_hal*, u_int16_t, \
1021 const HAL_KEYVAL *, const u_int8_t *, int); \
1022 _t HAL_BOOL (_a _n##_set_key_lladdr)(struct ath_hal*, \
1023 u_int16_t, const u_int8_t *); \
1024 _t HAL_BOOL (_a _n##_softcrypto)(struct ath_hal *, HAL_BOOL); \
1025 /* Power Management Functions */ \
1026 _t HAL_BOOL (_a _n##_set_power)(struct ath_hal*, \
1027 HAL_POWER_MODE mode, \
1028 HAL_BOOL set_chip, u_int16_t sleep_duration); \
1029 _t HAL_POWER_MODE (_a _n##_get_power_mode)(struct ath_hal*); \
1030 _t HAL_BOOL (_a _n##_query_pspoll_support)(struct ath_hal*); \
1031 _t HAL_BOOL (_a _n##_init_pspoll)(struct ath_hal*); \
1032 _t HAL_BOOL (_a _n##_enable_pspoll)(struct ath_hal *, u_int8_t *, \
1033 u_int16_t); \
1034 _t HAL_BOOL (_a _n##_disable_pspoll)(struct ath_hal *); \
1035 /* Beacon Management Functions */ \
1036 _t void (_a _n##_init_beacon)(struct ath_hal *, u_int32_t nexttbtt, \
1037 u_int32_t intval); \
1038 _t void (_a _n##_set_beacon_timers)(struct ath_hal *, \
1039 const HAL_BEACON_STATE *, u_int32_t tsf, u_int32_t dtimCount, \
1040 u_int32_t cfpCcount); \
1041 _t void (_a _n##_reset_beacon)(struct ath_hal *); \
1042 _t HAL_BOOL (_a _n##_wait_for_beacon)(struct ath_hal *, \
1043 bus_addr_t); \
1044 /* Interrupt functions */ \
1045 _t HAL_BOOL (_a _n##_is_intr_pending)(struct ath_hal *); \
1046 _t HAL_BOOL (_a _n##_get_isr)(struct ath_hal *, \
1047 u_int32_t *); \
1048 _t u_int32_t (_a _n##_get_intr)(struct ath_hal *); \
1049 _t HAL_INT (_a _n##_set_intr)(struct ath_hal *, HAL_INT); \
1050 /* Chipset functions (ar5k-specific, non-HAL) */ \
1051 _t HAL_BOOL (_a _n##_get_capabilities)(struct ath_hal *); \
1052 _t void (_a _n##_radar_alert)(struct ath_hal *, HAL_BOOL enable); \
1053 _t HAL_BOOL (_a _n##_eeprom_is_busy)(struct ath_hal *); \
1054 _t int (_a _n##_eeprom_read)(struct ath_hal *, u_int32_t offset, \
1055 u_int16_t *data); \
1056 _t int (_a _n##_eeprom_write)(struct ath_hal *, u_int32_t offset, \
1057 u_int16_t data); \
1058 /* Unused functions */ \
1059 _t HAL_BOOL (_a _n##_get_tx_queueprops)(struct ath_hal *, int, \
1060 HAL_TXQ_INFO *); \
1061 _t u_int32_t (_a _n##_num_tx_pending)(struct ath_hal *, u_int); \
1062 _t HAL_BOOL (_a _n##_phy_disable)(struct ath_hal *); \
1063 _t HAL_BOOL (_a _n##_set_txpower_limit)(struct ath_hal *, u_int); \
1064 _t void (_a _n##_set_def_antenna)(struct ath_hal *, u_int); \
1065 _t u_int (_a _n ##_get_def_antenna)(struct ath_hal *); \
1066 _t HAL_BOOL (_a _n##_set_bssid_mask)(struct ath_hal *, \
1067 const u_int8_t*);
1068
1069 #define AR5K_MAX_GPIO 10
1070 #define AR5K_MAX_RF_BANKS 8
1071
1072 struct ath_hal {
1073 u_int32_t ah_magic;
1074 u_int32_t ah_abi;
1075 u_int16_t ah_device;
1076 u_int16_t ah_sub_vendor;
1077
1078 void *ah_sc;
1079 bus_space_tag_t ah_st;
1080 bus_space_handle_t ah_sh;
1081
1082 HAL_INT ah_imr;
1083
1084 HAL_OPMODE ah_op_mode;
1085 HAL_POWER_MODE ah_power_mode;
1086 HAL_CHANNEL ah_current_channel;
1087 HAL_BOOL ah_calibration;
1088 HAL_BOOL ah_running;
1089 HAL_BOOL ah_single_chip;
1090 HAL_BOOL ah_pci_express;
1091 HAL_RFGAIN ah_rf_gain;
1092
1093 int ah_chanoff;
1094
1095 HAL_RATE_TABLE ah_rt_11a;
1096 HAL_RATE_TABLE ah_rt_11b;
1097 HAL_RATE_TABLE ah_rt_11g;
1098 HAL_RATE_TABLE ah_rt_xr;
1099
1100 u_int32_t ah_mac_srev;
1101 u_int16_t ah_mac_version;
1102 u_int16_t ah_mac_revision;
1103 u_int16_t ah_phy_revision;
1104 u_int16_t ah_radio_5ghz_revision;
1105 u_int16_t ah_radio_2ghz_revision;
1106
1107 enum ar5k_version ah_version;
1108 enum ar5k_radio ah_radio;
1109
1110 u_int32_t ah_phy;
1111 u_int32_t ah_phy_spending;
1112
1113 HAL_BOOL ah_5ghz;
1114 HAL_BOOL ah_2ghz;
1115
1116 #define ah_regdomain ah_capabilities.cap_regdomain.reg_current
1117 #define ah_regdomain_hw ah_capabilities.cap_regdomain.reg_hw
1118 #define ah_modes ah_capabilities.cap_mode
1119 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1120
1121 u_int32_t ah_atim_window;
1122 u_int32_t ah_aifs;
1123 u_int32_t ah_cw_min;
1124 u_int32_t ah_cw_max;
1125 HAL_BOOL ah_software_retry;
1126 u_int32_t ah_limit_tx_retries;
1127
1128 u_int32_t ah_antenna[AR5K_EEPROM_N_MODES][HAL_ANT_MAX];
1129 HAL_BOOL ah_ant_diversity;
1130
1131 u_int8_t ah_sta_id[IEEE80211_ADDR_LEN];
1132 u_int8_t ah_bssid[IEEE80211_ADDR_LEN];
1133
1134 u_int32_t ah_gpio[AR5K_MAX_GPIO];
1135 int ah_gpio_npins;
1136
1137 ar5k_capabilities_t ah_capabilities;
1138
1139 HAL_TXQ_INFO ah_txq[HAL_NUM_TX_QUEUES];
1140 u_int32_t ah_txq_interrupts;
1141
1142 u_int32_t *ah_rf_banks;
1143 size_t ah_rf_banks_size;
1144 struct ar5k_gain ah_gain;
1145 u_int32_t ah_offset[AR5K_MAX_RF_BANKS];
1146
1147 struct {
1148 u_int16_t txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
1149 u_int16_t txp_rates[AR5K_MAX_RATES];
1150 int16_t txp_min, txp_max;
1151 HAL_BOOL txp_tpc;
1152 int16_t txp_ofdm;
1153 } ah_txpower;
1154
1155 struct {
1156 HAL_BOOL r_enabled;
1157 int r_last_alert;
1158 HAL_CHANNEL r_last_channel;
1159 } ah_radar;
1160
1161 /*
1162 * Function pointers
1163 */
1164 AR5K_HAL_FUNCTIONS(, ah, *);
1165 };
1166
1167 /*
1168 * Common silicon revision/version values
1169 */
1170 enum ar5k_srev_type {
1171 AR5K_VERSION_VER,
1172 AR5K_VERSION_REV,
1173 AR5K_VERSION_RAD,
1174 AR5K_VERSION_DEV,
1175 };
1176
1177 struct ar5k_srev_name {
1178 const char *sr_name;
1179 enum ar5k_srev_type sr_type;
1180 u_int sr_val;
1181 };
1182
1183 #define AR5K_SREV_NAME { \
1184 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 }, \
1185 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 }, \
1186 { "5311a", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },\
1187 { "5311b", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },\
1188 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 }, \
1189 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 }, \
1190 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 }, \
1191 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },\
1192 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },\
1193 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },\
1194 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },\
1195 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },\
1196 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },\
1197 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },\
1198 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },\
1199 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },\
1200 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },\
1201 { "xxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN }, \
1202 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, \
1203 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, \
1204 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, \
1205 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, \
1206 { "5112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, \
1207 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, \
1208 { "2112a", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, \
1209 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 }, \
1210 { "2414", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 }, \
1211 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 }, \
1212 { "xxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, \
1213 { "2413", AR5K_VERSION_DEV, AR5K_DEVID_AR2413 }, \
1214 { "5413", AR5K_VERSION_DEV, AR5K_DEVID_AR5413 }, \
1215 { "5424", AR5K_VERSION_DEV, AR5K_DEVID_AR5424 }, \
1216 { "xxxx", AR5K_VERSION_DEV, AR5K_SREV_UNKNOWN } \
1217 }
1218 /* XXX: ar5k_printver() needs AR5K_SREV_UNKNOWN in the last member. */
1219
1220 #define AR5K_SREV_UNKNOWN 0xffff
1221
1222 #define AR5K_SREV_VER_AR5210 0x00
1223 #define AR5K_SREV_VER_AR5311 0x10
1224 #define AR5K_SREV_VER_AR5311A 0x20
1225 #define AR5K_SREV_VER_AR5311B 0x30
1226 #define AR5K_SREV_VER_AR5211 0x40
1227 #define AR5K_SREV_VER_AR5212 0x50
1228 #define AR5K_SREV_VER_AR5213 0x55
1229 #define AR5K_SREV_VER_AR5213A 0x59
1230 #define AR5K_SREV_VER_AR2413 0x78
1231 #define AR5K_SREV_VER_AR2414 0x79
1232 #define AR5K_SREV_VER_AR2424 0xa0 /* PCI-Express */
1233 #define AR5K_SREV_VER_AR5424 0xa3 /* PCI-Express */
1234 #define AR5K_SREV_VER_AR5413 0xa4
1235 #define AR5K_SREV_VER_AR5414 0xa5
1236 #define AR5K_SREV_VER_AR5416 0xc0 /* PCI-Express */
1237 #define AR5K_SREV_VER_AR5418 0xca /* PCI-Express */
1238 #define AR5K_SREV_VER_AR2425 0xe2 /* PCI-Express */
1239 #define AR5K_SREV_VER_UNSUPP 0xff
1240
1241 #define AR5K_SREV_RAD_5110 0x00
1242 #define AR5K_SREV_RAD_5111 0x10
1243 #define AR5K_SREV_RAD_5111A 0x15
1244 #define AR5K_SREV_RAD_2111 0x20
1245 #define AR5K_SREV_RAD_5112 0x30
1246 #define AR5K_SREV_RAD_5112A 0x35
1247 #define AR5K_SREV_RAD_2112 0x40
1248 #define AR5K_SREV_RAD_2112A 0x45
1249 #define AR5K_SREV_RAD_SC0 0x56
1250 #define AR5K_SREV_RAD_SC1 0x63
1251 #define AR5K_SREV_RAD_SC2 0xa2
1252 #define AR5K_SREV_RAD_5133 0xc0
1253 #define AR5K_SREV_RAD_UNSUPP 0xff
1254
1255 #define AR5K_DEVID_AR2413 0x001a
1256 #define AR5K_DEVID_AR5413 0x001b
1257 #define AR5K_DEVID_AR5424 0x001c
1258
1259 /*
1260 * Misc defines
1261 */
1262
1263 #define HAL_ABI_VERSION 0x04090901 /* YYMMDDnn */
1264
1265 #define AR5K_PRINTF(fmt, ...) printf("%s: " fmt, __func__, ##__VA_ARGS__)
1266 #define AR5K_PRINT(fmt) printf("%s: " fmt, __func__)
1267 #ifdef AR5K_DEBUG
1268 #define AR5K_TRACE printf("%s:%d\n", __func__, __LINE__)
1269 #else
1270 #define AR5K_TRACE
1271 #endif
1272 #define AR5K_DELAY(_n) delay(_n)
1273
1274 typedef struct ath_hal * (ar5k_attach_t)
1275 (u_int16_t, void *, bus_space_tag_t, bus_space_handle_t, HAL_STATUS *);
1276 typedef HAL_BOOL (ar5k_rfgain_t)
1277 (struct ath_hal *, HAL_CHANNEL *, u_int);
1278
1279 /*
1280 * Some tuneable values (these should be changeable by the user)
1281 */
1282
1283 #define AR5K_TUNE_DMA_BEACON_RESP 2
1284 #define AR5K_TUNE_SW_BEACON_RESP 10
1285 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
1286 #define AR5K_TUNE_RADAR_ALERT AH_FALSE
1287 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
1288 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
1289 #define AR5K_TUNE_RSSI_THRES 1792
1290 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
1291 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
1292 #define AR5K_TUNE_BEACON_INTERVAL 100
1293 #define AR5K_TUNE_AIFS 2
1294 #define AR5K_TUNE_AIFS_11B 2
1295 #define AR5K_TUNE_AIFS_XR 0
1296 #define AR5K_TUNE_CWMIN 15
1297 #define AR5K_TUNE_CWMIN_11B 31
1298 #define AR5K_TUNE_CWMIN_XR 3
1299 #define AR5K_TUNE_CWMAX 1023
1300 #define AR5K_TUNE_CWMAX_11B 1023
1301 #define AR5K_TUNE_CWMAX_XR 7
1302 #define AR5K_TUNE_NOISE_FLOOR -72
1303 #define AR5K_TUNE_MAX_TXPOWER 60
1304 #define AR5K_TUNE_DEFAULT_TXPOWER 30
1305 #define AR5K_TUNE_TPC_TXPOWER AH_TRUE
1306 #define AR5K_TUNE_ANT_DIVERSITY AH_TRUE
1307
1308 /* Default regulation domain if stored value EEPROM value is invalid */
1309 #define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */
1310
1311 /*
1312 * Common initial register values
1313 */
1314
1315 #define AR5K_INIT_MODE ( \
1316 IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN \
1317 )
1318 #define AR5K_INIT_TX_LATENCY 502
1319 #define AR5K_INIT_USEC 39
1320 #define AR5K_INIT_USEC_TURBO 79
1321 #define AR5K_INIT_USEC_32 31
1322 #define AR5K_INIT_CARR_SENSE_EN 1
1323 #define AR5K_INIT_PROG_IFS 920
1324 #define AR5K_INIT_PROG_IFS_TURBO 960
1325 #define AR5K_INIT_EIFS 3440
1326 #define AR5K_INIT_EIFS_TURBO 6880
1327 #define AR5K_INIT_SLOT_TIME 396
1328 #define AR5K_INIT_SLOT_TIME_TURBO 480
1329 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
1330 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
1331 #define AR5K_INIT_SIFS 560
1332 #define AR5K_INIT_SIFS_TURBO 480
1333 #define AR5K_INIT_SH_RETRY 10
1334 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
1335 #define AR5K_INIT_SSH_RETRY 32
1336 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
1337 #define AR5K_INIT_TX_RETRY 10
1338 #define AR5K_INIT_TOPS 8
1339 #define AR5K_INIT_RXNOFRM 8
1340 #define AR5K_INIT_RPGTO 0
1341 #define AR5K_INIT_TXNOFRM 0
1342 #define AR5K_INIT_BEACON_PERIOD 65535
1343 #define AR5K_INIT_TIM_OFFSET 0
1344 #define AR5K_INIT_BEACON_EN 0
1345 #define AR5K_INIT_RESET_TSF 0
1346 #define AR5K_INIT_TRANSMIT_LATENCY ( \
1347 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
1348 (AR5K_INIT_USEC) \
1349 )
1350 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
1351 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
1352 (AR5K_INIT_USEC_TURBO) \
1353 )
1354 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
1355 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
1356 (AR5K_INIT_PROG_IFS) \
1357 )
1358 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
1359 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) |\
1360 (AR5K_INIT_PROG_IFS_TURBO) \
1361 )
1362 #define AR5K_INIT_BEACON_CONTROL ( \
1363 (AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \
1364 (AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \
1365 )
1366
1367 /*
1368 * AR5k register access
1369 */
1370
1371 #define AR5K_REG_WRITE(_reg, _val) \
1372 bus_space_write_4(hal->ah_st, hal->ah_sh, (_reg), (_val))
1373 #define AR5K_REG_READ(_reg) \
1374 bus_space_read_4(hal->ah_st, hal->ah_sh, (_reg))
1375
1376 #define AR5K_REG_SM(_val, _flags) \
1377 (((uint32_t)(_val) << _flags##_S) & (_flags))
1378 #define AR5K_REG_MS(_val, _flags) \
1379 (((uint32_t)(_val) & (_flags)) >> _flags##_S)
1380 #define AR5K_REG_WRITE_BITS(_reg, _flags, _val) \
1381 AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) &~ (_flags)) | \
1382 (((_val) << _flags##_S) & (_flags)))
1383 #define AR5K_REG_MASKED_BITS(_reg, _flags, _mask) \
1384 AR5K_REG_WRITE(_reg, (AR5K_REG_READ(_reg) & (_mask)) | (_flags))
1385 #define AR5K_REG_ENABLE_BITS(_reg, _flags) \
1386 AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) | (_flags))
1387 #define AR5K_REG_DISABLE_BITS(_reg, _flags) \
1388 AR5K_REG_WRITE(_reg, AR5K_REG_READ(_reg) &~ (_flags))
1389
1390 #define AR5K_PHY_WRITE(_reg, _val) \
1391 AR5K_REG_WRITE(hal->ah_phy + ((_reg) << 2), _val)
1392 #define AR5K_PHY_READ(_reg) \
1393 AR5K_REG_READ(hal->ah_phy + ((_reg) << 2))
1394
1395 #define AR5K_REG_WAIT(_i) \
1396 if (_i % 64) \
1397 AR5K_DELAY(1);
1398
1399 #define AR5K_EEPROM_READ(_o, _v) { \
1400 if ((ret = hal->ah_eeprom_read(hal, (_o), \
1401 &(_v))) != 0) \
1402 return (ret); \
1403 }
1404 #define AR5K_EEPROM_READ_HDR(_o, _v) \
1405 AR5K_EEPROM_READ(_o, hal->ah_capabilities.cap_eeprom._v); \
1406
1407 /* Read status of selected queue */
1408 #define AR5K_REG_READ_Q(_reg, _queue) \
1409 (AR5K_REG_READ(_reg) & (1 << _queue)) \
1410
1411 #define AR5K_REG_WRITE_Q(_reg, _queue) \
1412 AR5K_REG_WRITE(_reg, (1 << _queue))
1413
1414 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
1415 _reg |= 1 << _queue; \
1416 } while (0)
1417
1418 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
1419 _reg &= ~(1 << _queue); \
1420 } while (0)
1421
1422 #define AR5K_LOW_ID(_a) ( \
1423 (_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
1424 )
1425 #define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
1426
1427 /*
1428 * Unaligned little endian access
1429 */
1430
1431 #define AR5K_LE_READ_2(_p) \
1432 (((const u_int8_t *)(_p))[0] | (((const u_int8_t *)(_p))[1] << 8))
1433 #define AR5K_LE_READ_4(_p) \
1434 (((const u_int8_t *)(_p))[0] | \
1435 (((const u_int8_t *)(_p))[1] << 8) | \
1436 (((const u_int8_t *)(_p))[2] << 16) | \
1437 (((const u_int8_t *)(_p))[3] << 24))
1438 #define AR5K_LE_WRITE_2(_p, _val) \
1439 ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \
1440 (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)))
1441 #define AR5K_LE_WRITE_4(_p, _val) \
1442 ((((u_int8_t *)(_p))[0] = ((u_int32_t)(_val) & 0xff)), \
1443 (((u_int8_t *)(_p))[1] = (((u_int32_t)(_val) >> 8) & 0xff)), \
1444 (((u_int8_t *)(_p))[2] = (((u_int32_t)(_val) >> 16) & 0xff)), \
1445 (((u_int8_t *)(_p))[3] = (((u_int32_t)(_val) >> 24) & 0xff)))
1446
1447 /*
1448 * Initial register values
1449 */
1450
1451 struct ar5k_ini {
1452 u_int16_t ini_register;
1453 u_int32_t ini_value;
1454
1455 enum {
1456 AR5K_INI_WRITE = 0,
1457 AR5K_INI_READ = 1,
1458 } ini_mode;
1459 };
1460
1461 #define AR5K_PCU_MIN 0x8000
1462 #define AR5K_PCU_MAX 0x8fff
1463
1464 #define AR5K_INI_VAL_11A 0
1465 #define AR5K_INI_VAL_11A_TURBO 1
1466 #define AR5K_INI_VAL_11B 2
1467 #define AR5K_INI_VAL_11G 3
1468 #define AR5K_INI_VAL_11G_TURBO 4
1469 #define AR5K_INI_VAL_XR 0
1470 #define AR5K_INI_VAL_MAX 5
1471
1472 struct ar5k_mode {
1473 u_int16_t mode_register;
1474 u_int32_t mode_value[AR5K_INI_VAL_MAX];
1475 };
1476
1477 #define AR5K_INI_PHY_5111 0
1478 #define AR5K_INI_PHY_5112 1
1479 #define AR5K_INI_PHY_511X 1
1480
1481 #define AR5K_AR5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
1482 #define AR5K_AR5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
1483
1484 struct ar5k_ini_rf {
1485 u_int8_t rf_bank;
1486 u_int16_t rf_register;
1487 u_int32_t rf_value[5];
1488 };
1489
1490 #define AR5K_AR5111_INI_RF { \
1491 { 0, 0x989c, \
1492 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1493 { 0, 0x989c, \
1494 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1495 { 0, 0x989c, \
1496 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1497 { 0, 0x989c, \
1498 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1499 { 0, 0x989c, \
1500 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1501 { 0, 0x989c, \
1502 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1503 { 0, 0x989c, \
1504 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1505 { 0, 0x989c, \
1506 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1507 { 0, 0x989c, \
1508 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1509 { 0, 0x989c, \
1510 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1511 { 0, 0x989c, \
1512 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1513 { 0, 0x989c, \
1514 { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } }, \
1515 { 0, 0x989c, \
1516 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1517 { 0, 0x989c, \
1518 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1519 { 0, 0x989c, \
1520 { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } }, \
1521 { 0, 0x989c, \
1522 { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } }, \
1523 { 0, 0x98d4, \
1524 { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } }, \
1525 { 1, 0x98d4, \
1526 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
1527 { 2, 0x98d4, \
1528 { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } }, \
1529 { 3, 0x98d8, \
1530 { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } }, \
1531 { 6, 0x989c, \
1532 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1533 { 6, 0x989c, \
1534 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1535 { 6, 0x989c, \
1536 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1537 { 6, 0x989c, \
1538 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1539 { 6, 0x989c, \
1540 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1541 { 6, 0x989c, \
1542 { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } }, \
1543 { 6, 0x989c, \
1544 { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } }, \
1545 { 6, 0x989c, \
1546 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1547 { 6, 0x989c, \
1548 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1549 { 6, 0x989c, \
1550 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1551 { 6, 0x989c, \
1552 { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } }, \
1553 { 6, 0x989c, \
1554 { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } }, \
1555 { 6, 0x989c, \
1556 { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } }, \
1557 { 6, 0x989c, \
1558 { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } }, \
1559 { 6, 0x989c, \
1560 { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } }, \
1561 { 6, 0x989c, \
1562 { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } }, \
1563 { 6, 0x98d4, \
1564 { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } }, \
1565 { 7, 0x989c, \
1566 { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } }, \
1567 { 7, 0x989c, \
1568 { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } }, \
1569 { 7, 0x989c, \
1570 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \
1571 { 7, 0x989c, \
1572 { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } }, \
1573 { 7, 0x989c, \
1574 { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } }, \
1575 { 7, 0x989c, \
1576 { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } }, \
1577 { 7, 0x989c, \
1578 { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } }, \
1579 { 7, 0x98cc, \
1580 { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } }, \
1581 }
1582
1583 #define AR5K_AR5112_INI_RF { \
1584 { 1, 0x98d4, \
1585 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
1586 { 2, 0x98d0, \
1587 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \
1588 { 3, 0x98dc, \
1589 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \
1590 { 6, 0x989c, \
1591 { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } }, \
1592 { 6, 0x989c, \
1593 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \
1594 { 6, 0x989c, \
1595 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1596 { 6, 0x989c, \
1597 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1598 { 6, 0x989c, \
1599 { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } }, \
1600 { 6, 0x989c, \
1601 { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } }, \
1602 { 6, 0x989c, \
1603 { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } }, \
1604 { 6, 0x989c, \
1605 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
1606 { 6, 0x989c, \
1607 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
1608 { 6, 0x989c, \
1609 { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } }, \
1610 { 6, 0x989c, \
1611 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1612 { 6, 0x989c, \
1613 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
1614 { 6, 0x989c, \
1615 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1616 { 6, 0x989c, \
1617 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1618 { 6, 0x989c, \
1619 { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } }, \
1620 { 6, 0x989c, \
1621 { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } }, \
1622 { 6, 0x989c, \
1623 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
1624 { 6, 0x989c, \
1625 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \
1626 { 6, 0x989c, \
1627 { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } }, \
1628 { 6, 0x989c, \
1629 { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } }, \
1630 { 6, 0x989c, \
1631 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \
1632 { 6, 0x989c, \
1633 { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } }, \
1634 { 6, 0x989c, \
1635 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
1636 { 6, 0x989c, \
1637 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
1638 { 6, 0x989c, \
1639 { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } }, \
1640 { 6, 0x989c, \
1641 { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } }, \
1642 { 6, 0x989c, \
1643 { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } }, \
1644 { 6, 0x989c, \
1645 { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } }, \
1646 { 6, 0x989c, \
1647 { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } }, \
1648 { 6, 0x989c, \
1649 { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } }, \
1650 { 6, 0x989c, \
1651 { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } }, \
1652 { 6, 0x989c, \
1653 { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } }, \
1654 { 6, 0x989c, \
1655 { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } }, \
1656 { 6, 0x989c, \
1657 { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } }, \
1658 { 6, 0x989c, \
1659 { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } }, \
1660 { 6, 0x989c, \
1661 { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } }, \
1662 { 6, 0x989c, \
1663 { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } }, \
1664 { 6, 0x98d0, \
1665 { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } }, \
1666 { 7, 0x989c, \
1667 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \
1668 { 7, 0x989c, \
1669 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \
1670 { 7, 0x989c, \
1671 { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } }, \
1672 { 7, 0x989c, \
1673 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \
1674 { 7, 0x989c, \
1675 { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } }, \
1676 { 7, 0x989c, \
1677 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \
1678 { 7, 0x989c, \
1679 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \
1680 { 7, 0x989c, \
1681 { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } }, \
1682 { 7, 0x989c, \
1683 { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } }, \
1684 { 7, 0x989c, \
1685 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \
1686 { 7, 0x989c, \
1687 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \
1688 { 7, 0x989c, \
1689 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \
1690 { 7, 0x98c4, \
1691 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
1692 }
1693
1694 #define AR5K_AR5112A_INI_RF { \
1695 { 1, 0x98d4, \
1696 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
1697 { 2, 0x98d0, \
1698 { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } }, \
1699 { 3, 0x98dc, \
1700 { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } }, \
1701 { 6, 0x989c, \
1702 { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } }, \
1703 { 6, 0x989c, \
1704 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1705 { 6, 0x989c, \
1706 { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } }, \
1707 { 6, 0x989c, \
1708 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
1709 { 6, 0x989c, \
1710 { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } }, \
1711 { 6, 0x989c, \
1712 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1713 { 6, 0x989c, \
1714 { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } }, \
1715 { 6, 0x989c, \
1716 { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } }, \
1717 { 6, 0x989c, \
1718 { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } }, \
1719 { 6, 0x989c, \
1720 { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } }, \
1721 { 6, 0x989c, \
1722 { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } }, \
1723 { 6, 0x989c, \
1724 { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } }, \
1725 { 6, 0x989c, \
1726 { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } }, \
1727 { 6, 0x989c, \
1728 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1729 { 6, 0x989c, \
1730 { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } }, \
1731 { 6, 0x989c, \
1732 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1733 { 6, 0x989c, \
1734 { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } }, \
1735 { 6, 0x989c, \
1736 { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } }, \
1737 { 6, 0x989c, \
1738 { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } }, \
1739 { 6, 0x989c, \
1740 { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } }, \
1741 { 6, 0x989c, \
1742 { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } }, \
1743 { 6, 0x989c, \
1744 { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } }, \
1745 { 6, 0x989c, \
1746 { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } }, \
1747 { 6, 0x989c, \
1748 { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } }, \
1749 { 6, 0x989c, \
1750 { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } }, \
1751 { 6, 0x989c, \
1752 { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } }, \
1753 { 6, 0x989c, \
1754 { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } }, \
1755 { 6, 0x989c, \
1756 { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } }, \
1757 { 6, 0x989c, \
1758 { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } }, \
1759 { 6, 0x989c, \
1760 { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } }, \
1761 { 6, 0x989c, \
1762 { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } }, \
1763 { 6, 0x989c, \
1764 { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } }, \
1765 { 6, 0x989c, \
1766 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
1767 { 6, 0x989c, \
1768 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1769 { 6, 0x989c, \
1770 { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } }, \
1771 { 6, 0x989c, \
1772 { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } }, \
1773 { 6, 0x989c, \
1774 { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } }, \
1775 { 6, 0x989c, \
1776 { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } }, \
1777 { 6, 0x989c, \
1778 { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } }, \
1779 { 6, 0x98d8, \
1780 { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } }, \
1781 { 7, 0x989c, \
1782 { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } }, \
1783 { 7, 0x989c, \
1784 { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } }, \
1785 { 7, 0x989c, \
1786 { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } }, \
1787 { 7, 0x989c, \
1788 { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } }, \
1789 { 7, 0x989c, \
1790 { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } }, \
1791 { 7, 0x989c, \
1792 { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } }, \
1793 { 7, 0x989c, \
1794 { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } }, \
1795 { 7, 0x989c, \
1796 { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } }, \
1797 { 7, 0x989c, \
1798 { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } }, \
1799 { 7, 0x989c, \
1800 { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } }, \
1801 { 7, 0x989c, \
1802 { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } }, \
1803 { 7, 0x989c, \
1804 { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } }, \
1805 { 7, 0x98c4, \
1806 { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } }, \
1807 }
1808
1809 #define AR5K_AR5413_INI_RF { \
1810 { 1, 0x98d4, \
1811 { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } }, \
1812 { 2, 0x98d0, \
1813 { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } }, \
1814 { 3, 0x98dc, \
1815 { 0x00a000c0, 0x00a000c0, 0x00e000c0, 0x00e000c0, 0x00e000c0 } }, \
1816 { 6, 0x989c, \
1817 { 0x33000000, 0x33000000, 0x33000000, 0x33000000, 0x33000000 } }, \
1818 { 6, 0x989c, \
1819 { 0x01000000, 0x01000000, 0x01000000, 0x01000000, 0x01000000 } }, \
1820 { 6, 0x989c, \
1821 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1822 { 6, 0x989c, \
1823 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1824 { 6, 0x989c, \
1825 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1826 { 6, 0x989c, \
1827 { 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000, 0x1f000000 } }, \
1828 { 6, 0x989c, \
1829 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1830 { 6, 0x989c, \
1831 { 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000, 0x00b80000 } }, \
1832 { 6, 0x989c, \
1833 { 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000, 0x00b70000 } }, \
1834 { 6, 0x989c, \
1835 { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } }, \
1836 { 6, 0x989c, \
1837 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } }, \
1838 { 6, 0x989c, \
1839 { 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000, 0x00c00000 } }, \
1840 { 6, 0x989c, \
1841 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1842 { 6, 0x989c, \
1843 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1844 { 6, 0x989c, \
1845 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1846 { 6, 0x989c, \
1847 { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } }, \
1848 { 6, 0x989c, \
1849 { 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000, 0x00d70000 } }, \
1850 { 6, 0x989c, \
1851 { 0x00610000, 0x00610000, 0x00610000, 0x00610000, 0x00610000 } }, \
1852 { 6, 0x989c, \
1853 { 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000, 0x00fe0000 } }, \
1854 { 6, 0x989c, \
1855 { 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000, 0x00de0000 } }, \
1856 { 6, 0x989c, \
1857 { 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000, 0x007f0000 } }, \
1858 { 6, 0x989c, \
1859 { 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000, 0x043d0000 } }, \
1860 { 6, 0x989c, \
1861 { 0x00770000, 0x00770000, 0x00770000, 0x00770000, 0x00770000 } }, \
1862 { 6, 0x989c, \
1863 { 0x00440000, 0x00440000, 0x00440000, 0x00440000, 0x00440000 } }, \
1864 { 6, 0x989c, \
1865 { 0x00980000, 0x00980000, 0x00980000, 0x00980000, 0x00980000 } }, \
1866 { 6, 0x989c, \
1867 { 0x00100080, 0x00100080, 0x00100080, 0x00100080, 0x00100080 } }, \
1868 { 6, 0x989c, \
1869 { 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034, 0x0005c034 } }, \
1870 { 6, 0x989c, \
1871 { 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0, 0x003100f0 } }, \
1872 { 6, 0x989c, \
1873 { 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f, 0x000c011f } }, \
1874 { 6, 0x989c, \
1875 { 0x00510040, 0x00510040, 0x005100a0, 0x005100a0, 0x005100a0 } }, \
1876 { 6, 0x989c, \
1877 { 0x0050006a, 0x0050006a, 0x005000dd, 0x005000dd, 0x005000dd } }, \
1878 { 6, 0x989c, \
1879 { 0x00000001, 0x00000001, 0x00000000, 0x00000000, 0x00000000 } }, \
1880 { 6, 0x989c, \
1881 { 0x00004044, 0x00004044, 0x00004044, 0x00004044, 0x00004044 } }, \
1882 { 6, 0x989c, \
1883 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } }, \
1884 { 6, 0x989c, \
1885 { 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0, 0x000060c0 } }, \
1886 { 6, 0x989c, \
1887 { 0x00002c00, 0x00002c00, 0x00003600, 0x00003600, 0x00003600 } }, \
1888 { 6, 0x98c8, \
1889 { 0x00000403, 0x00000403, 0x00040403, 0x00040403, 0x00040403 } }, \
1890 { 7, 0x989c, \
1891 { 0x00006400, 0x00006400, 0x00006400, 0x00006400, 0x00006400 } }, \
1892 { 7, 0x989c, \
1893 { 0x00000800, 0x00000800, 0x00000800, 0x00000800, 0x00000800 } }, \
1894 { 7, 0x98cc, \
1895 { 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e, 0x0000000e } }, \
1896 }
1897
1898 #define AR5K_AR2413_INI_RF { \
1899 { 1, 0x98d4, { 0, 0, 0x00000020, 0x00000020, 0x00000020 } }, \
1900 { 2, 0x98d0, { 0, 0, 0x02001408, 0x02001408, 0x02001408 } }, \
1901 { 3, 0x98dc, { 0, 0, 0x00e020c0, 0x00e020c0, 0x00e020c0 } }, \
1902 { 6, 0x989c, { 0, 0, 0xf0000000, 0xf0000000, 0xf0000000 } }, \
1903 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1904 { 6, 0x989c, { 0, 0, 0x03000000, 0x03000000, 0x03000000 } }, \
1905 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1906 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1907 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1908 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1909 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1910 { 6, 0x989c, { 0, 0, 0x40400000, 0x40400000, 0x40400000 } }, \
1911 { 6, 0x989c, { 0, 0, 0x65050000, 0x65050000, 0x65050000 } }, \
1912 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1913 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1914 { 6, 0x989c, { 0, 0, 0x00420000, 0x00420000, 0x00420000 } }, \
1915 { 6, 0x989c, { 0, 0, 0x00b50000, 0x00b50000, 0x00b50000 } }, \
1916 { 6, 0x989c, { 0, 0, 0x00030000, 0x00030000, 0x00030000 } }, \
1917 { 6, 0x989c, { 0, 0, 0x00f70000, 0x00f70000, 0x00f70000 } }, \
1918 { 6, 0x989c, { 0, 0, 0x009d0000, 0x009d0000, 0x009d0000 } }, \
1919 { 6, 0x989c, { 0, 0, 0x00220000, 0x00220000, 0x00220000 } }, \
1920 { 6, 0x989c, { 0, 0, 0x04220000, 0x04220000, 0x04220000 } }, \
1921 { 6, 0x989c, { 0, 0, 0x00230018, 0x00230018, 0x00230018 } }, \
1922 { 6, 0x989c, { 0, 0, 0x00280050, 0x00280050, 0x00280050 } }, \
1923 { 6, 0x989c, { 0, 0, 0x005000c3, 0x005000c3, 0x005000c3 } }, \
1924 { 6, 0x989c, { 0, 0, 0x0004007f, 0x0004007f, 0x0004007f } }, \
1925 { 6, 0x989c, { 0, 0, 0x00000458, 0x00000458, 0x00000458 } }, \
1926 { 6, 0x989c, { 0, 0, 0x00000000, 0x00000000, 0x00000000 } }, \
1927 { 6, 0x989c, { 0, 0, 0x0000c000, 0x0000c000, 0x0000c000 } }, \
1928 { 6, 0x98d8, { 0, 0, 0x00400230, 0x00400230, 0x00400230 } }, \
1929 { 7, 0x989c, { 0, 0, 0x00006400, 0x00006400, 0x00006400 } }, \
1930 { 7, 0x989c, { 0, 0, 0x00000800, 0x00000800, 0x00000800 } }, \
1931 { 7, 0x98cc, { 0, 0, 0x0000000e, 0x0000000e, 0x0000000e } }, \
1932 }
1933
1934 #define AR5K_AR2425_INI_RF { \
1935 { 1, 0x98d4, { 0, 0, 0, 0x00000020, 0x00000020 } }, \
1936 { 2, 0x98d0, { 0, 0, 0, 0x02001408, 0x02001408 } }, \
1937 { 3, 0x98dc, { 0, 0, 0, 0x00e020c0, 0x00e020c0 } }, \
1938 { 6, 0x989c, { 0, 0, 0, 0x10000000, 0x10000000 } }, \
1939 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1940 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1941 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1942 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1943 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1944 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1945 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1946 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1947 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1948 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1949 { 6, 0x989c, { 0, 0, 0, 0x002a0000, 0x002a0000 } }, \
1950 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1951 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1952 { 6, 0x989c, { 0, 0, 0, 0x00100000, 0x00100000 } }, \
1953 { 6, 0x989c, { 0, 0, 0, 0x00020000, 0x00020000 } }, \
1954 { 6, 0x989c, { 0, 0, 0, 0x00730000, 0x00730000 } }, \
1955 { 6, 0x989c, { 0, 0, 0, 0x00f80000, 0x00f80000 } }, \
1956 { 6, 0x989c, { 0, 0, 0, 0x00e70000, 0x00e70000 } }, \
1957 { 6, 0x989c, { 0, 0, 0, 0x00140000, 0x00140000 } }, \
1958 { 6, 0x989c, { 0, 0, 0, 0x00910040, 0x00910040 } }, \
1959 { 6, 0x989c, { 0, 0, 0, 0x0007001a, 0x0007001a } }, \
1960 { 6, 0x989c, { 0, 0, 0, 0x00410000, 0x00410000 } }, \
1961 { 6, 0x989c, { 0, 0, 0, 0x00810060, 0x00810060 } }, \
1962 { 6, 0x989c, { 0, 0, 0, 0x00020803, 0x00020803 } }, \
1963 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1964 { 6, 0x989c, { 0, 0, 0, 0x00000000, 0x00000000 } }, \
1965 { 6, 0x989c, { 0, 0, 0, 0x00001660, 0x00001660 } }, \
1966 { 6, 0x989c, { 0, 0, 0, 0x00001688, 0x00001688 } }, \
1967 { 6, 0x98c4, { 0, 0, 0, 0x00000001, 0x00000001 } }, \
1968 { 7, 0x989c, { 0, 0, 0, 0x00006400, 0x00006400 } }, \
1969 { 7, 0x989c, { 0, 0, 0, 0x00000800, 0x00000800 } }, \
1970 { 7, 0x98cc, { 0, 0, 0, 0x0000000e, 0x0000000e } } \
1971 }
1972
1973 struct ar5k_ini_rfgain {
1974 u_int16_t rfg_register;
1975 u_int32_t rfg_value[2];
1976
1977 #define AR5K_INI_RFGAIN_5GHZ 0
1978 #define AR5K_INI_RFGAIN_2GHZ 1
1979 #define AR5K_INI_RFGAIN(_n) (0x9a00 + ((_n) << 2))
1980 };
1981
1982 #define AR5K_AR5111_INI_RFGAIN { \
1983 { AR5K_INI_RFGAIN(0), { 0x000001a9, 0x00000000 } }, \
1984 { AR5K_INI_RFGAIN(1), { 0x000001e9, 0x00000040 } }, \
1985 { AR5K_INI_RFGAIN(2), { 0x00000029, 0x00000080 } }, \
1986 { AR5K_INI_RFGAIN(3), { 0x00000069, 0x00000150 } }, \
1987 { AR5K_INI_RFGAIN(4), { 0x00000199, 0x00000190 } }, \
1988 { AR5K_INI_RFGAIN(5), { 0x000001d9, 0x000001d0 } }, \
1989 { AR5K_INI_RFGAIN(6), { 0x00000019, 0x00000010 } }, \
1990 { AR5K_INI_RFGAIN(7), { 0x00000059, 0x00000044 } }, \
1991 { AR5K_INI_RFGAIN(8), { 0x00000099, 0x00000084 } }, \
1992 { AR5K_INI_RFGAIN(9), { 0x000001a5, 0x00000148 } }, \
1993 { AR5K_INI_RFGAIN(10), { 0x000001e5, 0x00000188 } }, \
1994 { AR5K_INI_RFGAIN(11), { 0x00000025, 0x000001c8 } }, \
1995 { AR5K_INI_RFGAIN(12), { 0x000001c8, 0x00000014 } }, \
1996 { AR5K_INI_RFGAIN(13), { 0x00000008, 0x00000042 } }, \
1997 { AR5K_INI_RFGAIN(14), { 0x00000048, 0x00000082 } }, \
1998 { AR5K_INI_RFGAIN(15), { 0x00000088, 0x00000178 } }, \
1999 { AR5K_INI_RFGAIN(16), { 0x00000198, 0x000001b8 } }, \
2000 { AR5K_INI_RFGAIN(17), { 0x000001d8, 0x000001f8 } }, \
2001 { AR5K_INI_RFGAIN(18), { 0x00000018, 0x00000012 } }, \
2002 { AR5K_INI_RFGAIN(19), { 0x00000058, 0x00000052 } }, \
2003 { AR5K_INI_RFGAIN(20), { 0x00000098, 0x00000092 } }, \
2004 { AR5K_INI_RFGAIN(21), { 0x000001a4, 0x0000017c } }, \
2005 { AR5K_INI_RFGAIN(22), { 0x000001e4, 0x000001bc } }, \
2006 { AR5K_INI_RFGAIN(23), { 0x00000024, 0x000001fc } }, \
2007 { AR5K_INI_RFGAIN(24), { 0x00000064, 0x0000000a } }, \
2008 { AR5K_INI_RFGAIN(25), { 0x000000a4, 0x0000004a } }, \
2009 { AR5K_INI_RFGAIN(26), { 0x000000e4, 0x0000008a } }, \
2010 { AR5K_INI_RFGAIN(27), { 0x0000010a, 0x0000015a } }, \
2011 { AR5K_INI_RFGAIN(28), { 0x0000014a, 0x0000019a } }, \
2012 { AR5K_INI_RFGAIN(29), { 0x0000018a, 0x000001da } }, \
2013 { AR5K_INI_RFGAIN(30), { 0x000001ca, 0x0000000e } }, \
2014 { AR5K_INI_RFGAIN(31), { 0x0000000a, 0x0000004e } }, \
2015 { AR5K_INI_RFGAIN(32), { 0x0000004a, 0x0000008e } }, \
2016 { AR5K_INI_RFGAIN(33), { 0x0000008a, 0x0000015e } }, \
2017 { AR5K_INI_RFGAIN(34), { 0x000001ba, 0x0000019e } }, \
2018 { AR5K_INI_RFGAIN(35), { 0x000001fa, 0x000001de } }, \
2019 { AR5K_INI_RFGAIN(36), { 0x0000003a, 0x00000009 } }, \
2020 { AR5K_INI_RFGAIN(37), { 0x0000007a, 0x00000049 } }, \
2021 { AR5K_INI_RFGAIN(38), { 0x00000186, 0x00000089 } }, \
2022 { AR5K_INI_RFGAIN(39), { 0x000001c6, 0x00000179 } }, \
2023 { AR5K_INI_RFGAIN(40), { 0x00000006, 0x000001b9 } }, \
2024 { AR5K_INI_RFGAIN(41), { 0x00000046, 0x000001f9 } }, \
2025 { AR5K_INI_RFGAIN(42), { 0x00000086, 0x00000039 } }, \
2026 { AR5K_INI_RFGAIN(43), { 0x000000c6, 0x00000079 } }, \
2027 { AR5K_INI_RFGAIN(44), { 0x000000c6, 0x000000b9 } }, \
2028 { AR5K_INI_RFGAIN(45), { 0x000000c6, 0x000001bd } }, \
2029 { AR5K_INI_RFGAIN(46), { 0x000000c6, 0x000001fd } }, \
2030 { AR5K_INI_RFGAIN(47), { 0x000000c6, 0x0000003d } }, \
2031 { AR5K_INI_RFGAIN(48), { 0x000000c6, 0x0000007d } }, \
2032 { AR5K_INI_RFGAIN(49), { 0x000000c6, 0x000000bd } }, \
2033 { AR5K_INI_RFGAIN(50), { 0x000000c6, 0x000000fd } }, \
2034 { AR5K_INI_RFGAIN(51), { 0x000000c6, 0x000000fd } }, \
2035 { AR5K_INI_RFGAIN(52), { 0x000000c6, 0x000000fd } }, \
2036 { AR5K_INI_RFGAIN(53), { 0x000000c6, 0x000000fd } }, \
2037 { AR5K_INI_RFGAIN(54), { 0x000000c6, 0x000000fd } }, \
2038 { AR5K_INI_RFGAIN(55), { 0x000000c6, 0x000000fd } }, \
2039 { AR5K_INI_RFGAIN(56), { 0x000000c6, 0x000000fd } }, \
2040 { AR5K_INI_RFGAIN(57), { 0x000000c6, 0x000000fd } }, \
2041 { AR5K_INI_RFGAIN(58), { 0x000000c6, 0x000000fd } }, \
2042 { AR5K_INI_RFGAIN(59), { 0x000000c6, 0x000000fd } }, \
2043 { AR5K_INI_RFGAIN(60), { 0x000000c6, 0x000000fd } }, \
2044 { AR5K_INI_RFGAIN(61), { 0x000000c6, 0x000000fd } }, \
2045 { AR5K_INI_RFGAIN(62), { 0x000000c6, 0x000000fd } }, \
2046 { AR5K_INI_RFGAIN(63), { 0x000000c6, 0x000000fd } } \
2047 }
2048
2049 #define AR5K_AR5112_INI_RFGAIN { \
2050 { AR5K_INI_RFGAIN(0), { 0x00000007, 0x00000007 } }, \
2051 { AR5K_INI_RFGAIN(1), { 0x00000047, 0x00000047 } }, \
2052 { AR5K_INI_RFGAIN(2), { 0x00000087, 0x00000087 } }, \
2053 { AR5K_INI_RFGAIN(3), { 0x000001a0, 0x000001a0 } }, \
2054 { AR5K_INI_RFGAIN(4), { 0x000001e0, 0x000001e0 } }, \
2055 { AR5K_INI_RFGAIN(5), { 0x00000020, 0x00000020 } }, \
2056 { AR5K_INI_RFGAIN(6), { 0x00000060, 0x00000060 } }, \
2057 { AR5K_INI_RFGAIN(7), { 0x000001a1, 0x000001a1 } }, \
2058 { AR5K_INI_RFGAIN(8), { 0x000001e1, 0x000001e1 } }, \
2059 { AR5K_INI_RFGAIN(9), { 0x00000021, 0x00000021 } }, \
2060 { AR5K_INI_RFGAIN(10), { 0x00000061, 0x00000061 } }, \
2061 { AR5K_INI_RFGAIN(11), { 0x00000162, 0x00000162 } }, \
2062 { AR5K_INI_RFGAIN(12), { 0x000001a2, 0x000001a2 } }, \
2063 { AR5K_INI_RFGAIN(13), { 0x000001e2, 0x000001e2 } }, \
2064 { AR5K_INI_RFGAIN(14), { 0x00000022, 0x00000022 } }, \
2065 { AR5K_INI_RFGAIN(15), { 0x00000062, 0x00000062 } }, \
2066 { AR5K_INI_RFGAIN(16), { 0x00000163, 0x00000163 } }, \
2067 { AR5K_INI_RFGAIN(17), { 0x000001a3, 0x000001a3 } }, \
2068 { AR5K_INI_RFGAIN(18), { 0x000001e3, 0x000001e3 } }, \
2069 { AR5K_INI_RFGAIN(19), { 0x00000023, 0x00000023 } }, \
2070 { AR5K_INI_RFGAIN(20), { 0x00000063, 0x00000063 } }, \
2071 { AR5K_INI_RFGAIN(21), { 0x00000184, 0x00000184 } }, \
2072 { AR5K_INI_RFGAIN(22), { 0x000001c4, 0x000001c4 } }, \
2073 { AR5K_INI_RFGAIN(23), { 0x00000004, 0x00000004 } }, \
2074 { AR5K_INI_RFGAIN(24), { 0x000001ea, 0x0000000b } }, \
2075 { AR5K_INI_RFGAIN(25), { 0x0000002a, 0x0000004b } }, \
2076 { AR5K_INI_RFGAIN(26), { 0x0000006a, 0x0000008b } }, \
2077 { AR5K_INI_RFGAIN(27), { 0x000000aa, 0x000001ac } }, \
2078 { AR5K_INI_RFGAIN(28), { 0x000001ab, 0x000001ec } }, \
2079 { AR5K_INI_RFGAIN(29), { 0x000001eb, 0x0000002c } }, \
2080 { AR5K_INI_RFGAIN(30), { 0x0000002b, 0x00000012 } }, \
2081 { AR5K_INI_RFGAIN(31), { 0x0000006b, 0x00000052 } }, \
2082 { AR5K_INI_RFGAIN(32), { 0x000000ab, 0x00000092 } }, \
2083 { AR5K_INI_RFGAIN(33), { 0x000001ac, 0x00000193 } }, \
2084 { AR5K_INI_RFGAIN(34), { 0x000001ec, 0x000001d3 } }, \
2085 { AR5K_INI_RFGAIN(35), { 0x0000002c, 0x00000013 } }, \
2086 { AR5K_INI_RFGAIN(36), { 0x0000003a, 0x00000053 } }, \
2087 { AR5K_INI_RFGAIN(37), { 0x0000007a, 0x00000093 } }, \
2088 { AR5K_INI_RFGAIN(38), { 0x000000ba, 0x00000194 } }, \
2089 { AR5K_INI_RFGAIN(39), { 0x000001bb, 0x000001d4 } }, \
2090 { AR5K_INI_RFGAIN(40), { 0x000001fb, 0x00000014 } }, \
2091 { AR5K_INI_RFGAIN(41), { 0x0000003b, 0x0000003a } }, \
2092 { AR5K_INI_RFGAIN(42), { 0x0000007b, 0x0000007a } }, \
2093 { AR5K_INI_RFGAIN(43), { 0x000000bb, 0x000000ba } }, \
2094 { AR5K_INI_RFGAIN(44), { 0x000001bc, 0x000001bb } }, \
2095 { AR5K_INI_RFGAIN(45), { 0x000001fc, 0x000001fb } }, \
2096 { AR5K_INI_RFGAIN(46), { 0x0000003c, 0x0000003b } }, \
2097 { AR5K_INI_RFGAIN(47), { 0x0000007c, 0x0000007b } }, \
2098 { AR5K_INI_RFGAIN(48), { 0x000000bc, 0x000000bb } }, \
2099 { AR5K_INI_RFGAIN(49), { 0x000000fc, 0x000001bc } }, \
2100 { AR5K_INI_RFGAIN(50), { 0x000000fc, 0x000001fc } }, \
2101 { AR5K_INI_RFGAIN(51), { 0x000000fc, 0x0000003c } }, \
2102 { AR5K_INI_RFGAIN(52), { 0x000000fc, 0x0000007c } }, \
2103 { AR5K_INI_RFGAIN(53), { 0x000000fc, 0x000000bc } }, \
2104 { AR5K_INI_RFGAIN(54), { 0x000000fc, 0x000000fc } }, \
2105 { AR5K_INI_RFGAIN(55), { 0x000000fc, 0x000000fc } }, \
2106 { AR5K_INI_RFGAIN(56), { 0x000000fc, 0x000000fc } }, \
2107 { AR5K_INI_RFGAIN(57), { 0x000000fc, 0x000000fc } }, \
2108 { AR5K_INI_RFGAIN(58), { 0x000000fc, 0x000000fc } }, \
2109 { AR5K_INI_RFGAIN(59), { 0x000000fc, 0x000000fc } }, \
2110 { AR5K_INI_RFGAIN(60), { 0x000000fc, 0x000000fc } }, \
2111 { AR5K_INI_RFGAIN(61), { 0x000000fc, 0x000000fc } }, \
2112 { AR5K_INI_RFGAIN(62), { 0x000000fc, 0x000000fc } }, \
2113 { AR5K_INI_RFGAIN(63), { 0x000000fc, 0x000000fc } }, \
2114 }
2115
2116 #define AR5K_AR5413_INI_RFGAIN { \
2117 { AR5K_INI_RFGAIN(0), { 0x00000000, 0x00000000 } }, \
2118 { AR5K_INI_RFGAIN(1), { 0x00000040, 0x00000040 } }, \
2119 { AR5K_INI_RFGAIN(2), { 0x00000080, 0x00000080 } }, \
2120 { AR5K_INI_RFGAIN(3), { 0x000001a1, 0x00000161 } }, \
2121 { AR5K_INI_RFGAIN(4), { 0x000001e1, 0x000001a1 } }, \
2122 { AR5K_INI_RFGAIN(5), { 0x00000021, 0x000001e1 } }, \
2123 { AR5K_INI_RFGAIN(6), { 0x00000061, 0x00000021 } }, \
2124 { AR5K_INI_RFGAIN(7), { 0x00000188, 0x00000061 } }, \
2125 { AR5K_INI_RFGAIN(8), { 0x000001c8, 0x00000188 } }, \
2126 { AR5K_INI_RFGAIN(9), { 0x00000008, 0x000001c8 } }, \
2127 { AR5K_INI_RFGAIN(10), { 0x00000048, 0x00000008 } }, \
2128 { AR5K_INI_RFGAIN(11), { 0x00000088, 0x00000048 } }, \
2129 { AR5K_INI_RFGAIN(12), { 0x000001a9, 0x00000088 } }, \
2130 { AR5K_INI_RFGAIN(13), { 0x000001e9, 0x00000169 } }, \
2131 { AR5K_INI_RFGAIN(14), { 0x00000029, 0x000001a9 } }, \
2132 { AR5K_INI_RFGAIN(15), { 0x00000069, 0x000001e9 } }, \
2133 { AR5K_INI_RFGAIN(16), { 0x000001d0, 0x00000029 } }, \
2134 { AR5K_INI_RFGAIN(17), { 0x00000010, 0x00000069 } }, \
2135 { AR5K_INI_RFGAIN(18), { 0x00000050, 0x00000190 } }, \
2136 { AR5K_INI_RFGAIN(19), { 0x00000090, 0x000001d0 } }, \
2137 { AR5K_INI_RFGAIN(20), { 0x000001b1, 0x00000010 } }, \
2138 { AR5K_INI_RFGAIN(21), { 0x000001f1, 0x00000050 } }, \
2139 { AR5K_INI_RFGAIN(22), { 0x00000031, 0x00000090 } }, \
2140 { AR5K_INI_RFGAIN(23), { 0x00000071, 0x00000171 } }, \
2141 { AR5K_INI_RFGAIN(24), { 0x000001b8, 0x000001b1 } }, \
2142 { AR5K_INI_RFGAIN(25), { 0x000001f8, 0x000001f1 } }, \
2143 { AR5K_INI_RFGAIN(26), { 0x00000038, 0x00000031 } }, \
2144 { AR5K_INI_RFGAIN(27), { 0x00000078, 0x00000071 } }, \
2145 { AR5K_INI_RFGAIN(28), { 0x00000199, 0x00000198 } }, \
2146 { AR5K_INI_RFGAIN(29), { 0x000001d9, 0x000001d8 } }, \
2147 { AR5K_INI_RFGAIN(30), { 0x00000019, 0x00000018 } }, \
2148 { AR5K_INI_RFGAIN(31), { 0x00000059, 0x00000058 } }, \
2149 { AR5K_INI_RFGAIN(32), { 0x00000099, 0x00000098 } }, \
2150 { AR5K_INI_RFGAIN(33), { 0x000000d9, 0x00000179 } }, \
2151 { AR5K_INI_RFGAIN(34), { 0x000000f9, 0x000001b9 } }, \
2152 { AR5K_INI_RFGAIN(35), { 0x000000f9, 0x000001f9 } }, \
2153 { AR5K_INI_RFGAIN(36), { 0x000000f9, 0x00000039 } }, \
2154 { AR5K_INI_RFGAIN(37), { 0x000000f9, 0x00000079 } }, \
2155 { AR5K_INI_RFGAIN(38), { 0x000000f9, 0x000000b9 } }, \
2156 { AR5K_INI_RFGAIN(39), { 0x000000f9, 0x000000f9 } }, \
2157 { AR5K_INI_RFGAIN(40), { 0x000000f9, 0x000000f9 } }, \
2158 { AR5K_INI_RFGAIN(41), { 0x000000f9, 0x000000f9 } }, \
2159 { AR5K_INI_RFGAIN(42), { 0x000000f9, 0x000000f9 } }, \
2160 { AR5K_INI_RFGAIN(43), { 0x000000f9, 0x000000f9 } }, \
2161 { AR5K_INI_RFGAIN(44), { 0x000000f9, 0x000000f9 } }, \
2162 { AR5K_INI_RFGAIN(45), { 0x000000f9, 0x000000f9 } }, \
2163 { AR5K_INI_RFGAIN(46), { 0x000000f9, 0x000000f9 } }, \
2164 { AR5K_INI_RFGAIN(47), { 0x000000f9, 0x000000f9 } }, \
2165 { AR5K_INI_RFGAIN(48), { 0x000000f9, 0x000000f9 } }, \
2166 { AR5K_INI_RFGAIN(49), { 0x000000f9, 0x000000f9 } }, \
2167 { AR5K_INI_RFGAIN(50), { 0x000000f9, 0x000000f9 } }, \
2168 { AR5K_INI_RFGAIN(51), { 0x000000f9, 0x000000f9 } }, \
2169 { AR5K_INI_RFGAIN(52), { 0x000000f9, 0x000000f9 } }, \
2170 { AR5K_INI_RFGAIN(53), { 0x000000f9, 0x000000f9 } }, \
2171 { AR5K_INI_RFGAIN(54), { 0x000000f9, 0x000000f9 } }, \
2172 { AR5K_INI_RFGAIN(55), { 0x000000f9, 0x000000f9 } }, \
2173 { AR5K_INI_RFGAIN(56), { 0x000000f9, 0x000000f9 } }, \
2174 { AR5K_INI_RFGAIN(57), { 0x000000f9, 0x000000f9 } }, \
2175 { AR5K_INI_RFGAIN(58), { 0x000000f9, 0x000000f9 } }, \
2176 { AR5K_INI_RFGAIN(59), { 0x000000f9, 0x000000f9 } }, \
2177 { AR5K_INI_RFGAIN(60), { 0x000000f9, 0x000000f9 } }, \
2178 { AR5K_INI_RFGAIN(61), { 0x000000f9, 0x000000f9 } }, \
2179 { AR5K_INI_RFGAIN(62), { 0x000000f9, 0x000000f9 } }, \
2180 { AR5K_INI_RFGAIN(63), { 0x000000f9, 0x000000f9 } } \
2181 }
2182
2183 #define AR5K_AR2413_INI_RFGAIN { \
2184 { AR5K_INI_RFGAIN(0), { 0, 0x00000000 } }, \
2185 { AR5K_INI_RFGAIN(1), { 0, 0x00000040 } }, \
2186 { AR5K_INI_RFGAIN(2), { 0, 0x00000080 } }, \
2187 { AR5K_INI_RFGAIN(3), { 0, 0x00000181 } }, \
2188 { AR5K_INI_RFGAIN(4), { 0, 0x000001c1 } }, \
2189 { AR5K_INI_RFGAIN(5), { 0, 0x00000001 } }, \
2190 { AR5K_INI_RFGAIN(6), { 0, 0x00000041 } }, \
2191 { AR5K_INI_RFGAIN(7), { 0, 0x00000081 } }, \
2192 { AR5K_INI_RFGAIN(8), { 0, 0x00000168 } }, \
2193 { AR5K_INI_RFGAIN(9), { 0, 0x000001a8 } }, \
2194 { AR5K_INI_RFGAIN(10), { 0, 0x000001e8 } }, \
2195 { AR5K_INI_RFGAIN(11), { 0, 0x00000028 } }, \
2196 { AR5K_INI_RFGAIN(12), { 0, 0x00000068 } }, \
2197 { AR5K_INI_RFGAIN(13), { 0, 0x00000189 } }, \
2198 { AR5K_INI_RFGAIN(14), { 0, 0x000001c9 } }, \
2199 { AR5K_INI_RFGAIN(15), { 0, 0x00000009 } }, \
2200 { AR5K_INI_RFGAIN(16), { 0, 0x00000049 } }, \
2201 { AR5K_INI_RFGAIN(17), { 0, 0x00000089 } }, \
2202 { AR5K_INI_RFGAIN(18), { 0, 0x00000190 } }, \
2203 { AR5K_INI_RFGAIN(19), { 0, 0x000001d0 } }, \
2204 { AR5K_INI_RFGAIN(20), { 0, 0x00000010 } }, \
2205 { AR5K_INI_RFGAIN(21), { 0, 0x00000050 } }, \
2206 { AR5K_INI_RFGAIN(22), { 0, 0x00000090 } }, \
2207 { AR5K_INI_RFGAIN(23), { 0, 0x00000191 } }, \
2208 { AR5K_INI_RFGAIN(24), { 0, 0x000001d1 } }, \
2209 { AR5K_INI_RFGAIN(25), { 0, 0x00000011 } }, \
2210 { AR5K_INI_RFGAIN(26), { 0, 0x00000051 } }, \
2211 { AR5K_INI_RFGAIN(27), { 0, 0x00000091 } }, \
2212 { AR5K_INI_RFGAIN(28), { 0, 0x00000178 } }, \
2213 { AR5K_INI_RFGAIN(29), { 0, 0x000001b8 } }, \
2214 { AR5K_INI_RFGAIN(30), { 0, 0x000001f8 } }, \
2215 { AR5K_INI_RFGAIN(31), { 0, 0x00000038 } }, \
2216 { AR5K_INI_RFGAIN(32), { 0, 0x00000078 } }, \
2217 { AR5K_INI_RFGAIN(33), { 0, 0x00000199 } }, \
2218 { AR5K_INI_RFGAIN(34), { 0, 0x000001d9 } }, \
2219 { AR5K_INI_RFGAIN(35), { 0, 0x00000019 } }, \
2220 { AR5K_INI_RFGAIN(36), { 0, 0x00000059 } }, \
2221 { AR5K_INI_RFGAIN(37), { 0, 0x00000099 } }, \
2222 { AR5K_INI_RFGAIN(38), { 0, 0x000000d9 } }, \
2223 { AR5K_INI_RFGAIN(39), { 0, 0x000000f9 } }, \
2224 { AR5K_INI_RFGAIN(40), { 0, 0x000000f9 } }, \
2225 { AR5K_INI_RFGAIN(41), { 0, 0x000000f9 } }, \
2226 { AR5K_INI_RFGAIN(42), { 0, 0x000000f9 } }, \
2227 { AR5K_INI_RFGAIN(43), { 0, 0x000000f9 } }, \
2228 { AR5K_INI_RFGAIN(44), { 0, 0x000000f9 } }, \
2229 { AR5K_INI_RFGAIN(45), { 0, 0x000000f9 } }, \
2230 { AR5K_INI_RFGAIN(46), { 0, 0x000000f9 } }, \
2231 { AR5K_INI_RFGAIN(47), { 0, 0x000000f9 } }, \
2232 { AR5K_INI_RFGAIN(48), { 0, 0x000000f9 } }, \
2233 { AR5K_INI_RFGAIN(49), { 0, 0x000000f9 } }, \
2234 { AR5K_INI_RFGAIN(50), { 0, 0x000000f9 } }, \
2235 { AR5K_INI_RFGAIN(51), { 0, 0x000000f9 } }, \
2236 { AR5K_INI_RFGAIN(52), { 0, 0x000000f9 } }, \
2237 { AR5K_INI_RFGAIN(53), { 0, 0x000000f9 } }, \
2238 { AR5K_INI_RFGAIN(54), { 0, 0x000000f9 } }, \
2239 { AR5K_INI_RFGAIN(55), { 0, 0x000000f9 } }, \
2240 { AR5K_INI_RFGAIN(56), { 0, 0x000000f9 } }, \
2241 { AR5K_INI_RFGAIN(57), { 0, 0x000000f9 } }, \
2242 { AR5K_INI_RFGAIN(58), { 0, 0x000000f9 } }, \
2243 { AR5K_INI_RFGAIN(59), { 0, 0x000000f9 } }, \
2244 { AR5K_INI_RFGAIN(60), { 0, 0x000000f9 } }, \
2245 { AR5K_INI_RFGAIN(61), { 0, 0x000000f9 } }, \
2246 { AR5K_INI_RFGAIN(62), { 0, 0x000000f9 } }, \
2247 { AR5K_INI_RFGAIN(63), { 0, 0x000000f9 } }, \
2248 }
2249
2250 /*
2251 * Prototypes
2252 */
2253
2254 __BEGIN_DECLS
2255
2256 const char *ath_hal_probe(u_int16_t, u_int16_t);
2257
2258 struct ath_hal *ath_hal_attach(u_int16_t, void *, bus_space_tag_t,
2259 bus_space_handle_t, u_int, HAL_STATUS *);
2260
2261 u_int16_t ath_hal_computetxtime(struct ath_hal *,
2262 const HAL_RATE_TABLE *, u_int32_t, u_int16_t, HAL_BOOL);
2263
2264 HAL_BOOL ath_hal_init_channels(struct ath_hal *, HAL_CHANNEL *,
2265 u_int, u_int *, u_int16_t, HAL_BOOL, HAL_BOOL);
2266
2267 const char *ar5k_printver(enum ar5k_srev_type, u_int32_t);
2268 void ar5k_radar_alert(struct ath_hal *);
2269 ieee80211_regdomain_t ar5k_regdomain_to_ieee(u_int16_t);
2270 u_int16_t ar5k_regdomain_from_ieee(ieee80211_regdomain_t);
2271 u_int16_t ar5k_get_regdomain(struct ath_hal *);
2272
2273 u_int32_t ar5k_bitswap(u_int32_t, u_int);
2274 u_int ar5k_clocktoh(u_int);
2275 u_int ar5k_htoclock(u_int);
2276 void ar5k_rt_copy(HAL_RATE_TABLE *, const HAL_RATE_TABLE *);
2277
2278 HAL_BOOL ar5k_register_timeout(struct ath_hal *, u_int32_t,
2279 u_int32_t, u_int32_t, HAL_BOOL);
2280
2281 int ar5k_eeprom_init(struct ath_hal *);
2282 int ar5k_eeprom_read_mac(struct ath_hal *, u_int8_t *);
2283 HAL_BOOL ar5k_eeprom_regulation_domain(struct ath_hal *,
2284 HAL_BOOL, ieee80211_regdomain_t *);
2285
2286 HAL_BOOL ar5k_channel(struct ath_hal *, HAL_CHANNEL *);
2287 HAL_BOOL ar5k_rfregs(struct ath_hal *, HAL_CHANNEL *, u_int);
2288 u_int32_t ar5k_rfregs_gainf_corr(struct ath_hal *);
2289 HAL_BOOL ar5k_rfregs_gain_readback(struct ath_hal *);
2290 int32_t ar5k_rfregs_gain_adjust(struct ath_hal *);
2291 HAL_BOOL ar5k_rfgain(struct ath_hal *, u_int);
2292
2293 void ar5k_txpower_table(struct ath_hal *, HAL_CHANNEL *,
2294 int16_t);
2295
2296 void ar5k_write_ini(struct ath_hal *,
2297 const struct ar5k_ini *, size_t, HAL_BOOL);
2298 void ar5k_write_mode(struct ath_hal *,
2299 const struct ar5k_mode *, size_t, u_int);
2300
2301 __END_DECLS
2302
2303 #endif /* _AR5K_H */
Cache object: d672ff83cb505fa09c8c8ff4b43d3121
|