FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/athvar.h
1 /* $NetBSD: athvar.h,v 1.19 2006/07/14 13:37:25 seanb Exp $ */
2
3 /*-
4 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
17 * 3. Neither the names of the above-listed copyright holders nor the names
18 * of any contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * Alternatively, this software may be distributed under the terms of the
22 * GNU General Public License ("GPL") version 2 as published by the Free
23 * Software Foundation.
24 *
25 * NO WARRANTY
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
29 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
30 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
31 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
34 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
36 * THE POSSIBILITY OF SUCH DAMAGES.
37 *
38 * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.29 2005/08/08 18:46:36 sam Exp $
39 */
40
41 /*
42 * Defintions for the Atheros Wireless LAN controller driver.
43 */
44 #ifndef _DEV_ATH_ATHVAR_H
45 #define _DEV_ATH_ATHVAR_H
46
47 #include <dev/ic/ath_netbsd.h>
48 #include <contrib/dev/ath/ah.h>
49 #include <net80211/ieee80211_radiotap.h>
50 #include <dev/ic/athioctl.h>
51 #include <dev/ic/athrate.h>
52
53 #define ATH_TIMEOUT 1000
54
55 #ifndef ATH_RXBUF
56 #define ATH_RXBUF 40 /* number of RX buffers */
57 #endif
58 #ifndef ATH_TXBUF
59 #define ATH_TXBUF 100 /* number of TX buffers */
60 #endif
61 #define ATH_TXDESC 10 /* number of descriptors per buffer */
62 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
63 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
64 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
65
66 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */
67 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
68 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
69
70 /*
71 * The key cache is used for h/w cipher state and also for
72 * tracking station state such as the current tx antenna.
73 * We also setup a mapping table between key cache slot indices
74 * and station state to short-circuit node lookups on rx.
75 * Different parts have different size key caches. We handle
76 * up to ATH_KEYMAX entries (could dynamically allocate state).
77 */
78 #define ATH_KEYMAX 128 /* max key cache size we handle */
79 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
80
81 /* driver-specific node state */
82 struct ath_node {
83 struct ieee80211_node an_node; /* base class */
84 u_int32_t an_avgrssi; /* average rssi over all rx frames */
85 /* variable-length rate control state follows */
86 };
87 #define ATH_NODE(ni) ((struct ath_node *)(ni))
88 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
89
90 #define ATH_RSSI_LPF_LEN 10
91 #define ATH_RSSI_DUMMY_MARKER 0x127
92 #define ATH_EP_MUL(x, mul) ((x) * (mul))
93 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
94 #define ATH_LPF_RSSI(x, y, len) \
95 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
96 #define ATH_RSSI_LPF(x, y) do { \
97 if ((y) >= -20) \
98 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
99 } while (0)
100
101 struct ath_buf {
102 STAILQ_ENTRY(ath_buf) bf_list;
103 #define bf_nseg bf_dmamap->dm_nsegs
104 int bf_flags; /* tx descriptor flags */
105 struct ath_desc *bf_desc; /* virtual addr of desc */
106 bus_addr_t bf_daddr; /* physical addr of desc */
107 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
108 struct mbuf *bf_m; /* mbuf for buf */
109 struct ieee80211_node *bf_node; /* pointer to the node */
110 #define bf_mapsize bf_dmamap->dm_mapsize
111 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
112 #define bf_segs bf_dmamap->dm_segs
113 };
114 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
115
116 /*
117 * DMA state for tx/rx descriptors.
118 */
119 struct ath_descdma {
120 const char* dd_name;
121 struct ath_desc *dd_desc; /* descriptors */
122 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
123 bus_addr_t dd_desc_len; /* size of dd_desc */
124 bus_dma_segment_t dd_dseg;
125 int dd_dnseg; /* number of segments */
126 bus_dma_tag_t dd_dmat; /* bus DMA tag */
127 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
128 struct ath_buf *dd_bufptr; /* associated buffers */
129 };
130
131 /*
132 * Data transmit queue state. One of these exists for each
133 * hardware transmit queue. Packets sent to us from above
134 * are assigned to queues based on their priority. Not all
135 * devices support a complete set of hardware transmit queues.
136 * For those devices the array sc_ac2q will map multiple
137 * priorities to fewer hardware queues (typically all to one
138 * hardware queue).
139 */
140 struct ath_txq {
141 u_int axq_qnum; /* hardware q number */
142 u_int axq_depth; /* queue depth (stat only) */
143 u_int axq_intrcnt; /* interrupt count */
144 u_int32_t *axq_link; /* link ptr in last TX desc */
145 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
146 ath_txq_lock_t axq_lock; /* lock on q and link */
147 /*
148 * State for patching up CTS when bursting.
149 */
150 struct ath_buf *axq_linkbuf; /* va of last buffer */
151 };
152
153 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
154 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
155 (_tq)->axq_depth++; \
156 } while (0)
157 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
158 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
159 (_tq)->axq_depth--; \
160 } while (0)
161
162 struct taskqueue;
163 struct ath_tx99;
164
165 struct ath_softc {
166 struct device sc_dev;
167 struct ethercom sc_ec; /* interface common */
168 struct ath_stats sc_stats; /* interface statistics */
169 struct ieee80211com sc_ic; /* IEEE 802.11 common */
170 int (*sc_enable)(struct ath_softc *);
171 void (*sc_disable)(struct ath_softc *);
172 void (*sc_power)(struct ath_softc *, int);
173 int sc_regdomain;
174 int sc_countrycode;
175 int sc_debug;
176 struct sysctllog *sc_sysctllog;
177 void (*sc_recv_mgmt)(struct ieee80211com *,
178 struct mbuf *,
179 struct ieee80211_node *,
180 int, int, u_int32_t);
181 int (*sc_newstate)(struct ieee80211com *,
182 enum ieee80211_state, int);
183 void (*sc_node_free)(struct ieee80211_node *);
184 HAL_BUS_TAG sc_st; /* bus space tag */
185 HAL_BUS_HANDLE sc_sh; /* bus space handle */
186 bus_dma_tag_t sc_dmat; /* bus DMA tag */
187 ath_lock_t sc_mtx; /* master lock (recursive) */
188 struct ath_hal *sc_ah; /* Atheros HAL */
189 struct ath_ratectrl *sc_rc; /* tx rate control support */
190 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
191 void (*sc_setdefantenna)(struct ath_softc *, u_int);
192 unsigned int sc_invalid : 1, /* disable hardware accesses */
193 sc_mrretry : 1, /* multi-rate retry support */
194 sc_softled : 1, /* enable LED gpio status */
195 sc_splitmic: 1, /* split TKIP MIC keys */
196 sc_needmib : 1, /* enable MIB stats intr */
197 sc_diversity : 1,/* enable rx diversity */
198 sc_hasveol : 1, /* tx VEOL support */
199 sc_ledstate: 1, /* LED on/off state */
200 sc_blinking: 1, /* LED blink operation active */
201 sc_mcastkey: 1, /* mcast key cache search */
202 sc_syncbeacon:1,/* sync/resync beacon timers */
203 sc_hasclrkey:1; /* CLR key supported */
204 /* rate tables */
205 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
206 const HAL_RATE_TABLE *sc_currates; /* current rate table */
207 enum ieee80211_phymode sc_curmode; /* current phy mode */
208 u_int16_t sc_curtxpow; /* current tx power limit */
209 HAL_CHANNEL sc_curchan; /* current h/w channel */
210 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
211 struct {
212 u_int8_t ieeerate; /* IEEE rate */
213 u_int8_t rxflags; /* radiotap rx flags */
214 u_int8_t txflags; /* radiotap tx flags */
215 u_int16_t ledon; /* softled on time */
216 u_int16_t ledoff; /* softled off time */
217 } sc_hwmap[32]; /* h/w rate ix mappings */
218 u_int8_t sc_minrateix; /* min h/w rate index */
219 u_int8_t sc_mcastrix; /* mcast h/w rate index */
220 u_int8_t sc_protrix; /* protection rate index */
221 u_int sc_mcastrate; /* ieee rate for mcastrateix */
222 u_int sc_txantenna; /* tx antenna (fixed or auto) */
223 HAL_INT sc_imask; /* interrupt mask copy */
224 u_int sc_keymax; /* size of key cache */
225 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
226
227 u_int sc_ledpin; /* GPIO pin for driving LED */
228 u_int sc_ledon; /* pin setting for LED on */
229 u_int sc_ledidle; /* idle polling interval */
230 int sc_ledevent; /* time of last LED event */
231 u_int8_t sc_rxrate; /* current rx rate for LED */
232 u_int8_t sc_txrate; /* current tx rate for LED */
233 u_int16_t sc_ledoff; /* off time for current blink */
234 struct callout sc_ledtimer; /* led off timer */
235
236 caddr_t sc_drvbpf;
237 union {
238 struct ath_tx_radiotap_header th;
239 u_int8_t pad[64];
240 } u_tx_rt;
241 int sc_tx_th_len;
242 union {
243 struct ath_rx_radiotap_header th;
244 u_int8_t pad[64];
245 } u_rx_rt;
246 int sc_rx_th_len;
247
248 ath_task_t sc_fataltask; /* fatal int processing */
249
250 struct ath_descdma sc_rxdma; /* RX descriptos */
251 ath_bufhead sc_rxbuf; /* receive buffer */
252 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
253 ath_task_t sc_rxtask; /* rx int processing */
254 ath_task_t sc_rxorntask; /* rxorn int processing */
255 ath_task_t sc_radartask; /* radar processing */
256 u_int8_t sc_defant; /* current default antenna */
257 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
258 u_int64_t sc_lastrx; /* tsf of last rx'd frame */
259
260 struct ath_descdma sc_txdma; /* TX descriptors */
261 ath_bufhead sc_txbuf; /* transmit buffer */
262 ath_txbuf_lock_t sc_txbuflock; /* txbuf lock */
263 int sc_tx_timer; /* transmit timeout */
264 u_int sc_txqsetup; /* h/w queues setup */
265 u_int sc_txintrperiod;/* tx interrupt batching */
266 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
267 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
268 ath_task_t sc_txtask; /* tx int processing */
269
270 struct ath_descdma sc_bdma; /* beacon descriptors */
271 ath_bufhead sc_bbuf; /* beacon buffers */
272 u_int sc_bhalq; /* HAL q for outgoing beacons */
273 u_int sc_bmisscount; /* missed beacon transmits */
274 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
275 struct ath_txq *sc_cabq; /* tx q for cab frames */
276 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
277 ath_task_t sc_bmisstask; /* bmiss int processing */
278 ath_task_t sc_bstucktask; /* stuck beacon processing */
279 enum {
280 OK, /* no change needed */
281 UPDATE, /* update pending */
282 COMMIT /* beacon sent, commit change */
283 } sc_updateslot; /* slot time update fsm */
284
285 struct callout sc_cal_ch; /* callout handle for cals */
286 int sc_calinterval; /* current polling interval */
287 int sc_caltries; /* cals at current interval */
288 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
289 struct callout sc_scan_ch; /* callout handle for scan */
290 struct callout sc_dfs_ch; /* callout handle for dfs */
291 void *sc_powerhook; /* power management hook */
292 u_int sc_flags; /* misc flags */
293 };
294 #define sc_if sc_ec.ec_if
295 #define sc_tx_th u_tx_rt.th
296 #define sc_rx_th u_rx_rt.th
297
298 #define ATH_ATTACHED 0x0001 /* attach has succeeded */
299 #define ATH_ENABLED 0x0002 /* chip is enabled */
300
301 #define ATH_IS_ENABLED(sc) ((sc)->sc_flags & ATH_ENABLED)
302
303 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
304
305 int ath_attach(u_int16_t, struct ath_softc *);
306 int ath_detach(struct ath_softc *);
307 void ath_resume(struct ath_softc *, int);
308 void ath_suspend(struct ath_softc *, int);
309 int ath_activate(struct device *, enum devact);
310 void ath_power(int, void *);
311 void ath_shutdown(void *);
312 int ath_intr(void *);
313 int ath_reset(struct ifnet *);
314 void ath_sysctlattach(struct ath_softc *);
315
316 extern int ath_dwelltime;
317 extern int ath_calinterval;
318 extern int ath_outdoor;
319 extern int ath_xchanmode;
320 extern int ath_countrycode;
321 extern int ath_regdomain;
322 extern int ath_debug;
323 extern int ath_rxbuf;
324 extern int ath_txbuf;
325
326 /*
327 * HAL definitions to comply with local coding convention.
328 */
329 #define ath_hal_detach(_ah) \
330 ((*(_ah)->ah_detach)((_ah)))
331 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
332 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
333 #define ath_hal_getratetable(_ah, _mode) \
334 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
335 #define ath_hal_getmac(_ah, _mac) \
336 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
337 #define ath_hal_setmac(_ah, _mac) \
338 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
339 #define ath_hal_intrset(_ah, _mask) \
340 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
341 #define ath_hal_intrget(_ah) \
342 ((*(_ah)->ah_getInterrupts)((_ah)))
343 #define ath_hal_intrpend(_ah) \
344 ((*(_ah)->ah_isInterruptPending)((_ah)))
345 #define ath_hal_getisr(_ah, _pmask) \
346 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
347 #define ath_hal_updatetxtriglevel(_ah, _inc) \
348 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
349 #define ath_hal_setpower(_ah, _mode) \
350 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
351 #define ath_hal_keycachesize(_ah) \
352 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
353 #define ath_hal_keyreset(_ah, _ix) \
354 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
355 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
356 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
357 #define ath_hal_keyisvalid(_ah, _ix) \
358 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
359 #define ath_hal_keysetmac(_ah, _ix, _mac) \
360 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
361 #define ath_hal_getrxfilter(_ah) \
362 ((*(_ah)->ah_getRxFilter)((_ah)))
363 #define ath_hal_setrxfilter(_ah, _filter) \
364 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
365 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
366 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
367 #define ath_hal_waitforbeacon(_ah, _bf) \
368 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
369 #define ath_hal_putrxbuf(_ah, _bufaddr) \
370 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
371 #define ath_hal_gettsf32(_ah) \
372 ((*(_ah)->ah_getTsf32)((_ah)))
373 #define ath_hal_gettsf64(_ah) \
374 ((*(_ah)->ah_getTsf64)((_ah)))
375 #define ath_hal_resettsf(_ah) \
376 ((*(_ah)->ah_resetTsf)((_ah)))
377 #define ath_hal_rxena(_ah) \
378 ((*(_ah)->ah_enableReceive)((_ah)))
379 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
380 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
381 #define ath_hal_gettxbuf(_ah, _q) \
382 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
383 #define ath_hal_numtxpending(_ah, _q) \
384 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
385 #define ath_hal_getrxbuf(_ah) \
386 ((*(_ah)->ah_getRxDP)((_ah)))
387 #define ath_hal_txstart(_ah, _q) \
388 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
389 #define ath_hal_setchannel(_ah, _chan) \
390 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
391 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
392 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
393 #define ath_hal_setledstate(_ah, _state) \
394 ((*(_ah)->ah_setLedState)((_ah), (_state)))
395 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
396 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
397 #define ath_hal_beaconreset(_ah) \
398 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
399 #define ath_hal_beacontimers(_ah, _bs) \
400 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
401 #define ath_hal_setassocid(_ah, _bss, _associd) \
402 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
403 #define ath_hal_phydisable(_ah) \
404 ((*(_ah)->ah_phyDisable)((_ah)))
405 #define ath_hal_setopmode(_ah) \
406 ((*(_ah)->ah_setPCUConfig)((_ah)))
407 #define ath_hal_stoptxdma(_ah, _qnum) \
408 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
409 #define ath_hal_stoppcurecv(_ah) \
410 ((*(_ah)->ah_stopPcuReceive)((_ah)))
411 #define ath_hal_startpcurecv(_ah) \
412 ((*(_ah)->ah_startPcuReceive)((_ah)))
413 #define ath_hal_stopdmarecv(_ah) \
414 ((*(_ah)->ah_stopDmaReceive)((_ah)))
415 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
416 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
417 (_indata), (_insize), (_outdata), (_outsize)))
418 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
419 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
420 #define ath_hal_resettxqueue(_ah, _q) \
421 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
422 #define ath_hal_releasetxqueue(_ah, _q) \
423 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
424 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
425 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
426 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
427 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
428 #define ath_hal_getrfgain(_ah) \
429 ((*(_ah)->ah_getRfGain)((_ah)))
430 #define ath_hal_getdefantenna(_ah) \
431 ((*(_ah)->ah_getDefAntenna)((_ah)))
432 #define ath_hal_setdefantenna(_ah, _ant) \
433 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
434 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
435 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
436 #define ath_hal_mibevent(_ah, _stats) \
437 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
438 #define ath_hal_setslottime(_ah, _us) \
439 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
440 #define ath_hal_getslottime(_ah) \
441 ((*(_ah)->ah_getSlotTime)((_ah)))
442 #define ath_hal_setacktimeout(_ah, _us) \
443 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
444 #define ath_hal_getacktimeout(_ah) \
445 ((*(_ah)->ah_getAckTimeout)((_ah)))
446 #define ath_hal_setctstimeout(_ah, _us) \
447 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
448 #define ath_hal_getctstimeout(_ah) \
449 ((*(_ah)->ah_getCTSTimeout)((_ah)))
450 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
451 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
452 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
453 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
454 #define ath_hal_ciphersupported(_ah, _cipher) \
455 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
456 #define ath_hal_getregdomain(_ah, _prd) \
457 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
458 #define ath_hal_setregdomain(_ah, _rd) \
459 ((*(_ah)->ah_setRegulatoryDomain)((_ah), (_rd), NULL))
460 #define ath_hal_getcountrycode(_ah, _pcc) \
461 (*(_pcc) = (_ah)->ah_countryCode)
462 #define ath_hal_tkipsplit(_ah) \
463 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
464 #define ath_hal_hwphycounters(_ah) \
465 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
466 #define ath_hal_hasdiversity(_ah) \
467 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
468 #define ath_hal_getdiversity(_ah) \
469 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
470 #define ath_hal_setdiversity(_ah, _v) \
471 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
472 #define ath_hal_getdiag(_ah, _pv) \
473 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
474 #define ath_hal_setdiag(_ah, _v) \
475 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
476 #define ath_hal_getnumtxqueues(_ah, _pv) \
477 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
478 #define ath_hal_hasveol(_ah) \
479 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
480 #define ath_hal_hastxpowlimit(_ah) \
481 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
482 #define ath_hal_settxpowlimit(_ah, _pow) \
483 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
484 #define ath_hal_gettxpowlimit(_ah, _ppow) \
485 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
486 #define ath_hal_getmaxtxpow(_ah, _ppow) \
487 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
488 #define ath_hal_gettpscale(_ah, _scale) \
489 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
490 #define ath_hal_settpscale(_ah, _v) \
491 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
492 #define ath_hal_hastpc(_ah) \
493 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
494 #define ath_hal_gettpc(_ah) \
495 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
496 #define ath_hal_settpc(_ah, _v) \
497 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
498 #define ath_hal_hasbursting(_ah) \
499 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
500 #ifdef notyet
501 #define ath_hal_hasmcastkeysearch(_ah) \
502 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
503 #define ath_hal_getmcastkeysearch(_ah) \
504 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
505 #else
506 #define ath_hal_getmcastkeysearch(_ah) 0
507 #endif
508 #define ath_hal_hasrfsilent(_ah) \
509 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
510 #define ath_hal_getrfkill(_ah) \
511 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
512 #define ath_hal_setrfkill(_ah, _onoff) \
513 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
514 #define ath_hal_getrfsilent(_ah, _prfsilent) \
515 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
516 #define ath_hal_setrfsilent(_ah, _rfsilent) \
517 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
518 #define ath_hal_gettpack(_ah, _ptpack) \
519 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
520 #define ath_hal_settpack(_ah, _tpack) \
521 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
522 #define ath_hal_gettpcts(_ah, _ptpcts) \
523 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
524 #define ath_hal_settpcts(_ah, _tpcts) \
525 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
526 #if HAL_ABI_VERSION < 0x05120700
527 #define ath_hal_process_noisefloor(_ah)
528 #define ath_hal_getchannoise(_ah, _c) (-96)
529 #define HAL_CAP_TPC_ACK 99
530 #define HAL_CAP_TPC_CTS 100
531 #else
532 #define ath_hal_getchannoise(_ah, _c) \
533 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
534 #endif
535
536 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
537 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
538 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
539 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0))
540 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
541 _txr0, _txtr0, _keyix, _ant, _flags, \
542 _rtsrate, _rtsdura) \
543 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
544 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
545 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
546 #define ath_hal_setupxtxdesc(_ah, _ds, \
547 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
548 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
549 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
550 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
551 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
552 #define ath_hal_txprocdesc(_ah, _ds) \
553 ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
554 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
555 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
556
557 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
558 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
559 #define ath_hal_gpioset(_ah, _gpio, _b) \
560 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
561
562 #define ath_hal_radar_event(_ah) \
563 ((*(_ah)->ah_radarHaveEvent)((_ah)))
564 #define ath_hal_procdfs(_ah, _chan) \
565 ((*(_ah)->ah_processDfs)((_ah), (_chan)))
566 #define ath_hal_checknol(_ah, _chan, _nchans) \
567 ((*(_ah)->ah_dfsNolCheck)((_ah), (_chan), (_nchans)))
568 #define ath_hal_radar_wait(_ah, _chan) \
569 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
570
571 #endif /* _DEV_ATH_ATHVAR_H */
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