The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/ic/athvar.h

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    1 /*      $NetBSD: athvar.h,v 1.25.4.2 2009/08/07 06:48:09 snj Exp $      */
    2 
    3 /*-
    4  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer,
   12  *    without modification.
   13  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   14  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   15  *    redistribution must be conditioned upon including a substantially
   16  *    similar Disclaimer requirement for further binary redistribution.
   17  * 3. Neither the names of the above-listed copyright holders nor the names
   18  *    of any contributors may be used to endorse or promote products derived
   19  *    from this software without specific prior written permission.
   20  *
   21  * Alternatively, this software may be distributed under the terms of the
   22  * GNU General Public License ("GPL") version 2 as published by the Free
   23  * Software Foundation.
   24  *
   25  * NO WARRANTY
   26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   28  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   29  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   30  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   31  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   34  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   36  * THE POSSIBILITY OF SUCH DAMAGES.
   37  *
   38  * $FreeBSD: src/sys/dev/ath/if_athvar.h,v 1.29 2005/08/08 18:46:36 sam Exp $
   39  */
   40 
   41 /*
   42  * Defintions for the Atheros Wireless LAN controller driver.
   43  */
   44 #ifndef _DEV_ATH_ATHVAR_H
   45 #define _DEV_ATH_ATHVAR_H
   46 
   47 #include <net80211/ieee80211_radiotap.h>
   48 
   49 #include <external/isc/atheros_hal/dist/ah.h>
   50 
   51 #include <dev/ic/ath_netbsd.h>
   52 #include <dev/ic/athioctl.h>
   53 #include <dev/ic/athrate.h>
   54 
   55 #define ATH_TIMEOUT             1000
   56 
   57 #ifndef ATH_RXBUF
   58 #define ATH_RXBUF       40              /* number of RX buffers */
   59 #endif
   60 #ifndef ATH_TXBUF
   61 #define ATH_TXBUF       200             /* number of TX buffers */
   62 #endif
   63 #define ATH_TXDESC      10              /* number of descriptors per buffer */
   64 #define ATH_TXMAXTRY    11              /* max number of transmit attempts */
   65 #define ATH_TXMGTTRY    4               /* xmit attempts for mgt/ctl frames */
   66 #define ATH_TXINTR_PERIOD 5             /* max number of batched tx descriptors */
   67 
   68 #define ATH_BEACON_AIFS_DEFAULT  0      /* default aifs for ap beacon q */
   69 #define ATH_BEACON_CWMIN_DEFAULT 0      /* default cwmin for ap beacon q */
   70 #define ATH_BEACON_CWMAX_DEFAULT 0      /* default cwmax for ap beacon q */
   71 
   72 /*
   73  * The key cache is used for h/w cipher state and also for
   74  * tracking station state such as the current tx antenna.
   75  * We also setup a mapping table between key cache slot indices
   76  * and station state to short-circuit node lookups on rx.
   77  * Different parts have different size key caches.  We handle
   78  * up to ATH_KEYMAX entries (could dynamically allocate state).
   79  */
   80 #define ATH_KEYMAX      128             /* max key cache size we handle */
   81 #define ATH_KEYBYTES    (ATH_KEYMAX/NBBY)       /* storage space in bytes */
   82 /*
   83  * Convert from net80211 layer values to Ath layer values. Hopefully this will
   84  * be optimised away when the two constants are the same.
   85  */
   86 typedef unsigned int ath_keyix_t;
   87 #define ATH_KEY(_keyix) ((_keyix == IEEE80211_KEYIX_NONE) ? HAL_TXKEYIX_INVALID : _keyix)
   88 
   89 /* driver-specific node state */
   90 struct ath_node {
   91         struct ieee80211_node an_node;  /* base class */
   92         u_int32_t       an_avgrssi;     /* average rssi over all rx frames */
   93         /* variable-length rate control state follows */
   94 };
   95 #define ATH_NODE(ni)    ((struct ath_node *)(ni))
   96 #define ATH_NODE_CONST(ni)      ((const struct ath_node *)(ni))
   97 
   98 #define ATH_RSSI_LPF_LEN        10
   99 #define ATH_RSSI_DUMMY_MARKER   0x127
  100 #define ATH_EP_MUL(x, mul)      ((x) * (mul))
  101 #define ATH_RSSI_IN(x)          (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
  102 #define ATH_LPF_RSSI(x, y, len) \
  103     ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
  104 #define ATH_RSSI_LPF(x, y) do {                                         \
  105     if ((y) >= -20)                                                     \
  106         x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN);      \
  107 } while (0)
  108 
  109 struct ath_buf {
  110         STAILQ_ENTRY(ath_buf)   bf_list;
  111 #define bf_nseg         bf_dmamap->dm_nsegs
  112         int                     bf_flags;       /* tx descriptor flags */
  113         struct ath_desc         *bf_desc;       /* virtual addr of desc */
  114         bus_addr_t              bf_daddr;       /* physical addr of desc */
  115         bus_dmamap_t            bf_dmamap;      /* DMA map for mbuf chain */
  116         struct mbuf             *bf_m;          /* mbuf for buf */
  117         struct ieee80211_node   *bf_node;       /* pointer to the node */
  118 #define bf_mapsize      bf_dmamap->dm_mapsize
  119 #define ATH_MAX_SCATTER         ATH_TXDESC      /* max(tx,rx,beacon) desc's */
  120 #define bf_segs         bf_dmamap->dm_segs
  121 };
  122 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
  123 
  124 /*
  125  * DMA state for tx/rx descriptors.
  126  */
  127 struct ath_descdma {
  128         const char*             dd_name;
  129         struct ath_desc         *dd_desc;       /* descriptors */
  130         bus_addr_t              dd_desc_paddr;  /* physical addr of dd_desc */
  131         bus_size_t              dd_desc_len;    /* size of dd_desc */
  132         bus_dma_segment_t       dd_dseg;
  133         int                     dd_dnseg;       /* number of segments */
  134         bus_dma_tag_t           dd_dmat;        /* bus DMA tag */
  135         bus_dmamap_t            dd_dmamap;      /* DMA map for descriptors */
  136         struct ath_buf          *dd_bufptr;     /* associated buffers */
  137 };
  138 
  139 /*
  140  * Data transmit queue state.  One of these exists for each
  141  * hardware transmit queue.  Packets sent to us from above
  142  * are assigned to queues based on their priority.  Not all
  143  * devices support a complete set of hardware transmit queues.
  144  * For those devices the array sc_ac2q will map multiple
  145  * priorities to fewer hardware queues (typically all to one
  146  * hardware queue).
  147  */
  148 struct ath_txq {
  149         u_int                   axq_qnum;       /* hardware q number */
  150         u_int                   axq_depth;      /* queue depth (stat only) */
  151         u_int                   axq_intrcnt;    /* interrupt count */
  152         u_int32_t               *axq_link;      /* link ptr in last TX desc */
  153         STAILQ_HEAD(, ath_buf)  axq_q;          /* transmit queue */
  154         ath_txq_lock_t          axq_lock;       /* lock on q and link */
  155         /*
  156          * State for patching up CTS when bursting.
  157          */
  158         struct  ath_buf         *axq_linkbuf;   /* va of last buffer */
  159         u_int                   axq_timer;      /* transmit timeout */
  160 };
  161 
  162 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
  163         STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
  164         (_tq)->axq_depth++; \
  165         (_tq)->axq_timer = 5; \
  166 } while (0)
  167 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
  168         STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
  169         if (--(_tq)->axq_depth == 0) \
  170                 (_tq)->axq_timer = 0; \
  171 } while (0)
  172 
  173 struct taskqueue;
  174 struct ath_tx99;
  175 
  176 struct ath_softc {
  177         device_t                sc_dev;
  178         struct ethercom         sc_ec;          /* interface common */
  179         struct ath_stats        sc_stats;       /* interface statistics */
  180         struct ieee80211com     sc_ic;          /* IEEE 802.11 common */
  181         void                    (*sc_power)(struct ath_softc *, int);
  182         int                     sc_regdomain;
  183         int                     sc_countrycode;
  184         int                     sc_debug;
  185         struct sysctllog        *sc_sysctllog;
  186         void                    (*sc_recv_mgmt)(struct ieee80211com *,
  187                                         struct mbuf *,
  188                                         struct ieee80211_node *,
  189                                         int, int, u_int32_t);
  190         int                     (*sc_newstate)(struct ieee80211com *,
  191                                         enum ieee80211_state, int);
  192         void                    (*sc_node_free)(struct ieee80211_node *);
  193         HAL_BUS_TAG             sc_st;          /* bus space tag */
  194         HAL_BUS_HANDLE          sc_sh;          /* bus space handle */
  195         bus_dma_tag_t           sc_dmat;        /* bus DMA tag */
  196         ath_lock_t              sc_mtx;         /* master lock (recursive) */
  197         struct ath_hal          *sc_ah;         /* Atheros HAL */
  198         struct ath_ratectrl     *sc_rc;         /* tx rate control support */
  199         struct ath_tx99         *sc_tx99;       /* tx99 adjunct state */
  200         void                    (*sc_setdefantenna)(struct ath_softc *, u_int);
  201         unsigned int            sc_mrretry : 1, /* multi-rate retry support */
  202                                 sc_softled : 1, /* enable LED gpio status */
  203                                 sc_splitmic: 1, /* split TKIP MIC keys */
  204                                 sc_needmib : 1, /* enable MIB stats intr */
  205                                 sc_diversity : 1,/* enable rx diversity */
  206                                 sc_hasveol : 1, /* tx VEOL support */
  207                                 sc_ledstate: 1, /* LED on/off state */
  208                                 sc_blinking: 1, /* LED blink operation active */
  209                                 sc_mcastkey: 1, /* mcast key cache search */
  210                                 sc_syncbeacon:1,/* sync/resync beacon timers */
  211                                 sc_hasclrkey:1; /* CLR key supported */
  212                                                 /* rate tables */
  213         const HAL_RATE_TABLE    *sc_rates[IEEE80211_MODE_MAX];
  214         const HAL_RATE_TABLE    *sc_currates;   /* current rate table */
  215         enum ieee80211_phymode  sc_curmode;     /* current phy mode */
  216         u_int16_t               sc_curtxpow;    /* current tx power limit */
  217         HAL_CHANNEL             sc_curchan;     /* current h/w channel */
  218         u_int8_t                sc_rixmap[256]; /* IEEE to h/w rate table ix */
  219         struct {
  220                 u_int8_t        ieeerate;       /* IEEE rate */
  221                 u_int8_t        rxflags;        /* radiotap rx flags */
  222                 u_int8_t        txflags;        /* radiotap tx flags */
  223                 u_int16_t       ledon;          /* softled on time */
  224                 u_int16_t       ledoff;         /* softled off time */
  225         } sc_hwmap[32];                         /* h/w rate ix mappings */
  226         u_int8_t                sc_minrateix;   /* min h/w rate index */
  227         u_int8_t                sc_mcastrix;    /* mcast h/w rate index */
  228         u_int8_t                sc_protrix;     /* protection rate index */
  229         u_int                   sc_mcastrate;   /* ieee rate for mcastrateix */
  230         u_int                   sc_txantenna;   /* tx antenna (fixed or auto) */
  231         HAL_INT                 sc_imask;       /* interrupt mask copy */
  232         u_int                   sc_keymax;      /* size of key cache */
  233         u_int8_t                sc_keymap[ATH_KEYBYTES];/* key use bit map */
  234 
  235         u_int                   sc_ledpin;      /* GPIO pin for driving LED */
  236         u_int                   sc_ledon;       /* pin setting for LED on */
  237         u_int                   sc_ledidle;     /* idle polling interval */
  238         int                     sc_ledevent;    /* time of last LED event */
  239         u_int8_t                sc_rxrate;      /* current rx rate for LED */
  240         u_int8_t                sc_txrate;      /* current tx rate for LED */
  241         u_int16_t               sc_ledoff;      /* off time for current blink */
  242         struct callout          sc_ledtimer;    /* led off timer */
  243 
  244         void *                  sc_drvbpf;
  245         union {
  246                 struct ath_tx_radiotap_header th;
  247                 u_int8_t        pad[64];
  248         } u_tx_rt;
  249         int                     sc_tx_th_len;
  250         union {
  251                 struct ath_rx_radiotap_header th;
  252                 u_int8_t        pad[64];
  253         } u_rx_rt;
  254         int                     sc_rx_th_len;
  255 
  256         ath_task_t              sc_fataltask;   /* fatal int processing */
  257 
  258         struct ath_descdma      sc_rxdma;       /* RX descriptos */
  259         ath_bufhead             sc_rxbuf;       /* receive buffer */
  260         u_int32_t               *sc_rxlink;     /* link ptr in last RX desc */
  261         ath_task_t              sc_rxtask;      /* rx int processing */
  262         ath_task_t              sc_rxorntask;   /* rxorn int processing */
  263         ath_task_t              sc_radartask;   /* radar processing */
  264         u_int8_t                sc_defant;      /* current default antenna */
  265         u_int8_t                sc_rxotherant;  /* rx's on non-default antenna*/
  266         u_int64_t               sc_lastrx;      /* tsf of last rx'd frame */
  267 
  268         struct ath_descdma      sc_txdma;       /* TX descriptors */
  269         ath_bufhead             sc_txbuf;       /* transmit buffer */
  270         ath_txbuf_lock_t        sc_txbuflock;   /* txbuf lock */
  271         u_int                   sc_txqsetup;    /* h/w queues setup */
  272         u_int                   sc_txintrperiod;/* tx interrupt batching */
  273         struct ath_txq          sc_txq[HAL_NUM_TX_QUEUES];
  274         struct ath_txq          *sc_ac2q[5];    /* WME AC -> h/w q map */
  275         ath_task_t              sc_txtask;      /* tx int processing */
  276 
  277         struct ath_descdma      sc_bdma;        /* beacon descriptors */
  278         ath_bufhead             sc_bbuf;        /* beacon buffers */
  279         u_int                   sc_bhalq;       /* HAL q for outgoing beacons */
  280         u_int                   sc_bmisscount;  /* missed beacon transmits */
  281         u_int32_t               sc_ant_tx[8];   /* recent tx frames/antenna */
  282         struct ath_txq          *sc_cabq;       /* tx q for cab frames */
  283         struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
  284         ath_task_t              sc_bmisstask;   /* bmiss int processing */
  285         ath_task_t              sc_bstucktask;  /* stuck beacon processing */
  286         enum {
  287                 OK,                             /* no change needed */
  288                 UPDATE,                         /* update pending */
  289                 COMMIT                          /* beacon sent, commit change */
  290         } sc_updateslot;                        /* slot time update fsm */
  291 
  292         struct callout          sc_cal_ch;      /* callout handle for cals */
  293         int                     sc_calinterval; /* current polling interval */
  294         int                     sc_caltries;    /* cals at current interval */
  295         HAL_NODE_STATS          sc_halstats;    /* station-mode rssi stats */
  296         struct callout          sc_scan_ch;     /* callout handle for scan */
  297         struct callout          sc_dfs_ch;      /* callout handle for dfs */
  298         u_int                   sc_flags;       /* misc flags */
  299 };
  300 #define sc_if                   sc_ec.ec_if
  301 #define sc_tx_th                u_tx_rt.th
  302 #define sc_rx_th                u_rx_rt.th
  303 
  304 #define ATH_ATTACHED            0x0001          /* attach has succeeded */
  305 
  306 #define ATH_TXQ_SETUP(sc, i)    ((sc)->sc_txqsetup & (1<<i))
  307 
  308 int     ath_attach(u_int16_t, struct ath_softc *);
  309 int     ath_detach(struct ath_softc *);
  310 int     ath_activate(struct device *, enum devact);
  311 bool    ath_resume(struct ath_softc *);
  312 void    ath_suspend(struct ath_softc *);
  313 int     ath_intr(void *);
  314 int     ath_reset(struct ifnet *);
  315 void    ath_sysctlattach(struct ath_softc *);
  316 
  317 extern int ath_dwelltime;
  318 extern int ath_calinterval;
  319 extern int ath_outdoor;
  320 extern int ath_xchanmode;
  321 extern int ath_countrycode;
  322 extern int ath_regdomain;
  323 extern int ath_debug;
  324 extern int ath_rxbuf;
  325 extern int ath_txbuf;
  326 
  327 /*
  328  * HAL definitions to comply with local coding convention.
  329  */
  330 #define ath_hal_detach(_ah) \
  331         ((*(_ah)->ah_detach)((_ah)))
  332 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
  333         ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
  334 #define ath_hal_getratetable(_ah, _mode) \
  335         ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
  336 #define ath_hal_getmac(_ah, _mac) \
  337         ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
  338 #define ath_hal_setmac(_ah, _mac) \
  339         ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
  340 #define ath_hal_intrset(_ah, _mask) \
  341         ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
  342 #define ath_hal_intrget(_ah) \
  343         ((*(_ah)->ah_getInterrupts)((_ah)))
  344 #define ath_hal_intrpend(_ah) \
  345         ((*(_ah)->ah_isInterruptPending)((_ah)))
  346 #define ath_hal_getisr(_ah, _pmask) \
  347         ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
  348 #define ath_hal_updatetxtriglevel(_ah, _inc) \
  349         ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
  350 #define ath_hal_setpower(_ah, _mode) \
  351         ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
  352 #define ath_hal_keycachesize(_ah) \
  353         ((*(_ah)->ah_getKeyCacheSize)((_ah)))
  354 #define ath_hal_keyreset(_ah, _ix) \
  355         ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
  356 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
  357         ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
  358 #define ath_hal_keyisvalid(_ah, _ix) \
  359         (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
  360 #define ath_hal_keysetmac(_ah, _ix, _mac) \
  361         ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
  362 #define ath_hal_getrxfilter(_ah) \
  363         ((*(_ah)->ah_getRxFilter)((_ah)))
  364 #define ath_hal_setrxfilter(_ah, _filter) \
  365         ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
  366 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
  367         ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
  368 #define ath_hal_waitforbeacon(_ah, _bf) \
  369         ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
  370 #define ath_hal_putrxbuf(_ah, _bufaddr) \
  371         ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
  372 #define ath_hal_gettsf32(_ah) \
  373         ((*(_ah)->ah_getTsf32)((_ah)))
  374 #define ath_hal_gettsf64(_ah) \
  375         ((*(_ah)->ah_getTsf64)((_ah)))
  376 #define ath_hal_resettsf(_ah) \
  377         ((*(_ah)->ah_resetTsf)((_ah)))
  378 #define ath_hal_rxena(_ah) \
  379         ((*(_ah)->ah_enableReceive)((_ah)))
  380 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
  381         ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
  382 #define ath_hal_gettxbuf(_ah, _q) \
  383         ((*(_ah)->ah_getTxDP)((_ah), (_q)))
  384 #define ath_hal_numtxpending(_ah, _q) \
  385         ((*(_ah)->ah_numTxPending)((_ah), (_q)))
  386 #define ath_hal_getrxbuf(_ah) \
  387         ((*(_ah)->ah_getRxDP)((_ah)))
  388 #define ath_hal_txstart(_ah, _q) \
  389         ((*(_ah)->ah_startTxDma)((_ah), (_q)))
  390 #define ath_hal_setchannel(_ah, _chan) \
  391         ((*(_ah)->ah_setChannel)((_ah), (_chan)))
  392 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
  393         ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
  394 #define ath_hal_setledstate(_ah, _state) \
  395         ((*(_ah)->ah_setLedState)((_ah), (_state)))
  396 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
  397         ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
  398 #define ath_hal_beaconreset(_ah) \
  399         ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
  400 #define ath_hal_beacontimers(_ah, _bs) \
  401         ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
  402 #define ath_hal_setassocid(_ah, _bss, _associd) \
  403         ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
  404 #define ath_hal_phydisable(_ah) \
  405         ((*(_ah)->ah_phyDisable)((_ah)))
  406 #define ath_hal_setopmode(_ah) \
  407         ((*(_ah)->ah_setPCUConfig)((_ah)))
  408 #define ath_hal_stoptxdma(_ah, _qnum) \
  409         ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
  410 #define ath_hal_stoppcurecv(_ah) \
  411         ((*(_ah)->ah_stopPcuReceive)((_ah)))
  412 #define ath_hal_startpcurecv(_ah) \
  413         ((*(_ah)->ah_startPcuReceive)((_ah)))
  414 #define ath_hal_stopdmarecv(_ah) \
  415         ((*(_ah)->ah_stopDmaReceive)((_ah)))
  416 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
  417         ((*(_ah)->ah_getDiagState)((_ah), (_id), \
  418                 (_indata), (_insize), (_outdata), (_outsize)))
  419 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
  420         ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
  421 #define ath_hal_resettxqueue(_ah, _q) \
  422         ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
  423 #define ath_hal_releasetxqueue(_ah, _q) \
  424         ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
  425 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
  426         ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
  427 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
  428         ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
  429 #define ath_hal_getrfgain(_ah) \
  430         ((*(_ah)->ah_getRfGain)((_ah)))
  431 #define ath_hal_getdefantenna(_ah) \
  432         ((*(_ah)->ah_getDefAntenna)((_ah)))
  433 #define ath_hal_setdefantenna(_ah, _ant) \
  434         ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
  435 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
  436         ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
  437 #define ath_hal_mibevent(_ah, _stats) \
  438         ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
  439 #define ath_hal_setslottime(_ah, _us) \
  440         ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
  441 #define ath_hal_getslottime(_ah) \
  442         ((*(_ah)->ah_getSlotTime)((_ah)))
  443 #define ath_hal_setacktimeout(_ah, _us) \
  444         ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
  445 #define ath_hal_getacktimeout(_ah) \
  446         ((*(_ah)->ah_getAckTimeout)((_ah)))
  447 #define ath_hal_setctstimeout(_ah, _us) \
  448         ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
  449 #define ath_hal_getctstimeout(_ah) \
  450         ((*(_ah)->ah_getCTSTimeout)((_ah)))
  451 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
  452         ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
  453 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
  454         ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
  455 #define ath_hal_ciphersupported(_ah, _cipher) \
  456         (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
  457 #define ath_hal_getregdomain(_ah, _prd) \
  458         (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
  459 #define ath_hal_setregdomain(_ah, _rd) \
  460         ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
  461 #define ath_hal_getcountrycode(_ah, _pcc) \
  462         (*(_pcc) = (_ah)->ah_countryCode)
  463 #define ath_hal_gettkipmic(_ah) \
  464         (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
  465 #define ath_hal_settkipmic(_ah, _v) \
  466         ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
  467 #define ath_hal_hastkipsplit(_ah) \
  468         (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
  469 #define ath_hal_gettkipsplit(_ah) \
  470         (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
  471 #define ath_hal_settkipsplit(_ah, _v) \
  472         ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
  473 #define ath_hal_haswmetkipmic(_ah) \
  474         (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
  475 #define ath_hal_hwphycounters(_ah) \
  476         (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
  477 #define ath_hal_hasdiversity(_ah) \
  478         (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
  479 #define ath_hal_getdiversity(_ah) \
  480         (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
  481 #define ath_hal_setdiversity(_ah, _v) \
  482         ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
  483 #define ath_hal_getdiag(_ah, _pv) \
  484         (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
  485 #define ath_hal_setdiag(_ah, _v) \
  486         ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
  487 #define ath_hal_getnumtxqueues(_ah, _pv) \
  488         (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
  489 #define ath_hal_hasveol(_ah) \
  490         (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
  491 #define ath_hal_hastxpowlimit(_ah) \
  492         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
  493 #define ath_hal_settxpowlimit(_ah, _pow) \
  494         ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
  495 #define ath_hal_gettxpowlimit(_ah, _ppow) \
  496         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
  497 #define ath_hal_getmaxtxpow(_ah, _ppow) \
  498         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
  499 #define ath_hal_gettpscale(_ah, _scale) \
  500         (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
  501 #define ath_hal_settpscale(_ah, _v) \
  502         ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
  503 #define ath_hal_hastpc(_ah) \
  504         (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
  505 #define ath_hal_gettpc(_ah) \
  506         (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
  507 #define ath_hal_settpc(_ah, _v) \
  508         ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
  509 #define ath_hal_hasbursting(_ah) \
  510         (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
  511 #ifdef notyet
  512 #define ath_hal_hasmcastkeysearch(_ah) \
  513         (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
  514 #define ath_hal_getmcastkeysearch(_ah) \
  515         (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
  516 #else
  517 #define ath_hal_getmcastkeysearch(_ah)  0
  518 #endif
  519 #define ath_hal_hasrfsilent(_ah) \
  520         (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
  521 #define ath_hal_getrfkill(_ah) \
  522         (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
  523 #define ath_hal_setrfkill(_ah, _onoff) \
  524         ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
  525 #define ath_hal_getrfsilent(_ah, _prfsilent) \
  526         (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
  527 #define ath_hal_setrfsilent(_ah, _rfsilent) \
  528         ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
  529 #define ath_hal_gettpack(_ah, _ptpack) \
  530         (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
  531 #define ath_hal_settpack(_ah, _tpack) \
  532         ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
  533 #define ath_hal_gettpcts(_ah, _ptpcts) \
  534         (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
  535 #define ath_hal_settpcts(_ah, _tpcts) \
  536         ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
  537 #define ath_hal_getchannoise(_ah, _c) \
  538         ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
  539 
  540 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
  541         ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
  542 #if 0
  543 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, tsf, a5) \
  544         ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), (tsf), (a5)))
  545 #else
  546 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
  547         ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
  548 #endif
  549 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
  550                 _txr0, _txtr0, _keyix, _ant, _flags, \
  551                 _rtsrate, _rtsdura) \
  552         ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
  553                 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
  554                 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
  555 #define ath_hal_setupxtxdesc(_ah, _ds, \
  556                 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
  557         ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
  558                 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
  559 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
  560         ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
  561 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
  562         ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
  563 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
  564         ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
  565 
  566 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
  567         ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
  568 #define ath_hal_gpioset(_ah, _gpio, _b) \
  569         ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
  570 
  571 #define ath_hal_radar_event(_ah) \
  572         ((*(_ah)->ah_radarHaveEvent)((_ah)))
  573 #define ath_hal_procdfs(_ah, _chan) \
  574         ((*(_ah)->ah_processDfs)((_ah), (_chan)))
  575 #define ath_hal_checknol(_ah, _chan, _nchans) \
  576         ((*(_ah)->ah_dfsNolCheck)((_ah), (_chan), (_nchans)))
  577 
  578 #endif /* _DEV_ATH_ATHVAR_H */

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