Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/atppcreg.h
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1 /* $NetBSD: atppcreg.h,v 1.3 2004/01/25 00:28:01 bjh21 Exp $ */ 2 3 /*- 4 * Copyright (c) 2001 Alcove - Nicolas Souchu 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp 29 * 30 */ 31 32 #ifndef __ATPPCREG_H 33 #define __ATPPCREG_H 34 35 /* Generic register definitions as offsets from a base address */ 36 37 #define ATPPC_SPP_DTR 0 /* SPP data register */ 38 #define ATPPC_ECP_A_FIFO 0 /* ECP Address fifo register */ 39 #define ATPPC_SPP_STR 1 /* SPP status register */ 40 #define ATPPC_SPP_CTR 2 /* SPP control register */ 41 #define ATPPC_EPP_ADDR 3 /* EPP address register (8 bit) */ 42 #define ATPPC_EPP_DATA 4 /* EPP data register (8, 16, 32 bit) */ 43 #define ATPPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 44 #define ATPPC_ECP_CNFGA 0x400 /* Configuration register A */ 45 #define ATPPC_ECP_CNFGB 0x401 /* Configuration register B */ 46 #define ATPPC_ECP_ECR 0x402 /* ECP extended control register */ 47 48 /* ECP control register commands/modes */ 49 #define ATPPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 50 #define ATPPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ 51 #define ATPPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */ 52 #define ATPPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */ 53 #define ATPPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */ 54 /* ecr register - bits 5 through 7 */ 55 #define ATPPC_ECR_STD 0x00 /* Standard mode */ 56 #define ATPPC_ECR_PS2 0x20 /* Bidirectional mode */ 57 #define ATPPC_ECR_FIFO 0x40 /* Fast Centronics mode */ 58 #define ATPPC_ECR_ECP 0x60 /* ECP mode */ 59 #define ATPPC_ECR_EPP 0x80 /* EPP mode */ 60 #define ATPPC_ECR_TST 0xd0 /* Test mode*/ 61 #define ATPPC_ECR_CFG 0xe0 /* Test mode*/ 62 63 64 65 /* To set "inverted" flags, do AND. Otherwise, do OR */ 66 /* 0 & x = 0, 1 | x = 1 */ 67 68 /* Clear flags: n(var) is equivalent to var = 0. 69 #define n(flags) (~(flags) & (flags))*/ 70 71 /* Invert flags 72 #define inv(flags) (~(flags))*/ 73 74 /* SPP mode control register bit positions. */ 75 #define STROBE 0x01 76 #define AUTOFEED 0x02 77 #define nINIT 0x04 78 #define SELECTIN 0x08 79 #define IRQENABLE 0x10 80 #define PCD 0x20 81 82 /* 83 #define nSTROBE inv(STROBE) 84 #define nAUTOFEED inv(AUTOFEED) 85 #define INIT inv(nINIT) 86 #define nSELECTIN inv(SELECTIN) 87 #define nPCD inv(PCD) 88 */ 89 90 /* SPP status register bit positions. */ 91 #define TIMEOUT 0x01 92 #define nFAULT 0x08 93 #define SELECT 0x10 94 #define PERROR 0x20 95 #define nACK 0x40 96 #define nBUSY 0x80 97 98 /* Flags indicating ready condition */ 99 #define SPP_READY (SELECT | nFAULT | nBUSY) 100 #define SPP_MASK (SELECT | nFAULT | PERROR | nBUSY) 101 102 /* Byte mode signals */ 103 #define HOSTCLK STROBE /* Also ECP mode signal */ 104 #define HOSTBUSY AUTOFEED 105 #define ACTIVE1284 SELECTIN /* Also ECP mode signal */ 106 #define PTRCLK nACK 107 #define PTRBUSY nBUSY 108 #define ACKDATAREQ PERROR 109 #define XFLAG SELECT /* Also ECP mode signal */ 110 #define nDATAVAIL nFAULT 111 112 /* ECP mode signals */ 113 #define HOSTACK AUTOFEED 114 #define nREVREQ nINIT 115 #define PERICLK nACK 116 #define PERIACK nBUSY 117 #define nACKREV PERROR 118 #define nPERIREQ nFAULT 119 120 /* EPP mode signals */ 121 #define nWRITE STROBE 122 #define nDATASTB AUTOFEED 123 #define nADDRSTB SELECTIN 124 #define nWAIT nBUSY 125 #define nRESET nINIT 126 #define nINTR nACK 127 128 129 /* 130 * Useful macros for reading/writing registers. 131 */ 132 133 /* Reading macros */ 134 #define atppc_r_dtr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 135 ATPPC_SPP_DTR) 136 #define atppc_r_str(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 137 ATPPC_SPP_STR) 138 #define atppc_r_ctr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 139 ATPPC_SPP_CTR) 140 #define atppc_r_eppA(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 141 ATPPC_EPP_ADDR) 142 #define atppc_r_eppD(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 143 ATPPC_EPP_DATA) 144 #define atppc_r_eppD_multi(atppc, buf, count) bus_space_read_multi_1( \ 145 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_EPP_DATA, (buf), (count)) 146 #define atppc_r_cnfgA(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 147 ATPPC_ECP_CNFGA) 148 #define atppc_r_cnfgB(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\ 149 ATPPC_ECP_CNFGB) 150 #define atppc_r_ecr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 151 ATPPC_ECP_ECR) 152 #define atppc_r_fifo(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \ 153 ATPPC_ECP_D_FIFO) 154 #define atppc_r_fifo_multi(atppc, buf, count) bus_space_read_multi_1( \ 155 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (buf), (count)) 156 157 /* Writing macros */ 158 #define atppc_w_dtr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 159 (atppc)->sc_ioh, ATPPC_SPP_DTR, (byte)) 160 #define atppc_w_str(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 161 (atppc)->sc_ioh, ATPPC_SPP_STR, (byte)) 162 #define atppc_w_ctr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 163 (atppc)->sc_ioh, ATPPC_SPP_CTR, (byte)) 164 #define atppc_w_eppA(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 165 (atppc)->sc_ioh, ATPPC_EPP_ADDR, (byte)) 166 #define atppc_w_eppD(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 167 (atppc)->sc_ioh, ATPPC_EPP_DATA, (byte)) 168 #define atppc_w_eppD_multi(atppc, buf, count) bus_space_write_multi_1( \ 169 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_EPP_DATA, (buf), (count)) 170 #define atppc_w_cnfgA(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 171 (atppc)->sc_ioh, ATPPC_ECP_CNFGA, (byte)) 172 #define atppc_w_cnfgB(atppc, byte) bus_space_read_1((atppc)->sc_iot, \ 173 (atppc)->sc_ioh, ATPPC_ECP_CNFGB, (byte)) 174 #define atppc_w_ecr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 175 (atppc)->sc_ioh, ATPPC_ECP_ECR, (byte)) 176 #define atppc_w_fifo(atppc, byte) bus_space_write_1((atppc)->sc_iot, \ 177 (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (byte)) 178 #define atppc_w_fifo_multi(atppc, buf, count) bus_space_write_multi_1( \ 179 (atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (buf), (count)) 180 181 /* Barrier macros for reads/writes */ 182 #define atppc_barrier_r(atppc) bus_space_barrier((atppc)->sc_iot, \ 183 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ) 184 #define atppc_barrier_w(atppc) bus_space_barrier((atppc)->sc_iot, \ 185 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE) 186 #define atppc_barrier(atppc) bus_space_barrier((atppc)->sc_iot, \ 187 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE | \ 188 BUS_SPACE_BARRIER_READ) 189 190 /* These are defined in man pages but don't actually exist for all acrhs */ 191 #define atppc_barrier_rr(atppc) bus_space_barrier((atppc)->sc_iot, \ 192 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ_BEFORE_READ) 193 #define atppc_barrier_rw(atppc) bus_space_barrier((atppc)->sc_iot, \ 194 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 195 #define atppc_barrier_rb(atppc) bus_space_barrier((atppc)->sc_iot, \ 196 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ_BEFORE_READ | \ 197 BUS_SPACE_BARRIER_READ_BEFORE_WRITE) 198 #define atppc_barrier_wr(atppc) bus_space_barrier((atppc)->sc_iot, \ 199 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE_BEFORE_READ) 200 #define atppc_barrier_ww(atppc) bus_space_barrier((atppc)->sc_iot, \ 201 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 202 #define atppc_barrier_wb(atppc) bus_space_barrier((atppc)->sc_iot, \ 203 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE_BEFORE_READ | \ 204 BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE) 205 #define atppc_barrier_sync(atppc) bus_space_barrier((atppc)->sc_iot, \ 206 (atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_SYNC) 207 208 /* 209 * Register defines for the PC873xx parts 210 */ 211 212 #define PC873_FER 0x00 213 #define PC873_PPENABLE (1<<0) 214 #define PC873_FAR 0x01 215 #define PC873_PTR 0x02 216 #define PC873_CFGLOCK (1<<6) 217 #define PC873_EPPRDIR (1<<7) 218 #define PC873_EXTENDED (1<<7) 219 #define PC873_LPTBIRQ7 (1<<3) 220 #define PC873_FCR 0x03 221 #define PC873_ZWS (1<<5) 222 #define PC873_ZWSPWDN (1<<6) 223 #define PC873_PCR 0x04 224 #define PC873_EPPEN (1<<0) 225 #define PC873_EPP19 (1<<1) 226 #define PC873_ECPEN (1<<2) 227 #define PC873_ECPCLK (1<<3) 228 #define PC873_PMC 0x06 229 #define PC873_TUP 0x07 230 #define PC873_SID 0x08 231 #define PC873_PNP0 0x1b 232 #define PC873_PNP1 0x1c 233 #define PC873_LPTBA 0x19 234 235 /* 236 * Register defines for the SMC FDC37C66xGT parts 237 */ 238 239 /* Init codes */ 240 #define SMC665_iCODE 0x55 241 #define SMC666_iCODE 0x44 242 243 /* Base configuration ports */ 244 #define SMC66x_CSR 0x3F0 245 #define SMC666_CSR 0x370 /* hard-configured value for 666 */ 246 247 /* Bits */ 248 #define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 249 #define SMC_CR1_MODE (1<<3) /* bit 3 */ 250 #define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 251 #define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */ 252 253 /* Extended modes */ 254 #define SMC_SPP 0x0 /* SPP */ 255 #define SMC_EPPSPP 0x1 /* EPP and SPP */ 256 #define SMC_ECP 0x2 /* ECP */ 257 #define SMC_ECPEPP 0x3 /* ECP and EPP */ 258 259 /* 260 * Register defines for the SMC FDC37C935 parts 261 */ 262 263 /* Configuration ports */ 264 #define SMC935_CFG 0x370 265 #define SMC935_IND 0x370 266 #define SMC935_DAT 0x371 267 268 /* Registers */ 269 #define SMC935_LOGDEV 0x7 270 #define SMC935_ID 0x20 271 #define SMC935_PORTHI 0x60 272 #define SMC935_PORTLO 0x61 273 #define SMC935_PPMODE 0xf0 274 275 /* Parallel port modes */ 276 #define SMC935_SPP 0x38 + 0 277 #define SMC935_EPP19SPP 0x38 + 1 278 #define SMC935_ECP 0x38 + 2 279 #define SMC935_ECPEPP19 0x38 + 3 280 #define SMC935_CENT 0x38 + 4 281 #define SMC935_EPP17SPP 0x38 + 5 282 #define SMC935_UNUSED 0x38 + 6 283 #define SMC935_ECPEPP17 0x38 + 7 284 285 /* 286 * Register defines for the Winbond W83877F parts 287 */ 288 289 #define WINB_W83877F_ID 0xa 290 #define WINB_W83877AF_ID 0xb 291 292 /* Configuration bits */ 293 #define WINB_HEFERE (1<<5) /* CROC bit 5 */ 294 #define WINB_HEFRAS (1<<0) /* CR16 bit 0 */ 295 296 #define WINB_PNPCVS (1<<2) /* CR16 bit 2 */ 297 #define WINB_CHIPID 0xf /* CR9 bits 0-3 */ 298 299 #define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */ 300 #define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */ 301 #define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */ 302 303 /* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */ 304 #define WINB_W83757 0x0 305 #define WINB_EXTFDC 0x4 306 #define WINB_EXTADP 0x8 307 #define WINB_EXT2FDD 0xc 308 #define WINB_JOYSTICK 0x80 309 310 #define WINB_PARALLEL 0x80 311 #define WINB_EPP_SPP 0x4 312 #define WINB_ECP 0x8 313 #define WINB_ECP_EPP 0xc 314 315 #endif /* __ATPPCREG_H */
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