FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/atppcvar.h
1 /* $NetBSD: atppcvar.h,v 1.3 2004/01/25 00:28:01 bjh21 Exp $ */
2
3 /*-
4 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp
29 *
30 */
31
32 #ifndef __ATPPCVAR_H
33 #define __ATPPCVAR_H
34
35 #include <machine/bus.h>
36 #include <machine/types.h>
37 #include <sys/device.h>
38 #include <sys/callout.h>
39
40 #include <dev/ppbus/ppbus_conf.h>
41
42
43 /* Maximum time to wait for device response */
44 #define MAXBUSYWAIT (5 * (hz))
45
46 /* Poll interval when wating for device to become ready */
47 #define ATPPC_POLL ((hz)/10)
48
49 /* Interrupt priority level for atppc device */
50 #define IPL_ATPPC IPL_TTY
51 #define splatppc spltty
52
53
54 /* Diagnostic and verbose printing macros */
55
56 #ifdef ATPPC_DEBUG
57 extern int atppc_debug;
58 #define ATPPC_DPRINTF(arg) if(atppc_debug) printf arg
59 #else
60 #define ATPPC_DPRINTF(arg)
61 #endif
62
63 #ifdef ATPPC_VERBOSE
64 extern int atppc_verbose;
65 #define ATPPC_VPRINTF(arg) if(atppc_verbose) printf arg
66 #else
67 #define ATPPC_VPRINTF(arg)
68 #endif
69
70
71 /* Flag used in DMA transfer */
72 #define ATPPC_DMA_MODE_READ 0x0
73 #define ATPPC_DMA_MODE_WRITE 0x1
74
75
76 /* Flags passed via config */
77 #define ATPPC_FLAG_DISABLE_INTR 0x01
78 #define ATPPC_FLAG_DISABLE_DMA 0x02
79
80
81 /* Locking for atppc device */
82 #if defined(MULTIPROCESSOR) || defined (LOCKDEBUG)
83 #include <sys/lock.h>
84 #define ATPPC_SC_LOCK(sc) (&((sc)->sc_lock))
85 #define ATPPC_LOCK(sc) simple_lock(ATPPC_SC_LOCK((sc)))
86 #define ATPPC_UNLOCK(sc) simple_unlock(ATPPC_SC_LOCK((sc)))
87 #else /* !(MULTIPROCESSOR) && !(LOCKDEBUG) */
88 #define ATPPC_LOCK(sc)
89 #define ATPPC_UNLOCK(sc)
90 #define ATPPC_SC_LOCK(sc) NULL
91 #endif /* MULTIPROCESSOR || LOCKDEBUG */
92
93 /* Single softintr callback entry */
94 struct atppc_handler_node {
95 void (*func)(void *);
96 void * arg;
97 SLIST_ENTRY(atppc_handler_node) entries;
98 };
99
100 /* Generic structure to hold parallel port chipset info. */
101 struct atppc_softc {
102 /* Generic device attributes */
103 struct device sc_dev;
104
105 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
106 /* Simple lock */
107 struct simplelock sc_lock;
108 #endif
109
110 /* Machine independent bus infrastructure */
111 bus_space_tag_t sc_iot;
112 bus_space_handle_t sc_ioh;
113 bus_dma_tag_t sc_dmat;
114 bus_dmamap_t sc_dmapt;
115 bus_size_t sc_dma_maxsize;
116
117 /* Child device */
118 struct device * child;
119
120 /* Opaque handle used for interrupt handler establishment */
121 void * sc_ieh;
122
123 /* List of soft interrupts to call */
124 SLIST_HEAD(handler_list, atppc_handler_node) sc_handler_listhead;
125
126 /* Input buffer: working pointers, and size in bytes. */
127 char * sc_inb;
128 char * sc_inbstart;
129 u_int32_t sc_inb_nbytes;
130 int sc_inerr;
131
132 /* Output buffer pointer, working pointer, and size in bytes. */
133 char * sc_outb;
134 char * sc_outbstart;
135 u_int32_t sc_outb_nbytes;
136 int sc_outerr;
137
138 /* DMA functions: setup by bus specific attach code */
139 int (*sc_dma_start)(struct atppc_softc *, void *, u_int, u_int8_t);
140 int (*sc_dma_finish)(struct atppc_softc *);
141 int (*sc_dma_abort)(struct atppc_softc *);
142 int (*sc_dma_malloc)(struct device *, caddr_t *, bus_addr_t *,
143 bus_size_t);
144 void (*sc_dma_free)(struct device *, caddr_t *, bus_addr_t *,
145 bus_size_t);
146
147 /* Microsequence related members */
148 char * sc_ptr; /* microseq current pointer */
149 int sc_accum; /* microseq accumulator */
150
151 /* Device attachment state */
152 #define ATPPC_ATTACHED 1
153 #define ATPPC_NOATTACH 0
154 u_int8_t sc_dev_ok;
155
156 /*
157 * Hardware capabilities flags: standard mode and nibble mode are
158 * assumed to always be available since if they aren't you don't
159 * HAVE a parallel port.
160 */
161 #define ATPPC_HAS_INTR 0x01 /* Interrupt available */
162 #define ATPPC_HAS_DMA 0x02 /* DMA available */
163 #define ATPPC_HAS_FIFO 0x04 /* FIFO available */
164 #define ATPPC_HAS_PS2 0x08 /* PS2 mode capable */
165 #define ATPPC_HAS_ECP 0x10 /* ECP mode available */
166 #define ATPPC_HAS_EPP 0x20 /* EPP mode available */
167 u_int8_t sc_has; /* Chipset detected capabilities */
168
169 /* Flags specifying mode of chipset operation . */
170 #define ATPPC_MODE_STD 0x01 /* Use centronics-compatible mode */
171 #define ATPPC_MODE_PS2 0x02 /* Use PS2 mode */
172 #define ATPPC_MODE_EPP 0x04 /* Use EPP mode */
173 #define ATPPC_MODE_ECP 0x08 /* Use ECP mode */
174 #define ATPPC_MODE_NIBBLE 0x10 /* Use nibble mode */
175 #define ATPPC_MODE_FAST 0x20 /* Use Fast Centronics mode */
176 u_int8_t sc_mode; /* Current operational mode */
177
178 /* Flags which further define chipset operation */
179 #define ATPPC_USE_INTR 0x01 /* Use interrupts */
180 #define ATPPC_USE_DMA 0x02 /* Use DMA */
181 u_int8_t sc_use; /* Capabilities to use */
182
183 /* Parallel Port Chipset model. */
184 #define SMC_LIKE 0
185 #define SMC_37C665GT 1
186 #define SMC_37C666GT 2
187 #define NS_PC87332 3
188 #define NS_PC87306 4
189 #define INTEL_820191AA 5 /* XXX not implemented */
190 #define GENERIC 6
191 #define WINB_W83877F 7
192 #define WINB_W83877AF 8
193 #define WINB_UNKNOWN 9
194 #define NS_PC87334 10
195 #define SMC_37C935 11
196 #define NS_PC87303 12
197 u_int8_t sc_model; /* chipset model */
198
199 /* EPP mode */
200 #define ATPPC_EPP_1_9 0x0
201 #define ATPPC_EPP_1_7 0x1
202 u_int8_t sc_epp;
203
204 /* Parallel Port Chipset Type. SMC versus GENERIC (others) */
205 #define ATPPC_TYPE_SMCLIKE 0
206 #define ATPPC_TYPE_GENERIC 1
207 u_int8_t sc_type; /* generic or smclike chipset type */
208
209 /* Stored register values after an interrupt occurs */
210 u_int8_t sc_ecr_intr;
211 u_int8_t sc_ctr_intr;
212 u_int8_t sc_str_intr;
213
214 #define ATPPC_IRQ_NONE 0x0
215 #define ATPPC_IRQ_nACK 0x1
216 #define ATPPC_IRQ_DMA 0x2
217 #define ATPPC_IRQ_FIFO 0x4
218 #define ATPPC_IRQ_nFAULT 0x8
219 u_int8_t sc_irqstat; /* Record irq settings */
220
221 #define ATPPC_DMA_INIT 0x01
222 #define ATPPC_DMA_STARTED 0x02
223 #define ATPPC_DMA_COMPLETE 0x03
224 #define ATPPC_DMA_INTERRUPTED 0x04
225 #define ATPPC_DMA_ERROR 0x05
226 u_int8_t sc_dmastat; /* Record dma state */
227
228 #define ATPPC_PWORD_MASK 0x30
229 #define ATPPC_PWORD_16 0x00
230 #define ATPPC_PWORD_8 0x10
231 #define ATPPC_PWORD_32 0x20
232 u_int8_t sc_pword; /* PWord size: used for FIFO DMA transfers */
233 u_int8_t sc_fifo; /* FIFO size */
234
235 /* Indicates number of PWords in FIFO queues that generate interrupt */
236 u_int8_t sc_wthr; /* writeIntrThresold */
237 u_int8_t sc_rthr; /* readIntrThresold */
238 };
239
240
241
242 #ifdef _KERNEL
243
244 /* Function prototypes */
245
246 /* Soft config attach/detach routines */
247 void atppc_sc_attach __P((struct atppc_softc *));
248 int atppc_sc_detach __P((struct atppc_softc *, int));
249
250 /* Detection routines */
251 int atppc_detect_port __P((bus_space_tag_t, bus_space_handle_t));
252
253 /* Interrupt handler for atppc device */
254 int atppcintr __P((void *));
255
256 #endif /* _KERNEL */
257
258 #endif /* __ATPPCVAR_H */
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