FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/atppcvar.h
1 /* $NetBSD: atppcvar.h,v 1.6 2005/02/27 00:27:00 perry Exp $ */
2
3 /*-
4 * Copyright (c) 2001 Alcove - Nicolas Souchu
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp
29 *
30 */
31
32 #ifndef __ATPPCVAR_H
33 #define __ATPPCVAR_H
34
35 #include <machine/bus.h>
36 #include <machine/types.h>
37 #include <sys/device.h>
38 #include <sys/callout.h>
39
40 #include <dev/ppbus/ppbus_conf.h>
41
42
43 /* Maximum time to wait for device response */
44 #define MAXBUSYWAIT (5 * (hz))
45
46 /* Poll interval when wating for device to become ready */
47 #define ATPPC_POLL ((hz)/10)
48
49 /* Interrupt priority level for atppc device */
50 #define IPL_ATPPC IPL_TTY
51 #define splatppc spltty
52
53
54 /* Diagnostic and verbose printing macros */
55
56 #ifdef ATPPC_DEBUG
57 extern int atppc_debug;
58 #define ATPPC_DPRINTF(arg) if(atppc_debug) printf arg
59 #else
60 #define ATPPC_DPRINTF(arg)
61 #endif
62
63 #ifdef ATPPC_VERBOSE
64 extern int atppc_verbose;
65 #define ATPPC_VPRINTF(arg) if(atppc_verbose) printf arg
66 #else
67 #define ATPPC_VPRINTF(arg)
68 #endif
69
70
71 /* Flag used in DMA transfer */
72 #define ATPPC_DMA_MODE_READ 0x0
73 #define ATPPC_DMA_MODE_WRITE 0x1
74
75
76 /* Flags passed via config */
77 #define ATPPC_FLAG_DISABLE_INTR 0x01
78 #define ATPPC_FLAG_DISABLE_DMA 0x02
79
80
81 /* Locking for atppc device */
82 #if defined(MULTIPROCESSOR) || defined (LOCKDEBUG)
83 #include <sys/lock.h>
84 #define ATPPC_SC_LOCK(sc) (&((sc)->sc_lock))
85 #define ATPPC_LOCK_INIT(sc) simple_lock_init(ATPPC_SC_LOCK((sc)))
86 #define ATPPC_LOCK(sc) simple_lock(ATPPC_SC_LOCK((sc)))
87 #define ATPPC_UNLOCK(sc) simple_unlock(ATPPC_SC_LOCK((sc)))
88 #else /* !(MULTIPROCESSOR) && !(LOCKDEBUG) */
89 #define ATPPC_LOCK_INIT(sc)
90 #define ATPPC_LOCK(sc)
91 #define ATPPC_UNLOCK(sc)
92 #define ATPPC_SC_LOCK(sc) NULL
93 #endif /* MULTIPROCESSOR || LOCKDEBUG */
94
95 /* Single softintr callback entry */
96 struct atppc_handler_node {
97 void (*func)(void *);
98 void * arg;
99 SLIST_ENTRY(atppc_handler_node) entries;
100 };
101
102 /* Generic structure to hold parallel port chipset info. */
103 struct atppc_softc {
104 /* Generic device attributes */
105 struct device sc_dev;
106
107 #if defined(MULTIPROCESSOR) || defined(LOCKDEBUG)
108 /* Simple lock */
109 struct simplelock sc_lock;
110 #endif
111
112 /* Machine independent bus infrastructure */
113 bus_space_tag_t sc_iot;
114 bus_space_handle_t sc_ioh;
115 bus_dma_tag_t sc_dmat;
116 bus_dmamap_t sc_dmapt;
117 bus_size_t sc_dma_maxsize;
118
119 /* Child device */
120 struct device * child;
121
122 /* Opaque handle used for interrupt handler establishment */
123 void * sc_ieh;
124
125 /* List of soft interrupts to call */
126 SLIST_HEAD(handler_list, atppc_handler_node) sc_handler_listhead;
127
128 /* Input buffer: working pointers, and size in bytes. */
129 char * sc_inb;
130 char * sc_inbstart;
131 u_int32_t sc_inb_nbytes;
132 int sc_inerr;
133
134 /* Output buffer pointer, working pointer, and size in bytes. */
135 char * sc_outb;
136 char * sc_outbstart;
137 u_int32_t sc_outb_nbytes;
138 int sc_outerr;
139
140 /* DMA functions: setup by bus specific attach code */
141 int (*sc_dma_start)(struct atppc_softc *, void *, u_int, u_int8_t);
142 int (*sc_dma_finish)(struct atppc_softc *);
143 int (*sc_dma_abort)(struct atppc_softc *);
144 int (*sc_dma_malloc)(struct device *, caddr_t *, bus_addr_t *,
145 bus_size_t);
146 void (*sc_dma_free)(struct device *, caddr_t *, bus_addr_t *,
147 bus_size_t);
148
149 /* Microsequence related members */
150 char * sc_ptr; /* microseq current pointer */
151 int sc_accum; /* microseq accumulator */
152
153 /* Device attachment state */
154 #define ATPPC_ATTACHED 1
155 #define ATPPC_NOATTACH 0
156 u_int8_t sc_dev_ok;
157
158 /*
159 * Hardware capabilities flags: standard mode and nibble mode are
160 * assumed to always be available since if they aren't you don't
161 * HAVE a parallel port.
162 */
163 #define ATPPC_HAS_INTR 0x01 /* Interrupt available */
164 #define ATPPC_HAS_DMA 0x02 /* DMA available */
165 #define ATPPC_HAS_FIFO 0x04 /* FIFO available */
166 #define ATPPC_HAS_PS2 0x08 /* PS2 mode capable */
167 #define ATPPC_HAS_ECP 0x10 /* ECP mode available */
168 #define ATPPC_HAS_EPP 0x20 /* EPP mode available */
169 u_int8_t sc_has; /* Chipset detected capabilities */
170
171 /* Flags specifying mode of chipset operation . */
172 #define ATPPC_MODE_STD 0x01 /* Use centronics-compatible mode */
173 #define ATPPC_MODE_PS2 0x02 /* Use PS2 mode */
174 #define ATPPC_MODE_EPP 0x04 /* Use EPP mode */
175 #define ATPPC_MODE_ECP 0x08 /* Use ECP mode */
176 #define ATPPC_MODE_NIBBLE 0x10 /* Use nibble mode */
177 #define ATPPC_MODE_FAST 0x20 /* Use Fast Centronics mode */
178 u_int8_t sc_mode; /* Current operational mode */
179
180 /* Flags which further define chipset operation */
181 #define ATPPC_USE_INTR 0x01 /* Use interrupts */
182 #define ATPPC_USE_DMA 0x02 /* Use DMA */
183 u_int8_t sc_use; /* Capabilities to use */
184
185 /* Parallel Port Chipset model. */
186 #define SMC_LIKE 0
187 #define SMC_37C665GT 1
188 #define SMC_37C666GT 2
189 #define NS_PC87332 3
190 #define NS_PC87306 4
191 #define INTEL_820191AA 5 /* XXX not implemented */
192 #define GENERIC 6
193 #define WINB_W83877F 7
194 #define WINB_W83877AF 8
195 #define WINB_UNKNOWN 9
196 #define NS_PC87334 10
197 #define SMC_37C935 11
198 #define NS_PC87303 12
199 u_int8_t sc_model; /* chipset model */
200
201 /* EPP mode */
202 #define ATPPC_EPP_1_9 0x0
203 #define ATPPC_EPP_1_7 0x1
204 u_int8_t sc_epp;
205
206 /* Parallel Port Chipset Type. SMC versus GENERIC (others) */
207 #define ATPPC_TYPE_SMCLIKE 0
208 #define ATPPC_TYPE_GENERIC 1
209 u_int8_t sc_type; /* generic or smclike chipset type */
210
211 /* Stored register values after an interrupt occurs */
212 u_int8_t sc_ecr_intr;
213 u_int8_t sc_ctr_intr;
214 u_int8_t sc_str_intr;
215
216 #define ATPPC_IRQ_NONE 0x0
217 #define ATPPC_IRQ_nACK 0x1
218 #define ATPPC_IRQ_DMA 0x2
219 #define ATPPC_IRQ_FIFO 0x4
220 #define ATPPC_IRQ_nFAULT 0x8
221 u_int8_t sc_irqstat; /* Record irq settings */
222
223 #define ATPPC_DMA_INIT 0x01
224 #define ATPPC_DMA_STARTED 0x02
225 #define ATPPC_DMA_COMPLETE 0x03
226 #define ATPPC_DMA_INTERRUPTED 0x04
227 #define ATPPC_DMA_ERROR 0x05
228 u_int8_t sc_dmastat; /* Record dma state */
229
230 #define ATPPC_PWORD_MASK 0x30
231 #define ATPPC_PWORD_16 0x00
232 #define ATPPC_PWORD_8 0x10
233 #define ATPPC_PWORD_32 0x20
234 u_int8_t sc_pword; /* PWord size: used for FIFO DMA transfers */
235 u_int8_t sc_fifo; /* FIFO size */
236
237 /* Indicates number of PWords in FIFO queues that generate interrupt */
238 u_int8_t sc_wthr; /* writeIntrThresold */
239 u_int8_t sc_rthr; /* readIntrThresold */
240 };
241
242
243
244 #ifdef _KERNEL
245
246 /* Function prototypes */
247
248 /* Soft config attach/detach routines */
249 void atppc_sc_attach(struct atppc_softc *);
250 int atppc_sc_detach(struct atppc_softc *, int);
251
252 /* Detection routines */
253 int atppc_detect_port(bus_space_tag_t, bus_space_handle_t);
254
255 /* Interrupt handler for atppc device */
256 int atppcintr(void *);
257
258 #endif /* _KERNEL */
259
260 #endif /* __ATPPCVAR_H */
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