FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/atw.c
1 /* $NetBSD: atw.c,v 1.125 2006/11/24 19:46:59 christos Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999, 2000, 2002, 2003, 2004 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by David Young, by Jason R. Thorpe, and by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Device driver for the ADMtek ADM8211 802.11 MAC/BBP.
41 */
42
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: atw.c,v 1.125 2006/11/24 19:46:59 christos Exp $");
45
46 #include "bpfilter.h"
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/callout.h>
51 #include <sys/mbuf.h>
52 #include <sys/malloc.h>
53 #include <sys/kernel.h>
54 #include <sys/socket.h>
55 #include <sys/ioctl.h>
56 #include <sys/errno.h>
57 #include <sys/device.h>
58 #include <sys/time.h>
59 #include <lib/libkern/libkern.h>
60
61 #include <machine/endian.h>
62
63 #include <uvm/uvm_extern.h>
64
65 #include <net/if.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_ether.h>
69
70 #include <net80211/ieee80211_netbsd.h>
71 #include <net80211/ieee80211_var.h>
72 #include <net80211/ieee80211_radiotap.h>
73
74 #if NBPFILTER > 0
75 #include <net/bpf.h>
76 #endif
77
78 #include <machine/bus.h>
79 #include <machine/intr.h>
80
81 #include <dev/ic/atwreg.h>
82 #include <dev/ic/rf3000reg.h>
83 #include <dev/ic/si4136reg.h>
84 #include <dev/ic/atwvar.h>
85 #include <dev/ic/smc93cx6var.h>
86
87 /* XXX TBD open questions
88 *
89 *
90 * When should I set DSSS PAD in reg 0x15 of RF3000? In 1-2Mbps
91 * modes only, or all modes (5.5-11 Mbps CCK modes, too?) Does the MAC
92 * handle this for me?
93 *
94 */
95 /* device attachment
96 *
97 * print TOFS[012]
98 *
99 * device initialization
100 *
101 * clear ATW_FRCTL_MAXPSP to disable max power saving
102 * set ATW_TXBR_ALCUPDATE to enable ALC
103 * set TOFS[012]? (hope not)
104 * disable rx/tx
105 * set ATW_PAR_SWR (software reset)
106 * wait for ATW_PAR_SWR clear
107 * disable interrupts
108 * ack status register
109 * enable interrupts
110 *
111 * rx/tx initialization
112 *
113 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
114 * allocate and init descriptor rings
115 * write ATW_PAR_DSL (descriptor skip length)
116 * write descriptor base addrs: ATW_TDBD, ATW_TDBP, write ATW_RDB
117 * write ATW_NAR_SQ for one/both transmit descriptor rings
118 * write ATW_NAR_SQ for one/both transmit descriptor rings
119 * enable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
120 *
121 * rx/tx end
122 *
123 * stop DMA
124 * disable rx/tx w/ ATW_NAR_SR, ATW_NAR_ST
125 * flush tx w/ ATW_NAR_HF
126 *
127 * scan
128 *
129 * initialize rx/tx
130 *
131 * BSS join: (re)association response
132 *
133 * set ATW_FRCTL_AID
134 *
135 * optimizations ???
136 *
137 */
138
139 #define ATW_REFSLAVE /* slavishly do what the reference driver does */
140
141 #define VOODOO_DUR_11_ROUNDING 0x01 /* necessary */
142 #define VOODOO_DUR_2_4_SPECIALCASE 0x02 /* NOT necessary */
143 int atw_voodoo = VOODOO_DUR_11_ROUNDING;
144
145 int atw_pseudo_milli = 1;
146 int atw_magic_delay1 = 100 * 1000;
147 int atw_magic_delay2 = 100 * 1000;
148 /* more magic multi-millisecond delays (units: microseconds) */
149 int atw_nar_delay = 20 * 1000;
150 int atw_magic_delay4 = 10 * 1000;
151 int atw_rf_delay1 = 10 * 1000;
152 int atw_rf_delay2 = 5 * 1000;
153 int atw_plcphd_delay = 2 * 1000;
154 int atw_bbp_io_enable_delay = 20 * 1000;
155 int atw_bbp_io_disable_delay = 2 * 1000;
156 int atw_writewep_delay = 1000;
157 int atw_beacon_len_adjust = 4;
158 int atw_dwelltime = 200;
159 int atw_xindiv2 = 0;
160
161 #ifdef ATW_DEBUG
162 int atw_debug = 0;
163
164 #define ATW_DPRINTF(x) if (atw_debug > 0) printf x
165 #define ATW_DPRINTF2(x) if (atw_debug > 1) printf x
166 #define ATW_DPRINTF3(x) if (atw_debug > 2) printf x
167 #define DPRINTF(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) printf x
168 #define DPRINTF2(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF2(x)
169 #define DPRINTF3(sc, x) if ((sc)->sc_if.if_flags & IFF_DEBUG) ATW_DPRINTF3(x)
170
171 static void atw_dump_pkt(struct ifnet *, struct mbuf *);
172 static void atw_print_regs(struct atw_softc *, const char *);
173
174 /* Note well: I never got atw_rf3000_read or atw_si4126_read to work. */
175 # ifdef ATW_BBPDEBUG
176 static void atw_rf3000_print(struct atw_softc *);
177 static int atw_rf3000_read(struct atw_softc *sc, u_int, u_int *);
178 # endif /* ATW_BBPDEBUG */
179
180 # ifdef ATW_SYNDEBUG
181 static void atw_si4126_print(struct atw_softc *);
182 static int atw_si4126_read(struct atw_softc *, u_int, u_int *);
183 # endif /* ATW_SYNDEBUG */
184
185 #else
186 #define ATW_DPRINTF(x)
187 #define ATW_DPRINTF2(x)
188 #define ATW_DPRINTF3(x)
189 #define DPRINTF(sc, x) /* nothing */
190 #define DPRINTF2(sc, x) /* nothing */
191 #define DPRINTF3(sc, x) /* nothing */
192 #endif
193
194 /* ifnet methods */
195 int atw_init(struct ifnet *);
196 int atw_ioctl(struct ifnet *, u_long, caddr_t);
197 void atw_start(struct ifnet *);
198 void atw_stop(struct ifnet *, int);
199 void atw_watchdog(struct ifnet *);
200
201 /* Device attachment */
202 void atw_attach(struct atw_softc *);
203 int atw_detach(struct atw_softc *);
204
205 /* Rx/Tx process */
206 int atw_add_rxbuf(struct atw_softc *, int);
207 void atw_idle(struct atw_softc *, u_int32_t);
208 void atw_rxdrain(struct atw_softc *);
209 void atw_txdrain(struct atw_softc *);
210
211 /* Device (de)activation and power state */
212 void atw_disable(struct atw_softc *);
213 int atw_enable(struct atw_softc *);
214 void atw_power(int, void *);
215 void atw_reset(struct atw_softc *);
216 void atw_shutdown(void *);
217
218 /* Interrupt handlers */
219 void atw_linkintr(struct atw_softc *, u_int32_t);
220 void atw_rxintr(struct atw_softc *);
221 void atw_txintr(struct atw_softc *);
222
223 /* 802.11 state machine */
224 static int atw_newstate(struct ieee80211com *, enum ieee80211_state, int);
225 static void atw_next_scan(void *);
226 static void atw_recv_mgmt(struct ieee80211com *, struct mbuf *,
227 struct ieee80211_node *, int, int, u_int32_t);
228 static int atw_tune(struct atw_softc *);
229
230 /* Device initialization */
231 static void atw_bbp_io_init(struct atw_softc *);
232 static void atw_cfp_init(struct atw_softc *);
233 static void atw_cmdr_init(struct atw_softc *);
234 static void atw_ifs_init(struct atw_softc *);
235 static void atw_nar_init(struct atw_softc *);
236 static void atw_response_times_init(struct atw_softc *);
237 static void atw_rf_reset(struct atw_softc *);
238 static void atw_test1_init(struct atw_softc *);
239 static void atw_tofs0_init(struct atw_softc *);
240 static void atw_tofs2_init(struct atw_softc *);
241 static void atw_txlmt_init(struct atw_softc *);
242 static void atw_wcsr_init(struct atw_softc *);
243
244 /* Key management */
245 static int atw_key_delete(struct ieee80211com *, const struct ieee80211_key *);
246 static int atw_key_set(struct ieee80211com *, const struct ieee80211_key *,
247 const u_int8_t[IEEE80211_ADDR_LEN]);
248 static void atw_key_update_begin(struct ieee80211com *);
249 static void atw_key_update_end(struct ieee80211com *);
250
251 /* RAM/ROM utilities */
252 static void atw_clear_sram(struct atw_softc *);
253 static void atw_write_sram(struct atw_softc *, u_int, u_int8_t *, u_int);
254 static int atw_read_srom(struct atw_softc *);
255
256 /* BSS setup */
257 static void atw_predict_beacon(struct atw_softc *);
258 static void atw_start_beacon(struct atw_softc *, int);
259 static void atw_write_bssid(struct atw_softc *);
260 static void atw_write_ssid(struct atw_softc *);
261 static void atw_write_sup_rates(struct atw_softc *);
262 static void atw_write_wep(struct atw_softc *);
263
264 /* Media */
265 static int atw_media_change(struct ifnet *);
266
267 static void atw_filter_setup(struct atw_softc *);
268
269 /* 802.11 utilities */
270 static uint64_t atw_get_tsft(struct atw_softc *);
271 static inline uint32_t atw_last_even_tsft(uint32_t, uint32_t,
272 uint32_t);
273 static struct ieee80211_node *atw_node_alloc(struct ieee80211_node_table *);
274 static void atw_node_free(struct ieee80211_node *);
275
276 /*
277 * Tuner/transceiver/modem
278 */
279 static void atw_bbp_io_enable(struct atw_softc *, int);
280
281 /* RFMD RF3000 Baseband Processor */
282 static int atw_rf3000_init(struct atw_softc *);
283 static int atw_rf3000_tune(struct atw_softc *, u_int);
284 static int atw_rf3000_write(struct atw_softc *, u_int, u_int);
285
286 /* Silicon Laboratories Si4126 RF/IF Synthesizer */
287 static void atw_si4126_tune(struct atw_softc *, u_int);
288 static void atw_si4126_write(struct atw_softc *, u_int, u_int);
289
290 const struct atw_txthresh_tab atw_txthresh_tab_lo[] = ATW_TXTHRESH_TAB_LO_RATE;
291 const struct atw_txthresh_tab atw_txthresh_tab_hi[] = ATW_TXTHRESH_TAB_HI_RATE;
292
293 const char *atw_tx_state[] = {
294 "STOPPED",
295 "RUNNING - read descriptor",
296 "RUNNING - transmitting",
297 "RUNNING - filling fifo", /* XXX */
298 "SUSPENDED",
299 "RUNNING -- write descriptor",
300 "RUNNING -- write last descriptor",
301 "RUNNING - fifo full"
302 };
303
304 const char *atw_rx_state[] = {
305 "STOPPED",
306 "RUNNING - read descriptor",
307 "RUNNING - check this packet, pre-fetch next",
308 "RUNNING - wait for reception",
309 "SUSPENDED",
310 "RUNNING - write descriptor",
311 "RUNNING - flush fifo",
312 "RUNNING - fifo drain"
313 };
314
315 static inline int
316 is_running(struct ifnet *ifp)
317 {
318 return (ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP);
319 }
320
321 int
322 atw_activate(struct device *self, enum devact act)
323 {
324 struct atw_softc *sc = (struct atw_softc *)self;
325 int rv = 0, s;
326
327 s = splnet();
328 switch (act) {
329 case DVACT_ACTIVATE:
330 rv = EOPNOTSUPP;
331 break;
332
333 case DVACT_DEACTIVATE:
334 if_deactivate(&sc->sc_if);
335 break;
336 }
337 splx(s);
338 return rv;
339 }
340
341 /*
342 * atw_enable:
343 *
344 * Enable the ADM8211 chip.
345 */
346 int
347 atw_enable(struct atw_softc *sc)
348 {
349
350 if (ATW_IS_ENABLED(sc) == 0) {
351 if (sc->sc_enable != NULL && (*sc->sc_enable)(sc) != 0) {
352 printf("%s: device enable failed\n",
353 sc->sc_dev.dv_xname);
354 return (EIO);
355 }
356 sc->sc_flags |= ATWF_ENABLED;
357 /* Power may have been removed, and WEP keys thus
358 * reset.
359 */
360 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
361 }
362 return (0);
363 }
364
365 /*
366 * atw_disable:
367 *
368 * Disable the ADM8211 chip.
369 */
370 void
371 atw_disable(struct atw_softc *sc)
372 {
373 if (!ATW_IS_ENABLED(sc))
374 return;
375 if (sc->sc_disable != NULL)
376 (*sc->sc_disable)(sc);
377 sc->sc_flags &= ~ATWF_ENABLED;
378 }
379
380 /* Returns -1 on failure. */
381 static int
382 atw_read_srom(struct atw_softc *sc)
383 {
384 struct seeprom_descriptor sd;
385 uint32_t test0, fail_bits;
386
387 (void)memset(&sd, 0, sizeof(sd));
388
389 test0 = ATW_READ(sc, ATW_TEST0);
390
391 switch (sc->sc_rev) {
392 case ATW_REVISION_BA:
393 case ATW_REVISION_CA:
394 fail_bits = ATW_TEST0_EPNE;
395 break;
396 default:
397 fail_bits = ATW_TEST0_EPNE|ATW_TEST0_EPSNM;
398 break;
399 }
400 if ((test0 & fail_bits) != 0) {
401 printf("%s: bad or missing/bad SROM\n", sc->sc_dev.dv_xname);
402 return -1;
403 }
404
405 switch (test0 & ATW_TEST0_EPTYP_MASK) {
406 case ATW_TEST0_EPTYP_93c66:
407 ATW_DPRINTF(("%s: 93c66 SROM\n", sc->sc_dev.dv_xname));
408 sc->sc_sromsz = 512;
409 sd.sd_chip = C56_66;
410 break;
411 case ATW_TEST0_EPTYP_93c46:
412 ATW_DPRINTF(("%s: 93c46 SROM\n", sc->sc_dev.dv_xname));
413 sc->sc_sromsz = 128;
414 sd.sd_chip = C46;
415 break;
416 default:
417 printf("%s: unknown SROM type %" __PRIuBITS "\n",
418 sc->sc_dev.dv_xname,
419 __SHIFTOUT(test0, ATW_TEST0_EPTYP_MASK));
420 return -1;
421 }
422
423 sc->sc_srom = malloc(sc->sc_sromsz, M_DEVBUF, M_NOWAIT);
424
425 if (sc->sc_srom == NULL) {
426 printf("%s: unable to allocate SROM buffer\n",
427 sc->sc_dev.dv_xname);
428 return -1;
429 }
430
431 (void)memset(sc->sc_srom, 0, sc->sc_sromsz);
432
433 /* ADM8211 has a single 32-bit register for controlling the
434 * 93cx6 SROM. Bit SRS enables the serial port. There is no
435 * "ready" bit. The ADM8211 input/output sense is the reverse
436 * of read_seeprom's.
437 */
438 sd.sd_tag = sc->sc_st;
439 sd.sd_bsh = sc->sc_sh;
440 sd.sd_regsize = 4;
441 sd.sd_control_offset = ATW_SPR;
442 sd.sd_status_offset = ATW_SPR;
443 sd.sd_dataout_offset = ATW_SPR;
444 sd.sd_CK = ATW_SPR_SCLK;
445 sd.sd_CS = ATW_SPR_SCS;
446 sd.sd_DI = ATW_SPR_SDO;
447 sd.sd_DO = ATW_SPR_SDI;
448 sd.sd_MS = ATW_SPR_SRS;
449 sd.sd_RDY = 0;
450
451 if (!read_seeprom(&sd, sc->sc_srom, 0, sc->sc_sromsz/2)) {
452 printf("%s: could not read SROM\n", sc->sc_dev.dv_xname);
453 free(sc->sc_srom, M_DEVBUF);
454 return -1;
455 }
456 #ifdef ATW_DEBUG
457 {
458 int i;
459 ATW_DPRINTF(("\nSerial EEPROM:\n\t"));
460 for (i = 0; i < sc->sc_sromsz/2; i = i + 1) {
461 if (((i % 8) == 0) && (i != 0)) {
462 ATW_DPRINTF(("\n\t"));
463 }
464 ATW_DPRINTF((" 0x%x", sc->sc_srom[i]));
465 }
466 ATW_DPRINTF(("\n"));
467 }
468 #endif /* ATW_DEBUG */
469 return 0;
470 }
471
472 #ifdef ATW_DEBUG
473 static void
474 atw_print_regs(struct atw_softc *sc, const char *where)
475 {
476 #define PRINTREG(sc, reg) \
477 ATW_DPRINTF2(("%s: reg[ " #reg " / %03x ] = %08x\n", \
478 sc->sc_dev.dv_xname, reg, ATW_READ(sc, reg)))
479
480 ATW_DPRINTF2(("%s: %s\n", sc->sc_dev.dv_xname, where));
481
482 PRINTREG(sc, ATW_PAR);
483 PRINTREG(sc, ATW_FRCTL);
484 PRINTREG(sc, ATW_TDR);
485 PRINTREG(sc, ATW_WTDP);
486 PRINTREG(sc, ATW_RDR);
487 PRINTREG(sc, ATW_WRDP);
488 PRINTREG(sc, ATW_RDB);
489 PRINTREG(sc, ATW_CSR3A);
490 PRINTREG(sc, ATW_TDBD);
491 PRINTREG(sc, ATW_TDBP);
492 PRINTREG(sc, ATW_STSR);
493 PRINTREG(sc, ATW_CSR5A);
494 PRINTREG(sc, ATW_NAR);
495 PRINTREG(sc, ATW_CSR6A);
496 PRINTREG(sc, ATW_IER);
497 PRINTREG(sc, ATW_CSR7A);
498 PRINTREG(sc, ATW_LPC);
499 PRINTREG(sc, ATW_TEST1);
500 PRINTREG(sc, ATW_SPR);
501 PRINTREG(sc, ATW_TEST0);
502 PRINTREG(sc, ATW_WCSR);
503 PRINTREG(sc, ATW_WPDR);
504 PRINTREG(sc, ATW_GPTMR);
505 PRINTREG(sc, ATW_GPIO);
506 PRINTREG(sc, ATW_BBPCTL);
507 PRINTREG(sc, ATW_SYNCTL);
508 PRINTREG(sc, ATW_PLCPHD);
509 PRINTREG(sc, ATW_MMIWADDR);
510 PRINTREG(sc, ATW_MMIRADDR1);
511 PRINTREG(sc, ATW_MMIRADDR2);
512 PRINTREG(sc, ATW_TXBR);
513 PRINTREG(sc, ATW_CSR15A);
514 PRINTREG(sc, ATW_ALCSTAT);
515 PRINTREG(sc, ATW_TOFS2);
516 PRINTREG(sc, ATW_CMDR);
517 PRINTREG(sc, ATW_PCIC);
518 PRINTREG(sc, ATW_PMCSR);
519 PRINTREG(sc, ATW_PAR0);
520 PRINTREG(sc, ATW_PAR1);
521 PRINTREG(sc, ATW_MAR0);
522 PRINTREG(sc, ATW_MAR1);
523 PRINTREG(sc, ATW_ATIMDA0);
524 PRINTREG(sc, ATW_ABDA1);
525 PRINTREG(sc, ATW_BSSID0);
526 PRINTREG(sc, ATW_TXLMT);
527 PRINTREG(sc, ATW_MIBCNT);
528 PRINTREG(sc, ATW_BCNT);
529 PRINTREG(sc, ATW_TSFTH);
530 PRINTREG(sc, ATW_TSC);
531 PRINTREG(sc, ATW_SYNRF);
532 PRINTREG(sc, ATW_BPLI);
533 PRINTREG(sc, ATW_CAP0);
534 PRINTREG(sc, ATW_CAP1);
535 PRINTREG(sc, ATW_RMD);
536 PRINTREG(sc, ATW_CFPP);
537 PRINTREG(sc, ATW_TOFS0);
538 PRINTREG(sc, ATW_TOFS1);
539 PRINTREG(sc, ATW_IFST);
540 PRINTREG(sc, ATW_RSPT);
541 PRINTREG(sc, ATW_TSFTL);
542 PRINTREG(sc, ATW_WEPCTL);
543 PRINTREG(sc, ATW_WESK);
544 PRINTREG(sc, ATW_WEPCNT);
545 PRINTREG(sc, ATW_MACTEST);
546 PRINTREG(sc, ATW_FER);
547 PRINTREG(sc, ATW_FEMR);
548 PRINTREG(sc, ATW_FPSR);
549 PRINTREG(sc, ATW_FFER);
550 #undef PRINTREG
551 }
552 #endif /* ATW_DEBUG */
553
554 /*
555 * Finish attaching an ADMtek ADM8211 MAC. Called by bus-specific front-end.
556 */
557 void
558 atw_attach(struct atw_softc *sc)
559 {
560 static const u_int8_t empty_macaddr[IEEE80211_ADDR_LEN] = {
561 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
562 };
563 struct ieee80211com *ic = &sc->sc_ic;
564 struct ifnet *ifp = &sc->sc_if;
565 int country_code, error, i, nrate, srom_major;
566 u_int32_t reg;
567 static const char *type_strings[] = {"Intersil (not supported)",
568 "RFMD", "Marvel (not supported)"};
569
570 sc->sc_txth = atw_txthresh_tab_lo;
571
572 SIMPLEQ_INIT(&sc->sc_txfreeq);
573 SIMPLEQ_INIT(&sc->sc_txdirtyq);
574
575 #ifdef ATW_DEBUG
576 atw_print_regs(sc, "atw_attach");
577 #endif /* ATW_DEBUG */
578
579 /*
580 * Allocate the control data structures, and create and load the
581 * DMA map for it.
582 */
583 if ((error = bus_dmamem_alloc(sc->sc_dmat,
584 sizeof(struct atw_control_data), PAGE_SIZE, 0, &sc->sc_cdseg,
585 1, &sc->sc_cdnseg, 0)) != 0) {
586 printf("%s: unable to allocate control data, error = %d\n",
587 sc->sc_dev.dv_xname, error);
588 goto fail_0;
589 }
590
591 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg,
592 sizeof(struct atw_control_data), (caddr_t *)&sc->sc_control_data,
593 BUS_DMA_COHERENT)) != 0) {
594 printf("%s: unable to map control data, error = %d\n",
595 sc->sc_dev.dv_xname, error);
596 goto fail_1;
597 }
598
599 if ((error = bus_dmamap_create(sc->sc_dmat,
600 sizeof(struct atw_control_data), 1,
601 sizeof(struct atw_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
602 printf("%s: unable to create control data DMA map, "
603 "error = %d\n", sc->sc_dev.dv_xname, error);
604 goto fail_2;
605 }
606
607 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
608 sc->sc_control_data, sizeof(struct atw_control_data), NULL,
609 0)) != 0) {
610 printf("%s: unable to load control data DMA map, error = %d\n",
611 sc->sc_dev.dv_xname, error);
612 goto fail_3;
613 }
614
615 /*
616 * Create the transmit buffer DMA maps.
617 */
618 sc->sc_ntxsegs = ATW_NTXSEGS;
619 for (i = 0; i < ATW_TXQUEUELEN; i++) {
620 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
621 sc->sc_ntxsegs, MCLBYTES, 0, 0,
622 &sc->sc_txsoft[i].txs_dmamap)) != 0) {
623 printf("%s: unable to create tx DMA map %d, "
624 "error = %d\n", sc->sc_dev.dv_xname, i, error);
625 goto fail_4;
626 }
627 }
628
629 /*
630 * Create the receive buffer DMA maps.
631 */
632 for (i = 0; i < ATW_NRXDESC; i++) {
633 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
634 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
635 printf("%s: unable to create rx DMA map %d, "
636 "error = %d\n", sc->sc_dev.dv_xname, i, error);
637 goto fail_5;
638 }
639 }
640 for (i = 0; i < ATW_NRXDESC; i++) {
641 sc->sc_rxsoft[i].rxs_mbuf = NULL;
642 }
643
644 switch (sc->sc_rev) {
645 case ATW_REVISION_AB:
646 case ATW_REVISION_AF:
647 sc->sc_sramlen = ATW_SRAM_A_SIZE;
648 break;
649 case ATW_REVISION_BA:
650 case ATW_REVISION_CA:
651 sc->sc_sramlen = ATW_SRAM_B_SIZE;
652 break;
653 }
654
655 /* Reset the chip to a known state. */
656 atw_reset(sc);
657
658 if (atw_read_srom(sc) == -1)
659 return;
660
661 sc->sc_rftype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],
662 ATW_SR_RFTYPE_MASK);
663
664 sc->sc_bbptype = __SHIFTOUT(sc->sc_srom[ATW_SR_CSR20],
665 ATW_SR_BBPTYPE_MASK);
666
667 if (sc->sc_rftype >= __arraycount(type_strings)) {
668 printf("%s: unknown RF\n", sc->sc_dev.dv_xname);
669 return;
670 }
671 if (sc->sc_bbptype >= __arraycount(type_strings)) {
672 printf("%s: unknown BBP\n", sc->sc_dev.dv_xname);
673 return;
674 }
675
676 printf("%s: %s RF, %s BBP", sc->sc_dev.dv_xname,
677 type_strings[sc->sc_rftype], type_strings[sc->sc_bbptype]);
678
679 /* XXX There exists a Linux driver which seems to use RFType = 0 for
680 * MARVEL. My bug, or theirs?
681 */
682
683 reg = __SHIFTIN(sc->sc_rftype, ATW_SYNCTL_RFTYPE_MASK);
684
685 switch (sc->sc_rftype) {
686 case ATW_RFTYPE_INTERSIL:
687 reg |= ATW_SYNCTL_CS1;
688 break;
689 case ATW_RFTYPE_RFMD:
690 reg |= ATW_SYNCTL_CS0;
691 break;
692 case ATW_RFTYPE_MARVEL:
693 break;
694 }
695
696 sc->sc_synctl_rd = reg | ATW_SYNCTL_RD;
697 sc->sc_synctl_wr = reg | ATW_SYNCTL_WR;
698
699 reg = __SHIFTIN(sc->sc_bbptype, ATW_BBPCTL_TYPE_MASK);
700
701 switch (sc->sc_bbptype) {
702 case ATW_BBPTYPE_INTERSIL:
703 reg |= ATW_BBPCTL_TWI;
704 break;
705 case ATW_BBPTYPE_RFMD:
706 reg |= ATW_BBPCTL_RF3KADDR_ADDR | ATW_BBPCTL_NEGEDGE_DO |
707 ATW_BBPCTL_CCA_ACTLO;
708 break;
709 case ATW_BBPTYPE_MARVEL:
710 break;
711 case ATW_C_BBPTYPE_RFMD:
712 printf("%s: ADM8211C MAC/RFMD BBP not supported yet.\n",
713 sc->sc_dev.dv_xname);
714 break;
715 }
716
717 sc->sc_bbpctl_wr = reg | ATW_BBPCTL_WR;
718 sc->sc_bbpctl_rd = reg | ATW_BBPCTL_RD;
719
720 /*
721 * From this point forward, the attachment cannot fail. A failure
722 * before this point releases all resources that may have been
723 * allocated.
724 */
725 sc->sc_flags |= ATWF_ATTACHED /* | ATWF_RTSCTS */;
726
727 ATW_DPRINTF((" SROM MAC %04x%04x%04x",
728 htole16(sc->sc_srom[ATW_SR_MAC00]),
729 htole16(sc->sc_srom[ATW_SR_MAC01]),
730 htole16(sc->sc_srom[ATW_SR_MAC10])));
731
732 srom_major = __SHIFTOUT(sc->sc_srom[ATW_SR_FORMAT_VERSION],
733 ATW_SR_MAJOR_MASK);
734
735 if (srom_major < 2)
736 sc->sc_rf3000_options1 = 0;
737 else if (sc->sc_rev == ATW_REVISION_BA) {
738 sc->sc_rf3000_options1 =
739 __SHIFTOUT(sc->sc_srom[ATW_SR_CR28_CR03],
740 ATW_SR_CR28_MASK);
741 } else
742 sc->sc_rf3000_options1 = 0;
743
744 sc->sc_rf3000_options2 = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],
745 ATW_SR_CR29_MASK);
746
747 country_code = __SHIFTOUT(sc->sc_srom[ATW_SR_CTRY_CR29],
748 ATW_SR_CTRY_MASK);
749
750 #define ADD_CHANNEL(_ic, _chan) do { \
751 _ic->ic_channels[_chan].ic_flags = IEEE80211_CHAN_B; \
752 _ic->ic_channels[_chan].ic_freq = \
753 ieee80211_ieee2mhz(_chan, _ic->ic_channels[_chan].ic_flags);\
754 } while (0)
755
756 /* Find available channels */
757 switch (country_code) {
758 case COUNTRY_MMK2: /* 1-14 */
759 ADD_CHANNEL(ic, 14);
760 /*FALLTHROUGH*/
761 case COUNTRY_ETSI: /* 1-13 */
762 for (i = 1; i <= 13; i++)
763 ADD_CHANNEL(ic, i);
764 break;
765 case COUNTRY_FCC: /* 1-11 */
766 case COUNTRY_IC: /* 1-11 */
767 for (i = 1; i <= 11; i++)
768 ADD_CHANNEL(ic, i);
769 break;
770 case COUNTRY_MMK: /* 14 */
771 ADD_CHANNEL(ic, 14);
772 break;
773 case COUNTRY_FRANCE: /* 10-13 */
774 for (i = 10; i <= 13; i++)
775 ADD_CHANNEL(ic, i);
776 break;
777 default: /* assume channels 10-11 */
778 case COUNTRY_SPAIN: /* 10-11 */
779 for (i = 10; i <= 11; i++)
780 ADD_CHANNEL(ic, i);
781 break;
782 }
783
784 /* Read the MAC address. */
785 reg = ATW_READ(sc, ATW_PAR0);
786 ic->ic_myaddr[0] = __SHIFTOUT(reg, ATW_PAR0_PAB0_MASK);
787 ic->ic_myaddr[1] = __SHIFTOUT(reg, ATW_PAR0_PAB1_MASK);
788 ic->ic_myaddr[2] = __SHIFTOUT(reg, ATW_PAR0_PAB2_MASK);
789 ic->ic_myaddr[3] = __SHIFTOUT(reg, ATW_PAR0_PAB3_MASK);
790 reg = ATW_READ(sc, ATW_PAR1);
791 ic->ic_myaddr[4] = __SHIFTOUT(reg, ATW_PAR1_PAB4_MASK);
792 ic->ic_myaddr[5] = __SHIFTOUT(reg, ATW_PAR1_PAB5_MASK);
793
794 if (IEEE80211_ADDR_EQ(ic->ic_myaddr, empty_macaddr)) {
795 printf(" could not get mac address, attach failed\n");
796 return;
797 }
798
799 printf(" 802.11 address %s\n", ether_sprintf(ic->ic_myaddr));
800
801 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
802 ifp->if_softc = sc;
803 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST |
804 IFF_NOTRAILERS;
805 ifp->if_ioctl = atw_ioctl;
806 ifp->if_start = atw_start;
807 ifp->if_watchdog = atw_watchdog;
808 ifp->if_init = atw_init;
809 ifp->if_stop = atw_stop;
810 IFQ_SET_READY(&ifp->if_snd);
811
812 ic->ic_ifp = ifp;
813 ic->ic_phytype = IEEE80211_T_DS;
814 ic->ic_opmode = IEEE80211_M_STA;
815 ic->ic_caps = IEEE80211_C_PMGT | IEEE80211_C_IBSS |
816 IEEE80211_C_HOSTAP | IEEE80211_C_MONITOR;
817
818 nrate = 0;
819 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 2;
820 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 4;
821 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 11;
822 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_rates[nrate++] = 22;
823 ic->ic_sup_rates[IEEE80211_MODE_11B].rs_nrates = nrate;
824
825 /*
826 * Call MI attach routines.
827 */
828
829 if_attach(ifp);
830 ieee80211_ifattach(ic);
831
832 sc->sc_newstate = ic->ic_newstate;
833 ic->ic_newstate = atw_newstate;
834
835 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
836 ic->ic_recv_mgmt = atw_recv_mgmt;
837
838 sc->sc_node_free = ic->ic_node_free;
839 ic->ic_node_free = atw_node_free;
840
841 sc->sc_node_alloc = ic->ic_node_alloc;
842 ic->ic_node_alloc = atw_node_alloc;
843
844 ic->ic_crypto.cs_key_delete = atw_key_delete;
845 ic->ic_crypto.cs_key_set = atw_key_set;
846 ic->ic_crypto.cs_key_update_begin = atw_key_update_begin;
847 ic->ic_crypto.cs_key_update_end = atw_key_update_end;
848
849 /* possibly we should fill in our own sc_send_prresp, since
850 * the ADM8211 is probably sending probe responses in ad hoc
851 * mode.
852 */
853
854 /* complete initialization */
855 ieee80211_media_init(ic, atw_media_change, ieee80211_media_status);
856 callout_init(&sc->sc_scan_ch);
857
858 #if NBPFILTER > 0
859 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
860 sizeof(struct ieee80211_frame) + 64, &sc->sc_radiobpf);
861 #endif
862
863 /*
864 * Make sure the interface is shutdown during reboot.
865 */
866 sc->sc_sdhook = shutdownhook_establish(atw_shutdown, sc);
867 if (sc->sc_sdhook == NULL)
868 printf("%s: WARNING: unable to establish shutdown hook\n",
869 sc->sc_dev.dv_xname);
870
871 /*
872 * Add a suspend hook to make sure we come back up after a
873 * resume.
874 */
875 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname,
876 atw_power, sc);
877 if (sc->sc_powerhook == NULL)
878 printf("%s: WARNING: unable to establish power hook\n",
879 sc->sc_dev.dv_xname);
880
881 memset(&sc->sc_rxtapu, 0, sizeof(sc->sc_rxtapu));
882 sc->sc_rxtap.ar_ihdr.it_len = htole16(sizeof(sc->sc_rxtapu));
883 sc->sc_rxtap.ar_ihdr.it_present = htole32(ATW_RX_RADIOTAP_PRESENT);
884
885 memset(&sc->sc_txtapu, 0, sizeof(sc->sc_txtapu));
886 sc->sc_txtap.at_ihdr.it_len = htole16(sizeof(sc->sc_txtapu));
887 sc->sc_txtap.at_ihdr.it_present = htole32(ATW_TX_RADIOTAP_PRESENT);
888
889 ieee80211_announce(ic);
890 return;
891
892 /*
893 * Free any resources we've allocated during the failed attach
894 * attempt. Do this in reverse order and fall through.
895 */
896 fail_5:
897 for (i = 0; i < ATW_NRXDESC; i++) {
898 if (sc->sc_rxsoft[i].rxs_dmamap == NULL)
899 continue;
900 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rxsoft[i].rxs_dmamap);
901 }
902 fail_4:
903 for (i = 0; i < ATW_TXQUEUELEN; i++) {
904 if (sc->sc_txsoft[i].txs_dmamap == NULL)
905 continue;
906 bus_dmamap_destroy(sc->sc_dmat, sc->sc_txsoft[i].txs_dmamap);
907 }
908 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
909 fail_3:
910 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
911 fail_2:
912 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
913 sizeof(struct atw_control_data));
914 fail_1:
915 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg);
916 fail_0:
917 return;
918 }
919
920 static struct ieee80211_node *
921 atw_node_alloc(struct ieee80211_node_table *nt)
922 {
923 struct atw_softc *sc = (struct atw_softc *)nt->nt_ic->ic_ifp->if_softc;
924 struct ieee80211_node *ni = (*sc->sc_node_alloc)(nt);
925
926 DPRINTF(sc, ("%s: alloc node %p\n", sc->sc_dev.dv_xname, ni));
927 return ni;
928 }
929
930 static void
931 atw_node_free(struct ieee80211_node *ni)
932 {
933 struct atw_softc *sc = (struct atw_softc *)ni->ni_ic->ic_ifp->if_softc;
934
935 DPRINTF(sc, ("%s: freeing node %p %s\n", sc->sc_dev.dv_xname, ni,
936 ether_sprintf(ni->ni_bssid)));
937 (*sc->sc_node_free)(ni);
938 }
939
940
941 static void
942 atw_test1_reset(struct atw_softc *sc)
943 {
944 switch (sc->sc_rev) {
945 case ATW_REVISION_BA:
946 if (1 /* XXX condition on transceiver type */) {
947 ATW_SET(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MONITOR);
948 }
949 break;
950 case ATW_REVISION_CA:
951 ATW_CLR(sc, ATW_TEST1, ATW_TEST1_TESTMODE_MASK);
952 break;
953 default:
954 break;
955 }
956 }
957
958 /*
959 * atw_reset:
960 *
961 * Perform a soft reset on the ADM8211.
962 */
963 void
964 atw_reset(struct atw_softc *sc)
965 {
966 int i;
967 uint32_t lpc;
968
969 ATW_WRITE(sc, ATW_NAR, 0x0);
970 DELAY(atw_nar_delay);
971
972 /* Reference driver has a cryptic remark indicating that this might
973 * power-on the chip. I know that it turns off power-saving....
974 */
975 ATW_WRITE(sc, ATW_FRCTL, 0x0);
976
977 ATW_WRITE(sc, ATW_PAR, ATW_PAR_SWR);
978
979 for (i = 0; i < 50000 / atw_pseudo_milli; i++) {
980 if ((ATW_READ(sc, ATW_PAR) & ATW_PAR_SWR) == 0)
981 break;
982 DELAY(atw_pseudo_milli);
983 }
984
985 /* ... and then pause 100ms longer for good measure. */
986 DELAY(atw_magic_delay1);
987
988 DPRINTF2(sc, ("%s: atw_reset %d iterations\n", sc->sc_dev.dv_xname, i));
989
990 if (ATW_ISSET(sc, ATW_PAR, ATW_PAR_SWR))
991 printf("%s: reset failed to complete\n", sc->sc_dev.dv_xname);
992
993 /*
994 * Initialize the PCI Access Register.
995 */
996 sc->sc_busmode = ATW_PAR_PBL_8DW;
997
998 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode);
999 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname,
1000 ATW_READ(sc, ATW_PAR), sc->sc_busmode));
1001
1002 atw_test1_reset(sc);
1003
1004 /* Turn off maximum power saving, etc. */
1005 ATW_WRITE(sc, ATW_FRCTL, 0x0);
1006
1007 DELAY(atw_magic_delay2);
1008
1009 /* Recall EEPROM. */
1010 ATW_SET(sc, ATW_TEST0, ATW_TEST0_EPRLD);
1011
1012 DELAY(atw_magic_delay4);
1013
1014 lpc = ATW_READ(sc, ATW_LPC);
1015
1016 DPRINTF(sc, ("%s: ATW_LPC %#08x\n", __func__, lpc));
1017
1018 /* A reset seems to affect the SRAM contents, so put them into
1019 * a known state.
1020 */
1021 atw_clear_sram(sc);
1022
1023 memset(sc->sc_bssid, 0xff, sizeof(sc->sc_bssid));
1024 }
1025
1026 static void
1027 atw_clear_sram(struct atw_softc *sc)
1028 {
1029 memset(sc->sc_sram, 0, sizeof(sc->sc_sram));
1030 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
1031 /* XXX not for revision 0x20. */
1032 atw_write_sram(sc, 0, sc->sc_sram, sc->sc_sramlen);
1033 }
1034
1035 /* TBD atw_init
1036 *
1037 * set MAC based on ic->ic_bss->myaddr
1038 * write WEP keys
1039 * set TX rate
1040 */
1041
1042 /* Tell the ADM8211 to raise ATW_INTR_LINKOFF if 7 beacon intervals pass
1043 * without receiving a beacon with the preferred BSSID & SSID.
1044 * atw_write_bssid & atw_write_ssid set the BSSID & SSID.
1045 */
1046 static void
1047 atw_wcsr_init(struct atw_softc *sc)
1048 {
1049 uint32_t wcsr;
1050
1051 wcsr = ATW_READ(sc, ATW_WCSR);
1052 wcsr &= ~(ATW_WCSR_BLN_MASK|ATW_WCSR_LSOE|ATW_WCSR_MPRE|ATW_WCSR_LSOE);
1053 wcsr |= __SHIFTIN(7, ATW_WCSR_BLN_MASK);
1054 ATW_WRITE(sc, ATW_WCSR, wcsr); /* XXX resets wake-up status bits */
1055
1056 DPRINTF(sc, ("%s: %s reg[WCSR] = %08x\n",
1057 sc->sc_dev.dv_xname, __func__, ATW_READ(sc, ATW_WCSR)));
1058 }
1059
1060 /* Turn off power management. Set Rx store-and-forward mode. */
1061 static void
1062 atw_cmdr_init(struct atw_softc *sc)
1063 {
1064 uint32_t cmdr;
1065 cmdr = ATW_READ(sc, ATW_CMDR);
1066 cmdr &= ~ATW_CMDR_APM;
1067 cmdr |= ATW_CMDR_RTE;
1068 cmdr &= ~ATW_CMDR_DRT_MASK;
1069 cmdr |= ATW_CMDR_DRT_SF;
1070
1071 ATW_WRITE(sc, ATW_CMDR, cmdr);
1072 }
1073
1074 static void
1075 atw_tofs2_init(struct atw_softc *sc)
1076 {
1077 uint32_t tofs2;
1078 /* XXX this magic can probably be figured out from the RFMD docs */
1079 #ifndef ATW_REFSLAVE
1080 tofs2 = __SHIFTIN(4, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
1081 __SHIFTIN(13, ATW_TOFS2_PWR0PAPE_MASK) | /* 13 us */
1082 __SHIFTIN(8, ATW_TOFS2_PWR1PAPE_MASK) | /* 8 us */
1083 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
1084 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
1085 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
1086 __SHIFTIN(4, ATW_TOFS2_PWR1PE2_MASK) | /* 4 us */
1087 __SHIFTIN(5, ATW_TOFS2_PWR0TXPE_MASK); /* 5 us */
1088 #else
1089 /* XXX new magic from reference driver source */
1090 tofs2 = __SHIFTIN(8, ATW_TOFS2_PWR1UP_MASK) | /* 8 ms = 4 * 2 ms */
1091 __SHIFTIN(8, ATW_TOFS2_PWR0PAPE_MASK) | /* 8 us */
1092 __SHIFTIN(1, ATW_TOFS2_PWR1PAPE_MASK) | /* 1 us */
1093 __SHIFTIN(5, ATW_TOFS2_PWR0TRSW_MASK) | /* 5 us */
1094 __SHIFTIN(12, ATW_TOFS2_PWR1TRSW_MASK) | /* 12 us */
1095 __SHIFTIN(13, ATW_TOFS2_PWR0PE2_MASK) | /* 13 us */
1096 __SHIFTIN(1, ATW_TOFS2_PWR1PE2_MASK) | /* 1 us */
1097 __SHIFTIN(8, ATW_TOFS2_PWR0TXPE_MASK); /* 8 us */
1098 #endif
1099 ATW_WRITE(sc, ATW_TOFS2, tofs2);
1100 }
1101
1102 static void
1103 atw_nar_init(struct atw_softc *sc)
1104 {
1105 ATW_WRITE(sc, ATW_NAR, ATW_NAR_SF|ATW_NAR_PB);
1106 }
1107
1108 static void
1109 atw_txlmt_init(struct atw_softc *sc)
1110 {
1111 ATW_WRITE(sc, ATW_TXLMT, __SHIFTIN(512, ATW_TXLMT_MTMLT_MASK) |
1112 __SHIFTIN(1, ATW_TXLMT_SRTYLIM_MASK));
1113 }
1114
1115 static void
1116 atw_test1_init(struct atw_softc *sc)
1117 {
1118 uint32_t test1;
1119
1120 test1 = ATW_READ(sc, ATW_TEST1);
1121 test1 &= ~(ATW_TEST1_DBGREAD_MASK|ATW_TEST1_CONTROL);
1122 /* XXX magic 0x1 */
1123 test1 |= __SHIFTIN(0x1, ATW_TEST1_DBGREAD_MASK) | ATW_TEST1_CONTROL;
1124 ATW_WRITE(sc, ATW_TEST1, test1);
1125 }
1126
1127 static void
1128 atw_rf_reset(struct atw_softc *sc)
1129 {
1130 /* XXX this resets an Intersil RF front-end? */
1131 /* TBD condition on Intersil RFType? */
1132 ATW_WRITE(sc, ATW_SYNRF, ATW_SYNRF_INTERSIL_EN);
1133 DELAY(atw_rf_delay1);
1134 ATW_WRITE(sc, ATW_SYNRF, 0);
1135 DELAY(atw_rf_delay2);
1136 }
1137
1138 /* Set 16 TU max duration for the contention-free period (CFP). */
1139 static void
1140 atw_cfp_init(struct atw_softc *sc)
1141 {
1142 uint32_t cfpp;
1143
1144 cfpp = ATW_READ(sc, ATW_CFPP);
1145 cfpp &= ~ATW_CFPP_CFPMD;
1146 cfpp |= __SHIFTIN(16, ATW_CFPP_CFPMD);
1147 ATW_WRITE(sc, ATW_CFPP, cfpp);
1148 }
1149
1150 static void
1151 atw_tofs0_init(struct atw_softc *sc)
1152 {
1153 /* XXX I guess that the Cardbus clock is 22 MHz?
1154 * I am assuming that the role of ATW_TOFS0_USCNT is
1155 * to divide the bus clock to get a 1 MHz clock---the datasheet is not
1156 * very clear on this point. It says in the datasheet that it is
1157 * possible for the ADM8211 to accommodate bus speeds between 22 MHz
1158 * and 33 MHz; maybe this is the way? I see a binary-only driver write
1159 * these values. These values are also the power-on default.
1160 */
1161 ATW_WRITE(sc, ATW_TOFS0,
1162 __SHIFTIN(22, ATW_TOFS0_USCNT_MASK) |
1163 ATW_TOFS0_TUCNT_MASK /* set all bits in TUCNT */);
1164 }
1165
1166 /* Initialize interframe spacing: 802.11b slot time, SIFS, DIFS, EIFS. */
1167 static void
1168 atw_ifs_init(struct atw_softc *sc)
1169 {
1170 uint32_t ifst;
1171 /* XXX EIFS=0x64, SIFS=110 are used by the reference driver.
1172 * Go figure.
1173 */
1174 ifst = __SHIFTIN(IEEE80211_DUR_DS_SLOT, ATW_IFST_SLOT_MASK) |
1175 __SHIFTIN(22 * 5 /* IEEE80211_DUR_DS_SIFS */ /* # of 22 MHz cycles */,
1176 ATW_IFST_SIFS_MASK) |
1177 __SHIFTIN(IEEE80211_DUR_DS_DIFS, ATW_IFST_DIFS_MASK) |
1178 __SHIFTIN(0x64 /* IEEE80211_DUR_DS_EIFS */, ATW_IFST_EIFS_MASK);
1179
1180 ATW_WRITE(sc, ATW_IFST, ifst);
1181 }
1182
1183 static void
1184 atw_response_times_init(struct atw_softc *sc)
1185 {
1186 /* XXX More magic. Relates to ACK timing? The datasheet seems to
1187 * indicate that the MAC expects at least SIFS + MIRT microseconds
1188 * to pass after it transmits a frame that requires a response;
1189 * it waits at most SIFS + MART microseconds for the response.
1190 * Surely this is not the ACK timeout?
1191 */
1192 ATW_WRITE(sc, ATW_RSPT, __SHIFTIN(0xffff, ATW_RSPT_MART_MASK) |
1193 __SHIFTIN(0xff, ATW_RSPT_MIRT_MASK));
1194 }
1195
1196 /* Set up the MMI read/write addresses for the baseband. The Tx/Rx
1197 * engines read and write baseband registers after Rx and before
1198 * Tx, respectively.
1199 */
1200 static void
1201 atw_bbp_io_init(struct atw_softc *sc)
1202 {
1203 uint32_t mmiraddr2;
1204
1205 /* XXX The reference driver does this, but is it *really*
1206 * necessary?
1207 */
1208 switch (sc->sc_rev) {
1209 case ATW_REVISION_AB:
1210 case ATW_REVISION_AF:
1211 mmiraddr2 = 0x0;
1212 break;
1213 default:
1214 mmiraddr2 = ATW_READ(sc, ATW_MMIRADDR2);
1215 mmiraddr2 &=
1216 ~(ATW_MMIRADDR2_PROREXT|ATW_MMIRADDR2_PRORLEN_MASK);
1217 break;
1218 }
1219
1220 switch (sc->sc_bbptype) {
1221 case ATW_BBPTYPE_INTERSIL:
1222 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_INTERSIL);
1223 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_INTERSIL);
1224 mmiraddr2 |= ATW_MMIRADDR2_INTERSIL;
1225 break;
1226 case ATW_BBPTYPE_MARVEL:
1227 /* TBD find out the Marvel settings. */
1228 break;
1229 case ATW_BBPTYPE_RFMD:
1230 default:
1231 ATW_WRITE(sc, ATW_MMIWADDR, ATW_MMIWADDR_RFMD);
1232 ATW_WRITE(sc, ATW_MMIRADDR1, ATW_MMIRADDR1_RFMD);
1233 mmiraddr2 |= ATW_MMIRADDR2_RFMD;
1234 break;
1235 }
1236 ATW_WRITE(sc, ATW_MMIRADDR2, mmiraddr2);
1237 ATW_WRITE(sc, ATW_MACTEST, ATW_MACTEST_MMI_USETXCLK);
1238 }
1239
1240 /*
1241 * atw_init: [ ifnet interface function ]
1242 *
1243 * Initialize the interface. Must be called at splnet().
1244 */
1245 int
1246 atw_init(struct ifnet *ifp)
1247 {
1248 struct atw_softc *sc = ifp->if_softc;
1249 struct ieee80211com *ic = &sc->sc_ic;
1250 struct atw_txsoft *txs;
1251 struct atw_rxsoft *rxs;
1252 int i, error = 0;
1253
1254 if ((error = atw_enable(sc)) != 0)
1255 goto out;
1256
1257 /*
1258 * Cancel any pending I/O. This also resets.
1259 */
1260 atw_stop(ifp, 0);
1261
1262 DPRINTF(sc, ("%s: channel %d freq %d flags 0x%04x\n",
1263 __func__, ieee80211_chan2ieee(ic, ic->ic_curchan),
1264 ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags));
1265
1266 atw_wcsr_init(sc);
1267
1268 atw_cmdr_init(sc);
1269
1270 /* Set data rate for PLCP Signal field, 1Mbps = 10 x 100Kb/s.
1271 *
1272 * XXX Set transmit power for ATIM, RTS, Beacon.
1273 */
1274 ATW_WRITE(sc, ATW_PLCPHD, __SHIFTIN(10, ATW_PLCPHD_SIGNAL_MASK) |
1275 __SHIFTIN(0xb0, ATW_PLCPHD_SERVICE_MASK));
1276
1277 atw_tofs2_init(sc);
1278
1279 atw_nar_init(sc);
1280
1281 atw_txlmt_init(sc);
1282
1283 atw_test1_init(sc);
1284
1285 atw_rf_reset(sc);
1286
1287 atw_cfp_init(sc);
1288
1289 atw_tofs0_init(sc);
1290
1291 atw_ifs_init(sc);
1292
1293 /* XXX Fall asleep after one second of inactivity.
1294 * XXX A frame may only dribble in for 65536us.
1295 */
1296 ATW_WRITE(sc, ATW_RMD,
1297 __SHIFTIN(1, ATW_RMD_PCNT) | __SHIFTIN(0xffff, ATW_RMD_RMRD_MASK));
1298
1299 atw_response_times_init(sc);
1300
1301 atw_bbp_io_init(sc);
1302
1303 ATW_WRITE(sc, ATW_STSR, 0xffffffff);
1304
1305 if ((error = atw_rf3000_init(sc)) != 0)
1306 goto out;
1307
1308 ATW_WRITE(sc, ATW_PAR, sc->sc_busmode);
1309 DPRINTF(sc, ("%s: ATW_PAR %08x busmode %08x\n", sc->sc_dev.dv_xname,
1310 ATW_READ(sc, ATW_PAR), sc->sc_busmode));
1311
1312 /*
1313 * Initialize the transmit descriptor ring.
1314 */
1315 memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
1316 for (i = 0; i < ATW_NTXDESC; i++) {
1317 sc->sc_txdescs[i].at_ctl = 0;
1318 /* no transmit chaining */
1319 sc->sc_txdescs[i].at_flags = 0 /* ATW_TXFLAG_TCH */;
1320 sc->sc_txdescs[i].at_buf2 =
1321 htole32(ATW_CDTXADDR(sc, ATW_NEXTTX(i)));
1322 }
1323 /* use ring mode */
1324 sc->sc_txdescs[ATW_NTXDESC - 1].at_flags |= htole32(ATW_TXFLAG_TER);
1325 ATW_CDTXSYNC(sc, 0, ATW_NTXDESC,
1326 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1327 sc->sc_txfree = ATW_NTXDESC;
1328 sc->sc_txnext = 0;
1329
1330 /*
1331 * Initialize the transmit job descriptors.
1332 */
1333 SIMPLEQ_INIT(&sc->sc_txfreeq);
1334 SIMPLEQ_INIT(&sc->sc_txdirtyq);
1335 for (i = 0; i < ATW_TXQUEUELEN; i++) {
1336 txs = &sc->sc_txsoft[i];
1337 txs->txs_mbuf = NULL;
1338 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1339 }
1340
1341 /*
1342 * Initialize the receive descriptor and receive job
1343 * descriptor rings.
1344 */
1345 for (i = 0; i < ATW_NRXDESC; i++) {
1346 rxs = &sc->sc_rxsoft[i];
1347 if (rxs->rxs_mbuf == NULL) {
1348 if ((error = atw_add_rxbuf(sc, i)) != 0) {
1349 printf("%s: unable to allocate or map rx "
1350 "buffer %d, error = %d\n",
1351 sc->sc_dev.dv_xname, i, error);
1352 /*
1353 * XXX Should attempt to run with fewer receive
1354 * XXX buffers instead of just failing.
1355 */
1356 atw_rxdrain(sc);
1357 goto out;
1358 }
1359 } else
1360 ATW_INIT_RXDESC(sc, i);
1361 }
1362 sc->sc_rxptr = 0;
1363
1364 /*
1365 * Initialize the interrupt mask and enable interrupts.
1366 */
1367 /* normal interrupts */
1368 sc->sc_inten = ATW_INTR_TCI | ATW_INTR_TDU | ATW_INTR_RCI |
1369 ATW_INTR_NISS | ATW_INTR_LINKON | ATW_INTR_BCNTC;
1370
1371 /* abnormal interrupts */
1372 sc->sc_inten |= ATW_INTR_TPS | ATW_INTR_TLT | ATW_INTR_TRT |
1373 ATW_INTR_TUF | ATW_INTR_RDU | ATW_INTR_RPS | ATW_INTR_AISS |
1374 ATW_INTR_FBE | ATW_INTR_LINKOFF | ATW_INTR_TSFTF | ATW_INTR_TSCZ;
1375
1376 sc->sc_linkint_mask = ATW_INTR_LINKON | ATW_INTR_LINKOFF |
1377 ATW_INTR_BCNTC | ATW_INTR_TSFTF | ATW_INTR_TSCZ;
1378 sc->sc_rxint_mask = ATW_INTR_RCI | ATW_INTR_RDU;
1379 sc->sc_txint_mask = ATW_INTR_TCI | ATW_INTR_TUF | ATW_INTR_TLT |
1380 ATW_INTR_TRT;
1381
1382 sc->sc_linkint_mask &= sc->sc_inten;
1383 sc->sc_rxint_mask &= sc->sc_inten;
1384 sc->sc_txint_mask &= sc->sc_inten;
1385
1386 ATW_WRITE(sc, ATW_IER, sc->sc_inten);
1387 ATW_WRITE(sc, ATW_STSR, 0xffffffff);
1388
1389 DPRINTF(sc, ("%s: ATW_IER %08x, inten %08x\n",
1390 sc->sc_dev.dv_xname, ATW_READ(sc, ATW_IER), sc->sc_inten));
1391
1392 /*
1393 * Give the transmit and receive rings to the ADM8211.
1394 */
1395 ATW_WRITE(sc, ATW_RDB, ATW_CDRXADDR(sc, sc->sc_rxptr));
1396 ATW_WRITE(sc, ATW_TDBD, ATW_CDTXADDR(sc, sc->sc_txnext));
1397
1398 sc->sc_txthresh = 0;
1399 sc->sc_opmode = ATW_NAR_SR | ATW_NAR_ST |
1400 sc->sc_txth[sc->sc_txthresh].txth_opmode;
1401
1402 /* common 802.11 configuration */
1403 ic->ic_flags &= ~IEEE80211_F_IBSSON;
1404 switch (ic->ic_opmode) {
1405 case IEEE80211_M_STA:
1406 break;
1407 case IEEE80211_M_AHDEMO: /* XXX */
1408 case IEEE80211_M_IBSS:
1409 ic->ic_flags |= IEEE80211_F_IBSSON;
1410 /*FALLTHROUGH*/
1411 case IEEE80211_M_HOSTAP: /* XXX */
1412 break;
1413 case IEEE80211_M_MONITOR: /* XXX */
1414 break;
1415 }
1416
1417 switch (ic->ic_opmode) {
1418 case IEEE80211_M_AHDEMO:
1419 case IEEE80211_M_HOSTAP:
1420 #ifndef IEEE80211_NO_HOSTAP
1421 ic->ic_bss->ni_intval = ic->ic_lintval;
1422 ic->ic_bss->ni_rssi = 0;
1423 ic->ic_bss->ni_rstamp = 0;
1424 #endif /* !IEEE80211_NO_HOSTAP */
1425 break;
1426 default: /* XXX */
1427 break;
1428 }
1429
1430 sc->sc_wepctl = 0;
1431
1432 atw_write_ssid(sc);
1433 atw_write_sup_rates(sc);
1434 atw_write_wep(sc);
1435
1436 ic->ic_state = IEEE80211_S_INIT;
1437
1438 /*
1439 * Set the receive filter. This will start the transmit and
1440 * receive processes.
1441 */
1442 atw_filter_setup(sc);
1443
1444 /*
1445 * Start the receive process.
1446 */
1447 ATW_WRITE(sc, ATW_RDR, 0x1);
1448
1449 /*
1450 * Note that the interface is now running.
1451 */
1452 ifp->if_flags |= IFF_RUNNING;
1453 ifp->if_flags &= ~IFF_OACTIVE;
1454
1455 /* send no beacons, yet. */
1456 atw_start_beacon(sc, 0);
1457
1458 if (ic->ic_opmode == IEEE80211_M_MONITOR)
1459 error = ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1460 else
1461 error = ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1462 out:
1463 if (error) {
1464 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1465 sc->sc_tx_timer = 0;
1466 ifp->if_timer = 0;
1467 printf("%s: interface not running\n", sc->sc_dev.dv_xname);
1468 }
1469 #ifdef ATW_DEBUG
1470 atw_print_regs(sc, "end of init");
1471 #endif /* ATW_DEBUG */
1472
1473 return (error);
1474 }
1475
1476 /* enable == 1: host control of RF3000/Si4126 through ATW_SYNCTL.
1477 * 0: MAC control of RF3000/Si4126.
1478 *
1479 * Applies power, or selects RF front-end? Sets reset condition.
1480 *
1481 * TBD support non-RFMD BBP, non-SiLabs synth.
1482 */
1483 static void
1484 atw_bbp_io_enable(struct atw_softc *sc, int enable)
1485 {
1486 if (enable) {
1487 ATW_WRITE(sc, ATW_SYNRF,
1488 ATW_SYNRF_SELRF|ATW_SYNRF_PE1|ATW_SYNRF_PHYRST);
1489 DELAY(atw_bbp_io_enable_delay);
1490 } else {
1491 ATW_WRITE(sc, ATW_SYNRF, 0);
1492 DELAY(atw_bbp_io_disable_delay); /* shorter for some reason */
1493 }
1494 }
1495
1496 static int
1497 atw_tune(struct atw_softc *sc)
1498 {
1499 int rc;
1500 u_int chan;
1501 struct ieee80211com *ic = &sc->sc_ic;
1502
1503 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
1504 if (chan == IEEE80211_CHAN_ANY)
1505 panic("%s: chan == IEEE80211_CHAN_ANY\n", __func__);
1506
1507 if (chan == sc->sc_cur_chan)
1508 return 0;
1509
1510 DPRINTF(sc, ("%s: chan %d -> %d\n", sc->sc_dev.dv_xname,
1511 sc->sc_cur_chan, chan));
1512
1513 atw_idle(sc, ATW_NAR_SR|ATW_NAR_ST);
1514
1515 atw_si4126_tune(sc, chan);
1516 if ((rc = atw_rf3000_tune(sc, chan)) != 0)
1517 printf("%s: failed to tune channel %d\n", sc->sc_dev.dv_xname,
1518 chan);
1519
1520 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
1521 DELAY(atw_nar_delay);
1522 ATW_WRITE(sc, ATW_RDR, 0x1);
1523
1524 if (rc == 0)
1525 sc->sc_cur_chan = chan;
1526
1527 return rc;
1528 }
1529
1530 #ifdef ATW_SYNDEBUG
1531 static void
1532 atw_si4126_print(struct atw_softc *sc)
1533 {
1534 struct ifnet *ifp = &sc->sc_if;
1535 u_int addr, val;
1536
1537 val = 0;
1538
1539 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0)
1540 return;
1541
1542 for (addr = 0; addr <= 8; addr++) {
1543 printf("%s: synth[%d] = ", sc->sc_dev.dv_xname, addr);
1544 if (atw_si4126_read(sc, addr, &val) == 0) {
1545 printf("<unknown> (quitting print-out)\n");
1546 break;
1547 }
1548 printf("%05x\n", val);
1549 }
1550 }
1551 #endif /* ATW_SYNDEBUG */
1552
1553 /* Tune to channel chan by adjusting the Si4126 RF/IF synthesizer.
1554 *
1555 * The RF/IF synthesizer produces two reference frequencies for
1556 * the RF2948B transceiver. The first frequency the RF2948B requires
1557 * is two times the so-called "intermediate frequency" (IF). Since
1558 * a SAW filter on the radio fixes the IF at 374 MHz, I program the
1559 * Si4126 to generate IF LO = 374 MHz x 2 = 748 MHz. The second
1560 * frequency required by the transceiver is the radio frequency
1561 * (RF). This is a superheterodyne transceiver; for f(chan) the
1562 * center frequency of the channel we are tuning, RF = f(chan) -
1563 * IF.
1564 *
1565 * XXX I am told by SiLabs that the Si4126 will accept a broader range
1566 * of XIN than the 2-25 MHz mentioned by the datasheet, even *without*
1567 * XINDIV2 = 1. I've tried this (it is necessary to double R) and it
1568 * works, but I have still programmed for XINDIV2 = 1 to be safe.
1569 */
1570 static void
1571 atw_si4126_tune(struct atw_softc *sc, u_int chan)
1572 {
1573 u_int mhz;
1574 u_int R;
1575 u_int32_t gpio;
1576 u_int16_t gain;
1577
1578 #ifdef ATW_SYNDEBUG
1579 atw_si4126_print(sc);
1580 #endif /* ATW_SYNDEBUG */
1581
1582 if (chan == 14)
1583 mhz = 2484;
1584 else
1585 mhz = 2412 + 5 * (chan - 1);
1586
1587 /* Tune IF to 748 MHz to suit the IF LO input of the
1588 * RF2494B, which is 2 x IF. No need to set an IF divider
1589 * because an IF in 526 MHz - 952 MHz is allowed.
1590 *
1591 * XIN is 44.000 MHz, so divide it by two to get allowable
1592 * range of 2-25 MHz. SiLabs tells me that this is not
1593 * strictly necessary.
1594 */
1595
1596 if (atw_xindiv2)
1597 R = 44;
1598 else
1599 R = 88;
1600
1601 /* Power-up RF, IF synthesizers. */
1602 atw_si4126_write(sc, SI4126_POWER,
1603 SI4126_POWER_PDIB|SI4126_POWER_PDRB);
1604
1605 /* set LPWR, too? */
1606 atw_si4126_write(sc, SI4126_MAIN,
1607 (atw_xindiv2) ? SI4126_MAIN_XINDIV2 : 0);
1608
1609 /* Set the phase-locked loop gain. If RF2 N > 2047, then
1610 * set KP2 to 1.
1611 *
1612 * REFDIF This is different from the reference driver, which
1613 * always sets SI4126_GAIN to 0.
1614 */
1615 gain = __SHIFTIN(((mhz - 374) > 2047) ? 1 : 0, SI4126_GAIN_KP2_MASK);
1616
1617 atw_si4126_write(sc, SI4126_GAIN, gain);
1618
1619 /* XIN = 44 MHz.
1620 *
1621 * If XINDIV2 = 1, IF = N/(2 * R) * XIN. I choose N = 1496,
1622 * R = 44 so that 1496/(2 * 44) * 44 MHz = 748 MHz.
1623 *
1624 * If XINDIV2 = 0, IF = N/R * XIN. I choose N = 1496, R = 88
1625 * so that 1496/88 * 44 MHz = 748 MHz.
1626 */
1627 atw_si4126_write(sc, SI4126_IFN, 1496);
1628
1629 atw_si4126_write(sc, SI4126_IFR, R);
1630
1631 #ifndef ATW_REFSLAVE
1632 /* Set RF1 arbitrarily. DO NOT configure RF1 after RF2, because
1633 * then RF1 becomes the active RF synthesizer, even on the Si4126,
1634 * which has no RF1!
1635 */
1636 atw_si4126_write(sc, SI4126_RF1R, R);
1637
1638 atw_si4126_write(sc, SI4126_RF1N, mhz - 374);
1639 #endif
1640
1641 /* N/R * XIN = RF. XIN = 44 MHz. We desire RF = mhz - IF,
1642 * where IF = 374 MHz. Let's divide XIN to 1 MHz. So R = 44.
1643 * Now let's multiply it to mhz. So mhz - IF = N.
1644 */
1645 atw_si4126_write(sc, SI4126_RF2R, R);
1646
1647 atw_si4126_write(sc, SI4126_RF2N, mhz - 374);
1648
1649 /* wait 100us from power-up for RF, IF to settle */
1650 DELAY(100);
1651
1652 gpio = ATW_READ(sc, ATW_GPIO);
1653 gpio &= ~(ATW_GPIO_EN_MASK|ATW_GPIO_O_MASK|ATW_GPIO_I_MASK);
1654 gpio |= __SHIFTIN(1, ATW_GPIO_EN_MASK);
1655
1656 if ((sc->sc_if.if_flags & IFF_LINK1) != 0 && chan != 14) {
1657 /* Set a Prism RF front-end to a special mode for channel 14?
1658 *
1659 * Apparently the SMC2635W needs this, although I don't think
1660 * it has a Prism RF.
1661 */
1662 gpio |= __SHIFTIN(1, ATW_GPIO_O_MASK);
1663 }
1664 ATW_WRITE(sc, ATW_GPIO, gpio);
1665
1666 #ifdef ATW_SYNDEBUG
1667 atw_si4126_print(sc);
1668 #endif /* ATW_SYNDEBUG */
1669 }
1670
1671 /* Baseline initialization of RF3000 BBP: set CCA mode and enable antenna
1672 * diversity.
1673 *
1674 * !!!
1675 * !!! Call this w/ Tx/Rx suspended, atw_idle(, ATW_NAR_ST|ATW_NAR_SR).
1676 * !!!
1677 */
1678 static int
1679 atw_rf3000_init(struct atw_softc *sc)
1680 {
1681 int rc = 0;
1682
1683 atw_bbp_io_enable(sc, 1);
1684
1685 /* CCA is acquisition sensitive */
1686 rc = atw_rf3000_write(sc, RF3000_CCACTL,
1687 __SHIFTIN(RF3000_CCACTL_MODE_BOTH, RF3000_CCACTL_MODE_MASK));
1688
1689 if (rc != 0)
1690 goto out;
1691
1692 /* enable diversity */
1693 rc = atw_rf3000_write(sc, RF3000_DIVCTL, RF3000_DIVCTL_ENABLE);
1694
1695 if (rc != 0)
1696 goto out;
1697
1698 /* sensible setting from a binary-only driver */
1699 rc = atw_rf3000_write(sc, RF3000_GAINCTL,
1700 __SHIFTIN(0x1d, RF3000_GAINCTL_TXVGC_MASK));
1701
1702 if (rc != 0)
1703 goto out;
1704
1705 /* magic from a binary-only driver */
1706 rc = atw_rf3000_write(sc, RF3000_LOGAINCAL,
1707 __SHIFTIN(0x38, RF3000_LOGAINCAL_CAL_MASK));
1708
1709 if (rc != 0)
1710 goto out;
1711
1712 rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, RF3000_HIGAINCAL_DSSSPAD);
1713
1714 if (rc != 0)
1715 goto out;
1716
1717 /* XXX Reference driver remarks that Abocom sets this to 50.
1718 * Meaning 0x50, I think.... 50 = 0x32, which would set a bit
1719 * in the "reserved" area of register RF3000_OPTIONS1.
1720 */
1721 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, sc->sc_rf3000_options1);
1722
1723 if (rc != 0)
1724 goto out;
1725
1726 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, sc->sc_rf3000_options2);
1727
1728 if (rc != 0)
1729 goto out;
1730
1731 out:
1732 atw_bbp_io_enable(sc, 0);
1733 return rc;
1734 }
1735
1736 #ifdef ATW_BBPDEBUG
1737 static void
1738 atw_rf3000_print(struct atw_softc *sc)
1739 {
1740 struct ifnet *ifp = &sc->sc_if;
1741 u_int addr, val;
1742
1743 if (atw_debug < 3 || (ifp->if_flags & IFF_DEBUG) == 0)
1744 return;
1745
1746 for (addr = 0x01; addr <= 0x15; addr++) {
1747 printf("%s: bbp[%d] = \n", sc->sc_dev.dv_xname, addr);
1748 if (atw_rf3000_read(sc, addr, &val) != 0) {
1749 printf("<unknown> (quitting print-out)\n");
1750 break;
1751 }
1752 printf("%08x\n", val);
1753 }
1754 }
1755 #endif /* ATW_BBPDEBUG */
1756
1757 /* Set the power settings on the BBP for channel `chan'. */
1758 static int
1759 atw_rf3000_tune(struct atw_softc *sc, u_int chan)
1760 {
1761 int rc = 0;
1762 u_int32_t reg;
1763 u_int16_t txpower, lpf_cutoff, lna_gs_thresh;
1764
1765 txpower = sc->sc_srom[ATW_SR_TXPOWER(chan)];
1766 lpf_cutoff = sc->sc_srom[ATW_SR_LPF_CUTOFF(chan)];
1767 lna_gs_thresh = sc->sc_srom[ATW_SR_LNA_GS_THRESH(chan)];
1768
1769 /* odd channels: LSB, even channels: MSB */
1770 if (chan % 2 == 1) {
1771 txpower &= 0xFF;
1772 lpf_cutoff &= 0xFF;
1773 lna_gs_thresh &= 0xFF;
1774 } else {
1775 txpower >>= 8;
1776 lpf_cutoff >>= 8;
1777 lna_gs_thresh >>= 8;
1778 }
1779
1780 #ifdef ATW_BBPDEBUG
1781 atw_rf3000_print(sc);
1782 #endif /* ATW_BBPDEBUG */
1783
1784 DPRINTF(sc, ("%s: chan %d txpower %02x, lpf_cutoff %02x, "
1785 "lna_gs_thresh %02x\n",
1786 sc->sc_dev.dv_xname, chan, txpower, lpf_cutoff, lna_gs_thresh));
1787
1788 atw_bbp_io_enable(sc, 1);
1789
1790 if ((rc = atw_rf3000_write(sc, RF3000_GAINCTL,
1791 __SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK))) != 0)
1792 goto out;
1793
1794 if ((rc = atw_rf3000_write(sc, RF3000_LOGAINCAL, lpf_cutoff)) != 0)
1795 goto out;
1796
1797 if ((rc = atw_rf3000_write(sc, RF3000_HIGAINCAL, lna_gs_thresh)) != 0)
1798 goto out;
1799
1800 rc = atw_rf3000_write(sc, RF3000_OPTIONS1, 0x0);
1801
1802 if (rc != 0)
1803 goto out;
1804
1805 rc = atw_rf3000_write(sc, RF3000_OPTIONS2, RF3000_OPTIONS2_LNAGS_DELAY);
1806
1807 if (rc != 0)
1808 goto out;
1809
1810 #ifdef ATW_BBPDEBUG
1811 atw_rf3000_print(sc);
1812 #endif /* ATW_BBPDEBUG */
1813
1814 out:
1815 atw_bbp_io_enable(sc, 0);
1816
1817 /* set beacon, rts, atim transmit power */
1818 reg = ATW_READ(sc, ATW_PLCPHD);
1819 reg &= ~ATW_PLCPHD_SERVICE_MASK;
1820 reg |= __SHIFTIN(__SHIFTIN(txpower, RF3000_GAINCTL_TXVGC_MASK),
1821 ATW_PLCPHD_SERVICE_MASK);
1822 ATW_WRITE(sc, ATW_PLCPHD, reg);
1823 DELAY(atw_plcphd_delay);
1824
1825 return rc;
1826 }
1827
1828 /* Write a register on the RF3000 baseband processor using the
1829 * registers provided by the ADM8211 for this purpose.
1830 *
1831 * Return 0 on success.
1832 */
1833 static int
1834 atw_rf3000_write(struct atw_softc *sc, u_int addr, u_int val)
1835 {
1836 u_int32_t reg;
1837 int i;
1838
1839 reg = sc->sc_bbpctl_wr |
1840 __SHIFTIN(val & 0xff, ATW_BBPCTL_DATA_MASK) |
1841 __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
1842
1843 for (i = 20000 / atw_pseudo_milli; --i >= 0; ) {
1844 ATW_WRITE(sc, ATW_BBPCTL, reg);
1845 DELAY(2 * atw_pseudo_milli);
1846 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_WR) == 0)
1847 break;
1848 }
1849
1850 if (i < 0) {
1851 printf("%s: BBPCTL still busy\n", sc->sc_dev.dv_xname);
1852 return ETIMEDOUT;
1853 }
1854 return 0;
1855 }
1856
1857 /* Read a register on the RF3000 baseband processor using the registers
1858 * the ADM8211 provides for this purpose.
1859 *
1860 * The 7-bit register address is addr. Record the 8-bit data in the register
1861 * in *val.
1862 *
1863 * Return 0 on success.
1864 *
1865 * XXX This does not seem to work. The ADM8211 must require more or
1866 * different magic to read the chip than to write it. Possibly some
1867 * of the magic I have derived from a binary-only driver concerns
1868 * the "chip address" (see the RF3000 manual).
1869 */
1870 #ifdef ATW_BBPDEBUG
1871 static int
1872 atw_rf3000_read(struct atw_softc *sc, u_int addr, u_int *val)
1873 {
1874 u_int32_t reg;
1875 int i;
1876
1877 for (i = 1000; --i >= 0; ) {
1878 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD|ATW_BBPCTL_WR) == 0)
1879 break;
1880 DELAY(100);
1881 }
1882
1883 if (i < 0) {
1884 printf("%s: start atw_rf3000_read, BBPCTL busy\n",
1885 sc->sc_dev.dv_xname);
1886 return ETIMEDOUT;
1887 }
1888
1889 reg = sc->sc_bbpctl_rd | __SHIFTIN(addr & 0x7f, ATW_BBPCTL_ADDR_MASK);
1890
1891 ATW_WRITE(sc, ATW_BBPCTL, reg);
1892
1893 for (i = 1000; --i >= 0; ) {
1894 DELAY(100);
1895 if (ATW_ISSET(sc, ATW_BBPCTL, ATW_BBPCTL_RD) == 0)
1896 break;
1897 }
1898
1899 ATW_CLR(sc, ATW_BBPCTL, ATW_BBPCTL_RD);
1900
1901 if (i < 0) {
1902 printf("%s: atw_rf3000_read wrote %08x; BBPCTL still busy\n",
1903 sc->sc_dev.dv_xname, reg);
1904 return ETIMEDOUT;
1905 }
1906 if (val != NULL)
1907 *val = __SHIFTOUT(reg, ATW_BBPCTL_DATA_MASK);
1908 return 0;
1909 }
1910 #endif /* ATW_BBPDEBUG */
1911
1912 /* Write a register on the Si4126 RF/IF synthesizer using the registers
1913 * provided by the ADM8211 for that purpose.
1914 *
1915 * val is 18 bits of data, and val is the 4-bit address of the register.
1916 *
1917 * Return 0 on success.
1918 */
1919 static void
1920 atw_si4126_write(struct atw_softc *sc, u_int addr, u_int val)
1921 {
1922 uint32_t bits, mask, reg;
1923 const int nbits = 22;
1924
1925 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0);
1926 KASSERT((val & ~__SHIFTOUT_MASK(SI4126_TWI_DATA_MASK)) == 0);
1927
1928 bits = __SHIFTIN(val, SI4126_TWI_DATA_MASK) |
1929 __SHIFTIN(addr, SI4126_TWI_ADDR_MASK);
1930
1931 reg = ATW_SYNRF_SELSYN;
1932 /* reference driver: reset Si4126 serial bus to initial
1933 * conditions?
1934 */
1935 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
1936 ATW_WRITE(sc, ATW_SYNRF, reg);
1937
1938 for (mask = __BIT(nbits - 1); mask != 0; mask >>= 1) {
1939 if ((bits & mask) != 0)
1940 reg |= ATW_SYNRF_SYNDATA;
1941 else
1942 reg &= ~ATW_SYNRF_SYNDATA;
1943 ATW_WRITE(sc, ATW_SYNRF, reg);
1944 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_SYNCLK);
1945 ATW_WRITE(sc, ATW_SYNRF, reg);
1946 }
1947 ATW_WRITE(sc, ATW_SYNRF, reg | ATW_SYNRF_LEIF);
1948 ATW_WRITE(sc, ATW_SYNRF, 0x0);
1949 }
1950
1951 /* Read 18-bit data from the 4-bit address addr in Si4126
1952 * RF synthesizer and write the data to *val. Return 0 on success.
1953 *
1954 * XXX This does not seem to work. The ADM8211 must require more or
1955 * different magic to read the chip than to write it.
1956 */
1957 #ifdef ATW_SYNDEBUG
1958 static int
1959 atw_si4126_read(struct atw_softc *sc, u_int addr, u_int *val)
1960 {
1961 u_int32_t reg;
1962 int i;
1963
1964 KASSERT((addr & ~__SHIFTOUT_MASK(SI4126_TWI_ADDR_MASK)) == 0);
1965
1966 for (i = 1000; --i >= 0; ) {
1967 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD|ATW_SYNCTL_WR) == 0)
1968 break;
1969 DELAY(100);
1970 }
1971
1972 if (i < 0) {
1973 printf("%s: start atw_si4126_read, SYNCTL busy\n",
1974 sc->sc_dev.dv_xname);
1975 return ETIMEDOUT;
1976 }
1977
1978 reg = sc->sc_synctl_rd | __SHIFTIN(addr, ATW_SYNCTL_DATA_MASK);
1979
1980 ATW_WRITE(sc, ATW_SYNCTL, reg);
1981
1982 for (i = 1000; --i >= 0; ) {
1983 DELAY(100);
1984 if (ATW_ISSET(sc, ATW_SYNCTL, ATW_SYNCTL_RD) == 0)
1985 break;
1986 }
1987
1988 ATW_CLR(sc, ATW_SYNCTL, ATW_SYNCTL_RD);
1989
1990 if (i < 0) {
1991 printf("%s: atw_si4126_read wrote %#08x, SYNCTL still busy\n",
1992 sc->sc_dev.dv_xname, reg);
1993 return ETIMEDOUT;
1994 }
1995 if (val != NULL)
1996 *val = __SHIFTOUT(ATW_READ(sc, ATW_SYNCTL),
1997 ATW_SYNCTL_DATA_MASK);
1998 return 0;
1999 }
2000 #endif /* ATW_SYNDEBUG */
2001
2002 /* XXX is the endianness correct? test. */
2003 #define atw_calchash(addr) \
2004 (ether_crc32_le((addr), IEEE80211_ADDR_LEN) & __BITS(5, 0))
2005
2006 /*
2007 * atw_filter_setup:
2008 *
2009 * Set the ADM8211's receive filter.
2010 */
2011 static void
2012 atw_filter_setup(struct atw_softc *sc)
2013 {
2014 struct ieee80211com *ic = &sc->sc_ic;
2015 struct ethercom *ec = &sc->sc_ec;
2016 struct ifnet *ifp = &sc->sc_if;
2017 int hash;
2018 u_int32_t hashes[2];
2019 struct ether_multi *enm;
2020 struct ether_multistep step;
2021
2022 /* According to comments in tlp_al981_filter_setup
2023 * (dev/ic/tulip.c) the ADMtek AL981 does not like for its
2024 * multicast filter to be set while it is running. Hopefully
2025 * the ADM8211 is not the same!
2026 */
2027 if ((ifp->if_flags & IFF_RUNNING) != 0)
2028 atw_idle(sc, ATW_NAR_SR);
2029
2030 sc->sc_opmode &= ~(ATW_NAR_PR|ATW_NAR_MM);
2031 ifp->if_flags &= ~IFF_ALLMULTI;
2032
2033 /* XXX in scan mode, do not filter packets. Maybe this is
2034 * unnecessary.
2035 */
2036 if (ic->ic_state == IEEE80211_S_SCAN ||
2037 (ifp->if_flags & IFF_PROMISC) != 0) {
2038 sc->sc_opmode |= ATW_NAR_PR;
2039 goto allmulti;
2040 }
2041
2042 hashes[0] = hashes[1] = 0x0;
2043
2044 /*
2045 * Program the 64-bit multicast hash filter.
2046 */
2047 ETHER_FIRST_MULTI(step, ec, enm);
2048 while (enm != NULL) {
2049 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
2050 ETHER_ADDR_LEN) != 0)
2051 goto allmulti;
2052
2053 hash = atw_calchash(enm->enm_addrlo);
2054 hashes[hash >> 5] |= 1 << (hash & 0x1f);
2055 ETHER_NEXT_MULTI(step, enm);
2056 sc->sc_opmode |= ATW_NAR_MM;
2057 }
2058 ifp->if_flags &= ~IFF_ALLMULTI;
2059 goto setit;
2060
2061 allmulti:
2062 sc->sc_opmode |= ATW_NAR_MM;
2063 ifp->if_flags |= IFF_ALLMULTI;
2064 hashes[0] = hashes[1] = 0xffffffff;
2065
2066 setit:
2067 ATW_WRITE(sc, ATW_MAR0, hashes[0]);
2068 ATW_WRITE(sc, ATW_MAR1, hashes[1]);
2069 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
2070 DELAY(atw_nar_delay);
2071 ATW_WRITE(sc, ATW_RDR, 0x1);
2072
2073 DPRINTF(sc, ("%s: ATW_NAR %08x opmode %08x\n", sc->sc_dev.dv_xname,
2074 ATW_READ(sc, ATW_NAR), sc->sc_opmode));
2075 }
2076
2077 /* Tell the ADM8211 our preferred BSSID. The ADM8211 must match
2078 * a beacon's BSSID and SSID against the preferred BSSID and SSID
2079 * before it will raise ATW_INTR_LINKON. When the ADM8211 receives
2080 * no beacon with the preferred BSSID and SSID in the number of
2081 * beacon intervals given in ATW_BPLI, then it raises ATW_INTR_LINKOFF.
2082 */
2083 static void
2084 atw_write_bssid(struct atw_softc *sc)
2085 {
2086 struct ieee80211com *ic = &sc->sc_ic;
2087 u_int8_t *bssid;
2088
2089 bssid = ic->ic_bss->ni_bssid;
2090
2091 ATW_WRITE(sc, ATW_BSSID0,
2092 __SHIFTIN(bssid[0], ATW_BSSID0_BSSIDB0_MASK) |
2093 __SHIFTIN(bssid[1], ATW_BSSID0_BSSIDB1_MASK) |
2094 __SHIFTIN(bssid[2], ATW_BSSID0_BSSIDB2_MASK) |
2095 __SHIFTIN(bssid[3], ATW_BSSID0_BSSIDB3_MASK));
2096
2097 ATW_WRITE(sc, ATW_ABDA1,
2098 (ATW_READ(sc, ATW_ABDA1) &
2099 ~(ATW_ABDA1_BSSIDB4_MASK|ATW_ABDA1_BSSIDB5_MASK)) |
2100 __SHIFTIN(bssid[4], ATW_ABDA1_BSSIDB4_MASK) |
2101 __SHIFTIN(bssid[5], ATW_ABDA1_BSSIDB5_MASK));
2102
2103 DPRINTF(sc, ("%s: BSSID %s -> ", sc->sc_dev.dv_xname,
2104 ether_sprintf(sc->sc_bssid)));
2105 DPRINTF(sc, ("%s\n", ether_sprintf(bssid)));
2106
2107 memcpy(sc->sc_bssid, bssid, sizeof(sc->sc_bssid));
2108 }
2109
2110 /* Write buflen bytes from buf to SRAM starting at the SRAM's ofs'th
2111 * 16-bit word.
2112 */
2113 static void
2114 atw_write_sram(struct atw_softc *sc, u_int ofs, u_int8_t *buf, u_int buflen)
2115 {
2116 u_int i;
2117 u_int8_t *ptr;
2118
2119 memcpy(&sc->sc_sram[ofs], buf, buflen);
2120
2121 KASSERT(ofs % 2 == 0 && buflen % 2 == 0);
2122
2123 KASSERT(buflen + ofs <= sc->sc_sramlen);
2124
2125 ptr = &sc->sc_sram[ofs];
2126
2127 for (i = 0; i < buflen; i += 2) {
2128 ATW_WRITE(sc, ATW_WEPCTL, ATW_WEPCTL_WR |
2129 __SHIFTIN((ofs + i) / 2, ATW_WEPCTL_TBLADD_MASK));
2130 DELAY(atw_writewep_delay);
2131
2132 ATW_WRITE(sc, ATW_WESK,
2133 __SHIFTIN((ptr[i + 1] << 8) | ptr[i], ATW_WESK_DATA_MASK));
2134 DELAY(atw_writewep_delay);
2135 }
2136 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl); /* restore WEP condition */
2137
2138 if (sc->sc_if.if_flags & IFF_DEBUG) {
2139 int n_octets = 0;
2140 printf("%s: wrote %d bytes at 0x%x wepctl 0x%08x\n",
2141 sc->sc_dev.dv_xname, buflen, ofs, sc->sc_wepctl);
2142 for (i = 0; i < buflen; i++) {
2143 printf(" %02x", ptr[i]);
2144 if (++n_octets % 24 == 0)
2145 printf("\n");
2146 }
2147 if (n_octets % 24 != 0)
2148 printf("\n");
2149 }
2150 }
2151
2152 static int
2153 atw_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
2154 {
2155 struct atw_softc *sc = ic->ic_ifp->if_softc;
2156 u_int keyix = k->wk_keyix;
2157
2158 DPRINTF(sc, ("%s: delete key %u\n", __func__, keyix));
2159
2160 if (keyix >= IEEE80211_WEP_NKID)
2161 return 0;
2162 if (k->wk_keylen != 0)
2163 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
2164
2165 return 1;
2166 }
2167
2168 static int
2169 atw_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
2170 const u_int8_t mac[IEEE80211_ADDR_LEN])
2171 {
2172 struct atw_softc *sc = ic->ic_ifp->if_softc;
2173
2174 DPRINTF(sc, ("%s: set key %u\n", __func__, k->wk_keyix));
2175
2176 if (k->wk_keyix >= IEEE80211_WEP_NKID)
2177 return 0;
2178
2179 sc->sc_flags &= ~ATWF_WEP_SRAM_VALID;
2180
2181 return 1;
2182 }
2183
2184 static void
2185 atw_key_update_begin(struct ieee80211com *ic)
2186 {
2187 #ifdef ATW_DEBUG
2188 struct ifnet *ifp = ic->ic_ifp;
2189 struct atw_softc *sc = ifp->if_softc;
2190 #endif
2191
2192 DPRINTF(sc, ("%s:\n", __func__));
2193 }
2194
2195 static void
2196 atw_key_update_end(struct ieee80211com *ic)
2197 {
2198 struct ifnet *ifp = ic->ic_ifp;
2199 struct atw_softc *sc = ifp->if_softc;
2200
2201 DPRINTF(sc, ("%s:\n", __func__));
2202
2203 if ((sc->sc_flags & ATWF_WEP_SRAM_VALID) != 0)
2204 return;
2205 if (ATW_IS_ENABLED(sc) == 0)
2206 return;
2207 atw_idle(sc, ATW_NAR_SR | ATW_NAR_ST);
2208 atw_write_wep(sc);
2209 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
2210 DELAY(atw_nar_delay);
2211 ATW_WRITE(sc, ATW_RDR, 0x1);
2212 }
2213
2214 /* Write WEP keys from the ieee80211com to the ADM8211's SRAM. */
2215 static void
2216 atw_write_wep(struct atw_softc *sc)
2217 {
2218 #if 0
2219 struct ieee80211com *ic = &sc->sc_ic;
2220 u_int32_t reg;
2221 int i;
2222 #endif
2223 /* SRAM shared-key record format: key0 flags key1 ... key12 */
2224 u_int8_t buf[IEEE80211_WEP_NKID]
2225 [1 /* key[0] */ + 1 /* flags */ + 12 /* key[1 .. 12] */];
2226
2227 sc->sc_wepctl = 0;
2228 ATW_WRITE(sc, ATW_WEPCTL, sc->sc_wepctl);
2229
2230 memset(&buf[0][0], 0, sizeof(buf));
2231
2232 #if 0
2233 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
2234 if (ic->ic_nw_keys[i].wk_keylen > 5) {
2235 buf[i][1] = ATW_WEP_ENABLED | ATW_WEP_104BIT;
2236 } else if (ic->ic_nw_keys[i].wk_keylen != 0) {
2237 buf[i][1] = ATW_WEP_ENABLED;
2238 } else {
2239 buf[i][1] = 0;
2240 continue;
2241 }
2242 buf[i][0] = ic->ic_nw_keys[i].wk_key[0];
2243 memcpy(&buf[i][2], &ic->ic_nw_keys[i].wk_key[1],
2244 ic->ic_nw_keys[i].wk_keylen - 1);
2245 }
2246
2247 reg = ATW_READ(sc, ATW_MACTEST);
2248 reg |= ATW_MACTEST_MMI_USETXCLK | ATW_MACTEST_FORCE_KEYID;
2249 reg &= ~ATW_MACTEST_KEYID_MASK;
2250 reg |= __SHIFTIN(ic->ic_def_txkey, ATW_MACTEST_KEYID_MASK);
2251 ATW_WRITE(sc, ATW_MACTEST, reg);
2252
2253 if ((ic->ic_flags & IEEE80211_F_PRIVACY) != 0)
2254 sc->sc_wepctl |= ATW_WEPCTL_WEPENABLE;
2255
2256 switch (sc->sc_rev) {
2257 case ATW_REVISION_AB:
2258 case ATW_REVISION_AF:
2259 /* Bypass WEP on Rx. */
2260 sc->sc_wepctl |= ATW_WEPCTL_WEPRXBYP;
2261 break;
2262 default:
2263 break;
2264 }
2265 #endif
2266
2267 atw_write_sram(sc, ATW_SRAM_ADDR_SHARED_KEY, (u_int8_t*)&buf[0][0],
2268 sizeof(buf));
2269
2270 sc->sc_flags |= ATWF_WEP_SRAM_VALID;
2271 }
2272
2273 static void
2274 atw_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2275 struct ieee80211_node *ni, int subtype, int rssi, u_int32_t rstamp)
2276 {
2277 struct atw_softc *sc = (struct atw_softc *)ic->ic_ifp->if_softc;
2278
2279 /* The ADM8211A answers probe requests. TBD ADM8211B/C. */
2280 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_REQ)
2281 return;
2282
2283 (*sc->sc_recv_mgmt)(ic, m, ni, subtype, rssi, rstamp);
2284
2285 switch (subtype) {
2286 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2287 case IEEE80211_FC0_SUBTYPE_BEACON:
2288 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2289 ic->ic_state == IEEE80211_S_RUN) {
2290 if (le64toh(ni->ni_tstamp.tsf) >= atw_get_tsft(sc))
2291 (void)ieee80211_ibss_merge(ni);
2292 }
2293 break;
2294 default:
2295 break;
2296 }
2297 return;
2298 }
2299
2300 /* Write the SSID in the ieee80211com to the SRAM on the ADM8211.
2301 * In ad hoc mode, the SSID is written to the beacons sent by the
2302 * ADM8211. In both ad hoc and infrastructure mode, beacons received
2303 * with matching SSID affect ATW_INTR_LINKON/ATW_INTR_LINKOFF
2304 * indications.
2305 */
2306 static void
2307 atw_write_ssid(struct atw_softc *sc)
2308 {
2309 struct ieee80211com *ic = &sc->sc_ic;
2310 /* 34 bytes are reserved in ADM8211 SRAM for the SSID, but
2311 * it only expects the element length, not its ID.
2312 */
2313 u_int8_t buf[roundup(1 /* length */ + IEEE80211_NWID_LEN, 2)];
2314
2315 memset(buf, 0, sizeof(buf));
2316 buf[0] = ic->ic_bss->ni_esslen;
2317 memcpy(&buf[1], ic->ic_bss->ni_essid, ic->ic_bss->ni_esslen);
2318
2319 atw_write_sram(sc, ATW_SRAM_ADDR_SSID, buf,
2320 roundup(1 + ic->ic_bss->ni_esslen, 2));
2321 }
2322
2323 /* Write the supported rates in the ieee80211com to the SRAM of the ADM8211.
2324 * In ad hoc mode, the supported rates are written to beacons sent by the
2325 * ADM8211.
2326 */
2327 static void
2328 atw_write_sup_rates(struct atw_softc *sc)
2329 {
2330 struct ieee80211com *ic = &sc->sc_ic;
2331 /* 14 bytes are probably (XXX) reserved in the ADM8211 SRAM for
2332 * supported rates
2333 */
2334 u_int8_t buf[roundup(1 /* length */ + IEEE80211_RATE_SIZE, 2)];
2335
2336 memset(buf, 0, sizeof(buf));
2337
2338 buf[0] = ic->ic_bss->ni_rates.rs_nrates;
2339
2340 memcpy(&buf[1], ic->ic_bss->ni_rates.rs_rates,
2341 ic->ic_bss->ni_rates.rs_nrates);
2342
2343 atw_write_sram(sc, ATW_SRAM_ADDR_SUPRATES, buf, sizeof(buf));
2344 }
2345
2346 /* Start/stop sending beacons. */
2347 void
2348 atw_start_beacon(struct atw_softc *sc, int start)
2349 {
2350 struct ieee80211com *ic = &sc->sc_ic;
2351 uint16_t chan;
2352 uint32_t bcnt, bpli, cap0, cap1, capinfo;
2353 size_t len;
2354
2355 if (ATW_IS_ENABLED(sc) == 0)
2356 return;
2357
2358 /* start beacons */
2359 len = sizeof(struct ieee80211_frame) +
2360 8 /* timestamp */ + 2 /* beacon interval */ +
2361 2 /* capability info */ +
2362 2 + ic->ic_bss->ni_esslen /* SSID element */ +
2363 2 + ic->ic_bss->ni_rates.rs_nrates /* rates element */ +
2364 3 /* DS parameters */ +
2365 IEEE80211_CRC_LEN;
2366
2367 bcnt = ATW_READ(sc, ATW_BCNT) & ~ATW_BCNT_BCNT_MASK;
2368 cap0 = ATW_READ(sc, ATW_CAP0) & ~ATW_CAP0_CHN_MASK;
2369 cap1 = ATW_READ(sc, ATW_CAP1) & ~ATW_CAP1_CAPI_MASK;
2370
2371 ATW_WRITE(sc, ATW_BCNT, bcnt);
2372 ATW_WRITE(sc, ATW_CAP1, cap1);
2373
2374 if (!start)
2375 return;
2376
2377 /* TBD use ni_capinfo */
2378
2379 capinfo = 0;
2380 if (sc->sc_flags & ATWF_SHORT_PREAMBLE)
2381 capinfo |= IEEE80211_CAPINFO_SHORT_PREAMBLE;
2382 if (ic->ic_flags & IEEE80211_F_PRIVACY)
2383 capinfo |= IEEE80211_CAPINFO_PRIVACY;
2384
2385 switch (ic->ic_opmode) {
2386 case IEEE80211_M_IBSS:
2387 len += 4; /* IBSS parameters */
2388 capinfo |= IEEE80211_CAPINFO_IBSS;
2389 break;
2390 case IEEE80211_M_HOSTAP:
2391 /* XXX 6-byte minimum TIM */
2392 len += atw_beacon_len_adjust;
2393 capinfo |= IEEE80211_CAPINFO_ESS;
2394 break;
2395 default:
2396 return;
2397 }
2398
2399 /* set listen interval
2400 * XXX do software units agree w/ hardware?
2401 */
2402 bpli = __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
2403 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval, ATW_BPLI_LI_MASK);
2404
2405 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
2406
2407 bcnt |= __SHIFTIN(len, ATW_BCNT_BCNT_MASK);
2408 cap0 |= __SHIFTIN(chan, ATW_CAP0_CHN_MASK);
2409 cap1 |= __SHIFTIN(capinfo, ATW_CAP1_CAPI_MASK);
2410
2411 ATW_WRITE(sc, ATW_BCNT, bcnt);
2412 ATW_WRITE(sc, ATW_BPLI, bpli);
2413 ATW_WRITE(sc, ATW_CAP0, cap0);
2414 ATW_WRITE(sc, ATW_CAP1, cap1);
2415
2416 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_BCNT] = %08x\n",
2417 sc->sc_dev.dv_xname, bcnt));
2418
2419 DPRINTF(sc, ("%s: atw_start_beacon reg[ATW_CAP1] = %08x\n",
2420 sc->sc_dev.dv_xname, cap1));
2421 }
2422
2423 /* Return the 32 lsb of the last TSFT divisible by ival. */
2424 static inline uint32_t
2425 atw_last_even_tsft(uint32_t tsfth, uint32_t tsftl, uint32_t ival)
2426 {
2427 /* Following the reference driver's lead, I compute
2428 *
2429 * (uint32_t)((((uint64_t)tsfth << 32) | tsftl) % ival)
2430 *
2431 * without using 64-bit arithmetic, using the following
2432 * relationship:
2433 *
2434 * (0x100000000 * H + L) % m
2435 * = ((0x100000000 % m) * H + L) % m
2436 * = (((0xffffffff + 1) % m) * H + L) % m
2437 * = ((0xffffffff % m + 1 % m) * H + L) % m
2438 * = ((0xffffffff % m + 1) * H + L) % m
2439 */
2440 return ((0xFFFFFFFF % ival + 1) * tsfth + tsftl) % ival;
2441 }
2442
2443 static uint64_t
2444 atw_get_tsft(struct atw_softc *sc)
2445 {
2446 int i;
2447 uint32_t tsfth, tsftl;
2448 for (i = 0; i < 2; i++) {
2449 tsfth = ATW_READ(sc, ATW_TSFTH);
2450 tsftl = ATW_READ(sc, ATW_TSFTL);
2451 if (ATW_READ(sc, ATW_TSFTH) == tsfth)
2452 break;
2453 }
2454 return ((uint64_t)tsfth << 32) | tsftl;
2455 }
2456
2457 /* If we've created an IBSS, write the TSF time in the ADM8211 to
2458 * the ieee80211com.
2459 *
2460 * Predict the next target beacon transmission time (TBTT) and
2461 * write it to the ADM8211.
2462 */
2463 static void
2464 atw_predict_beacon(struct atw_softc *sc)
2465 {
2466 #define TBTTOFS 20 /* TU */
2467
2468 struct ieee80211com *ic = &sc->sc_ic;
2469 uint64_t tsft;
2470 uint32_t ival, past_even, tbtt, tsfth, tsftl;
2471 union {
2472 uint64_t word;
2473 uint8_t tstamp[8];
2474 } u;
2475
2476 if ((ic->ic_opmode == IEEE80211_M_HOSTAP) ||
2477 ((ic->ic_opmode == IEEE80211_M_IBSS) &&
2478 (ic->ic_flags & IEEE80211_F_SIBSS))) {
2479 tsft = atw_get_tsft(sc);
2480 u.word = htole64(tsft);
2481 (void)memcpy(&ic->ic_bss->ni_tstamp, &u.tstamp[0],
2482 sizeof(ic->ic_bss->ni_tstamp));
2483 } else
2484 tsft = le64toh(ic->ic_bss->ni_tstamp.tsf);
2485
2486 ival = ic->ic_bss->ni_intval * IEEE80211_DUR_TU;
2487
2488 tsftl = tsft & 0xFFFFFFFF;
2489 tsfth = tsft >> 32;
2490
2491 /* We sent/received the last beacon `past' microseconds
2492 * after the interval divided the TSF timer.
2493 */
2494 past_even = tsftl - atw_last_even_tsft(tsfth, tsftl, ival);
2495
2496 /* Skip ten beacons so that the TBTT cannot pass before
2497 * we've programmed it. Ten is an arbitrary number.
2498 */
2499 tbtt = past_even + ival * 10;
2500
2501 ATW_WRITE(sc, ATW_TOFS1,
2502 __SHIFTIN(1, ATW_TOFS1_TSFTOFSR_MASK) |
2503 __SHIFTIN(TBTTOFS, ATW_TOFS1_TBTTOFS_MASK) |
2504 __SHIFTIN(__SHIFTOUT(tbtt - TBTTOFS * IEEE80211_DUR_TU,
2505 ATW_TBTTPRE_MASK), ATW_TOFS1_TBTTPRE_MASK));
2506 #undef TBTTOFS
2507 }
2508
2509 static void
2510 atw_next_scan(void *arg)
2511 {
2512 struct atw_softc *sc = arg;
2513 struct ieee80211com *ic = &sc->sc_ic;
2514 int s;
2515
2516 /* don't call atw_start w/o network interrupts blocked */
2517 s = splnet();
2518 if (ic->ic_state == IEEE80211_S_SCAN)
2519 ieee80211_next_scan(ic);
2520 splx(s);
2521 }
2522
2523 /* Synchronize the hardware state with the software state. */
2524 static int
2525 atw_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
2526 {
2527 struct ifnet *ifp = ic->ic_ifp;
2528 struct atw_softc *sc = ifp->if_softc;
2529 enum ieee80211_state ostate;
2530 int error = 0;
2531
2532 ostate = ic->ic_state;
2533 callout_stop(&sc->sc_scan_ch);
2534
2535 switch (nstate) {
2536 case IEEE80211_S_AUTH:
2537 case IEEE80211_S_ASSOC:
2538 atw_write_bssid(sc);
2539 error = atw_tune(sc);
2540 break;
2541 case IEEE80211_S_INIT:
2542 callout_stop(&sc->sc_scan_ch);
2543 sc->sc_cur_chan = IEEE80211_CHAN_ANY;
2544 atw_start_beacon(sc, 0);
2545 break;
2546 case IEEE80211_S_SCAN:
2547 error = atw_tune(sc);
2548 callout_reset(&sc->sc_scan_ch, atw_dwelltime * hz / 1000,
2549 atw_next_scan, sc);
2550 break;
2551 case IEEE80211_S_RUN:
2552 error = atw_tune(sc);
2553 atw_write_bssid(sc);
2554 atw_write_ssid(sc);
2555 atw_write_sup_rates(sc);
2556
2557 if (ic->ic_opmode == IEEE80211_M_AHDEMO ||
2558 ic->ic_opmode == IEEE80211_M_MONITOR)
2559 break;
2560
2561 /* set listen interval
2562 * XXX do software units agree w/ hardware?
2563 */
2564 ATW_WRITE(sc, ATW_BPLI,
2565 __SHIFTIN(ic->ic_bss->ni_intval, ATW_BPLI_BP_MASK) |
2566 __SHIFTIN(ic->ic_lintval / ic->ic_bss->ni_intval,
2567 ATW_BPLI_LI_MASK));
2568
2569 DPRINTF(sc, ("%s: reg[ATW_BPLI] = %08x\n", sc->sc_dev.dv_xname,
2570 ATW_READ(sc, ATW_BPLI)));
2571
2572 atw_predict_beacon(sc);
2573
2574 switch (ic->ic_opmode) {
2575 case IEEE80211_M_AHDEMO:
2576 case IEEE80211_M_HOSTAP:
2577 case IEEE80211_M_IBSS:
2578 atw_start_beacon(sc, 1);
2579 break;
2580 case IEEE80211_M_MONITOR:
2581 case IEEE80211_M_STA:
2582 break;
2583 }
2584
2585 break;
2586 }
2587 return (error != 0) ? error : (*sc->sc_newstate)(ic, nstate, arg);
2588 }
2589
2590 /*
2591 * atw_add_rxbuf:
2592 *
2593 * Add a receive buffer to the indicated descriptor.
2594 */
2595 int
2596 atw_add_rxbuf(struct atw_softc *sc, int idx)
2597 {
2598 struct atw_rxsoft *rxs = &sc->sc_rxsoft[idx];
2599 struct mbuf *m;
2600 int error;
2601
2602 MGETHDR(m, M_DONTWAIT, MT_DATA);
2603 if (m == NULL)
2604 return (ENOBUFS);
2605
2606 MCLGET(m, M_DONTWAIT);
2607 if ((m->m_flags & M_EXT) == 0) {
2608 m_freem(m);
2609 return (ENOBUFS);
2610 }
2611
2612 if (rxs->rxs_mbuf != NULL)
2613 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2614
2615 rxs->rxs_mbuf = m;
2616
2617 error = bus_dmamap_load(sc->sc_dmat, rxs->rxs_dmamap,
2618 m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
2619 BUS_DMA_READ|BUS_DMA_NOWAIT);
2620 if (error) {
2621 printf("%s: can't load rx DMA map %d, error = %d\n",
2622 sc->sc_dev.dv_xname, idx, error);
2623 panic("atw_add_rxbuf"); /* XXX */
2624 }
2625
2626 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
2627 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
2628
2629 ATW_INIT_RXDESC(sc, idx);
2630
2631 return (0);
2632 }
2633
2634 /*
2635 * Release any queued transmit buffers.
2636 */
2637 void
2638 atw_txdrain(struct atw_softc *sc)
2639 {
2640 struct atw_txsoft *txs;
2641
2642 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
2643 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
2644 if (txs->txs_mbuf != NULL) {
2645 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2646 m_freem(txs->txs_mbuf);
2647 txs->txs_mbuf = NULL;
2648 }
2649 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
2650 sc->sc_txfree += txs->txs_ndescs;
2651 }
2652
2653 KASSERT((sc->sc_if.if_flags & IFF_RUNNING) == 0 ||
2654 !(SIMPLEQ_EMPTY(&sc->sc_txfreeq) ||
2655 sc->sc_txfree != ATW_NTXDESC));
2656 sc->sc_if.if_flags &= ~IFF_OACTIVE;
2657 sc->sc_tx_timer = 0;
2658 }
2659
2660 /*
2661 * atw_stop: [ ifnet interface function ]
2662 *
2663 * Stop transmission on the interface.
2664 */
2665 void
2666 atw_stop(struct ifnet *ifp, int disable)
2667 {
2668 struct atw_softc *sc = ifp->if_softc;
2669 struct ieee80211com *ic = &sc->sc_ic;
2670
2671 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
2672
2673 /* Disable interrupts. */
2674 ATW_WRITE(sc, ATW_IER, 0);
2675
2676 /* Stop the transmit and receive processes. */
2677 sc->sc_opmode = 0;
2678 ATW_WRITE(sc, ATW_NAR, 0);
2679 DELAY(atw_nar_delay);
2680 ATW_WRITE(sc, ATW_TDBD, 0);
2681 ATW_WRITE(sc, ATW_TDBP, 0);
2682 ATW_WRITE(sc, ATW_RDB, 0);
2683
2684 atw_txdrain(sc);
2685
2686 if (disable) {
2687 atw_rxdrain(sc);
2688 atw_disable(sc);
2689 }
2690
2691 /*
2692 * Mark the interface down and cancel the watchdog timer.
2693 */
2694 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2695 sc->sc_tx_timer = 0;
2696 ifp->if_timer = 0;
2697
2698 if (!disable)
2699 atw_reset(sc);
2700 }
2701
2702 /*
2703 * atw_rxdrain:
2704 *
2705 * Drain the receive queue.
2706 */
2707 void
2708 atw_rxdrain(struct atw_softc *sc)
2709 {
2710 struct atw_rxsoft *rxs;
2711 int i;
2712
2713 for (i = 0; i < ATW_NRXDESC; i++) {
2714 rxs = &sc->sc_rxsoft[i];
2715 if (rxs->rxs_mbuf == NULL)
2716 continue;
2717 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2718 m_freem(rxs->rxs_mbuf);
2719 rxs->rxs_mbuf = NULL;
2720 }
2721 }
2722
2723 /*
2724 * atw_detach:
2725 *
2726 * Detach an ADM8211 interface.
2727 */
2728 int
2729 atw_detach(struct atw_softc *sc)
2730 {
2731 struct ifnet *ifp = &sc->sc_if;
2732 struct atw_rxsoft *rxs;
2733 struct atw_txsoft *txs;
2734 int i;
2735
2736 /*
2737 * Succeed now if there isn't any work to do.
2738 */
2739 if ((sc->sc_flags & ATWF_ATTACHED) == 0)
2740 return (0);
2741
2742 callout_stop(&sc->sc_scan_ch);
2743
2744 ieee80211_ifdetach(&sc->sc_ic);
2745 if_detach(ifp);
2746
2747 for (i = 0; i < ATW_NRXDESC; i++) {
2748 rxs = &sc->sc_rxsoft[i];
2749 if (rxs->rxs_mbuf != NULL) {
2750 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
2751 m_freem(rxs->rxs_mbuf);
2752 rxs->rxs_mbuf = NULL;
2753 }
2754 bus_dmamap_destroy(sc->sc_dmat, rxs->rxs_dmamap);
2755 }
2756 for (i = 0; i < ATW_TXQUEUELEN; i++) {
2757 txs = &sc->sc_txsoft[i];
2758 if (txs->txs_mbuf != NULL) {
2759 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
2760 m_freem(txs->txs_mbuf);
2761 txs->txs_mbuf = NULL;
2762 }
2763 bus_dmamap_destroy(sc->sc_dmat, txs->txs_dmamap);
2764 }
2765 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
2766 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
2767 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
2768 sizeof(struct atw_control_data));
2769 bus_dmamem_free(sc->sc_dmat, &sc->sc_cdseg, sc->sc_cdnseg);
2770
2771 shutdownhook_disestablish(sc->sc_sdhook);
2772 powerhook_disestablish(sc->sc_powerhook);
2773
2774 if (sc->sc_srom)
2775 free(sc->sc_srom, M_DEVBUF);
2776
2777 return (0);
2778 }
2779
2780 /* atw_shutdown: make sure the interface is stopped at reboot time. */
2781 void
2782 atw_shutdown(void *arg)
2783 {
2784 struct atw_softc *sc = arg;
2785
2786 atw_stop(&sc->sc_if, 1);
2787 }
2788
2789 int
2790 atw_intr(void *arg)
2791 {
2792 struct atw_softc *sc = arg;
2793 struct ifnet *ifp = &sc->sc_if;
2794 u_int32_t status, rxstatus, txstatus, linkstatus;
2795 int handled = 0, txthresh;
2796
2797 #ifdef DEBUG
2798 if (ATW_IS_ENABLED(sc) == 0)
2799 panic("%s: atw_intr: not enabled", sc->sc_dev.dv_xname);
2800 #endif
2801
2802 /*
2803 * If the interface isn't running, the interrupt couldn't
2804 * possibly have come from us.
2805 */
2806 if ((ifp->if_flags & IFF_RUNNING) == 0 ||
2807 !device_is_active(&sc->sc_dev))
2808 return (0);
2809
2810 for (;;) {
2811 status = ATW_READ(sc, ATW_STSR);
2812
2813 if (status)
2814 ATW_WRITE(sc, ATW_STSR, status);
2815
2816 #ifdef ATW_DEBUG
2817 #define PRINTINTR(flag) do { \
2818 if ((status & flag) != 0) { \
2819 printf("%s" #flag, delim); \
2820 delim = ","; \
2821 } \
2822 } while (0)
2823
2824 if (atw_debug > 1 && status) {
2825 const char *delim = "<";
2826
2827 printf("%s: reg[STSR] = %x",
2828 sc->sc_dev.dv_xname, status);
2829
2830 PRINTINTR(ATW_INTR_FBE);
2831 PRINTINTR(ATW_INTR_LINKOFF);
2832 PRINTINTR(ATW_INTR_LINKON);
2833 PRINTINTR(ATW_INTR_RCI);
2834 PRINTINTR(ATW_INTR_RDU);
2835 PRINTINTR(ATW_INTR_REIS);
2836 PRINTINTR(ATW_INTR_RPS);
2837 PRINTINTR(ATW_INTR_TCI);
2838 PRINTINTR(ATW_INTR_TDU);
2839 PRINTINTR(ATW_INTR_TLT);
2840 PRINTINTR(ATW_INTR_TPS);
2841 PRINTINTR(ATW_INTR_TRT);
2842 PRINTINTR(ATW_INTR_TUF);
2843 PRINTINTR(ATW_INTR_BCNTC);
2844 PRINTINTR(ATW_INTR_ATIME);
2845 PRINTINTR(ATW_INTR_TBTT);
2846 PRINTINTR(ATW_INTR_TSCZ);
2847 PRINTINTR(ATW_INTR_TSFTF);
2848 printf(">\n");
2849 }
2850 #undef PRINTINTR
2851 #endif /* ATW_DEBUG */
2852
2853 if ((status & sc->sc_inten) == 0)
2854 break;
2855
2856 handled = 1;
2857
2858 rxstatus = status & sc->sc_rxint_mask;
2859 txstatus = status & sc->sc_txint_mask;
2860 linkstatus = status & sc->sc_linkint_mask;
2861
2862 if (linkstatus) {
2863 atw_linkintr(sc, linkstatus);
2864 }
2865
2866 if (rxstatus) {
2867 /* Grab any new packets. */
2868 atw_rxintr(sc);
2869
2870 if (rxstatus & ATW_INTR_RDU) {
2871 printf("%s: receive ring overrun\n",
2872 sc->sc_dev.dv_xname);
2873 /* Get the receive process going again. */
2874 ATW_WRITE(sc, ATW_RDR, 0x1);
2875 break;
2876 }
2877 }
2878
2879 if (txstatus) {
2880 /* Sweep up transmit descriptors. */
2881 atw_txintr(sc);
2882
2883 if (txstatus & ATW_INTR_TLT) {
2884 DPRINTF(sc, ("%s: tx lifetime exceeded\n",
2885 sc->sc_dev.dv_xname));
2886 }
2887
2888 if (txstatus & ATW_INTR_TRT) {
2889 DPRINTF(sc, ("%s: tx retry limit exceeded\n",
2890 sc->sc_dev.dv_xname));
2891 }
2892
2893 /* If Tx under-run, increase our transmit threshold
2894 * if another is available.
2895 */
2896 txthresh = sc->sc_txthresh + 1;
2897 if ((txstatus & ATW_INTR_TUF) &&
2898 sc->sc_txth[txthresh].txth_name != NULL) {
2899 /* Idle the transmit process. */
2900 atw_idle(sc, ATW_NAR_ST);
2901
2902 sc->sc_txthresh = txthresh;
2903 sc->sc_opmode &= ~(ATW_NAR_TR_MASK|ATW_NAR_SF);
2904 sc->sc_opmode |=
2905 sc->sc_txth[txthresh].txth_opmode;
2906 printf("%s: transmit underrun; new "
2907 "threshold: %s\n", sc->sc_dev.dv_xname,
2908 sc->sc_txth[txthresh].txth_name);
2909
2910 /* Set the new threshold and restart
2911 * the transmit process.
2912 */
2913 ATW_WRITE(sc, ATW_NAR, sc->sc_opmode);
2914 DELAY(atw_nar_delay);
2915 ATW_WRITE(sc, ATW_RDR, 0x1);
2916 /* XXX Log every Nth underrun from
2917 * XXX now on?
2918 */
2919 }
2920 }
2921
2922 if (status & (ATW_INTR_TPS|ATW_INTR_RPS)) {
2923 if (status & ATW_INTR_TPS)
2924 printf("%s: transmit process stopped\n",
2925 sc->sc_dev.dv_xname);
2926 if (status & ATW_INTR_RPS)
2927 printf("%s: receive process stopped\n",
2928 sc->sc_dev.dv_xname);
2929 (void)atw_init(ifp);
2930 break;
2931 }
2932
2933 if (status & ATW_INTR_FBE) {
2934 printf("%s: fatal bus error\n", sc->sc_dev.dv_xname);
2935 (void)atw_init(ifp);
2936 break;
2937 }
2938
2939 /*
2940 * Not handled:
2941 *
2942 * Transmit buffer unavailable -- normal
2943 * condition, nothing to do, really.
2944 *
2945 * Early receive interrupt -- not available on
2946 * all chips, we just use RI. We also only
2947 * use single-segment receive DMA, so this
2948 * is mostly useless.
2949 *
2950 * TBD others
2951 */
2952 }
2953
2954 /* Try to get more packets going. */
2955 atw_start(ifp);
2956
2957 return (handled);
2958 }
2959
2960 /*
2961 * atw_idle:
2962 *
2963 * Cause the transmit and/or receive processes to go idle.
2964 *
2965 * XXX It seems that the ADM8211 will not signal the end of the Rx/Tx
2966 * process in STSR if I clear SR or ST after the process has already
2967 * ceased. Fair enough. But the Rx process status bits in ATW_TEST0
2968 * do not seem to be too reliable. Perhaps I have the sense of the
2969 * Rx bits switched with the Tx bits?
2970 */
2971 void
2972 atw_idle(struct atw_softc *sc, u_int32_t bits)
2973 {
2974 u_int32_t ackmask = 0, opmode, stsr, test0;
2975 int i, s;
2976
2977 s = splnet();
2978
2979 opmode = sc->sc_opmode & ~bits;
2980
2981 if (bits & ATW_NAR_SR)
2982 ackmask |= ATW_INTR_RPS;
2983
2984 if (bits & ATW_NAR_ST) {
2985 ackmask |= ATW_INTR_TPS;
2986 /* set ATW_NAR_HF to flush TX FIFO. */
2987 opmode |= ATW_NAR_HF;
2988 }
2989
2990 ATW_WRITE(sc, ATW_NAR, opmode);
2991 DELAY(atw_nar_delay);
2992
2993 for (i = 0; i < 1000; i++) {
2994 stsr = ATW_READ(sc, ATW_STSR);
2995 if ((stsr & ackmask) == ackmask)
2996 break;
2997 DELAY(10);
2998 }
2999
3000 ATW_WRITE(sc, ATW_STSR, stsr & ackmask);
3001
3002 if ((stsr & ackmask) == ackmask)
3003 goto out;
3004
3005 test0 = ATW_READ(sc, ATW_TEST0);
3006
3007 if ((bits & ATW_NAR_ST) != 0 && (stsr & ATW_INTR_TPS) == 0 &&
3008 (test0 & ATW_TEST0_TS_MASK) != ATW_TEST0_TS_STOPPED) {
3009 printf("%s: transmit process not idle [%s]\n",
3010 sc->sc_dev.dv_xname,
3011 atw_tx_state[__SHIFTOUT(test0, ATW_TEST0_TS_MASK)]);
3012 printf("%s: bits %08x test0 %08x stsr %08x\n",
3013 sc->sc_dev.dv_xname, bits, test0, stsr);
3014 }
3015
3016 if ((bits & ATW_NAR_SR) != 0 && (stsr & ATW_INTR_RPS) == 0 &&
3017 (test0 & ATW_TEST0_RS_MASK) != ATW_TEST0_RS_STOPPED) {
3018 DPRINTF2(sc, ("%s: receive process not idle [%s]\n",
3019 sc->sc_dev.dv_xname,
3020 atw_rx_state[__SHIFTOUT(test0, ATW_TEST0_RS_MASK)]));
3021 DPRINTF2(sc, ("%s: bits %08x test0 %08x stsr %08x\n",
3022 sc->sc_dev.dv_xname, bits, test0, stsr));
3023 }
3024 out:
3025 if ((bits & ATW_NAR_ST) != 0)
3026 atw_txdrain(sc);
3027 splx(s);
3028 return;
3029 }
3030
3031 /*
3032 * atw_linkintr:
3033 *
3034 * Helper; handle link-status interrupts.
3035 */
3036 void
3037 atw_linkintr(struct atw_softc *sc, u_int32_t linkstatus)
3038 {
3039 struct ieee80211com *ic = &sc->sc_ic;
3040
3041 if (ic->ic_state != IEEE80211_S_RUN)
3042 return;
3043
3044 if (linkstatus & ATW_INTR_LINKON) {
3045 DPRINTF(sc, ("%s: link on\n", sc->sc_dev.dv_xname));
3046 sc->sc_rescan_timer = 0;
3047 } else if (linkstatus & ATW_INTR_LINKOFF) {
3048 DPRINTF(sc, ("%s: link off\n", sc->sc_dev.dv_xname));
3049 if (ic->ic_opmode != IEEE80211_M_STA)
3050 return;
3051 sc->sc_rescan_timer = 3;
3052 sc->sc_if.if_timer = 1;
3053 }
3054 }
3055
3056 static inline int
3057 atw_hw_decrypted(struct atw_softc *sc, struct ieee80211_frame_min *wh)
3058 {
3059 if ((sc->sc_ic.ic_flags & IEEE80211_F_PRIVACY) == 0)
3060 return 0;
3061 if ((wh->i_fc[1] & IEEE80211_FC1_WEP) == 0)
3062 return 0;
3063 return (sc->sc_wepctl & ATW_WEPCTL_WEPRXBYP) == 0;
3064 }
3065
3066 /*
3067 * atw_rxintr:
3068 *
3069 * Helper; handle receive interrupts.
3070 */
3071 void
3072 atw_rxintr(struct atw_softc *sc)
3073 {
3074 static int rate_tbl[] = {2, 4, 11, 22, 44};
3075 struct ieee80211com *ic = &sc->sc_ic;
3076 struct ieee80211_node *ni;
3077 struct ieee80211_frame_min *wh;
3078 struct ifnet *ifp = &sc->sc_if;
3079 struct atw_rxsoft *rxs;
3080 struct mbuf *m;
3081 u_int32_t rxstat;
3082 int i, len, rate, rate0;
3083 u_int32_t rssi, rssi0;
3084
3085 for (i = sc->sc_rxptr;; i = ATW_NEXTRX(i)) {
3086 rxs = &sc->sc_rxsoft[i];
3087
3088 ATW_CDRXSYNC(sc, i, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3089
3090 rxstat = le32toh(sc->sc_rxdescs[i].ar_stat);
3091 rssi0 = le32toh(sc->sc_rxdescs[i].ar_rssi);
3092 rate0 = __SHIFTOUT(rxstat, ATW_RXSTAT_RXDR_MASK);
3093
3094 if (rxstat & ATW_RXSTAT_OWN)
3095 break; /* We have processed all receive buffers. */
3096
3097 DPRINTF3(sc,
3098 ("%s: rx stat %08x rssi0 %08x buf1 %08x buf2 %08x\n",
3099 sc->sc_dev.dv_xname,
3100 rxstat, rssi0,
3101 le32toh(sc->sc_rxdescs[i].ar_buf1),
3102 le32toh(sc->sc_rxdescs[i].ar_buf2)));
3103
3104 /*
3105 * Make sure the packet fits in one buffer. This should
3106 * always be the case.
3107 */
3108 if ((rxstat & (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) !=
3109 (ATW_RXSTAT_FS|ATW_RXSTAT_LS)) {
3110 printf("%s: incoming packet spilled, resetting\n",
3111 sc->sc_dev.dv_xname);
3112 (void)atw_init(ifp);
3113 return;
3114 }
3115
3116 /*
3117 * If an error occurred, update stats, clear the status
3118 * word, and leave the packet buffer in place. It will
3119 * simply be reused the next time the ring comes around.
3120 * If 802.1Q VLAN MTU is enabled, ignore the Frame Too Long
3121 * error.
3122 */
3123
3124 if ((rxstat & ATW_RXSTAT_ES) != 0 &&
3125 ((sc->sc_ec.ec_capenable & ETHERCAP_VLAN_MTU) == 0 ||
3126 (rxstat & (ATW_RXSTAT_DE | ATW_RXSTAT_SFDE |
3127 ATW_RXSTAT_SIGE | ATW_RXSTAT_CRC16E |
3128 ATW_RXSTAT_RXTOE | ATW_RXSTAT_CRC32E |
3129 ATW_RXSTAT_ICVE)) != 0)) {
3130 #define PRINTERR(bit, str) \
3131 if (rxstat & (bit)) \
3132 printf("%s: receive error: %s\n", \
3133 sc->sc_dev.dv_xname, str)
3134 ifp->if_ierrors++;
3135 PRINTERR(ATW_RXSTAT_DE, "descriptor error");
3136 PRINTERR(ATW_RXSTAT_SFDE, "PLCP SFD error");
3137 PRINTERR(ATW_RXSTAT_SIGE, "PLCP signal error");
3138 PRINTERR(ATW_RXSTAT_CRC16E, "PLCP CRC16 error");
3139 PRINTERR(ATW_RXSTAT_RXTOE, "time-out");
3140 PRINTERR(ATW_RXSTAT_CRC32E, "FCS error");
3141 PRINTERR(ATW_RXSTAT_ICVE, "WEP ICV error");
3142 #undef PRINTERR
3143 ATW_INIT_RXDESC(sc, i);
3144 continue;
3145 }
3146
3147 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
3148 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
3149
3150 /*
3151 * No errors; receive the packet. Note the ADM8211
3152 * includes the CRC in promiscuous mode.
3153 */
3154 len = __SHIFTOUT(rxstat, ATW_RXSTAT_FL_MASK);
3155
3156 /*
3157 * Allocate a new mbuf cluster. If that fails, we are
3158 * out of memory, and must drop the packet and recycle
3159 * the buffer that's already attached to this descriptor.
3160 */
3161 m = rxs->rxs_mbuf;
3162 if (atw_add_rxbuf(sc, i) != 0) {
3163 ifp->if_ierrors++;
3164 ATW_INIT_RXDESC(sc, i);
3165 bus_dmamap_sync(sc->sc_dmat, rxs->rxs_dmamap, 0,
3166 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
3167 continue;
3168 }
3169
3170 ifp->if_ipackets++;
3171 if (sc->sc_opmode & ATW_NAR_PR)
3172 len -= IEEE80211_CRC_LEN;
3173 m->m_pkthdr.rcvif = ifp;
3174 m->m_pkthdr.len = m->m_len = MIN(m->m_ext.ext_size, len);
3175
3176 if (rate0 >= sizeof(rate_tbl) / sizeof(rate_tbl[0]))
3177 rate = 0;
3178 else
3179 rate = rate_tbl[rate0];
3180
3181 /* The RSSI comes straight from a register in the
3182 * baseband processor. I know that for the RF3000,
3183 * the RSSI register also contains the antenna-selection
3184 * bits. Mask those off.
3185 *
3186 * TBD Treat other basebands.
3187 */
3188 if (sc->sc_bbptype == ATW_BBPTYPE_RFMD)
3189 rssi = rssi0 & RF3000_RSSI_MASK;
3190 else
3191 rssi = rssi0;
3192
3193 #if NBPFILTER > 0
3194 /* Pass this up to any BPF listeners. */
3195 if (sc->sc_radiobpf != NULL) {
3196 struct atw_rx_radiotap_header *tap = &sc->sc_rxtap;
3197
3198 tap->ar_rate = rate;
3199 tap->ar_chan_freq = htole16(ic->ic_curchan->ic_freq);
3200 tap->ar_chan_flags = htole16(ic->ic_curchan->ic_flags);
3201
3202 /* TBD verify units are dB */
3203 tap->ar_antsignal = (int)rssi;
3204 /* TBD tap->ar_flags */
3205
3206 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap,
3207 tap->ar_ihdr.it_len, m);
3208 }
3209 #endif /* NPBFILTER > 0 */
3210
3211 wh = mtod(m, struct ieee80211_frame_min *);
3212 ni = ieee80211_find_rxnode(ic, wh);
3213 #if 0
3214 if (atw_hw_decrypted(sc, wh)) {
3215 wh->i_fc[1] &= ~IEEE80211_FC1_WEP;
3216 DPRINTF(sc, ("%s: hw decrypted\n", __func__));
3217 }
3218 #endif
3219 ieee80211_input(ic, m, ni, (int)rssi, 0);
3220 ieee80211_free_node(ni);
3221 }
3222
3223 /* Update the receive pointer. */
3224 sc->sc_rxptr = i;
3225 }
3226
3227 /*
3228 * atw_txintr:
3229 *
3230 * Helper; handle transmit interrupts.
3231 */
3232 void
3233 atw_txintr(struct atw_softc *sc)
3234 {
3235 #define TXSTAT_ERRMASK (ATW_TXSTAT_TUF | ATW_TXSTAT_TLT | ATW_TXSTAT_TRT | \
3236 ATW_TXSTAT_TRO | ATW_TXSTAT_SOFBR)
3237 #define TXSTAT_FMT "\2\31ATW_TXSTAT_SOFBR\32ATW_TXSTAT_TRO\33ATW_TXSTAT_TUF" \
3238 "\34ATW_TXSTAT_TRT\35ATW_TXSTAT_TLT"
3239
3240 static char txstat_buf[sizeof("ffffffff<>" TXSTAT_FMT)];
3241 struct ifnet *ifp = &sc->sc_if;
3242 struct atw_txsoft *txs;
3243 u_int32_t txstat;
3244
3245 DPRINTF3(sc, ("%s: atw_txintr: sc_flags 0x%08x\n",
3246 sc->sc_dev.dv_xname, sc->sc_flags));
3247
3248 /*
3249 * Go through our Tx list and free mbufs for those
3250 * frames that have been transmitted.
3251 */
3252 while ((txs = SIMPLEQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
3253 ATW_CDTXSYNC(sc, txs->txs_lastdesc, 1,
3254 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3255
3256 #ifdef ATW_DEBUG
3257 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
3258 int i;
3259 printf(" txsoft %p transmit chain:\n", txs);
3260 ATW_CDTXSYNC(sc, txs->txs_firstdesc,
3261 txs->txs_ndescs - 1,
3262 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3263 for (i = txs->txs_firstdesc;; i = ATW_NEXTTX(i)) {
3264 printf(" descriptor %d:\n", i);
3265 printf(" at_status: 0x%08x\n",
3266 le32toh(sc->sc_txdescs[i].at_stat));
3267 printf(" at_flags: 0x%08x\n",
3268 le32toh(sc->sc_txdescs[i].at_flags));
3269 printf(" at_buf1: 0x%08x\n",
3270 le32toh(sc->sc_txdescs[i].at_buf1));
3271 printf(" at_buf2: 0x%08x\n",
3272 le32toh(sc->sc_txdescs[i].at_buf2));
3273 if (i == txs->txs_lastdesc)
3274 break;
3275 }
3276 }
3277 #endif
3278
3279 txstat = le32toh(sc->sc_txdescs[txs->txs_lastdesc].at_stat);
3280 if (txstat & ATW_TXSTAT_OWN)
3281 break;
3282
3283 SIMPLEQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
3284
3285 sc->sc_txfree += txs->txs_ndescs;
3286
3287 bus_dmamap_sync(sc->sc_dmat, txs->txs_dmamap,
3288 0, txs->txs_dmamap->dm_mapsize,
3289 BUS_DMASYNC_POSTWRITE);
3290 bus_dmamap_unload(sc->sc_dmat, txs->txs_dmamap);
3291 m_freem(txs->txs_mbuf);
3292 txs->txs_mbuf = NULL;
3293
3294 SIMPLEQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
3295
3296 KASSERT(!(SIMPLEQ_EMPTY(&sc->sc_txfreeq) ||
3297 sc->sc_txfree == 0));
3298 ifp->if_flags &= ~IFF_OACTIVE;
3299
3300 if ((ifp->if_flags & IFF_DEBUG) != 0 &&
3301 (txstat & TXSTAT_ERRMASK) != 0) {
3302 bitmask_snprintf(txstat & TXSTAT_ERRMASK, TXSTAT_FMT,
3303 txstat_buf, sizeof(txstat_buf));
3304 printf("%s: txstat %s %" __PRIuBITS "\n",
3305 sc->sc_dev.dv_xname, txstat_buf,
3306 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK));
3307 }
3308
3309 /*
3310 * Check for errors and collisions.
3311 */
3312 if (txstat & ATW_TXSTAT_TUF)
3313 sc->sc_stats.ts_tx_tuf++;
3314 if (txstat & ATW_TXSTAT_TLT)
3315 sc->sc_stats.ts_tx_tlt++;
3316 if (txstat & ATW_TXSTAT_TRT)
3317 sc->sc_stats.ts_tx_trt++;
3318 if (txstat & ATW_TXSTAT_TRO)
3319 sc->sc_stats.ts_tx_tro++;
3320 if (txstat & ATW_TXSTAT_SOFBR) {
3321 sc->sc_stats.ts_tx_sofbr++;
3322 }
3323
3324 if ((txstat & ATW_TXSTAT_ES) == 0)
3325 ifp->if_collisions +=
3326 __SHIFTOUT(txstat, ATW_TXSTAT_ARC_MASK);
3327 else
3328 ifp->if_oerrors++;
3329
3330 ifp->if_opackets++;
3331 }
3332
3333 /*
3334 * If there are no more pending transmissions, cancel the watchdog
3335 * timer.
3336 */
3337 if (txs == NULL) {
3338 KASSERT((ifp->if_flags & IFF_OACTIVE) == 0);
3339 sc->sc_tx_timer = 0;
3340 }
3341 #undef TXSTAT_ERRMASK
3342 #undef TXSTAT_FMT
3343 }
3344
3345 /*
3346 * atw_watchdog: [ifnet interface function]
3347 *
3348 * Watchdog timer handler.
3349 */
3350 void
3351 atw_watchdog(struct ifnet *ifp)
3352 {
3353 struct atw_softc *sc = ifp->if_softc;
3354 struct ieee80211com *ic = &sc->sc_ic;
3355
3356 ifp->if_timer = 0;
3357 if (ATW_IS_ENABLED(sc) == 0)
3358 return;
3359
3360 if (sc->sc_rescan_timer) {
3361 if (--sc->sc_rescan_timer == 0)
3362 (void)ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
3363 }
3364 if (sc->sc_tx_timer) {
3365 if (--sc->sc_tx_timer == 0 &&
3366 !SIMPLEQ_EMPTY(&sc->sc_txdirtyq)) {
3367 printf("%s: transmit timeout\n", ifp->if_xname);
3368 ifp->if_oerrors++;
3369 (void)atw_init(ifp);
3370 atw_start(ifp);
3371 }
3372 }
3373 if (sc->sc_tx_timer != 0 || sc->sc_rescan_timer != 0)
3374 ifp->if_timer = 1;
3375 ieee80211_watchdog(ic);
3376 }
3377
3378 #ifdef ATW_DEBUG
3379 static void
3380 atw_dump_pkt(struct ifnet *ifp, struct mbuf *m0)
3381 {
3382 struct atw_softc *sc = ifp->if_softc;
3383 struct mbuf *m;
3384 int i, noctets = 0;
3385
3386 printf("%s: %d-byte packet\n", sc->sc_dev.dv_xname,
3387 m0->m_pkthdr.len);
3388
3389 for (m = m0; m; m = m->m_next) {
3390 if (m->m_len == 0)
3391 continue;
3392 for (i = 0; i < m->m_len; i++) {
3393 printf(" %02x", ((u_int8_t*)m->m_data)[i]);
3394 if (++noctets % 24 == 0)
3395 printf("\n");
3396 }
3397 }
3398 printf("%s%s: %d bytes emitted\n",
3399 (noctets % 24 != 0) ? "\n" : "", sc->sc_dev.dv_xname, noctets);
3400 }
3401 #endif /* ATW_DEBUG */
3402
3403 /*
3404 * atw_start: [ifnet interface function]
3405 *
3406 * Start packet transmission on the interface.
3407 */
3408 void
3409 atw_start(struct ifnet *ifp)
3410 {
3411 struct atw_softc *sc = ifp->if_softc;
3412 struct ieee80211_key *k;
3413 struct ieee80211com *ic = &sc->sc_ic;
3414 struct ieee80211_node *ni;
3415 struct ieee80211_frame_min *whm;
3416 struct ieee80211_frame *wh;
3417 struct atw_frame *hh;
3418 struct mbuf *m0, *m;
3419 struct atw_txsoft *txs, *last_txs;
3420 struct atw_txdesc *txd;
3421 int npkt, rate;
3422 bus_dmamap_t dmamap;
3423 int ctl, error, firsttx, nexttx, lasttx, first, ofree, seg;
3424
3425 DPRINTF2(sc, ("%s: atw_start: sc_flags 0x%08x, if_flags 0x%08x\n",
3426 sc->sc_dev.dv_xname, sc->sc_flags, ifp->if_flags));
3427
3428 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3429 return;
3430
3431 /*
3432 * Remember the previous number of free descriptors and
3433 * the first descriptor we'll use.
3434 */
3435 ofree = sc->sc_txfree;
3436 firsttx = lasttx = sc->sc_txnext;
3437
3438 DPRINTF2(sc, ("%s: atw_start: txfree %d, txnext %d\n",
3439 sc->sc_dev.dv_xname, ofree, firsttx));
3440
3441 /*
3442 * Loop through the send queue, setting up transmit descriptors
3443 * until we drain the queue, or use up all available transmit
3444 * descriptors.
3445 */
3446 while ((txs = SIMPLEQ_FIRST(&sc->sc_txfreeq)) != NULL &&
3447 sc->sc_txfree != 0) {
3448
3449 /*
3450 * Grab a packet off the management queue, if it
3451 * is not empty. Otherwise, from the data queue.
3452 */
3453 IF_DEQUEUE(&ic->ic_mgtq, m0);
3454 if (m0 != NULL) {
3455 ni = (struct ieee80211_node *)m0->m_pkthdr.rcvif;
3456 m0->m_pkthdr.rcvif = NULL;
3457 } else if (ic->ic_state != IEEE80211_S_RUN)
3458 break; /* send no data until associated */
3459 else {
3460 IFQ_DEQUEUE(&ifp->if_snd, m0);
3461 if (m0 == NULL)
3462 break;
3463 #if NBPFILTER > 0
3464 if (ifp->if_bpf != NULL)
3465 bpf_mtap(ifp->if_bpf, m0);
3466 #endif /* NBPFILTER > 0 */
3467 ni = ieee80211_find_txnode(ic,
3468 mtod(m0, struct ether_header *)->ether_dhost);
3469 if (ni == NULL) {
3470 ifp->if_oerrors++;
3471 break;
3472 }
3473 if ((m0 = ieee80211_encap(ic, m0, ni)) == NULL) {
3474 ieee80211_free_node(ni);
3475 ifp->if_oerrors++;
3476 break;
3477 }
3478 }
3479
3480 rate = MAX(ieee80211_get_rate(ni), 2);
3481
3482 whm = mtod(m0, struct ieee80211_frame_min *);
3483
3484 if ((whm->i_fc[1] & IEEE80211_FC1_WEP) == 0)
3485 k = NULL;
3486 else if ((k = ieee80211_crypto_encap(ic, ni, m0)) == NULL) {
3487 m_freem(m0);
3488 ieee80211_free_node(ni);
3489 ifp->if_oerrors++;
3490 break;
3491 }
3492
3493 if (ieee80211_compute_duration(whm, k, m0->m_pkthdr.len,
3494 ic->ic_flags, ic->ic_fragthreshold, rate,
3495 &txs->txs_d0, &txs->txs_dn, &npkt, 0) == -1) {
3496 DPRINTF2(sc, ("%s: fail compute duration\n", __func__));
3497 m_freem(m0);
3498 break;
3499 }
3500
3501 /* XXX Misleading if fragmentation is enabled. Better
3502 * to fragment in software?
3503 */
3504 *(uint16_t *)whm->i_dur = htole16(txs->txs_d0.d_rts_dur);
3505
3506 #if NBPFILTER > 0
3507 /*
3508 * Pass the packet to any BPF listeners.
3509 */
3510 if (ic->ic_rawbpf != NULL)
3511 bpf_mtap((caddr_t)ic->ic_rawbpf, m0);
3512
3513 if (sc->sc_radiobpf != NULL) {
3514 struct atw_tx_radiotap_header *tap = &sc->sc_txtap;
3515
3516 tap->at_rate = rate;
3517 tap->at_chan_freq = htole16(ic->ic_curchan->ic_freq);
3518 tap->at_chan_flags = htole16(ic->ic_curchan->ic_flags);
3519
3520 /* TBD tap->at_flags */
3521
3522 bpf_mtap2(sc->sc_radiobpf, (caddr_t)tap,
3523 tap->at_ihdr.it_len, m0);
3524 }
3525 #endif /* NBPFILTER > 0 */
3526
3527 M_PREPEND(m0, offsetof(struct atw_frame, atw_ihdr), M_DONTWAIT);
3528
3529 if (ni != NULL)
3530 ieee80211_free_node(ni);
3531
3532 if (m0 == NULL) {
3533 ifp->if_oerrors++;
3534 break;
3535 }
3536
3537 /* just to make sure. */
3538 m0 = m_pullup(m0, sizeof(struct atw_frame));
3539
3540 if (m0 == NULL) {
3541 ifp->if_oerrors++;
3542 break;
3543 }
3544
3545 hh = mtod(m0, struct atw_frame *);
3546 wh = &hh->atw_ihdr;
3547
3548 /* Copy everything we need from the 802.11 header:
3549 * Frame Control; address 1, address 3, or addresses
3550 * 3 and 4. NIC fills in BSSID, SA.
3551 */
3552 if (wh->i_fc[1] & IEEE80211_FC1_DIR_TODS) {
3553 if (wh->i_fc[1] & IEEE80211_FC1_DIR_FROMDS)
3554 panic("%s: illegal WDS frame",
3555 sc->sc_dev.dv_xname);
3556 memcpy(hh->atw_dst, wh->i_addr3, IEEE80211_ADDR_LEN);
3557 } else
3558 memcpy(hh->atw_dst, wh->i_addr1, IEEE80211_ADDR_LEN);
3559
3560 *(u_int16_t*)hh->atw_fc = *(u_int16_t*)wh->i_fc;
3561
3562 /* initialize remaining Tx parameters */
3563 memset(&hh->u, 0, sizeof(hh->u));
3564
3565 hh->atw_rate = rate * 5;
3566 /* XXX this could be incorrect if M_FCS. _encap should
3567 * probably strip FCS just in case it sticks around in
3568 * bridged packets.
3569 */
3570 hh->atw_service = 0x00; /* XXX guess */
3571 hh->atw_paylen = htole16(m0->m_pkthdr.len -
3572 sizeof(struct atw_frame));
3573
3574 hh->atw_fragthr = htole16(ic->ic_fragthreshold);
3575 hh->atw_rtylmt = 3;
3576 hh->atw_hdrctl = htole16(ATW_HDRCTL_UNKNOWN1);
3577 #if 0
3578 if (do_encrypt) {
3579 hh->atw_hdrctl |= htole16(ATW_HDRCTL_WEP);
3580 hh->atw_keyid = ic->ic_def_txkey;
3581 }
3582 #endif
3583
3584 hh->atw_head_plcplen = htole16(txs->txs_d0.d_plcp_len);
3585 hh->atw_tail_plcplen = htole16(txs->txs_dn.d_plcp_len);
3586 if (txs->txs_d0.d_residue)
3587 hh->atw_head_plcplen |= htole16(0x8000);
3588 if (txs->txs_dn.d_residue)
3589 hh->atw_tail_plcplen |= htole16(0x8000);
3590 hh->atw_head_dur = htole16(txs->txs_d0.d_rts_dur);
3591 hh->atw_tail_dur = htole16(txs->txs_dn.d_rts_dur);
3592
3593 /* never fragment multicast frames */
3594 if (IEEE80211_IS_MULTICAST(hh->atw_dst)) {
3595 hh->atw_fragthr = htole16(ic->ic_fragthreshold);
3596 } else if (sc->sc_flags & ATWF_RTSCTS) {
3597 hh->atw_hdrctl |= htole16(ATW_HDRCTL_RTSCTS);
3598 }
3599
3600 #ifdef ATW_DEBUG
3601 hh->atw_fragnum = 0;
3602
3603 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
3604 printf("%s: dst = %s, rate = 0x%02x, "
3605 "service = 0x%02x, paylen = 0x%04x\n",
3606 sc->sc_dev.dv_xname, ether_sprintf(hh->atw_dst),
3607 hh->atw_rate, hh->atw_service, hh->atw_paylen);
3608
3609 printf("%s: fc[0] = 0x%02x, fc[1] = 0x%02x, "
3610 "dur1 = 0x%04x, dur2 = 0x%04x, "
3611 "dur3 = 0x%04x, rts_dur = 0x%04x\n",
3612 sc->sc_dev.dv_xname, hh->atw_fc[0], hh->atw_fc[1],
3613 hh->atw_tail_plcplen, hh->atw_head_plcplen,
3614 hh->atw_tail_dur, hh->atw_head_dur);
3615
3616 printf("%s: hdrctl = 0x%04x, fragthr = 0x%04x, "
3617 "fragnum = 0x%02x, rtylmt = 0x%04x\n",
3618 sc->sc_dev.dv_xname, hh->atw_hdrctl,
3619 hh->atw_fragthr, hh->atw_fragnum, hh->atw_rtylmt);
3620
3621 printf("%s: keyid = %d\n",
3622 sc->sc_dev.dv_xname, hh->atw_keyid);
3623
3624 atw_dump_pkt(ifp, m0);
3625 }
3626 #endif /* ATW_DEBUG */
3627
3628 dmamap = txs->txs_dmamap;
3629
3630 /*
3631 * Load the DMA map. Copy and try (once) again if the packet
3632 * didn't fit in the alloted number of segments.
3633 */
3634 for (first = 1;
3635 (error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
3636 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 && first;
3637 first = 0) {
3638 MGETHDR(m, M_DONTWAIT, MT_DATA);
3639 if (m == NULL) {
3640 printf("%s: unable to allocate Tx mbuf\n",
3641 sc->sc_dev.dv_xname);
3642 break;
3643 }
3644 if (m0->m_pkthdr.len > MHLEN) {
3645 MCLGET(m, M_DONTWAIT);
3646 if ((m->m_flags & M_EXT) == 0) {
3647 printf("%s: unable to allocate Tx "
3648 "cluster\n", sc->sc_dev.dv_xname);
3649 m_freem(m);
3650 break;
3651 }
3652 }
3653 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
3654 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
3655 m_freem(m0);
3656 m0 = m;
3657 m = NULL;
3658 }
3659 if (error != 0) {
3660 printf("%s: unable to load Tx buffer, "
3661 "error = %d\n", sc->sc_dev.dv_xname, error);
3662 m_freem(m0);
3663 break;
3664 }
3665
3666 /*
3667 * Ensure we have enough descriptors free to describe
3668 * the packet.
3669 */
3670 if (dmamap->dm_nsegs > sc->sc_txfree) {
3671 /*
3672 * Not enough free descriptors to transmit
3673 * this packet. Unload the DMA map and
3674 * drop the packet. Notify the upper layer
3675 * that there are no more slots left.
3676 *
3677 * XXX We could allocate an mbuf and copy, but
3678 * XXX it is worth it?
3679 */
3680 bus_dmamap_unload(sc->sc_dmat, dmamap);
3681 m_freem(m0);
3682 break;
3683 }
3684
3685 /*
3686 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
3687 */
3688
3689 /* Sync the DMA map. */
3690 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
3691 BUS_DMASYNC_PREWRITE);
3692
3693 /* XXX arbitrary retry limit; 8 because I have seen it in
3694 * use already and maybe 0 means "no tries" !
3695 */
3696 ctl = htole32(__SHIFTIN(8, ATW_TXCTL_TL_MASK));
3697
3698 DPRINTF2(sc, ("%s: TXDR <- max(10, %d)\n",
3699 sc->sc_dev.dv_xname, rate * 5));
3700 ctl |= htole32(__SHIFTIN(MAX(10, rate * 5), ATW_TXCTL_TXDR_MASK));
3701
3702 /*
3703 * Initialize the transmit descriptors.
3704 */
3705 for (nexttx = sc->sc_txnext, seg = 0;
3706 seg < dmamap->dm_nsegs;
3707 seg++, nexttx = ATW_NEXTTX(nexttx)) {
3708 /*
3709 * If this is the first descriptor we're
3710 * enqueueing, don't set the OWN bit just
3711 * yet. That could cause a race condition.
3712 * We'll do it below.
3713 */
3714 txd = &sc->sc_txdescs[nexttx];
3715 txd->at_ctl = ctl |
3716 ((nexttx == firsttx) ? 0 : htole32(ATW_TXCTL_OWN));
3717
3718 txd->at_buf1 = htole32(dmamap->dm_segs[seg].ds_addr);
3719 txd->at_flags =
3720 htole32(__SHIFTIN(dmamap->dm_segs[seg].ds_len,
3721 ATW_TXFLAG_TBS1_MASK)) |
3722 ((nexttx == (ATW_NTXDESC - 1))
3723 ? htole32(ATW_TXFLAG_TER) : 0);
3724 lasttx = nexttx;
3725 }
3726
3727 /* Set `first segment' and `last segment' appropriately. */
3728 sc->sc_txdescs[sc->sc_txnext].at_flags |=
3729 htole32(ATW_TXFLAG_FS);
3730 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_LS);
3731
3732 #ifdef ATW_DEBUG
3733 if ((ifp->if_flags & IFF_DEBUG) != 0 && atw_debug > 2) {
3734 printf(" txsoft %p transmit chain:\n", txs);
3735 for (seg = sc->sc_txnext;; seg = ATW_NEXTTX(seg)) {
3736 printf(" descriptor %d:\n", seg);
3737 printf(" at_ctl: 0x%08x\n",
3738 le32toh(sc->sc_txdescs[seg].at_ctl));
3739 printf(" at_flags: 0x%08x\n",
3740 le32toh(sc->sc_txdescs[seg].at_flags));
3741 printf(" at_buf1: 0x%08x\n",
3742 le32toh(sc->sc_txdescs[seg].at_buf1));
3743 printf(" at_buf2: 0x%08x\n",
3744 le32toh(sc->sc_txdescs[seg].at_buf2));
3745 if (seg == lasttx)
3746 break;
3747 }
3748 }
3749 #endif
3750
3751 /* Sync the descriptors we're using. */
3752 ATW_CDTXSYNC(sc, sc->sc_txnext, dmamap->dm_nsegs,
3753 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3754
3755 /*
3756 * Store a pointer to the packet so we can free it later,
3757 * and remember what txdirty will be once the packet is
3758 * done.
3759 */
3760 txs->txs_mbuf = m0;
3761 txs->txs_firstdesc = sc->sc_txnext;
3762 txs->txs_lastdesc = lasttx;
3763 txs->txs_ndescs = dmamap->dm_nsegs;
3764
3765 /* Advance the tx pointer. */
3766 sc->sc_txfree -= dmamap->dm_nsegs;
3767 sc->sc_txnext = nexttx;
3768
3769 SIMPLEQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
3770 SIMPLEQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
3771
3772 last_txs = txs;
3773 }
3774
3775 if (sc->sc_txfree != ofree) {
3776 DPRINTF2(sc, ("%s: packets enqueued, IC on %d, OWN on %d\n",
3777 sc->sc_dev.dv_xname, lasttx, firsttx));
3778 /*
3779 * Cause a transmit interrupt to happen on the
3780 * last packet we enqueued.
3781 */
3782 sc->sc_txdescs[lasttx].at_flags |= htole32(ATW_TXFLAG_IC);
3783 ATW_CDTXSYNC(sc, lasttx, 1,
3784 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3785
3786 /*
3787 * The entire packet chain is set up. Give the
3788 * first descriptor to the chip now.
3789 */
3790 sc->sc_txdescs[firsttx].at_ctl |= htole32(ATW_TXCTL_OWN);
3791 ATW_CDTXSYNC(sc, firsttx, 1,
3792 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3793
3794 /* Wake up the transmitter. */
3795 ATW_WRITE(sc, ATW_TDR, 0x1);
3796
3797 if (txs == NULL || sc->sc_txfree == 0)
3798 ifp->if_flags |= IFF_OACTIVE;
3799
3800 /* Set a watchdog timer in case the chip flakes out. */
3801 sc->sc_tx_timer = 5;
3802 ifp->if_timer = 1;
3803 }
3804 }
3805
3806 /*
3807 * atw_power:
3808 *
3809 * Power management (suspend/resume) hook.
3810 */
3811 void
3812 atw_power(int why, void *arg)
3813 {
3814 struct atw_softc *sc = arg;
3815 struct ifnet *ifp = &sc->sc_if;
3816 int s;
3817
3818 DPRINTF(sc, ("%s: atw_power(%d,)\n", sc->sc_dev.dv_xname, why));
3819
3820 s = splnet();
3821 switch (why) {
3822 case PWR_STANDBY:
3823 /* XXX do nothing. */
3824 break;
3825 case PWR_SUSPEND:
3826 atw_stop(ifp, 0);
3827 if (sc->sc_power != NULL)
3828 (*sc->sc_power)(sc, why);
3829 break;
3830 case PWR_RESUME:
3831 if (ifp->if_flags & IFF_UP) {
3832 if (sc->sc_power != NULL)
3833 (*sc->sc_power)(sc, why);
3834 atw_init(ifp);
3835 }
3836 break;
3837 case PWR_SOFTSUSPEND:
3838 case PWR_SOFTSTANDBY:
3839 case PWR_SOFTRESUME:
3840 break;
3841 }
3842 splx(s);
3843 }
3844
3845 /*
3846 * atw_ioctl: [ifnet interface function]
3847 *
3848 * Handle control requests from the operator.
3849 */
3850 int
3851 atw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
3852 {
3853 struct atw_softc *sc = ifp->if_softc;
3854 struct ifreq *ifr = (struct ifreq *)data;
3855 int s, error = 0;
3856
3857 /* XXX monkey see, monkey do. comes from wi_ioctl. */
3858 if (!device_is_active(&sc->sc_dev))
3859 return ENXIO;
3860
3861 s = splnet();
3862
3863 switch (cmd) {
3864 case SIOCSIFFLAGS:
3865 if (ifp->if_flags & IFF_UP) {
3866 if (ATW_IS_ENABLED(sc)) {
3867 /*
3868 * To avoid rescanning another access point,
3869 * do not call atw_init() here. Instead,
3870 * only reflect media settings.
3871 */
3872 atw_filter_setup(sc);
3873 } else
3874 error = atw_init(ifp);
3875 } else if (ATW_IS_ENABLED(sc))
3876 atw_stop(ifp, 1);
3877 break;
3878 case SIOCADDMULTI:
3879 case SIOCDELMULTI:
3880 error = (cmd == SIOCADDMULTI) ?
3881 ether_addmulti(ifr, &sc->sc_ec) :
3882 ether_delmulti(ifr, &sc->sc_ec);
3883 if (error == ENETRESET) {
3884 if (ifp->if_flags & IFF_RUNNING)
3885 atw_filter_setup(sc); /* do not rescan */
3886 error = 0;
3887 }
3888 break;
3889 default:
3890 error = ieee80211_ioctl(&sc->sc_ic, cmd, data);
3891 if (error == ENETRESET || error == ERESTART) {
3892 if (is_running(ifp))
3893 error = atw_init(ifp);
3894 else
3895 error = 0;
3896 }
3897 break;
3898 }
3899
3900 /* Try to get more packets going. */
3901 if (ATW_IS_ENABLED(sc))
3902 atw_start(ifp);
3903
3904 splx(s);
3905 return (error);
3906 }
3907
3908 static int
3909 atw_media_change(struct ifnet *ifp)
3910 {
3911 int error;
3912
3913 error = ieee80211_media_change(ifp);
3914 if (error == ENETRESET) {
3915 if (is_running(ifp))
3916 error = atw_init(ifp);
3917 else
3918 error = 0;
3919 }
3920 return error;
3921 }
Cache object: 80df769a192a0ca5f883dfd6649a998e
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