Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ic/atwreg.h
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1 /* $NetBSD: atwreg.h,v 1.7 2004/02/17 21:20:55 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. All rights reserved. 5 * 6 * This code is derived from software contributed to The NetBSD Foundation 7 * by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the NetBSD 20 * Foundation, Inc. and its contributors. 21 * 4. Neither the name of the author nor the names of any co-contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 35 * THE POSSIBILITY OF SUCH DAMAGE. 36 */ 37 38 /* glossary */ 39 40 /* DTIM Delivery Traffic Indication Map, sent by AP 41 * ATIM Ad Hoc Traffic Indication Map 42 * TU 1024 microseconds 43 * TSF time synchronization function 44 * TBTT target beacon transmission time 45 * DIFS distributed inter-frame space 46 * SIFS short inter-frame space 47 * EIFS extended inter-frame space 48 */ 49 50 /* Macros for bit twiddling. */ 51 52 #ifndef _BIT_TWIDDLE 53 #define _BIT_TWIDDLE 54 /* nth bit, BIT(0) == 0x1. */ 55 #define BIT(n) (((n) == 32) ? 0 : ((u_int32_t) 1 << (n))) 56 57 /* bits m through n, m < n. */ 58 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1)) 59 60 /* find least significant bit that is set */ 61 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x)) 62 63 /* for x a power of two and p a non-negative integer, is x a greater power than 2**p? */ 64 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0) 65 66 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0) 67 68 #define MASK_TO_SHIFT4(m) \ 69 (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \ 70 ? 2 + MASK_TO_SHIFT2((m) >> 2) \ 71 : MASK_TO_SHIFT2((m))) 72 73 #define MASK_TO_SHIFT8(m) \ 74 (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \ 75 ? 4 + MASK_TO_SHIFT4((m) >> 4) \ 76 : MASK_TO_SHIFT4((m))) 77 78 #define MASK_TO_SHIFT16(m) \ 79 (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \ 80 ? 8 + MASK_TO_SHIFT8((m) >> 8) \ 81 : MASK_TO_SHIFT8((m))) 82 83 #define MASK_TO_SHIFT(m) \ 84 (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \ 85 ? 16 + MASK_TO_SHIFT16((m) >> 16) \ 86 : MASK_TO_SHIFT16((m))) 87 88 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask)) 89 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask)) 90 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask)) 91 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m)) 92 93 #endif /* _BIT_TWIDDLE */ 94 95 /* ADM8211 Host Control and Status Registers */ 96 97 #define ATW_PAR 0x00 /* PCI access */ 98 #define ATW_FRCTL 0x04 /* Frame control */ 99 #define ATW_TDR 0x08 /* Transmit demand */ 100 #define ATW_WTDP 0x0C /* Current transmit descriptor pointer */ 101 #define ATW_RDR 0x10 /* Receive demand */ 102 #define ATW_WRDP 0x14 /* Current receive descriptor pointer */ 103 #define ATW_RDB 0x18 /* Receive descriptor base address */ 104 #define ATW_CSR3A 0x1C /* Unused */ 105 #define ATW_TDBD 0x20 /* Transmit descriptor base address, DCF */ 106 #define ATW_TDBP 0x24 /* Transmit descriptor base address, PCF */ 107 #define ATW_STSR 0x28 /* Status */ 108 #define ATW_CSR5A 0x2C /* Unused */ 109 #define ATW_NAR 0x30 /* Network access */ 110 #define ATW_CSR6A 0x34 /* Unused */ 111 #define ATW_IER 0x38 /* Interrupt enable */ 112 #define ATW_CSR7A 0x3C 113 #define ATW_LPC 0x40 /* Lost packet counter */ 114 #define ATW_TEST1 0x44 /* Test register 1 */ 115 #define ATW_SPR 0x48 /* Serial port */ 116 #define ATW_TEST0 0x4C /* Test register 0 */ 117 #define ATW_WCSR 0x50 /* Wake-up control/status */ 118 #define ATW_WPDR 0x54 /* Wake-up pattern data */ 119 #define ATW_GPTMR 0x58 /* General purpose timer */ 120 #define ATW_GPIO 0x5C /* GPIO[5:0] configuration and control */ 121 #define ATW_BBPCTL 0x60 /* BBP control port */ 122 #define ATW_SYNCTL 0x64 /* synthesizer control port */ 123 #define ATW_PLCPHD 0x68 /* PLCP header setting */ 124 #define ATW_MMIWADDR 0x6C /* MMI write address */ 125 #define ATW_MMIRADDR1 0x70 /* MMI read address 1 */ 126 #define ATW_MMIRADDR2 0x74 /* MMI read address 2 */ 127 #define ATW_TXBR 0x78 /* Transmit burst counter */ 128 #define ATW_CSR15A 0x7C /* Unused */ 129 #define ATW_ALCSTAT 0x80 /* ALC statistics */ 130 #define ATW_TOFS2 0x84 /* Timing offset parameter 2, 16b */ 131 #define ATW_CMDR 0x88 /* Command */ 132 #define ATW_PCIC 0x8C /* PCI bus performance counter */ 133 #define ATW_PMCSR 0x90 /* Power management command and status */ 134 #define ATW_PAR0 0x94 /* Local MAC address register 0, 32b */ 135 #define ATW_PAR1 0x98 /* Local MAC address register 1, 16b */ 136 #define ATW_MAR0 0x9C /* Multicast address hash table register 0 */ 137 #define ATW_MAR1 0xA0 /* Multicast address hash table register 1 */ 138 #define ATW_ATIMDA0 0xA4 /* Ad Hoc Traffic Indication Map (ATIM) 139 * frame DA, byte[3:0] 140 */ 141 #define ATW_ABDA1 0xA8 /* BSSID address byte[5:4]; 142 * ATIM frame DA byte[5:4] 143 */ 144 #define ATW_BSSID0 0xAC /* BSSID address byte[3:0] */ 145 #define ATW_TXLMT 0xB0 /* WLAN retry limit, 8b; 146 * Max TX MSDU lifetime, 16b 147 */ 148 #define ATW_MIBCNT 0xB4 /* RTS/ACK/FCS MIB count, 32b */ 149 #define ATW_BCNT 0xB8 /* Beacon transmission time, 32b */ 150 #define ATW_TSFTH 0xBC /* TSFT[63:32], 32b */ 151 #define ATW_TSC 0xC0 /* TSFT[39:32] down count value */ 152 #define ATW_SYNRF 0xC4 /* SYN RF IF direct control */ 153 #define ATW_BPLI 0xC8 /* Beacon interval, 16b. 154 * STA listen interval, 16b. 155 */ 156 #define ATW_CAP0 0xCC /* Current channel, 4b. RCVDTIM, 1b. */ 157 #define ATW_CAP1 0xD0 /* Capability information, 16b. 158 * ATIM window, 1b. 159 */ 160 #define ATW_RMD 0xD4 /* RX max reception duration, 16b */ 161 #define ATW_CFPP 0xD8 /* CFP parameter, 32b */ 162 #define ATW_TOFS0 0xDC /* Timing offset parameter 0, 28b */ 163 #define ATW_TOFS1 0xE0 /* Timing offset parameter 1, 24b */ 164 #define ATW_IFST 0xE4 /* IFS timing parameter 1, 32b */ 165 #define ATW_RSPT 0xE8 /* Response time, 24b */ 166 #define ATW_TSFTL 0xEC /* TSFT[31:0], 32b */ 167 #define ATW_WEPCTL 0xF0 /* WEP control */ 168 #define ATW_WESK 0xF4 /* Write entry for shared/individual key */ 169 #define ATW_WEPCNT 0xF8 /* WEP count */ 170 #define ATW_MACTEST 0xFC 171 172 #define ATW_FER 0x100 /* Function event */ 173 #define ATW_FEMR 0x104 /* Function event mask */ 174 #define ATW_FPSR 0x108 /* Function present state */ 175 #define ATW_FFER 0x10C /* Function force event */ 176 177 178 #define ATW_PAR_MWIE BIT(24) /* memory write and invalidate 179 * enable 180 */ 181 #define ATW_PAR_MRLE BIT(23) /* memory read line enable */ 182 #define ATW_PAR_MRME BIT(21) /* memory read multiple 183 * enable 184 */ 185 #define ATW_PAR_RAP_MASK BITS(17, 18) /* receive auto-polling in 186 * receive suspended state 187 */ 188 #define ATW_PAR_CAL_MASK BITS(14, 15) /* cache alignment */ 189 #define ATW_PAR_CAL_PBL 0x0 190 /* min(8 DW, PBL) */ 191 #define ATW_PAR_CAL_8DW LSHIFT(0x1, ATW_PAR_CAL_MASK) 192 /* min(16 DW, PBL) */ 193 #define ATW_PAR_CAL_16DW LSHIFT(0x2, ATW_PAR_CAL_MASK) 194 /* min(32 DW, PBL) */ 195 #define ATW_PAR_CAL_32DW LSHIFT(0x3, ATW_PAR_CAL_MASK) 196 #define ATW_PAR_PBL_MASK BITS(8, 13) /* programmable burst length */ 197 #define ATW_PAR_PBL_UNLIMITED 0x0 198 #define ATW_PAR_PBL_1DW LSHIFT(0x1, ATW_PAR_PBL_MASK) 199 #define ATW_PAR_PBL_2DW LSHIFT(0x2, ATW_PAR_PBL_MASK) 200 #define ATW_PAR_PBL_4DW LSHIFT(0x4, ATW_PAR_PBL_MASK) 201 #define ATW_PAR_PBL_8DW LSHIFT(0x8, ATW_PAR_PBL_MASK) 202 #define ATW_PAR_PBL_16DW LSHIFT(0x16, ATW_PAR_PBL_MASK) 203 #define ATW_PAR_PBL_32DW LSHIFT(0x32, ATW_PAR_PBL_MASK) 204 #define ATW_PAR_BLE BIT(7) /* big/little endian selection */ 205 #define ATW_PAR_DSL_MASK BITS(2, 6) /* descriptor skip length */ 206 #define ATW_PAR_BAR BIT(1) /* bus arbitration */ 207 #define ATW_PAR_SWR BIT(0) /* software reset */ 208 209 #define ATW_FRCTL_PWRMGMT BIT(31) /* power management */ 210 #define ATW_FRCTL_VER_MASK BITS(29, 30) /* protocol version */ 211 #define ATW_FRCTL_ORDER BIT(28) /* order bit */ 212 #define ATW_FRCTL_MAXPSP BIT(27) /* maximum power saving */ 213 #define ATW_FRCTL_DOZEFRM BIT(18) /* select pre-sleep frame */ 214 #define ATW_FRCTL_PSAWAKE BIT(17) /* MAC is awake (?) */ 215 #define ATW_FRCTL_PSMODE BIT(16) /* MAC is power-saving (?) */ 216 #define ATW_FRCTL_AID_MASK BITS(0, 15) /* STA Association ID */ 217 218 #define ATW_INTR_PCF BIT(31) /* started/ended CFP */ 219 #define ATW_INTR_BCNTC BIT(30) /* transmitted IBSS beacon */ 220 #define ATW_INTR_GPINT BIT(29) /* GPIO interrupt */ 221 #define ATW_INTR_LINKOFF BIT(28) /* lost ATW_WCSR_BLN beacons */ 222 #define ATW_INTR_ATIMTC BIT(27) /* transmitted ATIM */ 223 #define ATW_INTR_TSFTF BIT(26) /* TSFT out of range */ 224 #define ATW_INTR_TSCZ BIT(25) /* TSC countdown expired */ 225 #define ATW_INTR_LINKON BIT(24) /* matched SSID, BSSID */ 226 #define ATW_INTR_SQL BIT(23) /* Marvel signal quality */ 227 #define ATW_INTR_WEPTD BIT(22) /* switched WEP table */ 228 #define ATW_INTR_ATIME BIT(21) /* ended ATIM window */ 229 #define ATW_INTR_TBTT BIT(20) /* (TBTT) Target Beacon TX Time 230 * passed 231 */ 232 #define ATW_INTR_NISS BIT(16) /* normal interrupt status 233 * summary: any of 31, 30, 27, 234 * 24, 14, 12, 6, 2, 0. 235 */ 236 #define ATW_INTR_AISS BIT(15) /* abnormal interrupt status 237 * summary: any of 29, 28, 26, 238 * 25, 23, 22, 13, 11, 8, 7, 5, 239 * 4, 3, 1. 240 */ 241 #define ATW_INTR_TEIS BIT(14) /* transmit early interrupt 242 * status: moved TX packet to 243 * FIFO 244 */ 245 #define ATW_INTR_FBE BIT(13) /* fatal bus error */ 246 #define ATW_INTR_REIS BIT(12) /* receive early interrupt 247 * status: RX packet filled 248 * its first descriptor 249 */ 250 #define ATW_INTR_GPTT BIT(11) /* general purpose timer expired */ 251 #define ATW_INTR_RPS BIT(8) /* stopped receive process */ 252 #define ATW_INTR_RDU BIT(7) /* receive descriptor 253 * unavailable 254 */ 255 #define ATW_INTR_RCI BIT(6) /* completed packet reception */ 256 #define ATW_INTR_TUF BIT(5) /* transmit underflow */ 257 #define ATW_INTR_TRT BIT(4) /* transmit retry count 258 * expired 259 */ 260 #define ATW_INTR_TLT BIT(3) /* transmit lifetime exceeded */ 261 #define ATW_INTR_TDU BIT(2) /* transmit descriptor 262 * unavailable 263 */ 264 #define ATW_INTR_TPS BIT(1) /* stopped transmit process */ 265 #define ATW_INTR_TCI BIT(0) /* completed transmit */ 266 #define ATW_NAR_TXCF BIT(31) /* stop process on TX failure */ 267 #define ATW_NAR_HF BIT(30) /* flush TX FIFO to host (?) */ 268 #define ATW_NAR_UTR BIT(29) /* select retry count source */ 269 #define ATW_NAR_PCF BIT(28) /* use one/both transmit 270 * descriptor base addresses 271 */ 272 #define ATW_NAR_CFP BIT(27) /* indicate more TX data to 273 * point coordinator 274 */ 275 #define ATW_NAR_SF BIT(21) /* store and forward: ignore 276 * TX threshold 277 */ 278 #define ATW_NAR_TR_MASK BITS(14, 15) /* TX threshold */ 279 #define ATW_NAR_TR_L64 LSHIFT(0x0, ATW_NAR_TR_MASK) 280 #define ATW_NAR_TR_L160 LSHIFT(0x2, ATW_NAR_TR_MASK) 281 #define ATW_NAR_TR_L192 LSHIFT(0x3, ATW_NAR_TR_MASK) 282 #define ATW_NAR_TR_H96 LSHIFT(0x0, ATW_NAR_TR_MASK) 283 #define ATW_NAR_TR_H288 LSHIFT(0x2, ATW_NAR_TR_MASK) 284 #define ATW_NAR_TR_H544 LSHIFT(0x3, ATW_NAR_TR_MASK) 285 #define ATW_NAR_ST BIT(13) /* start/stop transmit */ 286 #define ATW_NAR_OM_MASK BITS(10, 11) /* operating mode */ 287 #define ATW_NAR_OM_NORMAL 0x0 288 #define ATW_NAR_OM_LOOPBACK LSHIFT(0x1, ATW_NAR_OM_MASK) 289 #define ATW_NAR_MM BIT(7) /* RX any multicast */ 290 #define ATW_NAR_PR BIT(6) /* promiscuous mode */ 291 #define ATW_NAR_EA BIT(5) /* match ad hoc packets (?) */ 292 #define ATW_NAR_PB BIT(3) /* pass bad packets */ 293 #define ATW_NAR_STPDMA BIT(2) /* stop DMA, abort packet */ 294 #define ATW_NAR_SR BIT(1) /* start/stop receive */ 295 #define ATW_NAR_CTX BIT(0) /* continuous TX mode */ 296 297 /* IER bits are identical to STSR bits. Use ATW_INTR_*. */ 298 #if 0 299 #define ATW_IER_NIE BIT(16) /* normal interrupt enable */ 300 #define ATW_IER_AIE BIT(15) /* abnormal interrupt enable */ 301 /* normal interrupts: combine with ATW_IER_NIE */ 302 #define ATW_IER_PCFIE BIT(31) /* STA entered CFP */ 303 #define ATW_IER_BCNTCIE BIT(30) /* STA TX'd beacon */ 304 #define ATW_IER_ATIMTCIE BIT(27) /* transmitted ATIM */ 305 #define ATW_IER_LINKONIE BIT(24) /* matched beacon */ 306 #define ATW_IER_ATIMIE BIT(21) /* ended ATIM window */ 307 #define ATW_IER_TBTTIE BIT(20) /* TBTT */ 308 #define ATW_IER_TEIE BIT(14) /* moved TX packet to FIFO */ 309 #define ATW_IER_REIE BIT(12) /* RX packet filled its first 310 * descriptor 311 */ 312 #define ATW_IER_RCIE BIT(6) /* completed RX */ 313 #define ATW_IER_TDUIE BIT(2) /* transmit descriptor 314 * unavailable 315 */ 316 #define ATW_IER_TCIE BIT(0) /* completed TX */ 317 /* abnormal interrupts: combine with ATW_IER_AIE */ 318 #define ATW_IER_GPIE BIT(29) /* GPIO interrupt */ 319 #define ATW_IER_LINKOFFIE BIT(28) /* lost beacon */ 320 #define ATW_IER_TSFTFIE BIT(26) /* TSFT out of range */ 321 #define ATW_IER_TSCIE BIT(25) /* TSC countdown expired */ 322 #define ATW_IER_SQLIE BIT(23) /* signal quality */ 323 #define ATW_IER_WEPIE BIT(22) /* finished WEP table switch */ 324 #define ATW_IER_FBEIE BIT(13) /* fatal bus error */ 325 #define ATW_IER_GPTIE BIT(11) /* general purpose timer expired */ 326 #define ATW_IER_RPSIE BIT(8) /* stopped receive process */ 327 #define ATW_IER_RUIE BIT(7) /* receive descriptor unavailable */ 328 #define ATW_IER_TUIE BIT(5) /* transmit underflow */ 329 #define ATW_IER_TRTIE BIT(4) /* exceeded transmit retry count */ 330 #define ATW_IER_TLTTIE BIT(3) /* transmit lifetime exceeded */ 331 #define ATW_IER_TPSIE BIT(1) /* stopped transmit process */ 332 #endif 333 334 #define ATW_LPC_LPCO BIT(16) /* lost packet counter overflow */ 335 #define ATW_LPC_LPC_MASK BITS(0, 15) /* lost packet counter */ 336 337 #define ATW_SPR_SRS BIT(11) /* activate SEEPROM access */ 338 #define ATW_SPR_SDO BIT(3) /* data out of SEEPROM */ 339 #define ATW_SPR_SDI BIT(2) /* data into SEEPROM */ 340 #define ATW_SPR_SCLK BIT(1) /* SEEPROM clock */ 341 #define ATW_SPR_SCS BIT(0) /* SEEPROM chip select */ 342 343 /* TBD CSR_TEST0 */ 344 #define ATW_TEST0_BE_MASK BITS(31, 29) /* Bus error state */ 345 #define ATW_TEST0_TS_MASK BITS(28, 26) /* Transmit process state */ 346 347 /* Stopped */ 348 #define ATW_TEST0_TS_STOPPED LSHIFT(0, ATW_TEST0_TS_MASK) 349 /* Running - fetch transmit descriptor */ 350 #define ATW_TEST0_TS_FETCH LSHIFT(1, ATW_TEST0_TS_MASK) 351 /* Running - wait for end of transmission */ 352 #define ATW_TEST0_TS_WAIT LSHIFT(2, ATW_TEST0_TS_MASK) 353 /* Running - read buffer from memory and queue into FIFO */ 354 #define ATW_TEST0_TS_READING LSHIFT(3, ATW_TEST0_TS_MASK) 355 #define ATW_TEST0_TS_RESERVED1 LSHIFT(4, ATW_TEST0_TS_MASK) 356 #define ATW_TEST0_TS_RESERVED2 LSHIFT(5, ATW_TEST0_TS_MASK) 357 /* Suspended */ 358 #define ATW_TEST0_TS_SUSPENDED LSHIFT(6, ATW_TEST0_TS_MASK) 359 /* Running - close transmit descriptor */ 360 #define ATW_TEST0_TS_CLOSE LSHIFT(7, ATW_TEST0_TS_MASK) 361 362 #define ATW_TEST0_RS_MASK BITS(25, 23) /* Receive process state */ 363 364 /* Stopped */ 365 #define ATW_TEST0_RS_STOPPED LSHIFT(0, ATW_TEST0_RS_MASK) 366 /* Running - fetch receive descriptor */ 367 #define ATW_TEST0_RS_FETCH LSHIFT(1, ATW_TEST0_RS_MASK) 368 /* Running - check for end of receive */ 369 #define ATW_TEST0_RS_CHECK LSHIFT(2, ATW_TEST0_RS_MASK) 370 /* Running - wait for packet */ 371 #define ATW_TEST0_RS_WAIT LSHIFT(3, ATW_TEST0_RS_MASK) 372 /* Suspended */ 373 #define ATW_TEST0_RS_SUSPENDED LSHIFT(4, ATW_TEST0_RS_MASK) 374 /* Running - close receive descriptor */ 375 #define ATW_TEST0_RS_CLOSE LSHIFT(5, ATW_TEST0_RS_MASK) 376 /* Running - flush current frame from FIFO */ 377 #define ATW_TEST0_RS_FLUSH LSHIFT(6, ATW_TEST0_RS_MASK) 378 /* Running - queue current frame from FIFO into buffer */ 379 #define ATW_TEST0_RS_QUEUE LSHIFT(7, ATW_TEST0_RS_MASK) 380 381 #define ATW_TEST0_EPNE BIT(18) /* SEEPROM not detected */ 382 #define ATW_TEST0_EPSNM BIT(17) /* SEEPROM bad signature */ 383 #define ATW_TEST0_EPTYP_MASK BIT(16) /* SEEPROM type 384 * 1: 93c66, 385 * 0: 93c46 386 */ 387 #define ATW_TEST0_EPTYP_93c66 ATW_TEST0_EPTYP_MASK 388 #define ATW_TEST0_EPTYP_93c46 0 389 #define ATW_TEST0_EPRLD BIT(15) /* recall SEEPROM (write 1) */ 390 391 #define ATW_WCSR_CRCT BIT(30) /* CRC-16 type */ 392 #define ATW_WCSR_WP1E BIT(29) /* match wake-up pattern 1 */ 393 #define ATW_WCSR_WP2E BIT(28) /* match wake-up pattern 2 */ 394 #define ATW_WCSR_WP3E BIT(27) /* match wake-up pattern 3 */ 395 #define ATW_WCSR_WP4E BIT(26) /* match wake-up pattern 4 */ 396 #define ATW_WCSR_WP5E BIT(25) /* match wake-up pattern 5 */ 397 #define ATW_WCSR_BLN_MASK BITS(21, 23) /* lose link after BLN lost 398 * beacons 399 */ 400 #define ATW_WCSR_TSFTWE BIT(20) /* wake up on TSFT out of 401 * range 402 */ 403 #define ATW_WCSR_TIMWE BIT(19) /* wake up on TIM */ 404 #define ATW_WCSR_ATIMWE BIT(18) /* wake up on ATIM */ 405 #define ATW_WCSR_KEYWE BIT(17) /* wake up on key update */ 406 #define ATW_WCSR_WFRE BIT(10) /* wake up on wake-up frame */ 407 #define ATW_WCSR_MPRE BIT(9) /* wake up on magic packet */ 408 #define ATW_WCSR_LSOE BIT(8) /* wake up on link loss */ 409 /* wake-up reasons correspond to enable bits */ 410 #define ATW_WCSR_KEYUP BIT(6) /* */ 411 #define ATW_WCSR_TSFTW BIT(5) /* */ 412 #define ATW_WCSR_TIMW BIT(4) /* */ 413 #define ATW_WCSR_ATIMW BIT(3) /* */ 414 #define ATW_WCSR_WFR BIT(2) /* */ 415 #define ATW_WCSR_MPR BIT(1) /* */ 416 #define ATW_WCSR_LSO BIT(0) /* */ 417 418 #define ATW_GPTMR_COM_MASK BIT(16) /* continuous operation mode */ 419 #define ATW_GPTMR_GTV_MASK BITS(0, 15) /* set countdown in 204us ticks */ 420 421 #define ATW_GPIO_EC1_MASK BITS(25, 24) /* GPIO1 event configuration */ 422 #define ATW_GPIO_LAT_MASK BITS(21, 20) /* input latch */ 423 #define ATW_GPIO_INTEN_MASK BITS(19, 18) /* interrupt enable */ 424 #define ATW_GPIO_EN_MASK BITS(17, 12) /* output enable */ 425 #define ATW_GPIO_O_MASK BITS(11, 6) /* output value */ 426 #define ATW_GPIO_I_MASK BITS(5, 0) /* pin static input */ 427 428 #define ATW_BBPCTL_TWI BIT(31) /* Intersil 3-wire interface */ 429 #define ATW_BBPCTL_RF3KADDR_MASK BITS(30, 24) /* Address for RF3000 */ 430 #define ATW_BBPCTL_RF3KADDR_ADDR LSHIFT(0x20, ATW_BBPCTL_RF3KADDR_MASK) 431 #define ATW_BBPCTL_NEGEDGE_DO BIT(23) /* data-out on negative edge */ 432 #define ATW_BBPCTL_NEGEDGE_DI BIT(22) /* data-in on negative edge */ 433 #define ATW_BBPCTL_CCA_ACTLO BIT(21) /* CCA low when busy */ 434 #define ATW_BBPCTL_TYPE_MASK BITS(20, 18) /* BBP type */ 435 #define ATW_BBPCTL_WR BIT(17) /* start write; reset on 436 * completion 437 */ 438 #define ATW_BBPCTL_RD BIT(16) /* start read; reset on 439 * completion 440 */ 441 #define ATW_BBPCTL_ADDR_MASK BITS(15, 8) /* BBP address */ 442 #define ATW_BBPCTL_DATA_MASK BITS(7, 0) /* BBP data */ 443 444 #define ATW_SYNCTL_WR BIT(31) /* start write; reset on 445 * completion 446 */ 447 #define ATW_SYNCTL_RD BIT(30) /* start read; reset on 448 * completion 449 */ 450 #define ATW_SYNCTL_CS0 BIT(29) /* chip select */ 451 #define ATW_SYNCTL_CS1 BIT(28) 452 #define ATW_SYNCTL_CAL BIT(27) /* generate RF CAL pulse after 453 * Rx 454 */ 455 #define ATW_SYNCTL_SELCAL BIT(26) /* RF CAL source, 0: CAL bit, 456 * 1: MAC; needed by Intersil 457 * BBP 458 */ 459 #define ATW_SYNCTL_RFTYPE_MASK BITS(24, 22) /* RF type */ 460 #define ATW_SYNCTL_DATA_MASK BITS(21, 0) /* synthesizer setting */ 461 462 #define ATW_PLCPHD_SIGNAL_MASK BITS(31, 24) /* signal field in PLCP header, 463 * only for beacon, ATIM, and 464 * RTS. 465 */ 466 #define ATW_PLCPHD_SERVICE_MASK BITS(23, 16) /* service field in PLCP 467 * header 468 */ 469 #define ATW_PLCPHD_PMBL BIT(15) /* 0: long preamble, 1: short */ 470 471 #define ATW_MMIWADDR_INTERSIL 0x100E0C0A 472 #define ATW_MMIWADDR_RFMD 0x00009101 473 474 #define ATW_MMIRADDR1_INTERSIL 0x00007c7e 475 #define ATW_MMIRADDR1_RFMD 0x00000301 476 477 #define ATW_MMIRADDR2_INTERSIL 0x00100000 478 #define ATW_MMIRADDR2_RFMD 0x7e100000 479 480 #define ATW_TXBR_ALCUPDATE_MASK BIT(31) /* auto-update BBP with ALCSET */ 481 #define ATW_TXBR_TBCNT_MASK BITS(16, 20) /* transmit burst count */ 482 #define ATW_TXBR_ALCSET_MASK BITS(8, 15) /* TX power level set point */ 483 #define ATW_TXBR_ALCREF_MASK BITS(0, 7) /* TX power level reference point */ 484 485 #define ATW_ALCSTAT_MCOV_MASK BIT(27) /* MPDU count overflow */ 486 #define ATW_ALCSTAT_ESOV_MASK BIT(26) /* error sum overflow */ 487 #define ATW_ALCSTAT_MCNT_MASK BITS(16, 25) /* MPDU count, unsigned integer */ 488 #define ATW_ALCSTAT_ERSUM_MASK BITS(0, 15) /* power error sum, 489 * 2's complement signed integer 490 */ 491 492 #define ATW_TOFS2_PWR1UP_MASK BITS(31, 28) /* delay of Tx/Rx from PE1, 493 * Radio, PHYRST change after 494 * power-up, in 2ms units 495 */ 496 #define ATW_TOFS2_PWR0PAPE_MASK BITS(27, 24) /* delay of PAPE going low 497 * after internal data 498 * transmit end, in us 499 */ 500 #define ATW_TOFS2_PWR1PAPE_MASK BITS(23, 20) /* delay of PAPE going high 501 * after TXPE asserted, in us 502 */ 503 #define ATW_TOFS2_PWR0TRSW_MASK BITS(19, 16) /* delay of TRSW going low 504 * after internal data transmit 505 * end, in us 506 */ 507 #define ATW_TOFS2_PWR1TRSW_MASK BITS(15, 12) /* delay of TRSW going high 508 * after TXPE asserted, in us 509 */ 510 #define ATW_TOFS2_PWR0PE2_MASK BITS(11, 8) /* delay of PE2 going low 511 * after internal data transmit 512 * end, in us 513 */ 514 #define ATW_TOFS2_PWR1PE2_MASK BITS(7, 4) /* delay of PE2 going high 515 * after TXPE asserted, in us 516 */ 517 #define ATW_TOFS2_PWR0TXPE_MASK BITS(3, 0) /* delay of TXPE going low 518 * after internal data transmit 519 * end, in us 520 */ 521 522 #define ATW_CMDR_PM BIT(19) /* enables power mgmt 523 * capabilities. 524 */ 525 #define ATW_CMDR_APM BIT(18) /* APM mode, effective when 526 * PM = 1. 527 */ 528 #define ATW_CMDR_RTE BIT(4) /* enable Rx FIFO threshold */ 529 #define ATW_CMDR_DRT_MASK BITS(3, 2) /* drain Rx FIFO threshold */ 530 #define ATW_CMDR_SINT_MASK BIT(1) /* software interrupt---huh? */ 531 532 /* TBD PCIC */ 533 534 /* TBD PMCSR */ 535 536 537 #define ATW_PAR0_PAB0_MASK BITS(0, 7) /* MAC address byte 0 */ 538 #define ATW_PAR0_PAB1_MASK BITS(8, 15) /* MAC address byte 1 */ 539 #define ATW_PAR0_PAB2_MASK BITS(16, 23) /* MAC address byte 2 */ 540 #define ATW_PAR0_PAB3_MASK BITS(24, 31) /* MAC address byte 3 */ 541 542 #define ATW_PAR1_PAB5_MASK BITS(8, 15) /* MAC address byte 5 */ 543 #define ATW_PAR1_PAB4_MASK BITS(0, 7) /* MAC address byte 4 */ 544 545 #define ATW_MAR0_MAB3_MASK BITS(31, 24) /* multicast table bits 31:24 */ 546 #define ATW_MAR0_MAB2_MASK BITS(23, 16) /* multicast table bits 23:16 */ 547 #define ATW_MAR0_MAB1_MASK BITS(15, 8) /* multicast table bits 15:8 */ 548 #define ATW_MAR0_MAB0_MASK BITS(7, 0) /* multicast table bits 7:0 */ 549 550 #define ATW_MAR1_MAB7_MASK BITS(31, 24) /* multicast table bits 63:56 */ 551 #define ATW_MAR1_MAB6_MASK BITS(23, 16) /* multicast table bits 55:48 */ 552 #define ATW_MAR1_MAB5_MASK BITS(15, 8) /* multicast table bits 47:40 */ 553 #define ATW_MAR1_MAB4_MASK BITS(7, 0) /* multicast table bits 39:32 */ 554 555 /* ATIM destination address */ 556 #define ATW_ATIMDA0_ATIMB3_MASK BITS(31,24) 557 #define ATW_ATIMDA0_ATIMB2_MASK BITS(23,16) 558 #define ATW_ATIMDA0_ATIMB1_MASK BITS(15,8) 559 #define ATW_ATIMDA0_ATIMB0_MASK BITS(7,0) 560 561 /* ATIM destination address, BSSID */ 562 #define ATW_ABDA1_BSSIDB5_MASK BITS(31,24) 563 #define ATW_ABDA1_BSSIDB4_MASK BITS(23,16) 564 #define ATW_ABDA1_ATIMB5_MASK BITS(15,8) 565 #define ATW_ABDA1_ATIMB4_MASK BITS(7,0) 566 567 /* BSSID */ 568 #define ATW_BSSID0_BSSIDB3_MASK BITS(31,24) 569 #define ATW_BSSID0_BSSIDB2_MASK BITS(23,16) 570 #define ATW_BSSID0_BSSIDB1_MASK BITS(15,8) 571 #define ATW_BSSID0_BSSIDB0_MASK BITS(7,0) 572 573 #define ATW_TXLMT_MTMLT_MASK BITS(31,16) /* max TX MSDU lifetime in TU */ 574 #define ATW_TXLMT_SRTYLIM_MASK BITS(7,0) /* short retry limit */ 575 576 #define ATW_MIBCNT_FFCNT_MASK BITS(31,24) /* FCS failure count */ 577 #define ATW_MIBCNT_AFCNT_MASK BITS(23,16) /* ACK failure count */ 578 #define ATW_MIBCNT_RSCNT_MASK BITS(15,8) /* RTS success count */ 579 #define ATW_MIBCNT_RFCNT_MASK BITS(7,0) /* RTS failure count */ 580 581 #define ATW_BCNT_PLCPH_MASK BITS(23,16) /* 11M PLCP length (us) */ 582 #define ATW_BCNT_PLCPL_MASK BITS(15,8) /* 5.5M PLCP length (us) */ 583 #define ATW_BCNT_BCNT_MASK BITS(7,0) /* byte count of beacon frame */ 584 585 #define ATW_TSC_TSC_MASK BITS(3,0) /* TSFT countdown value */ 586 587 #define ATW_SYNRF_SELSYN BIT(31) /* 0: MAC controls SYN IF pins, 588 * 1: ATW_SYNRF controls SYN IF pins. 589 */ 590 #define ATW_SYNRF_SELRF BIT(30) /* 0: MAC controls RF IF pins, 591 * 1: ATW_SYNRF controls RF IF pins. 592 */ 593 #define ATW_SYNRF_LERF BIT(29) /* if SELSYN = 1, direct control of 594 * LERF# pin 595 */ 596 #define ATW_SYNRF_LEIF BIT(28) /* if SELSYN = 1, direct control of 597 * LEIF# pin 598 */ 599 #define ATW_SYNRF_SYNCLK BIT(27) /* if SELSYN = 1, direct control of 600 * SYNCLK pin 601 */ 602 #define ATW_SYNRF_SYNDATA BIT(26) /* if SELSYN = 1, direct control of 603 * SYNDATA pin 604 */ 605 #define ATW_SYNRF_PE1 BIT(25) /* if SELRF = 1, direct control of 606 * PE1 pin 607 */ 608 #define ATW_SYNRF_PE2 BIT(24) /* if SELRF = 1, direct control of 609 * PE2 pin 610 */ 611 #define ATW_SYNRF_PAPE BIT(23) /* if SELRF = 1, direct control of 612 * PAPE pin 613 */ 614 #define ATW_SYNRF_INTERSIL_EN BIT(20) /* if SELRF = 1, enables 615 * some signal used by the 616 * Intersil RF front-end? 617 * Undocumented. 618 */ 619 #define ATW_SYNRF_PHYRST BIT(18) /* if SELRF = 1, direct control of 620 * PHYRST# pin 621 */ 622 623 #define ATW_BPLI_BP_MASK BITS(31,16) /* beacon interval in TU */ 624 #define ATW_BPLI_LI_MASK BITS(15,0) /* STA listen interval in 625 * beacon intervals 626 */ 627 628 #define ATW_CAP0_RCVDTIM BIT(4) /* receive every DTIM */ 629 #define ATW_CAP0_CHN_MASK BITS(3,0) /* current DSSS channel */ 630 631 #define ATW_CAP1_CAPI_MASK BITS(31,16) /* capability information */ 632 #define ATW_CAP1_ATIMW_MASK BITS(15,0) /* ATIM window in TU */ 633 634 #define ATW_RMD_ATIMST BIT(31) /* ATIM frame TX status */ 635 #define ATW_RMD_CFP BIT(30) /* CFP indicator */ 636 #define ATW_RMD_PCNT BITS(27,16) /* idle time between 637 * awake/ps mode 638 */ 639 #define ATW_RMD_RMRD BITS(15,0) /* max RX reception duration 640 * in us 641 */ 642 643 #define ATW_CFPP_CFPP BITS(31,24) /* CFP unit DTIM */ 644 #define ATW_CFPP_CFPMD BITS(23,8) /* CFP max duration in TU */ 645 #define ATW_CFPP_DTIMP BITS(7,0) /* DTIM period in beacon 646 * intervals 647 */ 648 #define ATW_TOFS0_USCNT_MASK BITS(29,24) /* number of system clocks 649 * in 1 microsecond. 650 * Depends PCI bus speed? 651 */ 652 #define ATW_TOFS0_TUCNT_MASK BITS(9,0) /* TU counter in microseconds */ 653 654 /* TBD TOFS1 */ 655 #define ATW_TOFS1_TSFTOFSR_MASK BITS(31,24) /* RX TSFT offset in 656 * microseconds: RF+BBP 657 * latency 658 */ 659 #define ATW_TOFS1_TBTTPRE_MASK BITS(23,8) /* prediction time, (next 660 * Nth TBTT - TBTTOFS) in 661 * microseconds (huh?). To 662 * match TSFT[25:10] (huh?). 663 */ 664 #define ATW_TOFS1_TBTTOFS_MASK BITS(7,0) /* wake-up time offset before 665 * TBTT in TU 666 */ 667 #define ATW_IFST_SLOT_MASK BITS(27,23) /* SLOT time in us */ 668 #define ATW_IFST_SIFS_MASK BITS(22,15) /* SIFS time in us */ 669 #define ATW_IFST_DIFS_MASK BITS(14,9) /* DIFS time in us */ 670 #define ATW_IFST_EIFS_MASK BITS(8,0) /* EIFS time in us */ 671 672 #define ATW_RSPT_MART_MASK BITS(31,16) /* max response time in us */ 673 #define ATW_RSPT_MIRT_MASK BITS(15,8) /* min response time in us */ 674 #define ATW_RSPT_TSFTOFST_MASK BITS(7,0) /* TX TSFT offset in us */ 675 676 #define ATW_WEPCTL_WEPENABLE BIT(31) /* enable WEP engine */ 677 #define ATW_WEPCTL_AUTOSWITCH BIT(30) /* auto-switch enable (huh?) */ 678 #define ATW_WEPCTL_CURTBL BIT(29) /* current table in use */ 679 #define ATW_WEPCTL_WR BIT(28) /* */ 680 #define ATW_WEPCTL_RD BIT(27) /* */ 681 #define ATW_WEPCTL_WEPRXBYP BIT(25) /* bypass WEP on RX */ 682 #define ATW_WEPCTL_UNKNOWN0 BIT(23) /* has something to do with 683 * revision 0x20. Possibly 684 * selects a different WEP 685 * table. 686 */ 687 #define ATW_WEPCTL_TBLADD_MASK BITS(8,0) /* add to table */ 688 689 /* set these bits in the second byte of a SRAM shared key record to affect 690 * the use and interpretation of the key in the record. 691 */ 692 #define ATW_WEP_ENABLED BIT(7) 693 #define ATW_WEP_104BIT BIT(6) 694 695 #define ATW_WESK_DATA_MASK BITS(15,0) /* data */ 696 #define ATW_WEPCNT_WIEC_MASK BITS(15,0) /* WEP ICV error count */ 697 698 #define ATW_MACTEST_FORCE_IV BIT(23) 699 #define ATW_MACTEST_FORCE_KEYID BIT(22) 700 #define ATW_MACTEST_KEYID_MASK BITS(21,20) 701 #define ATW_MACTEST_MMI_USETXCLK BIT(11) 702 703 /* Function Event/Status registers */ 704 705 #define ATW_FER_INTR BIT(15) /* interrupt: set regardless of mask */ 706 #define ATW_FER_GWAKE BIT(4) /* general wake-up: set regardless of mask */ 707 708 #define ATW_FEMR_INTR_EN BIT(15) /* enable INTA# */ 709 #define ATW_FEMR_WAKEUP_EN BIT(14) /* enable wake-up */ 710 #define ATW_FEMR_GWAKE_EN BIT(4) /* enable general wake-up */ 711 712 #define ATW_FPSR_INTR_STATUS BIT(15) /* interrupt status */ 713 #define ATW_FPSR_WAKEUP_STATUS BIT(4) /* CSTSCHG state */ 714 #define ATW_FFER_INTA_FORCE BIT(15) /* activate INTA (if not masked) */ 715 #define ATW_FFER_GWAKE_FORCE BIT(4) /* activate CSTSCHG (if not masked) */ 716 717 /* Serial EEPROM offsets */ 718 #define ATW_SR_CLASS_CODE (0x00/2) 719 #define ATW_SR_FORMAT_VERSION (0x02/2) 720 #define ATW_SR_MAC00 (0x08/2) /* CSR21 */ 721 #define ATW_SR_MAC01 (0x0A/2) /* CSR21/22 */ 722 #define ATW_SR_MAC10 (0x0C/2) /* CSR22 */ 723 #define ATW_SR_CSR20 (0x16/2) 724 #define ATW_SR_ANT_MASK BITS(12, 10) 725 #define ATW_SR_PWRSCALE_MASK BITS(9, 8) 726 #define ATW_SR_CLKSAVE_MASK BITS(7, 6) 727 #define ATW_SR_RFTYPE_MASK BITS(5, 3) 728 #define ATW_SR_BBPTYPE_MASK BITS(2, 0) 729 #define ATW_SR_CR28_CR03 (0x18/2) 730 #define ATW_SR_CTRY_CR29 (0x1A/2) 731 #define ATW_SR_CTRY_MASK BITS(15,8) /* country code */ 732 #define COUNTRY_FCC 0 733 #define COUNTRY_IC 1 734 #define COUNTRY_ETSI 2 735 #define COUNTRY_SPAIN 3 736 #define COUNTRY_FRANCE 4 737 #define COUNTRY_MMK 5 738 #define COUNTRY_MMK2 6 739 #define ATW_SR_PCI_DEVICE (0x20/2) /* CR0 */ 740 #define ATW_SR_PCI_VENDOR (0x22/2) /* CR0 */ 741 #define ATW_SR_SUB_DEVICE (0x24/2) /* CR11 */ 742 #define ATW_SR_SUB_VENDOR (0x26/2) /* CR11 */ 743 #define ATW_SR_CR15 (0x28/2) 744 #define ATW_SR_LOCISPTR (0x2A/2) /* CR10 */ 745 #define ATW_SR_HICISPTR (0x2C/2) /* CR10 */ 746 #define ATW_SR_CSR18 (0x2E/2) 747 #define ATW_SR_D0_D1_PWR (0x40/2) /* CR49 */ 748 #define ATW_SR_D2_D3_PWR (0x42/2) /* CR49 */ 749 #define ATW_SR_CIS_WORDS (0x52/2) 750 /* CR17 of RFMD RF3000 BBP: returns TWO channels */ 751 #define ATW_SR_TXPOWER(chnl) (0x54/2 + ((chnl) - 1)/2) 752 /* CR20 of RFMD RF3000 BBP: returns TWO channels */ 753 #define ATW_SR_LPF_CUTOFF(chnl) (0x62/2 + ((chnl) - 1)/2) 754 /* CR21 of RFMD RF3000 BBP: returns TWO channels */ 755 #define ATW_SR_LNA_GS_THRESH(chnl) (0x70/2 + ((chnl) - 1)/2) 756 #define ATW_SR_CHECKSUM (0x7e/2) /* for data 0x00-0x7d */ 757 #define ATW_SR_CIS (0x80/2) /* Cardbus CIS */ 758 759 /* Tx descriptor */ 760 struct atw_txdesc { 761 u_int32_t at_ctl; 762 #define at_stat at_ctl 763 u_int32_t at_flags; 764 u_int32_t at_buf1; 765 u_int32_t at_buf2; 766 }; 767 768 #define ATW_TXCTL_OWN BIT(31) /* 1: ready to transmit */ 769 #define ATW_TXCTL_DONE BIT(30) /* 0: not processed */ 770 #define ATW_TXCTL_TXDR_MASK BITS(27,20) /* TX data rate (?) */ 771 #define ATW_TXCTL_TL_MASK BITS(19,0) /* retry limit, 0 - 255 */ 772 773 #define ATW_TXSTAT_OWN ATW_TXCTL_OWN /* 0: not for transmission */ 774 #define ATW_TXSTAT_DONE ATW_TXCTL_DONE /* 1: been processed */ 775 #define ATW_TXSTAT_ES BIT(29) /* 0: TX successful */ 776 #define ATW_TXSTAT_TLT BIT(28) /* TX lifetime expired */ 777 #define ATW_TXSTAT_TRT BIT(27) /* TX retry limit expired */ 778 #define ATW_TXSTAT_TUF BIT(26) /* TX under-run error */ 779 #define ATW_TXSTAT_TRO BIT(25) /* TX over-run error */ 780 #define ATW_TXSTAT_SOFBR BIT(24) /* packet size != buffer size 781 * (?) 782 */ 783 #define ATW_TXSTAT_ARC_MASK BITS(11,0) /* accumulated retry count */ 784 785 #define ATW_TXFLAG_IC BIT(31) /* interrupt on completion */ 786 #define ATW_TXFLAG_LS BIT(30) /* packet's last descriptor */ 787 #define ATW_TXFLAG_FS BIT(29) /* packet's first descriptor */ 788 #define ATW_TXFLAG_TER BIT(25) /* end of ring */ 789 #define ATW_TXFLAG_TCH BIT(24) /* at_buf2 is 2nd chain */ 790 #define ATW_TXFLAG_TBS2_MASK BITS(23,12) /* at_buf2 byte count */ 791 #define ATW_TXFLAG_TBS1_MASK BITS(11,0) /* at_buf1 byte count */ 792 793 /* Rx descriptor */ 794 struct atw_rxdesc { 795 u_int32_t ar_stat; 796 u_int32_t ar_ctl; 797 u_int32_t ar_buf1; 798 u_int32_t ar_buf2; 799 }; 800 801 #define ar_rssi ar_ctl 802 803 #define ATW_RXCTL_RER BIT(25) /* end of ring */ 804 #define ATW_RXCTL_RCH BIT(24) /* ar_buf2 is 2nd chain */ 805 #define ATW_RXCTL_RBS2_MASK BITS(23,12) /* ar_buf2 byte count */ 806 #define ATW_RXCTL_RBS1_MASK BITS(11,0) /* ar_buf1 byte count */ 807 808 #define ATW_RXSTAT_OWN BIT(31) /* 1: NIC may fill descriptor */ 809 #define ATW_RXSTAT_ES BIT(30) /* error summary, 0 on 810 * success 811 */ 812 #define ATW_RXSTAT_SQL BIT(29) /* has signal quality (?) */ 813 #define ATW_RXSTAT_DE BIT(28) /* descriptor error---packet is 814 * truncated. last descriptor 815 * only 816 */ 817 #define ATW_RXSTAT_FS BIT(27) /* packet's first descriptor */ 818 #define ATW_RXSTAT_LS BIT(26) /* packet's last descriptor */ 819 #define ATW_RXSTAT_PCF BIT(25) /* received during CFP */ 820 #define ATW_RXSTAT_SFDE BIT(24) /* PLCP SFD error */ 821 #define ATW_RXSTAT_SIGE BIT(23) /* PLCP signal error */ 822 #define ATW_RXSTAT_CRC16E BIT(22) /* PLCP CRC16 error */ 823 #define ATW_RXSTAT_RXTOE BIT(21) /* RX time-out, last descriptor 824 * only. 825 */ 826 #define ATW_RXSTAT_CRC32E BIT(20) /* CRC32 error */ 827 #define ATW_RXSTAT_ICVE BIT(19) /* WEP ICV error */ 828 #define ATW_RXSTAT_DA1 BIT(17) /* DA bit 1, admin'd address */ 829 #define ATW_RXSTAT_DA0 BIT(16) /* DA bit 0, group address */ 830 #define ATW_RXSTAT_RXDR_MASK BITS(15,12) /* RX data rate */ 831 #define ATW_RXSTAT_FL_MASK BITS(11,0) /* RX frame length, last 832 * descriptor only 833 */ 834 835 /* Static RAM (contains WEP keys, beacon content). Addresses and size 836 * are in 16-bit words. 837 */ 838 #define ATW_SRAM_ADDR_INDIVL_KEY 0x0 839 #define ATW_SRAM_ADDR_SHARED_KEY (0x160 * 2) 840 #define ATW_SRAM_ADDR_SSID (0x180 * 2) 841 #define ATW_SRAM_ADDR_SUPRATES (0x191 * 2) 842 #define ATW_SRAM_SIZE (0x200 * 2) 843
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