FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/atwvar.h
1 /* $NetBSD: atwvar.h,v 1.8 2004/01/29 10:25:49 dyoung Exp $ */
2
3 /*
4 * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved.
5 *
6 * This code is derived from software contributed to The NetBSD Foundation
7 * by David Young.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by the NetBSD
20 * Foundation, Inc. and its contributors.
21 * 4. Neither the name of the author nor the names of any co-contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL David Young
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
35 * THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #ifndef _DEV_IC_ATWVAR_H_
39 #define _DEV_IC_ATWVAR_H_
40
41 #include <sys/queue.h>
42 #include <sys/callout.h>
43 #include <sys/time.h>
44
45 /*
46 * Some misc. statics, useful for debugging.
47 */
48 struct atw_stats {
49 u_long ts_tx_tuf; /* transmit underflow errors */
50 u_long ts_tx_tro; /* transmit jabber timeouts */
51 u_long ts_tx_trt; /* retry count exceeded */
52 u_long ts_tx_tlt; /* lifetime exceeded */
53 u_long ts_tx_sofbr; /* packet size mismatch */
54 };
55
56 /*
57 * Transmit descriptor list size. This is arbitrary, but allocate
58 * enough descriptors for 64 pending transmissions and 16 segments
59 * per packet. Since a descriptor holds 2 buffer addresses, that's
60 * 8 descriptors per packet. This MUST work out to a power of 2.
61 */
62 #define ATW_NTXSEGS 16
63
64 #define ATW_TXQUEUELEN 64
65 #define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS)
66 #define ATW_NTXDESC_MASK (ATW_NTXDESC - 1)
67 #define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK)
68
69 /*
70 * Receive descriptor list size. We have one Rx buffer per incoming
71 * packet, so this logic is a little simpler.
72 */
73 #define ATW_NRXDESC 64
74 #define ATW_NRXDESC_MASK (ATW_NRXDESC - 1)
75 #define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK)
76
77 /*
78 * Control structures are DMA'd to the ADM8211 chip. We allocate them in
79 * a single clump that maps to a single DMA segment to make several things
80 * easier.
81 */
82 struct atw_control_data {
83 /*
84 * The transmit descriptors.
85 */
86 struct atw_txdesc acd_txdescs[ATW_NTXDESC];
87
88 /*
89 * The receive descriptors.
90 */
91 struct atw_rxdesc acd_rxdescs[ATW_NRXDESC];
92 };
93
94 #define ATW_CDOFF(x) offsetof(struct atw_control_data, x)
95 #define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)])
96 #define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)])
97 /*
98 * Software state for transmit jobs.
99 */
100 struct atw_txsoft {
101 struct mbuf *txs_mbuf; /* head of our mbuf chain */
102 bus_dmamap_t txs_dmamap; /* our DMA map */
103 int txs_firstdesc; /* first descriptor in packet */
104 int txs_lastdesc; /* last descriptor in packet */
105 int txs_ndescs; /* number of descriptors */
106 SIMPLEQ_ENTRY(atw_txsoft) txs_q;
107 };
108
109 SIMPLEQ_HEAD(atw_txsq, atw_txsoft);
110
111 /*
112 * Software state for receive jobs.
113 */
114 struct atw_rxsoft {
115 struct mbuf *rxs_mbuf; /* head of our mbuf chain */
116 bus_dmamap_t rxs_dmamap; /* our DMA map */
117 };
118
119 /*
120 * Table which describes the transmit threshold mode. We generally
121 * start at index 0. Whenever we get a transmit underrun, we increment
122 * our index, falling back if we encounter the NULL terminator.
123 */
124 struct atw_txthresh_tab {
125 u_int32_t txth_opmode; /* OPMODE bits */
126 const char *txth_name; /* name of mode */
127 };
128
129 #define ATW_TXTHRESH_TAB_LO_RATE { \
130 { ATW_NAR_TR_L64, "64 bytes" }, \
131 { ATW_NAR_TR_L160, "160 bytes" }, \
132 { ATW_NAR_TR_L192, "192 bytes" }, \
133 { ATW_NAR_SF, "store and forward" }, \
134 { 0, NULL }, \
135 }
136
137 #define ATW_TXTHRESH_TAB_HI_RATE { \
138 { ATW_NAR_TR_H96, "96 bytes" }, \
139 { ATW_NAR_TR_H288, "288 bytes" }, \
140 { ATW_NAR_TR_H544, "544 bytes" }, \
141 { ATW_NAR_SF, "store and forward" }, \
142 { 0, NULL }, \
143 }
144
145 enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1,
146 ATW_RFTYPE_MARVEL = 2 };
147
148 enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1,
149 ATW_BBPTYPE_MARVEL = 2 };
150
151 /* Radio capture format for ADMtek. */
152
153 #define ATW_RX_RADIOTAP_PRESENT \
154 ((1 << IEEE80211_RADIOTAP_FLAGS) | (1 << IEEE80211_RADIOTAP_RATE) | \
155 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
156 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL))
157
158 struct atw_rx_radiotap_header {
159 struct ieee80211_radiotap_header ar_ihdr;
160 u_int8_t ar_flags;
161 u_int8_t ar_rate;
162 u_int16_t ar_chan_freq;
163 u_int16_t ar_chan_flags;
164 u_int8_t ar_antsignal;
165 } __attribute__((__packed__));
166
167 #define ATW_TX_RADIOTAP_PRESENT ((1 << IEEE80211_RADIOTAP_FLAGS) | \
168 (1 << IEEE80211_RADIOTAP_RATE) | \
169 (1 << IEEE80211_RADIOTAP_CHANNEL))
170
171 struct atw_tx_radiotap_header {
172 struct ieee80211_radiotap_header at_ihdr;
173 u_int8_t at_flags;
174 u_int8_t at_rate;
175 u_int16_t at_chan_freq;
176 u_int16_t at_chan_flags;
177 } __attribute__((__packed__));
178
179 struct atw_softc {
180 struct device sc_dev;
181 struct ieee80211com sc_ic;
182 int (*sc_enable)(struct atw_softc *);
183 void (*sc_disable)(struct atw_softc *);
184 void (*sc_power)(struct atw_softc *, int);
185 int (*sc_newstate)(struct ieee80211com *,
186 enum ieee80211_state, int);
187 void (*sc_recv_mgmt)(struct ieee80211com *,
188 struct mbuf *, struct ieee80211_node *,
189 int, int, u_int32_t);
190 struct ieee80211_node *(*sc_node_alloc)(struct ieee80211com *);
191 void (*sc_node_free)(struct ieee80211com *,
192 struct ieee80211_node *);
193
194 struct atw_stats sc_stats; /* debugging stats */
195
196 int sc_tx_timer;
197 int sc_rescan_timer;
198
199 bus_space_tag_t sc_st; /* bus space tag */
200 bus_space_handle_t sc_sh; /* bus space handle */
201 bus_dma_tag_t sc_dmat; /* bus dma tag */
202 void *sc_sdhook; /* shutdown hook */
203 void *sc_powerhook; /* power management hook */
204 u_int32_t sc_cacheline; /* cache line size */
205 u_int32_t sc_maxburst; /* maximum burst length */
206
207 const struct atw_txthresh_tab *sc_txth;
208 int sc_txthresh; /* current tx threshold */
209
210 u_int sc_cur_chan; /* current channel */
211
212 int sc_flags;
213
214 u_int16_t *sc_srom;
215 u_int16_t sc_sromsz;
216
217 caddr_t sc_radiobpf;
218
219 bus_dma_segment_t sc_cdseg; /* control data memory */
220 int sc_cdnseg; /* number of segments */
221 bus_dmamap_t sc_cddmamap; /* control data DMA map */
222 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
223
224 /*
225 * Software state for transmit and receive descriptors.
226 */
227 struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN];
228 struct atw_rxsoft sc_rxsoft[ATW_NRXDESC];
229
230 /*
231 * Control data structures.
232 */
233 struct atw_control_data *sc_control_data;
234 #define sc_txdescs sc_control_data->acd_txdescs
235 #define sc_rxdescs sc_control_data->acd_rxdescs
236 #define sc_setup_desc sc_control_data->acd_setup_desc
237
238 int sc_txfree; /* number of free Tx descriptors */
239 int sc_txnext; /* next ready Tx descriptor */
240 int sc_ntxsegs; /* number of transmit segs per pkt */
241
242 struct atw_txsq sc_txfreeq; /* free Tx descsofts */
243 struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */
244
245 int sc_rxptr; /* next ready RX descriptor/descsoft */
246
247 u_int32_t sc_busmode; /* copy of ATW_PAR */
248 u_int32_t sc_opmode; /* copy of ATW_NAR */
249 u_int32_t sc_inten; /* copy of ATW_IER */
250 u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */
251
252 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */
253 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */
254 u_int32_t sc_linkint_mask;/* link-state interrupts mask */
255
256 /* interrupt acknowledge hook */
257 void (*sc_intr_ack)(struct atw_softc *);
258
259 enum atw_rftype sc_rftype;
260 enum atw_bbptype sc_bbptype;
261 u_int32_t sc_synctl_rd;
262 u_int32_t sc_synctl_wr;
263 u_int32_t sc_bbpctl_rd;
264 u_int32_t sc_bbpctl_wr;
265
266 void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *,
267 int, u_int32_t);
268 void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *,
269 int, u_int32_t);
270
271 /* ADM8211 state variables. */
272 u_int8_t sc_sram[ATW_SRAM_SIZE];
273 u_int8_t sc_bssid[IEEE80211_ADDR_LEN];
274 u_int8_t sc_lost_bcn_thresh;
275
276 struct timeval sc_last_beacon;
277 struct callout sc_scan_ch;
278 union {
279 struct atw_rx_radiotap_header tap;
280 u_int8_t pad[64];
281 } sc_rxtapu;
282 union {
283 struct atw_tx_radiotap_header tap;
284 u_int8_t pad[64];
285 } sc_txtapu;
286 };
287
288 #define sc_rxtap sc_rxtapu.tap
289 #define sc_txtap sc_txtapu.tap
290
291 #define sc_if sc_ic.ic_if
292
293 /* XXX this is fragile. try not to introduce any u_int32_t's. */
294 struct atw_frame {
295 /*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN];
296 /*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */
297 /*07*/ u_int8_t atw_service; /* 0 */
298 /*08*/ u_int16_t atw_paylen; /* payload length */
299 /*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame
300 * Control
301 */
302 /* 802.11 PLCP Length for first & last fragment */
303 /*0c*/ u_int16_t atw_tail_plcplen;
304 /*0e*/ u_int16_t atw_head_plcplen;
305 /* 802.11 Duration for first & last fragment */
306 /*10*/ u_int16_t atw_tail_dur;
307 /*12*/ u_int16_t atw_head_dur;
308 /*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN];
309 union {
310 struct {
311 /*1a*/ u_int16_t hdrctl; /*transmission control*/
312 /*1c*/ u_int16_t fragthr;/* fragmentation threshold
313 * [0:11], zero [12:15].
314 */
315 /*1e*/ u_int8_t fragnum;/* fragment number [4:7],
316 * zero [0:3].
317 */
318 /*1f*/ u_int8_t rtylmt; /* retry limit */
319 /*20*/ u_int8_t wepkey0[4];/* ??? */
320 /*24*/ u_int8_t wepkey1[4];/* ??? */
321 /*28*/ u_int8_t wepkey2[4];/* ??? */
322 /*2c*/ u_int8_t wepkey3[4];/* ??? */
323 /*30*/ u_int8_t keyid;
324 /*31*/ u_int8_t reserved0[7];
325 } s1;
326 struct {
327 u_int8_t pad[6];
328 struct ieee80211_frame ihdr;
329 } s2;
330 } u;
331 } __attribute__((__packed__));
332
333 #define atw_hdrctl u.s1.hdrctl
334 #define atw_fragthr u.s1.fragthr
335 #define atw_fragnum u.s1.fragnum
336 #define atw_rtylmt u.s1.rtylmt
337 #define atw_keyid u.s1.keyid
338 #define atw_ihdr u.s2.ihdr
339
340 #define ATW_HDRCTL_SHORT_PREAMBLE BIT(0) /* use short preamble */
341 #define ATW_HDRCTL_RTSCTS BIT(4) /* send RTS */
342 #define ATW_HDRCTL_WEP BIT(5)
343 #define ATW_HDRCTL_UNKNOWN1 BIT(15) /* MAC adds FCS? */
344 #define ATW_HDRCTL_UNKNOWN2 BIT(8)
345
346 #define ATW_FRAGTHR_FRAGTHR_MASK BITS(0, 11)
347 #define ATW_FRAGNUM_FRAGNUM_MASK BITS(4, 7)
348
349 /* Values for sc_flags. */
350 #define ATWF_MRL 0x00000010 /* memory read line okay */
351 #define ATWF_MRM 0x00000020 /* memory read multi okay */
352 #define ATWF_MWI 0x00000040 /* memory write inval okay */
353 #define ATWF_SHORT_PREAMBLE 0x00000080 /* short preamble enabled */
354 #define ATWF_RTSCTS 0x00000100 /* RTS/CTS enabled */
355 #define ATWF_ATTACHED 0x00000800 /* attach has succeeded */
356 #define ATWF_ENABLED 0x00001000 /* chip is enabled */
357
358 #define ATW_IS_ENABLED(sc) ((sc)->sc_flags & ATWF_ENABLED)
359
360 #define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x)))
361 #define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x)))
362
363 #define ATW_CDTXSYNC(sc, x, n, ops) \
364 do { \
365 int __x, __n; \
366 \
367 __x = (x); \
368 __n = (n); \
369 \
370 /* If it will wrap around, sync to the end of the ring. */ \
371 if ((__x + __n) > ATW_NTXDESC) { \
372 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
373 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \
374 (ATW_NTXDESC - __x), (ops)); \
375 __n -= (ATW_NTXDESC - __x); \
376 __x = 0; \
377 } \
378 \
379 /* Now sync whatever is left. */ \
380 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
381 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \
382 } while (0)
383
384 #define ATW_CDRXSYNC(sc, x, ops) \
385 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \
386 ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops))
387
388 /*
389 * Note we rely on MCLBYTES being a power of two. Because the `length'
390 * field is only 11 bits, we must subtract 1 from the length to avoid
391 * having it truncated to 0!
392 *
393 * Apparently we have to set ATW_RXSTAT_SQL to make the ADM8211 tell
394 * us RSSI.
395 */
396 #define ATW_INIT_RXDESC(sc, x) \
397 do { \
398 struct atw_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \
399 struct atw_rxdesc *__rxd = &sc->sc_rxdescs[(x)]; \
400 struct mbuf *__m = __rxs->rxs_mbuf; \
401 \
402 __m->m_data = __m->m_ext.ext_buf; \
403 __rxd->ar_buf1 = \
404 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \
405 __rxd->ar_buf2 = /* for descriptor chaining */ \
406 htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \
407 __rxd->ar_ctl = \
408 htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \
409 ATW_RXCTL_RBS1_MASK) | \
410 0 /* ATW_RXCTL_RCH */ | \
411 ((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \
412 __rxd->ar_stat = \
413 htole32(ATW_RXSTAT_OWN|ATW_RXSTAT_SQL|ATW_RXSTAT_FS| \
414 ATW_RXSTAT_LS); \
415 ATW_CDRXSYNC((sc), (x), \
416 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
417 } while (0)
418
419 /* country codes from ADM8211 SROM */
420 #define ATW_COUNTRY_FCC 0 /* USA 1-11 */
421 #define ATW_COUNTRY_IC 1 /* Canada 1-11 */
422 #define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */
423 #define ATW_COUNTRY_SPAIN 3 /* 10-11 */
424 #define ATW_COUNTRY_FRANCE 4 /* 10-13 */
425 #define ATW_COUNTRY_MKK 5 /* Japan: 14 */
426 #define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */
427
428 /* One Time Unit (TU) is 1Kus = 1024 microseconds. */
429 #define IEEE80211_DUR_TU 1024
430
431 /* IEEE 802.11b durations for DSSS PHY in microseconds */
432 #define IEEE80211_DUR_DS_LONG_PREAMBLE 144
433 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
434 #define IEEE80211_DUR_DS_FAST_PLCPHDR 24
435 #define IEEE80211_DUR_DS_SLOW_PLCPHDR 48
436 #define IEEE80211_DUR_DS_SLOW_ACK 112
437 #define IEEE80211_DUR_DS_FAST_ACK 56
438 #define IEEE80211_DUR_DS_SLOW_CTS 112
439 #define IEEE80211_DUR_DS_FAST_CTS 56
440 #define IEEE80211_DUR_DS_SLOT 20
441 #define IEEE80211_DUR_DS_SIFS 10
442 #define IEEE80211_DUR_DS_PIFS (IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT)
443 #define IEEE80211_DUR_DS_DIFS (IEEE80211_DUR_DS_SIFS + \
444 2 * IEEE80211_DUR_DS_SLOT)
445 #define IEEE80211_DUR_DS_EIFS (IEEE80211_DUR_DS_SIFS + \
446 IEEE80211_DUR_DS_SLOW_ACK + \
447 IEEE80211_DUR_DS_LONG_PREAMBLE + \
448 IEEE80211_DUR_DS_SLOW_PLCPHDR + \
449 IEEE80211_DUR_DIFS)
450
451 /*
452 * register space access macros
453 */
454 #define ATW_READ(sc, reg) \
455 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
456
457 #define ATW_WRITE(sc, reg, val) \
458 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
459
460 #define ATW_SET(sc, reg, mask) \
461 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))
462
463 #define ATW_CLR(sc, reg, mask) \
464 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))
465
466 #define ATW_ISSET(sc, reg, mask) \
467 (ATW_READ((sc), (reg)) & (mask))
468
469 void atw_attach(struct atw_softc *);
470 int atw_detach(struct atw_softc *);
471 int atw_activate(struct device *, enum devact);
472 int atw_intr(void *arg);
473 void atw_power(int, void *);
474 void atw_shutdown(void *);
475
476 #endif /* _DEV_IC_ATWVAR_H_ */
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