The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/atwvar.h

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    1 /*      $NetBSD: atwvar.h,v 1.22 2006/08/31 19:24:37 dyoung Exp $       */
    2 
    3 /*
    4  * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc.  All rights reserved.
    5  *
    6  * This code is derived from software contributed to The NetBSD Foundation
    7  * by David Young.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed by the NetBSD
   20  *      Foundation, Inc. and its contributors.
   21  * 4. Neither the name of the author nor the names of any co-contributors
   22  *    may be used to endorse or promote products derived from this software
   23  *    without specific prior written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   27  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   28  * ARE DISCLAIMED.  IN NO EVENT SHALL David Young
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   35  * THE POSSIBILITY OF SUCH DAMAGE.
   36  */
   37 
   38 #ifndef _DEV_IC_ATWVAR_H_
   39 #define _DEV_IC_ATWVAR_H_
   40 
   41 #include <sys/queue.h>
   42 #include <sys/callout.h>
   43 #include <sys/time.h>
   44 
   45 /*
   46  * Some misc. statics, useful for debugging.
   47  */
   48 struct atw_stats {
   49         u_long          ts_tx_tuf;      /* transmit underflow errors */
   50         u_long          ts_tx_tro;      /* transmit jabber timeouts */
   51         u_long          ts_tx_trt;      /* retry count exceeded */
   52         u_long          ts_tx_tlt;      /* lifetime exceeded */
   53         u_long          ts_tx_sofbr;    /* packet size mismatch */
   54 };
   55 
   56 /*
   57  * Transmit descriptor list size.  This is arbitrary, but allocate
   58  * enough descriptors for 64 pending transmissions and 16 segments
   59  * per packet.  Since a descriptor holds 2 buffer addresses, that's
   60  * 8 descriptors per packet.  This MUST work out to a power of 2.
   61  */
   62 #define ATW_NTXSEGS             16
   63 
   64 #define ATW_TXQUEUELEN  64
   65 #define ATW_NTXDESC             (ATW_TXQUEUELEN * ATW_NTXSEGS)
   66 #define ATW_NTXDESC_MASK        (ATW_NTXDESC - 1)
   67 #define ATW_NEXTTX(x)           ((x + 1) & ATW_NTXDESC_MASK)
   68 
   69 /*
   70  * Receive descriptor list size.  We have one Rx buffer per incoming
   71  * packet, so this logic is a little simpler.
   72  */
   73 #define ATW_NRXDESC             64
   74 #define ATW_NRXDESC_MASK        (ATW_NRXDESC - 1)
   75 #define ATW_NEXTRX(x)           ((x + 1) & ATW_NRXDESC_MASK)
   76 
   77 /*
   78  * Control structures are DMA'd to the ADM8211 chip.  We allocate them in
   79  * a single clump that maps to a single DMA segment to make several things
   80  * easier.
   81  */
   82 struct atw_control_data {
   83         /*
   84          * The transmit descriptors.
   85          */
   86         struct atw_txdesc acd_txdescs[ATW_NTXDESC];
   87 
   88         /*
   89          * The receive descriptors.
   90          */
   91         struct atw_rxdesc acd_rxdescs[ATW_NRXDESC];
   92 };
   93 
   94 #define ATW_CDOFF(x)            offsetof(struct atw_control_data, x)
   95 #define ATW_CDTXOFF(x)  ATW_CDOFF(acd_txdescs[(x)])
   96 #define ATW_CDRXOFF(x)  ATW_CDOFF(acd_rxdescs[(x)])
   97 /*
   98  * Software state for transmit jobs.
   99  */
  100 struct atw_txsoft {
  101         struct mbuf *txs_mbuf;          /* head of our mbuf chain */
  102         bus_dmamap_t txs_dmamap;        /* our DMA map */
  103         int txs_firstdesc;              /* first descriptor in packet */
  104         int txs_lastdesc;               /* last descriptor in packet */
  105         int txs_ndescs;                 /* number of descriptors */
  106         struct ieee80211_duration       txs_d0;
  107         struct ieee80211_duration       txs_dn;
  108         SIMPLEQ_ENTRY(atw_txsoft) txs_q;
  109 };
  110 
  111 SIMPLEQ_HEAD(atw_txsq, atw_txsoft);
  112 
  113 /*
  114  * Software state for receive jobs.
  115  */
  116 struct atw_rxsoft {
  117         struct mbuf *rxs_mbuf;          /* head of our mbuf chain */
  118         bus_dmamap_t rxs_dmamap;        /* our DMA map */
  119 };
  120 
  121 /*
  122  * Table which describes the transmit threshold mode.  We generally
  123  * start at index 0.  Whenever we get a transmit underrun, we increment
  124  * our index, falling back if we encounter the NULL terminator.
  125  */
  126 struct atw_txthresh_tab {
  127         u_int32_t txth_opmode;          /* OPMODE bits */
  128         const char *txth_name;          /* name of mode */
  129 };
  130 
  131 #define ATW_TXTHRESH_TAB_LO_RATE {                                      \
  132         { ATW_NAR_TR_L64,       "64 bytes" },                           \
  133         { ATW_NAR_TR_L160,      "160 bytes" },                          \
  134         { ATW_NAR_TR_L192,      "192 bytes" },                          \
  135         { ATW_NAR_SF,           "store and forward" },                  \
  136         { 0,                    NULL },                                 \
  137 }
  138 
  139 #define ATW_TXTHRESH_TAB_HI_RATE {                                      \
  140         { ATW_NAR_TR_H96,       "96 bytes" },                           \
  141         { ATW_NAR_TR_H288,      "288 bytes" },                          \
  142         { ATW_NAR_TR_H544,      "544 bytes" },                          \
  143         { ATW_NAR_SF,           "store and forward" },                  \
  144         { 0,                    NULL },                                 \
  145 }
  146 
  147 enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD  = 1,
  148        ATW_RFTYPE_MARVEL = 2 };
  149 
  150 enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD  = 1,
  151        ATW_BBPTYPE_MARVEL = 2, ATW_C_BBPTYPE_RFMD  = 5 };
  152 
  153 /* Radio capture format for ADMtek. */
  154 
  155 #define ATW_RX_RADIOTAP_PRESENT \
  156         ((1 << IEEE80211_RADIOTAP_FLAGS) | (1 << IEEE80211_RADIOTAP_RATE) | \
  157          (1 << IEEE80211_RADIOTAP_CHANNEL) | \
  158          (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL))
  159 
  160 struct atw_rx_radiotap_header {
  161         struct ieee80211_radiotap_header        ar_ihdr;
  162         u_int8_t                                ar_flags;
  163         u_int8_t                                ar_rate;
  164         u_int16_t                               ar_chan_freq;
  165         u_int16_t                               ar_chan_flags;
  166         u_int8_t                                ar_antsignal;
  167 } __attribute__((__packed__));
  168 
  169 #define ATW_TX_RADIOTAP_PRESENT ((1 << IEEE80211_RADIOTAP_FLAGS) | \
  170                                  (1 << IEEE80211_RADIOTAP_RATE) | \
  171                                  (1 << IEEE80211_RADIOTAP_CHANNEL))
  172 
  173 struct atw_tx_radiotap_header {
  174         struct ieee80211_radiotap_header        at_ihdr;
  175         u_int8_t                                at_flags;
  176         u_int8_t                                at_rate;
  177         u_int16_t                               at_chan_freq;
  178         u_int16_t                               at_chan_flags;
  179 } __attribute__((__packed__));
  180 
  181 enum atw_revision {
  182         ATW_REVISION_AB = 0x11, /* ADM8211A */
  183         ATW_REVISION_AF = 0x15, /* ADM8211A? */
  184         ATW_REVISION_BA = 0x20, /* ADM8211B */
  185         ATW_REVISION_CA = 0x30  /* ADM8211C/CR */
  186 };
  187 
  188 struct atw_softc {
  189         struct device           sc_dev;
  190         struct ethercom         sc_ec;
  191         struct ieee80211com     sc_ic;
  192         int                     (*sc_enable)(struct atw_softc *);
  193         void                    (*sc_disable)(struct atw_softc *);
  194         void                    (*sc_power)(struct atw_softc *, int);
  195         int                     (*sc_newstate)(struct ieee80211com *,
  196                                         enum ieee80211_state, int);
  197         void                    (*sc_recv_mgmt)(struct ieee80211com *,
  198                                     struct mbuf *, struct ieee80211_node *,
  199                                     int, int, u_int32_t);
  200         struct ieee80211_node   *(*sc_node_alloc)(struct ieee80211_node_table*);
  201         void                    (*sc_node_free)(struct ieee80211_node *);
  202 
  203         struct atw_stats sc_stats;      /* debugging stats */
  204 
  205         int                     sc_tx_timer;
  206         int                     sc_rescan_timer;
  207 
  208         bus_space_tag_t         sc_st;          /* bus space tag */
  209         bus_space_handle_t      sc_sh;          /* bus space handle */
  210         bus_dma_tag_t           sc_dmat;        /* bus dma tag */
  211         void                    *sc_sdhook;     /* shutdown hook */
  212         void                    *sc_powerhook;  /* power management hook */
  213         u_int32_t               sc_cacheline;   /* cache line size */
  214         u_int32_t               sc_maxburst;    /* maximum burst length */
  215 
  216         const struct atw_txthresh_tab   *sc_txth;
  217         int                             sc_txthresh; /* current tx threshold */
  218 
  219         u_int                   sc_cur_chan;    /* current channel */
  220 
  221         int                     sc_flags;
  222 
  223         u_int16_t               *sc_srom;
  224         u_int16_t               sc_sromsz;
  225 
  226         caddr_t                 sc_radiobpf;
  227 
  228         bus_dma_segment_t       sc_cdseg;       /* control data memory */
  229         int                     sc_cdnseg;      /* number of segments */
  230         bus_dmamap_t            sc_cddmamap;    /* control data DMA map */
  231 #define sc_cddma        sc_cddmamap->dm_segs[0].ds_addr
  232 
  233         /*
  234          * Software state for transmit and receive descriptors.
  235          */
  236         struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN];
  237         struct atw_rxsoft sc_rxsoft[ATW_NRXDESC];
  238 
  239         /*
  240          * Control data structures.
  241          */
  242         struct atw_control_data *sc_control_data;
  243 #define sc_txdescs      sc_control_data->acd_txdescs
  244 #define sc_rxdescs      sc_control_data->acd_rxdescs
  245 #define sc_setup_desc   sc_control_data->acd_setup_desc
  246 
  247         int     sc_txfree;              /* number of free Tx descriptors */
  248         int     sc_txnext;              /* next ready Tx descriptor */
  249         int     sc_ntxsegs;             /* number of transmit segs per pkt */
  250 
  251         struct atw_txsq sc_txfreeq;     /* free Tx descsofts */
  252         struct atw_txsq sc_txdirtyq;    /* dirty Tx descsofts */
  253 
  254         int     sc_rxptr;               /* next ready RX descriptor/descsoft */
  255 
  256         u_int32_t       sc_busmode;     /* copy of ATW_PAR */
  257         u_int32_t       sc_opmode;      /* copy of ATW_NAR */
  258         u_int32_t       sc_inten;       /* copy of ATW_IER */
  259         u_int32_t       sc_wepctl;      /* copy of ATW_WEPCTL */
  260 
  261         u_int32_t       sc_rxint_mask;  /* mask of Rx interrupts we want */
  262         u_int32_t       sc_txint_mask;  /* mask of Tx interrupts we want */
  263         u_int32_t       sc_linkint_mask;/* link-state interrupts mask */
  264 
  265         /* interrupt acknowledge hook */
  266         void (*sc_intr_ack)(struct atw_softc *);
  267 
  268         enum atw_rftype         sc_rftype;
  269         enum atw_bbptype        sc_bbptype;
  270         u_int32_t       sc_synctl_rd;
  271         u_int32_t       sc_synctl_wr;
  272         u_int32_t       sc_bbpctl_rd;
  273         u_int32_t       sc_bbpctl_wr;
  274 
  275         void            (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *,
  276                             int, u_int32_t);
  277         void            (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *,
  278                             int, u_int32_t);
  279 
  280         /* ADM8211 state variables. */
  281         u_int8_t        sc_sram[ATW_SRAM_MAXSIZE];
  282         u_int           sc_sramlen;
  283         u_int8_t        sc_bssid[IEEE80211_ADDR_LEN];
  284         uint8_t         sc_rev;
  285         uint8_t         sc_rf3000_options1;
  286         uint8_t         sc_rf3000_options2;
  287 
  288         struct callout  sc_scan_ch;
  289         union {
  290                 struct atw_rx_radiotap_header   tap;
  291                 u_int8_t                        pad[64];
  292         } sc_rxtapu;
  293         union {
  294                 struct atw_tx_radiotap_header   tap;
  295                 u_int8_t                        pad[64];
  296         } sc_txtapu;
  297 };
  298 
  299 #define sc_if           sc_ec.ec_if
  300 #define sc_rxtap        sc_rxtapu.tap
  301 #define sc_txtap        sc_txtapu.tap
  302 
  303 /* XXX this is fragile. try not to introduce any u_int32_t's. */
  304 struct atw_frame {
  305 /*00*/  u_int8_t                        atw_dst[IEEE80211_ADDR_LEN];
  306 /*06*/  u_int8_t                        atw_rate;       /* TX rate in 100Kbps */
  307 /*07*/  u_int8_t                        atw_service;    /* 0 */
  308 /*08*/  u_int16_t                       atw_paylen;     /* payload length */
  309 /*0a*/  u_int8_t                        atw_fc[2];      /* 802.11 Frame
  310                                                          * Control
  311                                                          */
  312         /* 802.11 PLCP Length for first & last fragment */
  313 /*0c*/  u_int16_t                       atw_tail_plcplen;
  314 /*0e*/  u_int16_t                       atw_head_plcplen;
  315         /* 802.11 Duration for first & last fragment */
  316 /*10*/  u_int16_t                       atw_tail_dur;
  317 /*12*/  u_int16_t                       atw_head_dur;
  318 /*14*/  u_int8_t                        atw_addr4[IEEE80211_ADDR_LEN];
  319         union {
  320                 struct {
  321 /*1a*/                  u_int16_t       hdrctl; /*transmission control*/
  322 /*1c*/                  u_int16_t       fragthr;/* fragmentation threshold
  323                                                  * [0:11], zero [12:15].
  324                                                  */
  325 /*1e*/                  u_int8_t        fragnum;/* fragment number [4:7],
  326                                                  * zero [0:3].
  327                                                  */
  328 /*1f*/                  u_int8_t        rtylmt; /* retry limit */
  329 /*20*/                  u_int8_t        wepkey0[4];/* ??? */
  330 /*24*/                  u_int8_t        wepkey1[4];/* ??? */
  331 /*28*/                  u_int8_t        wepkey2[4];/* ??? */
  332 /*2c*/                  u_int8_t        wepkey3[4];/* ??? */
  333 /*30*/                  u_int8_t        keyid;
  334 /*31*/                  u_int8_t        reserved0[7];
  335                 } s1;
  336                 struct {
  337                         u_int8_t                pad[6];
  338                         struct ieee80211_frame  ihdr;
  339                 } s2;
  340         } u;
  341 } __attribute__((__packed__));
  342 
  343 #define atw_hdrctl      u.s1.hdrctl
  344 #define atw_fragthr     u.s1.fragthr
  345 #define atw_fragnum     u.s1.fragnum
  346 #define atw_rtylmt      u.s1.rtylmt
  347 #define atw_keyid       u.s1.keyid
  348 #define atw_ihdr        u.s2.ihdr
  349 
  350 #define ATW_HDRCTL_SHORT_PREAMBLE       __BIT(0)        /* use short preamble */
  351 #define ATW_HDRCTL_RTSCTS               __BIT(4)        /* send RTS */
  352 #define ATW_HDRCTL_WEP                  __BIT(5)
  353 #define ATW_HDRCTL_UNKNOWN1             __BIT(15) /* MAC adds FCS? */
  354 #define ATW_HDRCTL_UNKNOWN2             __BIT(8)
  355 
  356 #define ATW_FRAGTHR_FRAGTHR_MASK        __BITS(0, 11)
  357 #define ATW_FRAGNUM_FRAGNUM_MASK        __BITS(4, 7)
  358 
  359 /* Values for sc_flags. */
  360 #define ATWF_MRL                0x00000001      /* memory read line okay */
  361 #define ATWF_MRM                0x00000002      /* memory read multi okay */
  362 #define ATWF_MWI                0x00000004      /* memory write inval okay */
  363 #define ATWF_SHORT_PREAMBLE     0x00000008      /* short preamble enabled */
  364 #define ATWF_RTSCTS             0x00000010      /* RTS/CTS enabled */
  365 #define ATWF_ATTACHED           0x00000020      /* attach has succeeded */
  366 #define ATWF_ENABLED            0x00000040      /* chip is enabled */
  367 #define ATWF_WEP_SRAM_VALID     0x00000080      /* SRAM matches s/w state */
  368 
  369 #define ATW_IS_ENABLED(sc)      ((sc)->sc_flags & ATWF_ENABLED)
  370 
  371 #define ATW_CDTXADDR(sc, x)     ((sc)->sc_cddma + ATW_CDTXOFF((x)))
  372 #define ATW_CDRXADDR(sc, x)     ((sc)->sc_cddma + ATW_CDRXOFF((x)))
  373 
  374 #define ATW_CDTXSYNC(sc, x, n, ops)                                     \
  375 do {                                                                    \
  376         int __x, __n;                                                   \
  377                                                                         \
  378         __x = (x);                                                      \
  379         __n = (n);                                                      \
  380                                                                         \
  381         /* If it will wrap around, sync to the end of the ring. */      \
  382         if ((__x + __n) > ATW_NTXDESC) {                                \
  383                 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,       \
  384                     ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) *       \
  385                     (ATW_NTXDESC - __x), (ops));                        \
  386                 __n -= (ATW_NTXDESC - __x);                             \
  387                 __x = 0;                                                \
  388         }                                                               \
  389                                                                         \
  390         /* Now sync whatever is left. */                                \
  391         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  392             ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \
  393 } while (0)
  394 
  395 #define ATW_CDRXSYNC(sc, x, ops)                                        \
  396         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  397             ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops))
  398 
  399 /*
  400  * Note we rely on MCLBYTES being a power of two.  Because the `length'
  401  * field is only 11 bits, we must subtract 1 from the length to avoid
  402  * having it truncated to 0!
  403  */
  404 #define ATW_INIT_RXDESC(sc, x)                                          \
  405 do {                                                                    \
  406         struct atw_rxsoft *__rxs = &sc->sc_rxsoft[(x)];                 \
  407         struct atw_rxdesc *__rxd = &sc->sc_rxdescs[(x)];                \
  408         struct mbuf *__m = __rxs->rxs_mbuf;                             \
  409                                                                         \
  410         __rxd->ar_buf1 =                                                \
  411             htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr);             \
  412         __rxd->ar_buf2 =        /* for descriptor chaining */           \
  413             htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x))));               \
  414         __rxd->ar_ctl =                                                 \
  415             htole32(__SHIFTIN(((__m->m_ext.ext_size - 1) & ~0x3U),      \
  416                            ATW_RXCTL_RBS1_MASK) |                       \
  417                     0 /* ATW_RXCTL_RCH */ |                             \
  418             ((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0));            \
  419         __rxd->ar_stat = htole32(ATW_RXSTAT_OWN);                       \
  420                                                                         \
  421         ATW_CDRXSYNC((sc), (x),                                         \
  422             BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);                  \
  423 } while (0)
  424 
  425 /* country codes from ADM8211 SROM */
  426 #define ATW_COUNTRY_FCC 0               /* USA 1-11 */
  427 #define ATW_COUNTRY_IC 1                /* Canada 1-11 */
  428 #define ATW_COUNTRY_ETSI 2              /* European Union (?) 1-13 */
  429 #define ATW_COUNTRY_SPAIN 3             /* 10-11 */
  430 #define ATW_COUNTRY_FRANCE 4            /* 10-13 */
  431 #define ATW_COUNTRY_MKK 5               /* Japan: 14 */
  432 #define ATW_COUNTRY_MKK2 6              /* Japan: 1-14 */
  433 
  434 /*
  435  * register space access macros
  436  */
  437 #define ATW_READ(sc, reg)                                               \
  438         bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
  439 
  440 #define ATW_WRITE(sc, reg, val)                                 \
  441         bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
  442 
  443 #define ATW_SET(sc, reg, mask)                                  \
  444         ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask))
  445 
  446 #define ATW_CLR(sc, reg, mask)                                  \
  447         ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask))
  448 
  449 #define ATW_ISSET(sc, reg, mask)                                        \
  450         (ATW_READ((sc), (reg)) & (mask))
  451 
  452 void    atw_attach(struct atw_softc *);
  453 int     atw_detach(struct atw_softc *);
  454 int     atw_activate(struct device *, enum devact);
  455 int     atw_intr(void *arg);
  456 void    atw_power(int, void *);
  457 void    atw_shutdown(void *);
  458 
  459 #endif /* _DEV_IC_ATWVAR_H_ */

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