Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/atwvar.h
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1 /* $OpenBSD: atwvar.h,v 1.26 2013/12/06 21:03:02 deraadt Exp $ */ 2 /* $NetBSD: atwvar.h,v 1.13 2004/07/23 07:07:55 dyoung Exp $ */ 3 4 /* 5 * Copyright (c) 2003, 2004 The NetBSD Foundation, Inc. All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL David Young 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _DEV_IC_ATWVAR_H_ 33 #define _DEV_IC_ATWVAR_H_ 34 35 #include <sys/queue.h> 36 #include <sys/time.h> 37 #include <sys/timeout.h> 38 39 /* 40 * Some misc. statics, useful for debugging. 41 */ 42 struct atw_stats { 43 u_long ts_tx_tuf; /* transmit underflow errors */ 44 u_long ts_tx_tro; /* transmit jabber timeouts */ 45 u_long ts_tx_trt; /* retry count exceeded */ 46 u_long ts_tx_tlt; /* lifetime exceeded */ 47 u_long ts_tx_sofbr; /* packet size mismatch */ 48 }; 49 50 /* 51 * Transmit descriptor list size. This is arbitrary, but allocate 52 * enough descriptors for 64 pending transmissions and 16 segments 53 * per packet. Since a descriptor holds 2 buffer addresses, that's 54 * 8 descriptors per packet. This MUST work out to a power of 2. 55 */ 56 #define ATW_NTXSEGS 16 57 58 #define ATW_TXQUEUELEN 64 59 #define ATW_NTXDESC (ATW_TXQUEUELEN * ATW_NTXSEGS) 60 #define ATW_NTXDESC_MASK (ATW_NTXDESC - 1) 61 #define ATW_NEXTTX(x) ((x + 1) & ATW_NTXDESC_MASK) 62 63 /* 64 * Receive descriptor list size. We have one Rx buffer per incoming 65 * packet, so this logic is a little simpler. 66 */ 67 #define ATW_NRXDESC 64 68 #define ATW_NRXDESC_MASK (ATW_NRXDESC - 1) 69 #define ATW_NEXTRX(x) ((x + 1) & ATW_NRXDESC_MASK) 70 71 /* 72 * Control structures are DMA'd to the ADM8211 chip. We allocate them in 73 * a single clump that maps to a single DMA segment to make several things 74 * easier. 75 */ 76 struct atw_control_data { 77 /* 78 * The transmit descriptors. 79 */ 80 struct atw_txdesc acd_txdescs[ATW_NTXDESC]; 81 82 /* 83 * The receive descriptors. 84 */ 85 struct atw_rxdesc acd_rxdescs[ATW_NRXDESC]; 86 }; 87 88 #define ATW_CDOFF(x) offsetof(struct atw_control_data, x) 89 #define ATW_CDTXOFF(x) ATW_CDOFF(acd_txdescs[(x)]) 90 #define ATW_CDRXOFF(x) ATW_CDOFF(acd_rxdescs[(x)]) 91 92 struct atw_duration { 93 uint16_t d_rts_dur; 94 uint16_t d_data_dur; 95 uint16_t d_plcp_len; 96 uint8_t d_residue; /* unused octets in time slot */ 97 }; 98 99 /* 100 * Software state for transmit jobs. 101 */ 102 struct atw_txsoft { 103 struct mbuf *txs_mbuf; /* head of our mbuf chain */ 104 bus_dmamap_t txs_dmamap; /* our DMA map */ 105 int txs_firstdesc; /* first descriptor in packet */ 106 int txs_lastdesc; /* last descriptor in packet */ 107 int txs_ndescs; /* number of descriptors */ 108 struct atw_duration txs_d0; 109 struct atw_duration txs_dn; 110 SIMPLEQ_ENTRY(atw_txsoft) txs_q; 111 }; 112 113 SIMPLEQ_HEAD(atw_txsq, atw_txsoft); 114 115 /* 116 * Software state for receive jobs. 117 */ 118 struct atw_rxsoft { 119 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 120 bus_dmamap_t rxs_dmamap; /* our DMA map */ 121 }; 122 123 /* 124 * Table which describes the transmit threshold mode. We generally 125 * start at index 0. Whenever we get a transmit underrun, we increment 126 * our index, falling back if we encounter the NULL terminator. 127 */ 128 struct atw_txthresh_tab { 129 u_int32_t txth_opmode; /* OPMODE bits */ 130 const char *txth_name; /* name of mode */ 131 }; 132 133 enum atw_rftype { ATW_RFTYPE_INTERSIL = 0, ATW_RFTYPE_RFMD = 1, 134 ATW_RFTYPE_MARVEL = 2 }; 135 136 enum atw_bbptype { ATW_BBPTYPE_INTERSIL = 0, ATW_BBPTYPE_RFMD = 1, 137 ATW_BBPTYPE_MARVEL = 2, ATW_C_BBPTYPE_RFMD = 5 }; 138 139 /* Radio capture format for ADMtek. */ 140 141 #define ATW_RX_RADIOTAP_PRESENT \ 142 ((1 << IEEE80211_RADIOTAP_FLAGS) | (1 << IEEE80211_RADIOTAP_RATE) | \ 143 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 144 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL)) 145 146 struct atw_rx_radiotap_header { 147 struct ieee80211_radiotap_header ar_ihdr; 148 u_int8_t ar_flags; 149 u_int8_t ar_rate; 150 u_int16_t ar_chan_freq; 151 u_int16_t ar_chan_flags; 152 u_int8_t ar_antsignal; 153 } __packed; 154 155 #define ATW_TX_RADIOTAP_PRESENT ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 156 (1 << IEEE80211_RADIOTAP_RATE) | \ 157 (1 << IEEE80211_RADIOTAP_CHANNEL)) 158 159 struct atw_tx_radiotap_header { 160 struct ieee80211_radiotap_header at_ihdr; 161 u_int8_t at_flags; 162 u_int8_t at_rate; 163 u_int16_t at_chan_freq; 164 u_int16_t at_chan_flags; 165 } __packed; 166 167 enum atw_revision { 168 ATW_REVISION_AB = 0x11, /* ADM8211A */ 169 ATW_REVISION_AF = 0x15, /* ADM8211A? */ 170 ATW_REVISION_BA = 0x20, /* ADM8211B */ 171 ATW_REVISION_CA = 0x30 /* ADM8211C/CR */ 172 }; 173 174 struct atw_softc { 175 struct device sc_dev; 176 struct ieee80211com sc_ic; 177 int (*sc_enable)(struct atw_softc *); 178 void (*sc_disable)(struct atw_softc *); 179 void (*sc_power)(struct atw_softc *, int); 180 int (*sc_newstate)(struct ieee80211com *, 181 enum ieee80211_state, int); 182 void (*sc_recv_mgmt)(struct ieee80211com *, 183 struct mbuf *, struct ieee80211_node *, 184 struct ieee80211_rxinfo *, int); 185 struct ieee80211_node *(*sc_node_alloc)(struct ieee80211com *); 186 void (*sc_node_free)(struct ieee80211com *, 187 struct ieee80211_node *); 188 189 struct atw_stats sc_stats; /* debugging stats */ 190 191 int sc_tx_timer; 192 int sc_rescan_timer; 193 194 bus_space_tag_t sc_st; /* bus space tag */ 195 bus_space_handle_t sc_sh; /* bus space handle */ 196 bus_size_t sc_mapsize; /* mapping size */ 197 bus_dma_tag_t sc_dmat; /* bus dma tag */ 198 u_int32_t sc_cacheline; /* cache line size */ 199 u_int32_t sc_maxburst; /* maximum burst length */ 200 201 const struct atw_txthresh_tab *sc_txth; 202 int sc_txthresh; /* current tx threshold */ 203 204 u_int sc_cur_chan; /* current channel */ 205 206 int sc_flags; 207 208 u_int16_t *sc_srom; 209 u_int16_t sc_sromsz; 210 211 caddr_t sc_radiobpf; 212 213 bus_dma_segment_t sc_cdseg; /* control data memory */ 214 int sc_cdnseg; /* number of segments */ 215 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 216 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 217 218 /* 219 * Software state for transmit and receive descriptors. 220 */ 221 struct atw_txsoft sc_txsoft[ATW_TXQUEUELEN]; 222 struct atw_rxsoft sc_rxsoft[ATW_NRXDESC]; 223 224 /* 225 * Control data structures. 226 */ 227 struct atw_control_data *sc_control_data; 228 #define sc_txdescs sc_control_data->acd_txdescs 229 #define sc_rxdescs sc_control_data->acd_rxdescs 230 #define sc_setup_desc sc_control_data->acd_setup_desc 231 232 int sc_txfree; /* number of free Tx descriptors */ 233 int sc_txnext; /* next ready Tx descriptor */ 234 int sc_ntxsegs; /* number of transmit segs per pkt */ 235 236 struct atw_txsq sc_txfreeq; /* free Tx descsofts */ 237 struct atw_txsq sc_txdirtyq; /* dirty Tx descsofts */ 238 239 int sc_rxptr; /* next ready RX descriptor/descsoft */ 240 241 u_int32_t sc_busmode; /* copy of ATW_PAR */ 242 u_int32_t sc_opmode; /* copy of ATW_NAR */ 243 u_int32_t sc_inten; /* copy of ATW_IER */ 244 u_int32_t sc_wepctl; /* copy of ATW_WEPCTL */ 245 246 u_int32_t sc_rxint_mask; /* mask of Rx interrupts we want */ 247 u_int32_t sc_txint_mask; /* mask of Tx interrupts we want */ 248 u_int32_t sc_linkint_mask;/* link-state interrupts mask */ 249 250 enum atw_rftype sc_rftype; 251 enum atw_bbptype sc_bbptype; 252 u_int32_t sc_synctl_rd; 253 u_int32_t sc_synctl_wr; 254 u_int32_t sc_bbpctl_rd; 255 u_int32_t sc_bbpctl_wr; 256 257 void (*sc_recv_beacon)(struct ieee80211com *, struct mbuf *, 258 int, u_int32_t); 259 void (*sc_recv_prresp)(struct ieee80211com *, struct mbuf *, 260 int, u_int32_t); 261 262 /* ADM8211 state variables. */ 263 u_int8_t sc_sram[ATW_SRAM_MAXSIZE]; 264 u_int sc_sramlen; 265 u_int8_t sc_bssid[IEEE80211_ADDR_LEN]; 266 u_int8_t sc_rev; 267 u_int8_t sc_rf3000_options1; 268 u_int8_t sc_rf3000_options2; 269 270 struct timeval sc_last_beacon; 271 struct timeout sc_scan_to; 272 union { 273 struct atw_rx_radiotap_header tap; 274 u_int8_t pad[64]; 275 } sc_rxtapu; 276 union { 277 struct atw_tx_radiotap_header tap; 278 u_int8_t pad[64]; 279 } sc_txtapu; 280 }; 281 282 #define sc_rxtap sc_rxtapu.tap 283 #define sc_txtap sc_txtapu.tap 284 285 #define sc_if sc_ic.ic_if 286 287 /* XXX this is fragile. try not to introduce any u_int32_t's. */ 288 struct atw_frame { 289 /*00*/ u_int8_t atw_dst[IEEE80211_ADDR_LEN]; 290 /*06*/ u_int8_t atw_rate; /* TX rate in 100Kbps */ 291 /*07*/ u_int8_t atw_service; /* 0 */ 292 /*08*/ u_int16_t atw_paylen; /* payload length */ 293 /*0a*/ u_int8_t atw_fc[2]; /* 802.11 Frame 294 * Control 295 */ 296 /* 802.11 PLCP Length for first & last fragment */ 297 /*0c*/ u_int16_t atw_tail_plcplen; 298 /*0e*/ u_int16_t atw_head_plcplen; 299 /* 802.11 Duration for first & last fragment */ 300 /*10*/ u_int16_t atw_tail_dur; 301 /*12*/ u_int16_t atw_head_dur; 302 /*14*/ u_int8_t atw_addr4[IEEE80211_ADDR_LEN]; 303 union { 304 struct { 305 /*1a*/ u_int16_t hdrctl; /*transmission control*/ 306 /*1c*/ u_int16_t fragthr;/* fragmentation threshold 307 * [0:11], zero [12:15]. 308 */ 309 /*1e*/ u_int8_t fragnum;/* fragment number [4:7], 310 * zero [0:3]. 311 */ 312 /*1f*/ u_int8_t rtylmt; /* retry limit */ 313 /*20*/ u_int8_t wepkey0[4];/* ??? */ 314 /*24*/ u_int8_t wepkey1[4];/* ??? */ 315 /*28*/ u_int8_t wepkey2[4];/* ??? */ 316 /*2c*/ u_int8_t wepkey3[4];/* ??? */ 317 /*30*/ u_int8_t keyid; 318 /*31*/ u_int8_t reserved0[7]; 319 } s1; 320 struct { 321 u_int8_t pad[6]; 322 struct ieee80211_frame ihdr; 323 } s2; 324 } u; 325 } __packed; 326 327 #define atw_hdrctl u.s1.hdrctl 328 #define atw_fragthr u.s1.fragthr 329 #define atw_fragnum u.s1.fragnum 330 #define atw_rtylmt u.s1.rtylmt 331 #define atw_keyid u.s1.keyid 332 #define atw_ihdr u.s2.ihdr 333 334 #define ATW_HDRCTL_SHORT_PREAMBLE (1<<0) /* use short preamble */ 335 #define ATW_HDRCTL_RTSCTS (1<<4) /* send RTS */ 336 #define ATW_HDRCTL_WEP (1<<5) 337 #define ATW_HDRCTL_UNKNOWN1 (1<<15) /* MAC adds FCS? */ 338 #define ATW_HDRCTL_UNKNOWN2 (1<<8) 339 340 #define ATW_FRAGTHR_FRAGTHR_MASK 0x0fff 341 #define ATW_FRAGNUM_FRAGNUM_MASK 0x00f0 342 343 /* Values for sc_flags. */ 344 #define ATWF_MRL 0x00000010 /* memory read line okay */ 345 #define ATWF_MRM 0x00000020 /* memory read multi okay */ 346 #define ATWF_MWI 0x00000040 /* memory write inval okay */ 347 #define ATWF_SHORT_PREAMBLE 0x00000080 /* short preamble enabled */ 348 #define ATWF_RTSCTS 0x00000100 /* RTS/CTS enabled */ 349 #define ATWF_ATTACHED 0x00000800 /* attach has succeeded */ 350 #define ATWF_ENABLED 0x00001000 /* chip is enabled */ 351 352 #define ATW_IS_ENABLED(sc) ((sc)->sc_flags & ATWF_ENABLED) 353 354 #define ATW_CDTXADDR(sc, x) ((sc)->sc_cddma + ATW_CDTXOFF((x))) 355 #define ATW_CDRXADDR(sc, x) ((sc)->sc_cddma + ATW_CDRXOFF((x))) 356 357 #define ATW_CDTXSYNC(sc, x, n, ops) \ 358 do { \ 359 int __x, __n; \ 360 \ 361 __x = (x); \ 362 __n = (n); \ 363 \ 364 /* If it will wrap around, sync to the end of the ring. */ \ 365 if ((__x + __n) > ATW_NTXDESC) { \ 366 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 367 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * \ 368 (ATW_NTXDESC - __x), (ops)); \ 369 __n -= (ATW_NTXDESC - __x); \ 370 __x = 0; \ 371 } \ 372 \ 373 /* Now sync whatever is left. */ \ 374 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 375 ATW_CDTXOFF(__x), sizeof(struct atw_txdesc) * __n, (ops)); \ 376 } while (0) 377 378 #define ATW_CDRXSYNC(sc, x, ops) \ 379 bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap, \ 380 ATW_CDRXOFF((x)), sizeof(struct atw_rxdesc), (ops)) 381 382 /* 383 * Note we rely on MCLBYTES being a power of two. Because the `length' 384 * field is only 11 bits, we must subtract 1 from the length to avoid 385 * having it truncated to 0! 386 */ 387 #define ATW_INIT_RXDESC(sc, x) \ 388 do { \ 389 struct atw_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 390 struct atw_rxdesc *__rxd = &sc->sc_rxdescs[(x)]; \ 391 struct mbuf *__m = __rxs->rxs_mbuf; \ 392 \ 393 __rxd->ar_buf1 = \ 394 htole32(__rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 395 __rxd->ar_buf2 = /* for descriptor chaining */ \ 396 htole32(ATW_CDRXADDR((sc), ATW_NEXTRX((x)))); \ 397 __rxd->ar_ctl = \ 398 htole32(LSHIFT(((__m->m_ext.ext_size - 1) & ~0x3U), \ 399 ATW_RXCTL_RBS1_MASK) | \ 400 0 /* ATW_RXCTL_RCH */ | \ 401 ((x) == (ATW_NRXDESC - 1) ? ATW_RXCTL_RER : 0)); \ 402 __rxd->ar_stat = htole32(ATW_RXSTAT_OWN); \ 403 \ 404 ATW_CDRXSYNC((sc), (x), \ 405 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 406 } while (0) 407 408 /* country codes from ADM8211 SROM */ 409 #define ATW_COUNTRY_FCC 0 /* USA 1-11 */ 410 #define ATW_COUNTRY_IC 1 /* Canada 1-11 */ 411 #define ATW_COUNTRY_ETSI 2 /* European Union (?) 1-13 */ 412 #define ATW_COUNTRY_SPAIN 3 /* 10-11 */ 413 #define ATW_COUNTRY_FRANCE 4 /* 10-13 */ 414 #define ATW_COUNTRY_MKK 5 /* Japan: 14 */ 415 #define ATW_COUNTRY_MKK2 6 /* Japan: 1-14 */ 416 417 /* 418 * register space access macros 419 */ 420 #define ATW_READ(sc, reg) \ 421 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 422 423 #define ATW_WRITE(sc, reg, val) \ 424 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 425 426 #define ATW_SET(sc, reg, mask) \ 427 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) | (mask)) 428 429 #define ATW_CLR(sc, reg, mask) \ 430 ATW_WRITE((sc), (reg), ATW_READ((sc), (reg)) & ~(mask)) 431 432 #define ATW_ISSET(sc, reg, mask) \ 433 (ATW_READ((sc), (reg)) & (mask)) 434 435 void atw_attach(struct atw_softc *); 436 int atw_detach(struct atw_softc *); 437 int atw_activate(struct device *, int); 438 int atw_intr(void *arg); 439 int atw_enable(struct atw_softc *); 440 void atw_wakeup(struct atw_softc *); 441 442 #endif /* _DEV_IC_ATWVAR_H_ */
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