The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/bhavar.h

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    1 /*      $NetBSD: bhavar.h,v 1.24 2008/04/28 20:23:49 martin Exp $       */
    2 
    3 /*-
    4  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
    9  * Simulation Facility, NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30  * POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #ifndef _DEV_IC_BHAVAR_H_
   34 #define _DEV_IC_BHAVAR_H_
   35 
   36 #include <sys/queue.h>
   37 
   38 /* XXX adjust hash for large numbers of CCBs */
   39 #define CCB_HASH_SIZE   32      /* hash table size for phystokv */
   40 #define CCB_HASH_SHIFT  9
   41 #define CCB_HASH(x)     ((((long)(x))>>CCB_HASH_SHIFT) & (CCB_HASH_SIZE - 1))
   42 
   43 /*
   44  * A CCB allocation group.  Each group is a page size.  We can find
   45  * the allocation group for a CCB by truncating the CCB address to
   46  * a page boundary, and the offset from the group's DMA mapping
   47  * by taking the offset of the CCB into the page.
   48  */
   49 #define BHA_CCBS_PER_GROUP      ((PAGE_SIZE - sizeof(bus_dmamap_t)) /   \
   50                                  sizeof(struct bha_ccb))
   51 struct bha_ccb_group {
   52         bus_dmamap_t bcg_dmamap;
   53         struct bha_ccb bcg_ccbs[1];     /* determined at run-time */
   54 };
   55 
   56 #define BHA_CCB_GROUP(ccb)                                              \
   57         (struct bha_ccb_group *)(trunc_page((vaddr_t)ccb))
   58 #define BHA_CCB_OFFSET(ccb)     ((vaddr_t)(ccb) & PAGE_MASK)
   59 
   60 #define BHA_CCB_SYNC(sc, ccb, ops)                                      \
   61 do {                                                                    \
   62         struct bha_ccb_group *bcg = BHA_CCB_GROUP((ccb));               \
   63                                                                         \
   64         bus_dmamap_sync((sc)->sc_dmat, bcg->bcg_dmamap,                 \
   65             BHA_CCB_OFFSET(ccb), sizeof(struct bha_ccb), (ops));        \
   66 } while (0)
   67 
   68 /*
   69  * Offset in the DMA mapping for mailboxes.
   70  * Since all mailboxes are allocated on a single DMA'able memory
   71  * due to the hardware limitation, an offset of any mailboxes can be
   72  * calculated using same expression.
   73  */
   74 #define BHA_MBX_OFFSET(sc, mbx) ((u_long)(mbx) - (u_long)(sc)->sc_mbo)
   75 
   76 #define BHA_MBI_SYNC(sc, mbi, ops)                                      \
   77 do {                                                                    \
   78         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap_mbox,            \
   79             BHA_MBX_OFFSET((sc), (mbi)), sizeof(struct bha_mbx_in), (ops)); \
   80 } while (0)
   81 
   82 #define BHA_MBO_SYNC(sc, mbo, ops)                                      \
   83 do {                                                                    \
   84         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_dmamap_mbox,            \
   85             BHA_MBX_OFFSET((sc), (mbo)), sizeof(struct bha_mbx_out), (ops)); \
   86 } while (0)
   87 
   88 struct bha_softc {
   89         struct device sc_dev;
   90 
   91         bus_space_tag_t sc_iot;
   92         bus_space_handle_t sc_ioh;
   93         bus_dma_tag_t sc_dmat;
   94         bus_dmamap_t sc_dmamap_mbox;    /* maps the mailboxes */
   95         int sc_dmaflags;                /* bus-specific dma map flags */
   96         void *sc_ih;
   97 
   98         int sc_scsi_id;                 /* host adapter SCSI ID */
   99 
  100         int sc_flags;
  101 #define BHAF_WIDE               0x01    /* device is wide */
  102 #define BHAF_DIFFERENTIAL       0x02    /* device is differential */
  103 #define BHAF_ULTRA              0x04    /* device is ultra-scsi */
  104 #define BHAF_TAGGED_QUEUEING    0x08    /* device supports tagged queueing */
  105 #define BHAF_WIDE_LUN           0x10    /* device supported wide lun CCBs */
  106 #define BHAF_STRICT_ROUND_ROBIN 0x20    /* device supports strict RR mode */
  107 
  108         int sc_max_dmaseg;              /* maximum number of DMA segments */
  109         int sc_max_ccbs;                /* maximum number of CCBs (HW) */
  110         int sc_cur_ccbs;                /* current number of CCBs */
  111 
  112         int sc_disc_mask;               /* mask of targets allowing discnnct */
  113         int sc_ultra_mask;              /* mask of targets allowing ultra */
  114         int sc_fast_mask;               /* mask of targets allowing fast */
  115         int sc_sync_mask;               /* mask of targets allowing sync */
  116         int sc_wide_mask;               /* mask of targets allowing wide */
  117         int sc_tag_mask;                /* mask of targets allowing t/q'ing */
  118 
  119         /*
  120          * In and Out mailboxes.
  121          */
  122         struct bha_mbx_out *sc_mbo;
  123         struct bha_mbx_in *sc_mbi;
  124 
  125         struct bha_mbx_out *sc_cmbo;    /* Collection Mail Box out */
  126         struct bha_mbx_out *sc_tmbo;    /* Target Mail Box out */
  127 
  128         int sc_mbox_count;              /* number of mailboxes */
  129         int sc_mbofull;                 /* number of full Mail Box Out */
  130 
  131         struct bha_mbx_in *sc_tmbi;     /* Target Mail Box in */
  132 
  133         struct bha_ccb *sc_ccbhash[CCB_HASH_SIZE];
  134         TAILQ_HEAD(, bha_ccb)   sc_free_ccb,
  135                                 sc_waiting_ccb,
  136                                 sc_allocating_ccbs;
  137 
  138         struct scsipi_adapter sc_adapter;
  139         struct scsipi_channel sc_channel;
  140 
  141         char sc_model[7],
  142              sc_firmware[6];
  143 };
  144 
  145 struct bha_probe_data {
  146         int sc_irq, sc_drq;
  147 };
  148 
  149 int     bha_find(bus_space_tag_t, bus_space_handle_t);
  150 int     bha_inquire_config(bus_space_tag_t, bus_space_handle_t,
  151             struct bha_probe_data *);
  152 void    bha_attach(struct bha_softc *);
  153 int     bha_info(struct bha_softc *);
  154 int     bha_intr(void *);
  155 
  156 int     bha_disable_isacompat(struct bha_softc *);
  157 int     bha_probe_inquiry(bus_space_tag_t, bus_space_handle_t,
  158             struct bha_probe_data *);
  159 
  160 #endif /* _DEV_IC_BHAVAR_H_ */

Cache object: 4ef88a7428e0f7be1dfbd99c0dc2fc3c


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