The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/bt463reg.h

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    1 /*      $NetBSD: bt463reg.h,v 1.1 1998/08/18 07:43:09 thorpej Exp $     */
    2 
    3 /*-
    4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * Register definitions for the Brooktree Bt463 135MHz Monolithic
   42  * CMOS TrueVu RAMDAC.
   43  */
   44 
   45 /*
   46  * Directly-accessible registers.  Note the address register is
   47  * auto-incrementing.
   48  */
   49 #define BT463_REG_ADDR_LOW              0x00    /* C1,C0 == 0,0 */
   50 #define BT463_REG_ADDR_HIGH             0x01    /* C1,C0 == 0,1 */
   51 #define BT463_REG_IREG_DATA             0x02    /* C1,C0 == 1,0 */
   52 #define BT463_REG_CMAP_DATA             0x03    /* C1,C0 == 1,1 */
   53 
   54 #define BT463_REG_MAX                   BT463_REG_CMAP_DATA
   55 
   56 /*
   57  * All internal register access to the Bt463 is done indirectly via the
   58  * Address Register (mapped into the host bus in a device-specific
   59  * fashion).  The following register definitions are in terms of
   60  * their address register address values.
   61  */
   62 
   63 /* C1,C0 must be 1,0 */
   64 #define BT463_IREG_CURSOR_COLOR_0       0x0100  /* 3 r/w cycles */
   65 #define BT463_IREG_CURSOR_COLOR_1       0x0101  /* 3 r/w cycles */
   66 #define BT463_IREG_ID                   0x0200
   67 #define BT463_IREG_COMMAND_0            0x0201
   68 #define BT463_IREG_COMMAND_1            0x0202
   69 #define BT463_IREG_COMMAND_2            0x0203
   70 #define BT463_IREG_READ_MASK_P0_P7      0x0205
   71 #define BT463_IREG_READ_MASK_P8_P15     0x0206
   72 #define BT463_IREG_READ_MASK_P16_P23    0x0207
   73 #define BT463_IREG_READ_MASK_P24_P27    0x0208
   74 #define BT463_IREG_BLINK_MASK_P0_P7     0x0209
   75 #define BT463_IREG_BLINK_MASK_P8_P15    0x020a
   76 #define BT463_IREG_BLINK_MASK_P16_P23   0x020b
   77 #define BT463_IREG_BLINK_MASK_P24_P27   0x020c
   78 #define BT463_IREG_TEST                 0x020d
   79 #define BT463_IREG_INPUT_SIG            0x020e  /* 2 of 3 r/w cycles */
   80 #define BT463_IREG_OUTPUT_SIG           0x020f  /* 3 r/w cycles */
   81 #define BT463_IREG_REVISION             0x0220
   82 #define BT463_IREG_WINDOW_TYPE_TABLE    0x0300  /* 3 r/w cycles */
   83 
   84 #define BT463_NWTYPE_ENTRIES            0x10    /* 16 window type entries */
   85 
   86 /* C1,C0 must be 1,1 */
   87 #define BT463_IREG_CPALETTE_RAM         0x0000  /* 3 r/w cycles */
   88 
   89 #define BT463_NCMAP_ENTRIES             0x210   /* 528 CMAP entries */

Cache object: 87b73acff84ebc9e7d6dcf8001eba4cf


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