FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/bt463reg.h
1 /* $OpenBSD: bt463reg.h,v 1.3 2008/06/26 05:42:15 ray Exp $ */
2 /* $NetBSD: bt463reg.h,v 1.1 1998/08/18 07:43:09 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 * Register definitions for the Brooktree Bt463 135MHz Monolithic
36 * CMOS TrueVu RAMDAC.
37 */
38
39 /*
40 * Directly-accessible registers. Note the address register is
41 * auto-incrementing.
42 */
43 #define BT463_REG_ADDR_LOW 0x00 /* C1,C0 == 0,0 */
44 #define BT463_REG_ADDR_HIGH 0x01 /* C1,C0 == 0,1 */
45 #define BT463_REG_IREG_DATA 0x02 /* C1,C0 == 1,0 */
46 #define BT463_REG_CMAP_DATA 0x03 /* C1,C0 == 1,1 */
47
48 #define BT463_REG_MAX BT463_REG_CMAP_DATA
49
50 /*
51 * All internal register access to the Bt463 is done indirectly via the
52 * Address Register (mapped into the host bus in a device-specific
53 * fashion). The following register definitions are in terms of
54 * their address register address values.
55 */
56
57 /* C1,C0 must be 1,0 */
58 #define BT463_IREG_CURSOR_COLOR_0 0x0100 /* 3 r/w cycles */
59 #define BT463_IREG_CURSOR_COLOR_1 0x0101 /* 3 r/w cycles */
60 #define BT463_IREG_ID 0x0200
61 #define BT463_IREG_COMMAND_0 0x0201
62 #define BT463_IREG_COMMAND_1 0x0202
63 #define BT463_IREG_COMMAND_2 0x0203
64 #define BT463_IREG_READ_MASK_P0_P7 0x0205
65 #define BT463_IREG_READ_MASK_P8_P15 0x0206
66 #define BT463_IREG_READ_MASK_P16_P23 0x0207
67 #define BT463_IREG_READ_MASK_P24_P27 0x0208
68 #define BT463_IREG_BLINK_MASK_P0_P7 0x0209
69 #define BT463_IREG_BLINK_MASK_P8_P15 0x020a
70 #define BT463_IREG_BLINK_MASK_P16_P23 0x020b
71 #define BT463_IREG_BLINK_MASK_P24_P27 0x020c
72 #define BT463_IREG_TEST 0x020d
73 #define BT463_IREG_INPUT_SIG 0x020e /* 2 of 3 r/w cycles */
74 #define BT463_IREG_OUTPUT_SIG 0x020f /* 3 r/w cycles */
75 #define BT463_IREG_REVISION 0x0220
76 #define BT463_IREG_WINDOW_TYPE_TABLE 0x0300 /* 3 r/w cycles */
77
78 #define BT463_NWTYPE_ENTRIES 0x10 /* 16 window type entries */
79
80 /* C1,C0 must be 1,1 */
81 #define BT463_IREG_CPALETTE_RAM 0x0000 /* 3 r/w cycles */
82
83 #define BT463_NCMAP_ENTRIES 0x210 /* 528 CMAP entries */
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