The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/cd1190reg.h

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    1 /*      $NetBSD: cd1190reg.h,v 1.4 2005/12/11 12:21:26 christos Exp $   */
    2 /*
    3  * Copyright (c) 1998 Iain Hibbert.
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. The name Iain Hibbert may not be used to endorse or promote products
   15  *    derived from this software without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY ``AS IS'' AND ANY EXPRESS OR IMPLIED
   18  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
   19  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
   20  * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
   21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
   22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
   23  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
   24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
   25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
   26  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 /*
   30  * Definitions for Cirrus Logic CD1190 parallel chips.
   31  */
   32 
   33 /* ACK Width Register */
   34 #define CD1190_AWR              0x03
   35 
   36 /* Controller Command Register */
   37 #define CD1190_CCR              0x0b
   38 #define CD1190_CCR_CGC          (1<<7)  /* Change Global Config Command */
   39 #define CD1190_CCR_CGC_RESET    (1<<0) /* CGC Reset Command */
   40 #define CD1190_CCR_PAR          (1<<6)  /* Parallel Command */
   41 #define CD1190_CCR_PAR_DISABLE  (1<<2) /* PAR Parallel Disable */
   42 #define CD1190_CCR_PAR_FLUSH    (1<<1) /* PAR Flush FIFO */
   43 #define CD1190_CCR_PAR_ENABLE   (1<<0) /* PAR Parallel Enable */
   44 #define CD1190_CCR_SIG          (1<<5)  /* Signal Command */
   45 #define CD1190_CCR_SIG_SET_BUSY (1<<2) /* SIG Set Busy Output */
   46 #define CD1190_CCR_SIG_ACK      (1<<1) /* SIG Pulse ACK Output */
   47 #define CD1190_CCR_SIG_CLR_BUSY (1<<0) /* SIG Clear Busy Output */
   48 #define CD1190_CCR_TIM          (1<<4)  /* Timer Command */
   49 #define CD1190_CCR_TIM_ENABLE   (1<<3) /* Timer Enabled */
   50 
   51 /* Data Time-0ut Register */
   52 #define CD1190_DTR              0x09
   53 
   54 /* End Of Service Request Register */
   55 #define CD1190_ESR              0x10
   56 
   57 /* FIFO Count Register */
   58 #define CD1190_FCR              0x0e
   59 
   60 /* FIFO Data Register */
   61 #define CD1190_FDR              0x12
   62 
   63 /* Firmware Revision Register */
   64 #define CD1190_FRR              0x0f
   65 
   66 /* FIFO Threshold Register */
   67 #define CD1190_FTR              0x08
   68 
   69 /* Global Config Register */
   70 #define CD1190_GCR              0x0a
   71 #define CD1190_GCR_NOACK        (1<<2) /* NO-ACK handshaking */
   72 #define CD1190_GCR_MODE         (1<<1) /* Peripheral/Controller Mode */
   73 #define CD1190_GCR_DIR          (1<<0) /* Input/Output Direction */
   74 
   75 /* defines for variable CD1190_IO */
   76 #define CD1190_CO               0x00
   77 #define CD1190_CI               0x01
   78 #define CD1190_PO               0x02
   79 #define CD1190_PI               0x03
   80 
   81 /* Interrupt Config Register */
   82 #define CD1190_ICR              0x01
   83 #define CD1190_ICR_ENABLE       (1<<7) /* Enable Interrupts */
   84 #define CD1190_ICR_ACK          (1<<3) /* Enable: Unsolicited ACK */
   85 #define CD1190_ICR_FIFO         (1<<2) /* Enable: FIFO Thresh/Time */
   86 #define CD1190_ICR_SIGNAL       (1<<1) /* Enable: Signal Status */
   87 #define CD1190_ICR_TIMER        (1<<0) /* Enable: Timer Expired */
   88 
   89 /* Interrupt Status Register */
   90 #define CD1190_ISR              0x0c
   91 #define CD1190_ISR_INTERRUPT    (1<<7) /* Interrupt Has Occurred */
   92 #define CD1190_ISR_ACK          (1<<3) /* Unsolicited ACK */
   93 #define CD1190_ISR_FIFO         (1<<2) /* FIFO Thresh/Time */
   94 #define CD1190_ISR_SIGNAL       (1<<1) /* Signal Status */
   95 #define CD1190_ISR_TIMER        (1<<0) /* Timer Expired */
   96 
   97 /* Interrupt Vector Register */
   98 #define CD1190_IVR              0x00
   99 
  100 /* Parallel Status Register */
  101 #define CD1190_PSR              0x1c
  102 #define CD1190_PSR_ENP          (1<<7) /* Parallel Enabled */
  103 #define CD1190_PSR_BUSY         (1<<6) /* Parallel Busy */
  104 #define CD1190_PSR_ACK          (1<<5) /* Parallel Acknowledge */
  105 #define CD1190_PSR_STATUS       (CD1190_PSR_ENP | CD1190_PSR_BUSY)
  106 #define CD1190_PSR_NORMAL       CD1190_PSR_ENP
  107 
  108 /* Signal Control Register */
  109 #define CD1190_SCR              0x1e
  110 #define CD1190_SCR_WRRD         (1<<7) /* Read Only: Write/Read */
  111 #define CD1190_SCR_IP3          (1<<6) /* Read Only: Input Line 3 */
  112 #define CD1190_SCR_IP2          (1<<5) /* Read Only: Input Line 2 */
  113 #define CD1190_SCR_IP1          (1<<4) /* Read Only: Input Line 1 */
  114 #define CD1190_SCR_WR_WRRD      (1<<3) /* Write/Read */
  115 #define CD1190_SCR_OP3          (1<<2) /* Output Line 3 */
  116 #define CD1190_SCR_OP2          (1<<1) /* Output Line 2 */
  117 #define CD1190_SCR_OP1          (1<<0) /* Output Line 1 */
  118 
  119 /* Input signals
  120  *
  121  *      IP3     -       *ERROR
  122  *      IP2     -       PAPER EMPTY / FAULT
  123  *      IP1     -       SELECT
  124  *      WRRD    -       AFD
  125  *      OP3     -       SLIN
  126  *      OP2     -       *INIT / *RESET
  127  *      OP1     -       N/A
  128  */
  129 #define CD1190_SCR_NOERROR      CD1190_SCR_IP3 /* Printer Error (active low) */
  130 #define CD1190_SCR_PE           CD1190_SCR_IP2 /* Paper Empty */
  131 #define CD1190_SCR_SELECT       CD1190_SCR_IP1 /* Printer Select */
  132 
  133 #define CD1190_SCR_STATUS       (CD1190_SCR_IP3 | CD1190_SCR_IP2 | CD1190_SCR_IP1)
  134 
  135 /* Outout signals - Active High?
  136  *
  137  *      IP3     -       SLIN
  138  *      IP2     -       *INIT / *RESET
  139  *      IP1     -       N/A
  140  *      WRRD    -       AFD
  141  *      OP3     -       *ERROR
  142  *      OP2     -       SELECT
  143  *      OP1     -       PAPER EMPTY / FAULT
  144  */
  145 #define CD1190_SCR_RESET        CD1190_SCR_OP2
  146 #define CD1190_SCR_SEL_IN       CD1190_SCR_OP3
  147 
  148 /* Specification Register ZEROes */
  149 #define CD1190_SR0              0x06
  150 #define CD1190_SR0_WRRD         (1<<7) /* WR/RD 1 to 0 Change */
  151 #define CD1190_SR0_IP3          (1<<6) /* IP3 1 to 0 Change */
  152 #define CD1190_SR0_IP2          (1<<5) /* IP2 1 to 0 Change */
  153 #define CD1190_SR0_IP1          (1<<4) /* IP1 1 to 0 Change */
  154 
  155 /* Specification Register ONEs */
  156 #define CD1190_SR1              0x07
  157 #define CD1190_SR1_WRRD         (1<<7) /* WR/RD 0 to 1 Change */
  158 #define CD1190_SR1_IP3          (1<<6) /* IP3 0 to 1 Change */
  159 #define CD1190_SR1_IP2          (1<<5) /* IP2 0 to 1 Change */
  160 #define CD1190_SR1_IP1          (1<<4) /* IP1 0 to 1 Change */
  161 
  162 /* Signal Status Register */
  163 #define CD1190_SSR              0x0d
  164 #define CD1190_SSR_WRRD         (1<<7) /* WR/RD Change */
  165 #define CD1190_SSR_IP3          (1<<6) /* IP3 Change */
  166 #define CD1190_SSR_IP2          (1<<5) /* IP2 Change */
  167 #define CD1190_SSR_IP1          (1<<4) /* IP1 Change */
  168 
  169 /* Strobe Width Register */
  170 #define CD1190_SWR              0x02
  171 
  172 /* Timer Multipler Register */
  173 #define CD1190_TMR              0x05
  174 
  175 /* Timer Prescale Register */
  176 #define CD1190_TPR              0x04

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