FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/cd18xxreg.h
1 /* $NetBSD: cd18xxreg.h,v 1.3 2005/12/11 12:21:26 christos Exp $ */
2
3 /*
4 * Copyright (c) 1998, 2001 Matthew R. Green
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * cirrus-logic CL-CD180/CD1864/CD1865 register definitions, from the
33 * CL-CD1865 data book.
34 */
35
36
37 /*
38 * available registers for us.
39 *
40 * the cd1865 provides 4 types of registers: global, indexed indirect,
41 * channel, and unavailable. we should never touch the unavailable, as it
42 * may cause the cd1865 to fail. the indexed indirect registers are
43 * really pointers to the correct channel we are currently servicing, and
44 * as such must only be accessed during service-request service routines.
45 * global registers set and provide common functionality between all of
46 * the channels. channel registers only affect the specific channel.
47 * access to channel registers is limited to the current channel, as
48 * specified in the CAR register, ie. to access different channels, the CAR
49 * register must be changed first.
50 */
51
52
53 /*
54 * the registers themselves.
55 */
56
57 /* global registers */
58 #define CD18xx_GFRCR 0x6b /* global firmware revision code */
59 #define CD18xx_SRCR 0x66 /* service request configuration */
60 #define CD18xx_PPRH 0x70 /* prescaler period (high) */
61 #define CD18xx_PPRL 0x71 /* prescaler period (low) */
62 #define CD18xx_MSMR 0x61 /* modem service match */
63 #define CD18xx_TSMR 0x62 /* transmit service match */
64 #define CD18xx_RSMR 0x63 /* receive service match */
65 #define CD18xx_GSVR 0x40 /* global service vector */
66 #define CD18xx_SRSR 0x65 /* service request status */
67 #define CD18xx_MRAR 0x75 /* modem request acknowledge */
68 #define CD18xx_TRAR 0x76 /* transmit request acknowledge */
69 #define CD18xx_RRAR 0x77 /* receive request acknowledge */
70 #define CD18xx_GSCR1 0x41 /* global service channel (1) */
71 #define CD18xx_GSCR2 0x42 /* global service channel (2) */
72 #define CD18xx_GSCR3 0x43 /* global service channel (3) */
73 #define CD18xx_CAR 0x64 /* channel access register */
74
75 /* indexed indirect registers */
76 #define CD18xx_RDCR 0x07 /* receive data count */
77 #define CD18xx_RDR 0x78 /* receiver data register */
78 #define CD18xx_RCSR 0x7a /* receiver channel status */
79 #define CD18xx_TDR 0x7b /* transmit data register */
80 #define CD18xx_EOSRR 0x7f /* end of service request */
81
82 /* channel registers */
83 #define CD18xx_SRER 0x02 /* service request enable */
84 #define CD18xx_CCR 0x01 /* channel command */
85 #define CD18xx_COR1 0x03 /* channel option (1) */
86 #define CD18xx_COR2 0x04 /* channel option (2) */
87 #define CD18xx_COR3 0x05 /* channel option (3) */
88 #define CD18xx_CCSR 0x06 /* channel control status */
89 #define CD18xx_RBR 0x33 /* receiver bit */
90 #define CD18xx_RTPR 0x18 /* receive time-out period */
91 #define CD18xx_RBPRH 0x31 /* receive bit rate period (high) */
92 #define CD18xx_RBPRL 0x32 /* receive bit rate period (low) */
93 #define CD18xx_TBPRH 0x39 /* transmit bit rate period (high) */
94 #define CD18xx_TBPRL 0x3a /* transmit bit rate period (low) */
95 #define CD18xx_SCHR1 0x09 /* special character (1) */
96 #define CD18xx_SCHR2 0x0a /* special character (2) */
97 #define CD18xx_SCHR3 0x0b /* special character (3) */
98 #define CD18xx_SCHR4 0x0c /* special character (4) */
99 #define CD18xx_MCR 0x10 /* modem change */
100 #define CD18xx_MCOR1 0x10 /* modem change option (1) */
101 #define CD18xx_MCOR2 0x11 /* modem change option (2) */
102 #define CD18xx_MSVR 0x28 /* modem signal value */
103 #define CD18xx_MSVRTS 0x29 /* modem signal value RTS */
104 #define CD18xx_MSVDTR 0x2a /* mdoem signal value DTR */
105
106
107 /*
108 * inside the registers
109 */
110
111 /* global registers */
112
113 /* global firmware revision code */
114 #define CD180_GFRCR_REV_B 0x81 /* CL-CD180B */
115 #define CD180_GFRCR_REV_C 0x82 /* CL-CD180C */
116 #define CD1864_GFRCR_REVISION_A 0x82 /* CL-CD1864A */
117 #define CD1865_GFRCR_REVISION_A 0x83 /* CL-CD1865A */
118 #define CD1865_GFRCR_REVISION_B 0x84 /* CL-CD1865B */
119 #define CD1865_GFRCR_REVISION_C 0x85 /* CL-CD1865C */
120
121 /* service request configuration register */
122 #define CD18xx_SRCR_PKGTYP 0x80 /* package type (RO) */
123 #define CD18xx_SRCR_REGACKEN 0x40 /* enable register acks */
124 #define CD18xx_SRCR_DAISYEN 0x20 /* enable daisy-chain */
125 #define CD18xx_SRCR_GLOBPRI 0x10 /* global priority */
126 #define CD18xx_SRCR_UNFAIR 0x08 /* unfair override */
127 #define CD18xx_SRCR_AUTOPRI 0x02 /* auto prioritizing */
128 #define CD18xx_SRCR_PRISEL 0x01 /* priority selection */
129
130 /* global service vector register */
131 #define CD18xx_GSVR_CLEAR 0x00 /* clear GSVR for reset */
132 #define CD18xx_GSVR_READY 0xff /* modem is ready */
133 #define CD18xx_GSVR_IDMASK 0xf8 /* unique ID per-chip */
134 #define CD18xx_GSVR_SETID(sc) ((((sc)->sc_chip_id & ~1) << 5) | \
135 (((sc)->sc_chip_id & 1) << 3))
136 #define CD18xx_GSVR_GROUPTYPE 0x07 /* group/type */
137 #define CD18xx_GSVR_NOREQPEND 0x00 /* no request pending */
138 #define CD18xx_GSVR_MODEM 0x01 /* modem signal change */
139 #define CD18xx_GSVR_TXDATA 0x02 /* tx data */
140 #define CD18xx_GSVR_RXDATA 0x03 /* rx good data */
141 #define CD18xx_GSVR_RXEXCEPTION 0x07 /* request exception */
142 #define CD18xx_GSVR_RXINTR(x) \
143 (((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_RXDATA || \
144 ((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_RXEXCEPTION)
145 #define CD18xx_GSVR_TXINTR(x) \
146 (((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_TXDATA)
147 #define CD18xx_GSVR_MXINTR(x) \
148 (((x) & CD18xx_GSVR_GROUPTYPE) == CD18xx_GSVR_MODEM)
149
150 /* service request status register */
151 #define CD18xx_SRSR_CONTEXT 0xc0 /* service request context */
152 #define CD18xx_SRSR_PENDING 0x15 /* get status bits for each */
153 #define CD18xx_SRSR_RxPEND 0x10 /* got a Rx interrupt */
154 #define CD18xx_SRSR_TxPEND 0x04 /* got a Tx interrupt */
155 #define CD18xx_SRSR_MxPEND 0x01 /* got a modem interrupt */
156
157 /* global service channel registers */
158 #define CD18xx_GSCR_USER1 0xe0 /* 3 bits of user-defined data */
159 #define CD18xx_GSCR_CAR 0x1c /* CAR of current channel */
160 #define CD18xx_GSCR_USER2 0x03 /* 2 bits of user-defined data */
161
162 /* indexed indirect registers */
163
164 /* receive data count register */
165 #define CD18xx_RDCR_ZERO 0xf0 /* reserved, must be zero */
166 #define CD18xx_RDCR_GOODBYTES 0x0f /* number of good bytes */
167
168 /* receive character status register */
169 #define CD18xx_RCSR_TIMEOUT 0x80 /* timeout has occurred on channel */
170 #define CD18xx_RCSR_SCD 0x70 /* special character detect */
171 #define CD18xx_RCSR_BREAK 0x08 /* line break detected */
172 #define CD18xx_RCSR_PARITYERR 0x04 /* parity error detected */
173 #define CD18xx_RCSR_FRAMERR 0x02 /* framing error detected */
174 #define CD18xx_RCSR_OVERRUNERR 0x01 /* overrun error detected */
175
176 /* transmit data register */
177 #define CD18xx_TDR_ETC_BYTE 0x00 /* first byte of break message */
178 #define CD18xx_TDR_BREAK_BYTE 0x81 /* first byte of break message */
179 #define CD18xx_TDR_NOBREAK_BYTE 0x83 /* first byte of clean break message */
180
181 /* channel registers */
182
183 /* service request enable register */
184 #define CD18xx_SRER_DSR 0x80 /* DSR service request */
185 #define CD18xx_SRER_CD 0x40 /* CD service request */
186 #define CD18xx_SRER_CTS 0x20 /* CTS service request */
187 #define CD18xx_SRER_Rx 0x10 /* Rx data service request */
188 #define CD18xx_SRER_RxSC 0x08 /* Rx special char service request */
189 #define CD18xx_SRER_Tx 0x04 /* Tx ready service request */
190 #define CD18xx_SRER_TxEMPTY 0x02 /* Tx empty service request */
191 #define CD18xx_SRER_NNDT 0x01 /* no new data timeout service request */
192
193 /* channel command register */
194 #define CD18xx_CCR_RESET 0x80 /* reset channel command */
195 #define CD18xx_CCR_CORCHG 0x40 /* COR change command */
196 #define CD18xx_CCR_SENDSC 0x20 /* send special character command */
197 #define CD18xx_CCR_CHANCTL 0x10 /* channel control command */
198
199 /* bits inside CCR's least significant half-byte */
200 #define CD18xx_CCR_RESET_HARD 0x01 /* full, hard reset */
201 #define CD18xx_CCR_RESET_CHAN 0x00 /* reset only the current channel */
202 #define CD18xx_CCR_CORCHG_COR3 0x08 /* change COR3 command */
203 #define CD18xx_CCR_CORCHG_COR2 0x04 /* change COR2 command */
204 #define CD18xx_CCR_CORCHG_COR1 0x02 /* change COR1 command */
205 #define CD18xx_CCR_SENDSC_SEND1 0x01 /* send SC 1, or 1&3 */
206 #define CD18xx_CCR_SENDSC_SEND2 0x02 /* send SC 2, or 2&4 */
207 #define CD18xx_CCR_SENDSC_SEND3 0x03 /* send SC 3 */
208 #define CD18xx_CCR_SENDSC_SEND4 0x04 /* send SC 4 */
209 /* note that these are slower than enabling/disabling SRER */
210 #define CD18xx_CCR_CHANCTL_TxEN 0x08 /* transmitter enable */
211 #define CD18xx_CCR_CHANCTL_TxDI 0x04 /* transmitter disable */
212 #define CD18xx_CCR_CHANCTL_RxEN 0x02 /* receiver enable */
213 #define CD18xx_CCR_CHANCTL_RxDI 0x01 /* receiver disable */
214
215 /* channel option register 1 */
216 #define CD18xx_COR1_PARITY 0x80 /* parity */
217 #define CD18xx_COR1_PARITY_ODD 0x80 /* odd parity */
218 #define CD18xx_COR1_PARITY_EVEN 0x00 /* even parity */
219 #define CD18xx_COR1_PARITY_MODE 0x60 /* parity mode */
220 #define CD18xx_COR1_PARITY_NONE 0x00 /* no parity */
221 #define CD18xx_COR1_PARITY_FORCE 0x20 /* force parity */
222 #define CD18xx_COR1_PARITY_NORMAL 0x40 /* normal parity */
223 #define CD18xx_COR1_IGNORE 0x10 /* parity ignore mode */
224 #define CD18xx_COR1_STOPBITLEN 0x0c /* stop bit length */
225 #define CD18xx_COR1_STOPBIT_1 0x00 /* 1 stop bit */
226 #define CD18xx_COR1_STOPBIT_1_5 0x04 /* 1.5 stop bits */
227 #define CD18xx_COR1_STOPBIT_2 0x08 /* 2 stop bits */
228 #define CD18xx_COR1_STOPBIT_2_5 0x0c /* 2.5 stop bits */
229 #define CD18xx_COR1_CHARLEN 0x03 /* character length */
230 #define CD18xx_COR1_CS5 0x00 /* 5 bit chars */
231 #define CD18xx_COR1_CS6 0x01 /* 7 bit chars */
232 #define CD18xx_COR1_CS7 0x02 /* 7 bit chars */
233 #define CD18xx_COR1_CS8 0x03 /* 8 bit chars */
234
235 /* channel option register 2 */
236 #define CD18xx_COR2_IXM 0x80 /* implied XON mode */
237 #define CD18xx_COR2_TxIBE 0x40 /* Tx inband flow control auto enable */
238 #define CD18xx_COR2_ETC 0x20 /* embedded Tx command enable */
239 #define CD18xx_COR2_LLM 0x10 /* local loopback mode */
240 #define CD18xx_COR2_RLM 0x08 /* remote loopback mode */
241 #define CD18xx_COR2_RTSAOE 0x04 /* RTS auto output enable */
242 #define CD18xx_COR2_CTSAE 0x02 /* CTS auto enable */
243 #define CD18xx_COR2_DSRAE 0x01 /* DSR auto enable */
244
245 /* channel option register 3 */
246 #define CD18xx_COR3_XONCH 0x80 /* XON character definition */
247 #define CD18xx_COR3_XOFFCH 0x40 /* XOFF character definition */
248 #define CD18xx_COR3_FCTM 0x20 /* flow control transparency mode */
249 #define CD18xx_COR3_SCDE 0x10 /* special character detection enable */
250 #define CD18xx_COR3_FIFOTHRESH 0x08 /* Rx FIFO threshold */
251
252 /* channel control status register */
253 #define CD18xx_CCSR_RxEN 0x80 /* Rx enable */
254 #define CD18xx_CCSR_RxFLOFF 0x40 /* Rx flow control off enable */
255 #define CD18xx_CCSR_RxFLON 0x20 /* Rx flow control on enable */
256 #define CD18xx_CCSR_TxEN 0x08 /* Tx enable */
257 #define CD18xx_CCSR_TxFLOFF 0x04 /* Tx flow control off enable */
258 #define CD18xx_CCSR_TxFLON 0x02 /* Tx flow control on enable */
259
260 /* receiver bit register */
261 #define CD18xx_RBR_RxD 0x40 /* last RxD input */
262 #define CD18xx_RBR_STARTHUNT 0x20 /* hunting for a start bit */
263
264 /* bit rate period resisters */
265 #define CD18xx_xBRPR_TPC 0x10 /* ticks per character */
266
267 /* mode change register */
268 #define CD18xx_MCR_DSR 0x80 /* DSR changed */
269 #define CD18xx_MCR_CD 0x40 /* CD changed */
270 #define CD18xx_MCR_CTS 0x20 /* CST changed */
271
272 /* modem change option register 1 */
273 #define CD18xx_MCOR1_DSR 0x80 /* high-to-low on DSR */
274 #define CD18xx_MCOR1_CD 0x40 /* high-to-low on CD */
275 #define CD18xx_MCOR1_CTS 0x20 /* high-to-low on CTS */
276 #define CD18xx_MCOR1_DTR 0x08 /* high-to-low on DSR mode */
277
278 /* modem change option register 2 */
279 #define CD18xx_MCOR2_DSR 0x80 /* low-to-high on DSR */
280 #define CD18xx_MCOR2_CD 0x40 /* low-to-high on CD */
281 #define CD18xx_MCOR2_CTS 0x20 /* low-to-high on CST */
282
283 /* modem signal value register */
284 #define CD18xx_MSVR_DSR 0x80 /* current DSR state */
285 #define CD18xx_MSVR_CD 0x40 /* current CD state */
286 #define CD18xx_MSVR_CTS 0x20 /* current CTS state */
287 #define CD18xx_MSVR_DTR 0x02 /* current DTR state */
288 #define CD18xx_MSVR_RTS 0x01 /* current RTS state */
289 #define CD18xx_MSVR_RESET (CD18xx_MSVR_DSR|CD18xx_MSVR_CD| \
290 CD18xx_MSVR_CTS|CD18xx_MSVR_DTR| \
291 CD18xx_MSVR_RTS)
292
293 /* modem signal value request-to-send register */
294 #define CD18xx_MSVRTS_RTS 0x01 /* change RTS and not DTR */
295
296 /* modem signal value data-terminal-ready register */
297 #define CD18xx_MSVDTR_DTR 0x01 /* change DTR and not RTS */
298
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