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sys/dev/ic/clmpcc.c
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1 /* $NetBSD: clmpcc.c,v 1.22 2002/10/23 09:13:14 jdolecek Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.22 2002/10/23 09:13:14 jdolecek Exp $"); 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/ioctl.h> 51 #include <sys/select.h> 52 #include <sys/tty.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/conf.h> 56 #include <sys/file.h> 57 #include <sys/uio.h> 58 #include <sys/kernel.h> 59 #include <sys/syslog.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 #include <machine/param.h> 66 67 #include <dev/ic/clmpccreg.h> 68 #include <dev/ic/clmpccvar.h> 69 #include <dev/cons.h> 70 71 72 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 73 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 74 #endif 75 76 77 static int clmpcc_init __P((struct clmpcc_softc *sc)); 78 static void clmpcc_shutdown __P((struct clmpcc_chan *)); 79 static int clmpcc_speed __P((struct clmpcc_softc *, speed_t, 80 int *, int *)); 81 static int clmpcc_param __P((struct tty *, struct termios *)); 82 static void clmpcc_set_params __P((struct clmpcc_chan *)); 83 static void clmpcc_start __P((struct tty *)); 84 static int clmpcc_modem_control __P((struct clmpcc_chan *, int, int)); 85 86 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 87 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 88 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 89 90 /* 91 * These should be in a header file somewhere... 92 */ 93 #define ISSET(v, f) (((v) & (f)) != 0) 94 #define ISCLR(v, f) (((v) & (f)) == 0) 95 #define SET(v, f) (v) |= (f) 96 #define CLR(v, f) (v) &= ~(f) 97 98 99 extern struct cfdriver clmpcc_cd; 100 101 dev_type_open(clmpccopen); 102 dev_type_close(clmpccclose); 103 dev_type_read(clmpccread); 104 dev_type_write(clmpccwrite); 105 dev_type_ioctl(clmpccioctl); 106 dev_type_stop(clmpccstop); 107 dev_type_tty(clmpcctty); 108 dev_type_poll(clmpccpoll); 109 110 const struct cdevsw clmpcc_cdevsw = { 111 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl, 112 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY 113 }; 114 115 /* 116 * Make this an option variable one can patch. 117 */ 118 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 119 120 121 /* 122 * Things needed when the device is used as a console 123 */ 124 static struct clmpcc_softc *cons_sc = NULL; 125 static int cons_chan; 126 static int cons_rate; 127 128 static int clmpcc_common_getc __P((struct clmpcc_softc *, int)); 129 static void clmpcc_common_putc __P((struct clmpcc_softc *, int, int)); 130 int clmpcccngetc __P((dev_t)); 131 void clmpcccnputc __P((dev_t, int)); 132 133 134 /* 135 * Convenience functions, inlined for speed 136 */ 137 #define integrate static inline 138 integrate u_int8_t clmpcc_rdreg __P((struct clmpcc_softc *, u_int)); 139 integrate void clmpcc_wrreg __P((struct clmpcc_softc *, u_int, u_int)); 140 integrate u_int8_t clmpcc_rdreg_odd __P((struct clmpcc_softc *, u_int)); 141 integrate void clmpcc_wrreg_odd __P((struct clmpcc_softc *, u_int, u_int)); 142 integrate void clmpcc_wrtx_multi __P((struct clmpcc_softc *, u_int8_t *, 143 u_int)); 144 integrate u_int8_t clmpcc_select_channel __P((struct clmpcc_softc *, u_int)); 145 integrate void clmpcc_channel_cmd __P((struct clmpcc_softc *,int,int)); 146 integrate void clmpcc_enable_transmitter __P((struct clmpcc_chan *)); 147 148 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 149 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 150 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 151 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 152 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 153 154 155 integrate u_int8_t 156 clmpcc_rdreg(sc, offset) 157 struct clmpcc_softc *sc; 158 u_int offset; 159 { 160 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 161 offset ^= sc->sc_byteswap; 162 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 163 offset ^= CLMPCC_BYTESWAP_HIGH; 164 #endif 165 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 166 } 167 168 integrate void 169 clmpcc_wrreg(sc, offset, val) 170 struct clmpcc_softc *sc; 171 u_int offset; 172 u_int val; 173 { 174 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 175 offset ^= sc->sc_byteswap; 176 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 177 offset ^= CLMPCC_BYTESWAP_HIGH; 178 #endif 179 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 180 } 181 182 integrate u_int8_t 183 clmpcc_rdreg_odd(sc, offset) 184 struct clmpcc_softc *sc; 185 u_int offset; 186 { 187 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 188 offset ^= (sc->sc_byteswap & 2); 189 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 190 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 191 #endif 192 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 193 } 194 195 integrate void 196 clmpcc_wrreg_odd(sc, offset, val) 197 struct clmpcc_softc *sc; 198 u_int offset; 199 u_int val; 200 { 201 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 202 offset ^= (sc->sc_byteswap & 2); 203 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 204 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 205 #endif 206 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 207 } 208 209 integrate void 210 clmpcc_wrtx_multi(sc, buff, count) 211 struct clmpcc_softc *sc; 212 u_int8_t *buff; 213 u_int count; 214 { 215 u_int offset = CLMPCC_REG_TDR; 216 217 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 218 offset ^= (sc->sc_byteswap & 2); 219 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 220 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 221 #endif 222 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 223 } 224 225 integrate u_int8_t 226 clmpcc_select_channel(sc, new_chan) 227 struct clmpcc_softc *sc; 228 u_int new_chan; 229 { 230 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 231 232 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 233 234 return old_chan; 235 } 236 237 integrate void 238 clmpcc_channel_cmd(sc, chan, cmd) 239 struct clmpcc_softc *sc; 240 int chan; 241 int cmd; 242 { 243 int i; 244 245 for (i = 5000; i; i--) { 246 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 247 break; 248 delay(1); 249 } 250 251 if ( i == 0 ) 252 printf("%s: channel %d command timeout (idle)\n", 253 sc->sc_dev.dv_xname, chan); 254 255 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 256 } 257 258 integrate void 259 clmpcc_enable_transmitter(ch) 260 struct clmpcc_chan *ch; 261 { 262 u_int old; 263 int s; 264 265 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 266 267 s = splserial(); 268 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 269 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 270 SET(ch->ch_tty->t_state, TS_BUSY); 271 splx(s); 272 273 clmpcc_select_channel(ch->ch_sc, old); 274 } 275 276 static int 277 clmpcc_speed(sc, speed, cor, bpr) 278 struct clmpcc_softc *sc; 279 speed_t speed; 280 int *cor, *bpr; 281 { 282 int c, co, br; 283 284 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 285 br = ((sc->sc_clk / c) / speed) - 1; 286 if ( br < 0x100 ) { 287 *cor = co; 288 *bpr = br; 289 return 0; 290 } 291 } 292 293 return -1; 294 } 295 296 void 297 clmpcc_attach(sc) 298 struct clmpcc_softc *sc; 299 { 300 struct clmpcc_chan *ch; 301 struct tty *tp; 302 int chan; 303 304 if ( cons_sc != NULL && 305 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 306 cons_sc = sc; 307 308 /* Initialise the chip */ 309 clmpcc_init(sc); 310 311 printf(": Cirrus Logic CD240%c Serial Controller\n", 312 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '' : '1'); 313 314 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 315 sc->sc_soft_running = 0; 316 #else 317 sc->sc_softintr_cookie = 318 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc); 319 #ifdef DEBUG 320 if (sc->sc_softintr_cookie == NULL) 321 panic("clmpcc_attach: softintr_establish"); 322 #endif 323 #endif 324 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 325 326 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 327 ch = &sc->sc_chans[chan]; 328 329 ch->ch_sc = sc; 330 ch->ch_car = chan; 331 332 tp = ttymalloc(); 333 tp->t_oproc = clmpcc_start; 334 tp->t_param = clmpcc_param; 335 336 ch->ch_tty = tp; 337 338 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 339 if ( ch->ch_ibuf == NULL ) { 340 printf("%s(%d): unable to allocate ring buffer\n", 341 sc->sc_dev.dv_xname, chan); 342 return; 343 } 344 345 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 346 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 347 348 tty_attach(tp); 349 } 350 351 printf("%s: %d channels available", sc->sc_dev.dv_xname, 352 CLMPCC_NUM_CHANS); 353 if ( cons_sc == sc ) { 354 printf(", console on channel %d.\n", cons_chan); 355 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 356 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 357 } else 358 printf(".\n"); 359 } 360 361 static int 362 clmpcc_init(sc) 363 struct clmpcc_softc *sc; 364 { 365 u_int tcor, tbpr; 366 u_int rcor, rbpr; 367 u_int msvr_rts, msvr_dtr; 368 u_int ccr; 369 int is_console; 370 int i; 371 372 /* 373 * All we're really concerned about here is putting the chip 374 * into a quiescent state so that it won't do anything until 375 * clmpccopen() is called. (Except the console channel.) 376 */ 377 378 /* 379 * If the chip is acting as console, set all channels to the supplied 380 * console baud rate. Otherwise, plump for 9600. 381 */ 382 if ( cons_sc && 383 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 384 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 385 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 386 is_console = 1; 387 } else { 388 clmpcc_speed(sc, 9600, &tcor, &tbpr); 389 clmpcc_speed(sc, 9600, &rcor, &rbpr); 390 is_console = 0; 391 } 392 393 /* Allow any pending output to be sent */ 394 delay(10000); 395 396 /* Send the Reset All command to channel 0 (resets all channels!) */ 397 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 398 399 delay(1000); 400 401 /* 402 * The chip will set it's firmware revision register to a non-zero 403 * value to indicate completion of reset. 404 */ 405 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 406 delay(1); 407 408 if ( i == 0 ) { 409 /* 410 * Watch out... If this chip is console, the message 411 * probably won't be sent since we just reset it! 412 */ 413 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 414 return -1; 415 } 416 417 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 418 clmpcc_select_channel(sc, i); 419 420 /* All interrupts are disabled to begin with */ 421 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 422 423 /* Make sure the channel interrupts on the correct vectors */ 424 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 425 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 426 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 427 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 428 429 /* Receive timer prescaler set to 1ms */ 430 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 431 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 432 433 /* We support Async mode only */ 434 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 435 436 /* Set the required baud rate */ 437 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 438 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 439 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 440 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 441 442 /* Always default to 8N1 (XXX what about console?) */ 443 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 444 CLMPCC_COR1_NO_PARITY | 445 CLMPCC_COR1_IGNORE_PAR); 446 447 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 448 449 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 450 451 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 452 CLMPCC_COR4_CDzd | 453 CLMPCC_COR4_CTSzd); 454 455 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 456 CLMPCC_COR5_CDod | 457 CLMPCC_COR5_CTSod | 458 CLMPCC_COR5_FLOW_NORM); 459 460 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 461 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 462 463 /* Set the receive FIFO timeout */ 464 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 465 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 466 467 /* At this point, we set up the console differently */ 468 if ( is_console && i == cons_chan ) { 469 msvr_rts = CLMPCC_MSVR_RTS; 470 msvr_dtr = CLMPCC_MSVR_DTR; 471 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 472 } else { 473 msvr_rts = 0; 474 msvr_dtr = 0; 475 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 476 } 477 478 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 479 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 480 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 481 delay(100); 482 } 483 484 return 0; 485 } 486 487 static void 488 clmpcc_shutdown(ch) 489 struct clmpcc_chan *ch; 490 { 491 int oldch; 492 493 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 494 495 /* Turn off interrupts. */ 496 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 497 498 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 499 /* Disable the transmitter and receiver */ 500 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 501 CLMPCC_CCR_T0_TX_DIS); 502 503 /* Drop RTS and DTR */ 504 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 505 } 506 507 clmpcc_select_channel(ch->ch_sc, oldch); 508 } 509 510 int 511 clmpccopen(dev, flag, mode, p) 512 dev_t dev; 513 int flag, mode; 514 struct proc *p; 515 { 516 struct clmpcc_softc *sc; 517 struct clmpcc_chan *ch; 518 struct tty *tp; 519 int oldch; 520 int error; 521 522 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 523 if (sc == NULL) 524 return (ENXIO); 525 526 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 527 528 tp = ch->ch_tty; 529 530 if ( ISSET(tp->t_state, TS_ISOPEN) && 531 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 532 return EBUSY; 533 534 /* 535 * Do the following iff this is a first open. 536 */ 537 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 538 539 ttychars(tp); 540 541 tp->t_dev = dev; 542 tp->t_iflag = TTYDEF_IFLAG; 543 tp->t_oflag = TTYDEF_OFLAG; 544 tp->t_lflag = TTYDEF_LFLAG; 545 tp->t_cflag = TTYDEF_CFLAG; 546 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 547 548 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 549 SET(tp->t_cflag, CLOCAL); 550 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 551 SET(tp->t_cflag, CRTSCTS); 552 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 553 SET(tp->t_cflag, MDMBUF); 554 555 /* 556 * Override some settings if the channel is being 557 * used as the console. 558 */ 559 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 560 tp->t_ospeed = tp->t_ispeed = cons_rate; 561 SET(tp->t_cflag, CLOCAL); 562 CLR(tp->t_cflag, CRTSCTS); 563 CLR(tp->t_cflag, HUPCL); 564 } 565 566 ch->ch_control = 0; 567 568 clmpcc_param(tp, &tp->t_termios); 569 ttsetwater(tp); 570 571 /* Clear the input ring */ 572 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 573 574 /* Select the channel */ 575 oldch = clmpcc_select_channel(sc, ch->ch_car); 576 577 /* Reset it */ 578 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 579 CLMPCC_CCR_T0_RX_EN | 580 CLMPCC_CCR_T0_TX_EN); 581 582 /* Enable receiver and modem change interrupts. */ 583 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 584 CLMPCC_IER_RET | 585 CLMPCC_IER_RX_FIFO); 586 587 /* Raise RTS and DTR */ 588 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 589 590 clmpcc_select_channel(sc, oldch); 591 } else 592 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 ) 593 return EBUSY; 594 595 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 596 if (error) 597 goto bad; 598 599 error = (*tp->t_linesw->l_open)(dev, tp); 600 if (error) 601 goto bad; 602 603 return 0; 604 605 bad: 606 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 607 /* 608 * We failed to open the device, and nobody else had it opened. 609 * Clean up the state as appropriate. 610 */ 611 clmpcc_shutdown(ch); 612 } 613 614 return error; 615 } 616 617 int 618 clmpccclose(dev, flag, mode, p) 619 dev_t dev; 620 int flag, mode; 621 struct proc *p; 622 { 623 struct clmpcc_softc *sc = 624 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 625 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 626 struct tty *tp = ch->ch_tty; 627 int s; 628 629 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 630 return 0; 631 632 (*tp->t_linesw->l_close)(tp, flag); 633 634 s = spltty(); 635 636 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 637 /* 638 * Although we got a last close, the device may still be in 639 * use; e.g. if this was the dialout node, and there are still 640 * processes waiting for carrier on the non-dialout node. 641 */ 642 clmpcc_shutdown(ch); 643 } 644 645 ttyclose(tp); 646 647 splx(s); 648 649 return 0; 650 } 651 652 int 653 clmpccread(dev, uio, flag) 654 dev_t dev; 655 struct uio *uio; 656 int flag; 657 { 658 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 659 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 660 661 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 662 } 663 664 int 665 clmpccwrite(dev, uio, flag) 666 dev_t dev; 667 struct uio *uio; 668 int flag; 669 { 670 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 671 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 672 673 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 674 } 675 676 int 677 clmpccpoll(dev, events, p) 678 dev_t dev; 679 int events; 680 struct proc *p; 681 { 682 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 683 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 684 685 return ((*tp->t_linesw->l_poll)(tp, events, p)); 686 } 687 688 struct tty * 689 clmpcctty(dev) 690 dev_t dev; 691 { 692 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 693 694 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 695 } 696 697 int 698 clmpccioctl(dev, cmd, data, flag, p) 699 dev_t dev; 700 u_long cmd; 701 caddr_t data; 702 int flag; 703 struct proc *p; 704 { 705 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 706 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 707 struct tty *tp = ch->ch_tty; 708 int error; 709 710 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p); 711 if (error != EPASSTHROUGH) 712 return error; 713 714 error = ttioctl(tp, cmd, data, flag, p); 715 if (error != EPASSTHROUGH) 716 return error; 717 718 error = 0; 719 720 switch (cmd) { 721 case TIOCSBRK: 722 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 723 clmpcc_enable_transmitter(ch); 724 break; 725 726 case TIOCCBRK: 727 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 728 clmpcc_enable_transmitter(ch); 729 break; 730 731 case TIOCSDTR: 732 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 733 break; 734 735 case TIOCCDTR: 736 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 737 break; 738 739 case TIOCMSET: 740 clmpcc_modem_control(ch, *((int *)data), DMSET); 741 break; 742 743 case TIOCMBIS: 744 clmpcc_modem_control(ch, *((int *)data), DMBIS); 745 break; 746 747 case TIOCMBIC: 748 clmpcc_modem_control(ch, *((int *)data), DMBIC); 749 break; 750 751 case TIOCMGET: 752 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 753 break; 754 755 case TIOCGFLAGS: 756 *((int *)data) = ch->ch_openflags; 757 break; 758 759 case TIOCSFLAGS: 760 error = suser(p->p_ucred, &p->p_acflag); 761 if ( error ) 762 break; 763 ch->ch_openflags = *((int *)data) & 764 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 765 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 766 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 767 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 768 break; 769 770 default: 771 error = EPASSTHROUGH; 772 break; 773 } 774 775 return error; 776 } 777 778 int 779 clmpcc_modem_control(ch, bits, howto) 780 struct clmpcc_chan *ch; 781 int bits; 782 int howto; 783 { 784 struct clmpcc_softc *sc = ch->ch_sc; 785 struct tty *tp = ch->ch_tty; 786 int oldch; 787 int msvr; 788 int rbits = 0; 789 790 oldch = clmpcc_select_channel(sc, ch->ch_car); 791 792 switch ( howto ) { 793 case DMGET: 794 msvr = clmpcc_rd_msvr(sc); 795 796 if ( sc->sc_swaprtsdtr ) { 797 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 798 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 799 } else { 800 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 801 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 802 } 803 804 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 805 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 806 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 807 break; 808 809 case DMSET: 810 if ( sc->sc_swaprtsdtr ) { 811 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 812 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 813 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 814 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 815 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 816 } else { 817 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 818 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 819 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 820 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 821 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 822 } 823 break; 824 825 case DMBIS: 826 if ( sc->sc_swaprtsdtr ) { 827 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 828 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 829 if ( ISSET(bits, TIOCM_DTR) ) 830 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 831 } else { 832 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 833 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 834 if ( ISSET(bits, TIOCM_DTR) ) 835 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 836 } 837 break; 838 839 case DMBIC: 840 if ( sc->sc_swaprtsdtr ) { 841 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 842 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 843 if ( ISCLR(bits, TIOCM_DTR) ) 844 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 845 } else { 846 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 847 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 848 if ( ISCLR(bits, TIOCM_DTR) ) 849 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 850 } 851 break; 852 } 853 854 clmpcc_select_channel(sc, oldch); 855 856 return rbits; 857 } 858 859 static int 860 clmpcc_param(tp, t) 861 struct tty *tp; 862 struct termios *t; 863 { 864 struct clmpcc_softc *sc = 865 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 866 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 867 u_char cor; 868 u_char oldch; 869 int oclk, obpr; 870 int iclk, ibpr; 871 int s; 872 873 /* Check requested parameters. */ 874 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 875 return EINVAL; 876 877 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 878 return EINVAL; 879 880 /* 881 * For the console, always force CLOCAL and !HUPCL, so that the port 882 * is always active. 883 */ 884 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 885 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 886 SET(t->c_cflag, CLOCAL); 887 CLR(t->c_cflag, HUPCL); 888 } 889 890 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 891 892 /* If ospeed it zero, hangup the line */ 893 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 894 895 if ( t->c_ospeed ) { 896 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 897 ch->ch_tbpr = obpr; 898 } else { 899 ch->ch_tcor = 0; 900 ch->ch_tbpr = 0; 901 } 902 903 if ( t->c_ispeed ) { 904 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 905 ch->ch_rbpr = ibpr; 906 } else { 907 ch->ch_rcor = 0; 908 ch->ch_rbpr = 0; 909 } 910 911 /* Work out value to use for COR1 */ 912 cor = 0; 913 if ( ISSET(t->c_cflag, PARENB) ) { 914 cor |= CLMPCC_COR1_NORM_PARITY; 915 if ( ISSET(t->c_cflag, PARODD) ) 916 cor |= CLMPCC_COR1_ODD_PARITY; 917 } 918 919 if ( ISCLR(t->c_cflag, INPCK) ) 920 cor |= CLMPCC_COR1_IGNORE_PAR; 921 922 switch ( t->c_cflag & CSIZE ) { 923 case CS5: 924 cor |= CLMPCC_COR1_CHAR_5BITS; 925 break; 926 927 case CS6: 928 cor |= CLMPCC_COR1_CHAR_6BITS; 929 break; 930 931 case CS7: 932 cor |= CLMPCC_COR1_CHAR_7BITS; 933 break; 934 935 case CS8: 936 cor |= CLMPCC_COR1_CHAR_8BITS; 937 break; 938 } 939 940 ch->ch_cor1 = cor; 941 942 /* 943 * The only interesting bit in COR2 is 'CTS Automatic Enable' 944 * when hardware flow control is in effect. 945 */ 946 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 947 948 /* COR3 needs to be set to the number of stop bits... */ 949 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 950 CLMPCC_COR3_STOP_1; 951 952 /* 953 * COR4 contains the FIFO threshold setting. 954 * We adjust the threshold depending on the input speed... 955 */ 956 if ( t->c_ispeed <= 1200 ) 957 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 958 else if ( t->c_ispeed <= 19200 ) 959 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 960 else 961 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 962 963 /* 964 * If chip is used with CTS and DTR swapped, we can enable 965 * automatic hardware flow control. 966 */ 967 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 968 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 969 else 970 ch->ch_cor5 = 0; 971 972 s = splserial(); 973 oldch = clmpcc_select_channel(sc, ch->ch_car); 974 975 /* 976 * COR2 needs to be set immediately otherwise we might never get 977 * a Tx EMPTY interrupt to change the other parameters. 978 */ 979 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 980 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 981 982 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 983 clmpcc_set_params(ch); 984 else 985 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 986 987 clmpcc_select_channel(sc, oldch); 988 989 splx(s); 990 991 return 0; 992 } 993 994 static void 995 clmpcc_set_params(ch) 996 struct clmpcc_chan *ch; 997 { 998 struct clmpcc_softc *sc = ch->ch_sc; 999 u_char r1; 1000 u_char r2; 1001 1002 if ( ch->ch_tcor || ch->ch_tbpr ) { 1003 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 1004 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 1005 /* Only write Tx rate if it really has changed */ 1006 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 1007 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 1008 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 1009 } 1010 } 1011 1012 if ( ch->ch_rcor || ch->ch_rbpr ) { 1013 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 1014 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 1015 /* Only write Rx rate if it really has changed */ 1016 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 1017 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 1018 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1019 } 1020 } 1021 1022 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1023 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1024 /* Any change to COR1 requires an INIT command */ 1025 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1026 } 1027 1028 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1029 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1030 1031 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1032 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1033 /* 1034 * Note: If the FIFO has changed, we always set it to 1035 * zero here and disable the Receive Timeout interrupt. 1036 * It's up to the Rx Interrupt handler to pick the 1037 * appropriate moment to write the new FIFO length. 1038 */ 1039 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1040 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1041 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1042 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1043 } 1044 1045 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1046 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1047 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1048 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1049 } 1050 } 1051 1052 static void 1053 clmpcc_start(tp) 1054 struct tty *tp; 1055 { 1056 struct clmpcc_softc *sc = 1057 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1058 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1059 u_int oldch; 1060 int s; 1061 1062 s = spltty(); 1063 1064 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1065 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1066 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1067 CLR(tp->t_state, TS_ASLEEP); 1068 wakeup(&tp->t_outq); 1069 } 1070 selwakeup(&tp->t_wsel); 1071 } 1072 1073 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1074 CLMPCC_FLG_END_BREAK) || 1075 tp->t_outq.c_cc > 0 ) { 1076 1077 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1078 CLMPCC_FLG_END_BREAK) ) { 1079 ch->ch_obuf_addr = tp->t_outq.c_cf; 1080 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1081 } 1082 1083 /* Enable TX empty interrupts */ 1084 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1085 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1086 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1087 CLMPCC_IER_TX_EMPTY); 1088 clmpcc_select_channel(ch->ch_sc, oldch); 1089 SET(tp->t_state, TS_BUSY); 1090 } 1091 } 1092 1093 splx(s); 1094 } 1095 1096 /* 1097 * Stop output on a line. 1098 */ 1099 void 1100 clmpccstop(tp, flag) 1101 struct tty *tp; 1102 int flag; 1103 { 1104 struct clmpcc_softc *sc = 1105 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1106 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1107 int s; 1108 1109 s = splserial(); 1110 1111 if ( ISSET(tp->t_state, TS_BUSY) ) { 1112 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1113 SET(tp->t_state, TS_FLUSH); 1114 ch->ch_obuf_size = 0; 1115 } 1116 splx(s); 1117 } 1118 1119 /* 1120 * RX interrupt routine 1121 */ 1122 int 1123 clmpcc_rxintr(arg) 1124 void *arg; 1125 { 1126 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1127 struct clmpcc_chan *ch; 1128 u_int8_t *put, *end, rxd; 1129 u_char errstat; 1130 u_char fc, tc; 1131 u_char risr; 1132 u_char rir; 1133 #ifdef DDB 1134 int saw_break = 0; 1135 #endif 1136 1137 /* Receive interrupt active? */ 1138 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1139 1140 /* 1141 * If we're using auto-vectored interrupts, we have to 1142 * verify if the chip is generating the interrupt. 1143 */ 1144 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1145 return 0; 1146 1147 /* Get pointer to interrupting channel's data structure */ 1148 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1149 1150 /* Get the interrupt status register */ 1151 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1152 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1153 u_char reg; 1154 /* 1155 * Set the FIFO threshold to zero, and disable 1156 * further receive timeout interrupts. 1157 */ 1158 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1159 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1160 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1161 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1162 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1163 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1164 return 1; 1165 } 1166 1167 /* How many bytes are waiting in the FIFO? */ 1168 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1169 1170 #ifdef DDB 1171 /* 1172 * Allow BREAK on the console to drop to the debugger. 1173 */ 1174 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1175 risr & CLMPCC_RISR_BREAK ) { 1176 saw_break = 1; 1177 } 1178 #endif 1179 1180 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1181 /* Just get rid of the data */ 1182 while ( fc-- ) 1183 (void) clmpcc_rd_rxdata(sc); 1184 goto rx_done; 1185 } 1186 1187 put = ch->ch_ibuf_wr; 1188 end = ch->ch_ibuf_end; 1189 1190 /* 1191 * Note: The chip is completely hosed WRT these error 1192 * conditions; there seems to be no way to associate 1193 * the error with the correct character in the FIFO. 1194 * We compromise by tagging the first character we read 1195 * with the error. Not perfect, but there's no other way. 1196 */ 1197 errstat = 0; 1198 if ( risr & CLMPCC_RISR_PARITY ) 1199 errstat |= TTY_PE; 1200 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1201 errstat |= TTY_FE; 1202 1203 /* 1204 * As long as there are characters in the FIFO, and we 1205 * have space for them... 1206 */ 1207 while ( fc > 0 ) { 1208 1209 *put++ = rxd = clmpcc_rd_rxdata(sc); 1210 *put++ = errstat; 1211 1212 if ( put >= end ) 1213 put = ch->ch_ibuf; 1214 1215 if ( put == ch->ch_ibuf_rd ) { 1216 put -= 2; 1217 if ( put < ch->ch_ibuf ) 1218 put = end - 2; 1219 } 1220 1221 errstat = 0; 1222 fc--; 1223 } 1224 1225 ch->ch_ibuf_wr = put; 1226 1227 #if 0 1228 if ( sc->sc_swaprtsdtr == 0 && 1229 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1230 /* 1231 * If RTS/DTR are not physically swapped, we have to 1232 * do hardware flow control manually 1233 */ 1234 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1235 } 1236 #endif 1237 1238 rx_done: 1239 if ( fc != tc ) { 1240 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1241 u_char reg; 1242 /* 1243 * Set the FIFO threshold to the preset value, 1244 * and enable receive timeout interrupts. 1245 */ 1246 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1247 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1248 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1249 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1250 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1251 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1252 } 1253 1254 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1255 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1256 if ( sc->sc_soft_running == 0 ) { 1257 sc->sc_soft_running = 1; 1258 (sc->sc_softhook)(sc); 1259 } 1260 #else 1261 softintr_schedule(sc->sc_softintr_cookie); 1262 #endif 1263 } else 1264 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1265 1266 #ifdef DDB 1267 /* 1268 * Only =after= we write REOIR is it safe to drop to the debugger. 1269 */ 1270 if ( saw_break ) 1271 Debugger(); 1272 #endif 1273 1274 return 1; 1275 } 1276 1277 /* 1278 * Tx interrupt routine 1279 */ 1280 int 1281 clmpcc_txintr(arg) 1282 void *arg; 1283 { 1284 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1285 struct clmpcc_chan *ch; 1286 struct tty *tp; 1287 u_char ftc, oftc; 1288 u_char tir, teoir; 1289 int etcmode = 0; 1290 1291 /* Tx interrupt active? */ 1292 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1293 1294 /* 1295 * If we're using auto-vectored interrupts, we have to 1296 * verify if the chip is generating the interrupt. 1297 */ 1298 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1299 return 0; 1300 1301 /* Get pointer to interrupting channel's data structure */ 1302 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1303 tp = ch->ch_tty; 1304 1305 /* Dummy read of the interrupt status register */ 1306 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1307 1308 /* Make sure embedded transmit commands are disabled */ 1309 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1310 1311 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1312 1313 /* Handle a delayed parameter change */ 1314 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1315 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1316 clmpcc_set_params(ch); 1317 } 1318 1319 if ( ch->ch_obuf_size > 0 ) { 1320 u_int n = min(ch->ch_obuf_size, ftc); 1321 1322 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1323 1324 ftc -= n; 1325 ch->ch_obuf_size -= n; 1326 ch->ch_obuf_addr += n; 1327 1328 } else { 1329 /* 1330 * Check if we should start/stop a break 1331 */ 1332 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1333 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1334 /* Enable embedded transmit commands */ 1335 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1336 ch->ch_cor2 | CLMPCC_COR2_ETC); 1337 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1338 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1339 ftc -= 2; 1340 etcmode = 1; 1341 } 1342 1343 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1344 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1345 /* Enable embedded transmit commands */ 1346 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1347 ch->ch_cor2 | CLMPCC_COR2_ETC); 1348 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1349 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1350 ftc -= 2; 1351 etcmode = 1; 1352 } 1353 } 1354 1355 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1356 1357 if ( ftc != oftc ) { 1358 /* 1359 * Enable/disable the Tx FIFO threshold interrupt 1360 * according to how much data is in the FIFO. 1361 * However, always disable the FIFO threshold if 1362 * we've left the channel in 'Embedded Transmit 1363 * Command' mode. 1364 */ 1365 if ( etcmode || ftc >= ch->ch_cor4 ) 1366 tir &= ~CLMPCC_IER_TX_FIFO; 1367 else 1368 tir |= CLMPCC_IER_TX_FIFO; 1369 teoir = 0; 1370 } else { 1371 /* 1372 * No data was sent. 1373 * Disable transmit interrupt. 1374 */ 1375 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1376 teoir = CLMPCC_TEOIR_NO_TRANS; 1377 1378 /* 1379 * Request Tx processing in the soft interrupt handler 1380 */ 1381 ch->ch_tx_done = 1; 1382 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1383 if ( sc->sc_soft_running == 0 ) { 1384 sc->sc_soft_running = 1; 1385 (sc->sc_softhook)(sc); 1386 } 1387 #else 1388 softintr_schedule(sc->sc_softintr_cookie); 1389 #endif 1390 } 1391 1392 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1393 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1394 1395 return 1; 1396 } 1397 1398 /* 1399 * Modem change interrupt routine 1400 */ 1401 int 1402 clmpcc_mdintr(arg) 1403 void *arg; 1404 { 1405 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1406 u_char mir; 1407 1408 /* Modem status interrupt active? */ 1409 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1410 1411 /* 1412 * If we're using auto-vectored interrupts, we have to 1413 * verify if the chip is generating the interrupt. 1414 */ 1415 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1416 return 0; 1417 1418 /* Dummy read of the interrupt status register */ 1419 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1420 1421 /* Retrieve current status of modem lines. */ 1422 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1423 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1424 1425 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1426 1427 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1428 if ( sc->sc_soft_running == 0 ) { 1429 sc->sc_soft_running = 1; 1430 (sc->sc_softhook)(sc); 1431 } 1432 #else 1433 softintr_schedule(sc->sc_softintr_cookie); 1434 #endif 1435 1436 return 1; 1437 } 1438 1439 void 1440 clmpcc_softintr(arg) 1441 void *arg; 1442 { 1443 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1444 struct clmpcc_chan *ch; 1445 struct tty *tp; 1446 int (*rint) __P((int, struct tty *)); 1447 u_char *get; 1448 u_char reg; 1449 u_int c; 1450 int chan; 1451 1452 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1453 sc->sc_soft_running = 0; 1454 #endif 1455 1456 /* Handle Modem state changes too... */ 1457 1458 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1459 ch = &sc->sc_chans[chan]; 1460 tp = ch->ch_tty; 1461 1462 get = ch->ch_ibuf_rd; 1463 rint = tp->t_linesw->l_rint; 1464 1465 /* Squirt buffered incoming data into the tty layer */ 1466 while ( get != ch->ch_ibuf_wr ) { 1467 c = get[0]; 1468 c |= ((u_int)get[1]) << 8; 1469 if ( (rint)(c, tp) == -1 ) { 1470 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1471 break; 1472 } 1473 1474 get += 2; 1475 if ( get == ch->ch_ibuf_end ) 1476 get = ch->ch_ibuf; 1477 1478 ch->ch_ibuf_rd = get; 1479 } 1480 1481 /* 1482 * Is the transmitter idle and in need of attention? 1483 */ 1484 if ( ch->ch_tx_done ) { 1485 ch->ch_tx_done = 0; 1486 1487 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1488 clmpcc_channel_cmd(sc, ch->ch_car, 1489 CLMPCC_CCR_T0_INIT | 1490 CLMPCC_CCR_T0_RX_EN | 1491 CLMPCC_CCR_T0_TX_EN); 1492 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1493 1494 /* 1495 * Allow time for the channel to initialise. 1496 * (Empirically derived duration; there must 1497 * be another way to determine the command 1498 * has completed without busy-waiting...) 1499 */ 1500 delay(800); 1501 1502 /* 1503 * Update the tty layer's idea of the carrier 1504 * bit, in case we changed CLOCAL or MDMBUF. 1505 * We don't hang up here; we only do that by 1506 * explicit request. 1507 */ 1508 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1509 (*tp->t_linesw->l_modem)(tp, reg != 0); 1510 } 1511 1512 CLR(tp->t_state, TS_BUSY); 1513 if ( ISSET(tp->t_state, TS_FLUSH) ) 1514 CLR(tp->t_state, TS_FLUSH); 1515 else 1516 ndflush(&tp->t_outq, 1517 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1518 1519 (*tp->t_linesw->l_start)(tp); 1520 } 1521 } 1522 } 1523 1524 1525 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1526 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1527 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1528 /* 1529 * Following are all routines needed for a cd240x channel to act as console 1530 */ 1531 int 1532 clmpcc_cnattach(sc, chan, rate) 1533 struct clmpcc_softc *sc; 1534 int chan; 1535 int rate; 1536 { 1537 cons_sc = sc; 1538 cons_chan = chan; 1539 cons_rate = rate; 1540 1541 return (clmpcc_init(sc)); 1542 } 1543 1544 /* 1545 * The following functions are polled getc and putc routines, for console use. 1546 */ 1547 static int 1548 clmpcc_common_getc(sc, chan) 1549 struct clmpcc_softc *sc; 1550 int chan; 1551 { 1552 u_char old_chan; 1553 u_char old_ier; 1554 u_char ch, rir, risr; 1555 int s; 1556 1557 s = splhigh(); 1558 1559 /* Save the currently active channel */ 1560 old_chan = clmpcc_select_channel(sc, chan); 1561 1562 /* 1563 * We have to put the channel into RX interrupt mode before 1564 * trying to read the Rx data register. So save the previous 1565 * interrupt mode. 1566 */ 1567 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1568 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1569 1570 /* Loop until we get a character */ 1571 for (;;) { 1572 /* 1573 * The REN bit will be set in the Receive Interrupt Register 1574 * when the CD240x has a character to process. Remember, 1575 * the RACT bit won't be set until we generate an interrupt 1576 * acknowledge cycle via the MD front-end. 1577 */ 1578 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1579 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1580 continue; 1581 1582 /* Acknowledge the request */ 1583 if ( sc->sc_iackhook ) 1584 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1585 1586 /* 1587 * Determine if the interrupt is for the required channel 1588 * and if valid data is available. 1589 */ 1590 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1591 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1592 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1593 risr != 0 ) { 1594 /* Rx error, or BREAK */ 1595 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1596 CLMPCC_REOIR_NO_TRANS); 1597 } else { 1598 /* Dummy read of the FIFO count register */ 1599 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1600 1601 /* Fetch the received character */ 1602 ch = clmpcc_rd_rxdata(sc); 1603 1604 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1605 break; 1606 } 1607 } 1608 1609 /* Restore the original IER and CAR register contents */ 1610 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1611 clmpcc_select_channel(sc, old_chan); 1612 1613 splx(s); 1614 return ch; 1615 } 1616 1617 1618 static void 1619 clmpcc_common_putc(sc, chan, c) 1620 struct clmpcc_softc *sc; 1621 int chan; 1622 int c; 1623 { 1624 u_char old_chan; 1625 int s = splhigh(); 1626 1627 /* Save the currently active channel */ 1628 old_chan = clmpcc_select_channel(sc, chan); 1629 1630 /* 1631 * Since we can only access the Tx Data register from within 1632 * the interrupt handler, the easiest way to get console data 1633 * onto the wire is using one of the Special Transmit Character 1634 * registers. 1635 */ 1636 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1637 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1638 CLMPCC_STCR_SND_SPC); 1639 1640 /* Wait until the "Send Special Character" command is accepted */ 1641 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1642 ; 1643 1644 /* Restore the previous channel selected */ 1645 clmpcc_select_channel(sc, old_chan); 1646 1647 splx(s); 1648 } 1649 1650 int 1651 clmpcccngetc(dev) 1652 dev_t dev; 1653 { 1654 return clmpcc_common_getc(cons_sc, cons_chan); 1655 } 1656 1657 /* 1658 * Console kernel output character routine. 1659 */ 1660 void 1661 clmpcccnputc(dev, c) 1662 dev_t dev; 1663 int c; 1664 { 1665 if ( c == '\n' ) 1666 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1667 1668 clmpcc_common_putc(cons_sc, cons_chan, c); 1669 }
Cache object: a7f2939699e8a0427739f73a91e1c7d6
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