FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/clmpcc.c
1 /* $NetBSD: clmpcc.c,v 1.24 2005/02/27 00:27:01 perry Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Steve C. Woodford.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /*
40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller.
41 */
42
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.24 2005/02/27 00:27:01 perry Exp $");
45
46 #include "opt_ddb.h"
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/ioctl.h>
51 #include <sys/select.h>
52 #include <sys/tty.h>
53 #include <sys/proc.h>
54 #include <sys/user.h>
55 #include <sys/conf.h>
56 #include <sys/file.h>
57 #include <sys/uio.h>
58 #include <sys/kernel.h>
59 #include <sys/syslog.h>
60 #include <sys/device.h>
61 #include <sys/malloc.h>
62
63 #include <machine/bus.h>
64 #include <machine/intr.h>
65 #include <machine/param.h>
66
67 #include <dev/ic/clmpccreg.h>
68 #include <dev/ic/clmpccvar.h>
69 #include <dev/cons.h>
70
71
72 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH)
73 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive."
74 #endif
75
76
77 static int clmpcc_init(struct clmpcc_softc *sc);
78 static void clmpcc_shutdown(struct clmpcc_chan *);
79 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *);
80 static int clmpcc_param(struct tty *, struct termios *);
81 static void clmpcc_set_params(struct clmpcc_chan *);
82 static void clmpcc_start(struct tty *);
83 static int clmpcc_modem_control(struct clmpcc_chan *, int, int);
84
85 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc)
86 #define CLMPCCCHAN(x) (minor(x) & 0x00003)
87 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000)
88
89 /*
90 * These should be in a header file somewhere...
91 */
92 #define ISSET(v, f) (((v) & (f)) != 0)
93 #define ISCLR(v, f) (((v) & (f)) == 0)
94 #define SET(v, f) (v) |= (f)
95 #define CLR(v, f) (v) &= ~(f)
96
97
98 extern struct cfdriver clmpcc_cd;
99
100 dev_type_open(clmpccopen);
101 dev_type_close(clmpccclose);
102 dev_type_read(clmpccread);
103 dev_type_write(clmpccwrite);
104 dev_type_ioctl(clmpccioctl);
105 dev_type_stop(clmpccstop);
106 dev_type_tty(clmpcctty);
107 dev_type_poll(clmpccpoll);
108
109 const struct cdevsw clmpcc_cdevsw = {
110 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl,
111 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY
112 };
113
114 /*
115 * Make this an option variable one can patch.
116 */
117 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE;
118
119
120 /*
121 * Things needed when the device is used as a console
122 */
123 static struct clmpcc_softc *cons_sc = NULL;
124 static int cons_chan;
125 static int cons_rate;
126
127 static int clmpcc_common_getc(struct clmpcc_softc *, int);
128 static void clmpcc_common_putc(struct clmpcc_softc *, int, int);
129 int clmpcccngetc(dev_t);
130 void clmpcccnputc(dev_t, int);
131
132
133 /*
134 * Convenience functions, inlined for speed
135 */
136 #define integrate static inline
137 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int);
138 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int);
139 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int);
140 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int);
141 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *,
142 u_int);
143 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int);
144 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int);
145 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *);
146
147 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR)
148 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v)
149 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v)
150 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR)
151 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v)
152
153
154 integrate u_int8_t
155 clmpcc_rdreg(sc, offset)
156 struct clmpcc_softc *sc;
157 u_int offset;
158 {
159 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
160 offset ^= sc->sc_byteswap;
161 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
162 offset ^= CLMPCC_BYTESWAP_HIGH;
163 #endif
164 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
165 }
166
167 integrate void
168 clmpcc_wrreg(sc, offset, val)
169 struct clmpcc_softc *sc;
170 u_int offset;
171 u_int val;
172 {
173 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
174 offset ^= sc->sc_byteswap;
175 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
176 offset ^= CLMPCC_BYTESWAP_HIGH;
177 #endif
178 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
179 }
180
181 integrate u_int8_t
182 clmpcc_rdreg_odd(sc, offset)
183 struct clmpcc_softc *sc;
184 u_int offset;
185 {
186 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
187 offset ^= (sc->sc_byteswap & 2);
188 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
189 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
190 #endif
191 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
192 }
193
194 integrate void
195 clmpcc_wrreg_odd(sc, offset, val)
196 struct clmpcc_softc *sc;
197 u_int offset;
198 u_int val;
199 {
200 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
201 offset ^= (sc->sc_byteswap & 2);
202 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
203 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
204 #endif
205 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
206 }
207
208 integrate void
209 clmpcc_wrtx_multi(sc, buff, count)
210 struct clmpcc_softc *sc;
211 u_int8_t *buff;
212 u_int count;
213 {
214 u_int offset = CLMPCC_REG_TDR;
215
216 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
217 offset ^= (sc->sc_byteswap & 2);
218 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
219 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
220 #endif
221 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count);
222 }
223
224 integrate u_int8_t
225 clmpcc_select_channel(sc, new_chan)
226 struct clmpcc_softc *sc;
227 u_int new_chan;
228 {
229 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR);
230
231 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan);
232
233 return old_chan;
234 }
235
236 integrate void
237 clmpcc_channel_cmd(sc, chan, cmd)
238 struct clmpcc_softc *sc;
239 int chan;
240 int cmd;
241 {
242 int i;
243
244 for (i = 5000; i; i--) {
245 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 )
246 break;
247 delay(1);
248 }
249
250 if ( i == 0 )
251 printf("%s: channel %d command timeout (idle)\n",
252 sc->sc_dev.dv_xname, chan);
253
254 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd);
255 }
256
257 integrate void
258 clmpcc_enable_transmitter(ch)
259 struct clmpcc_chan *ch;
260 {
261 u_int old;
262 int s;
263
264 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
265
266 s = splserial();
267 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
268 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY);
269 SET(ch->ch_tty->t_state, TS_BUSY);
270 splx(s);
271
272 clmpcc_select_channel(ch->ch_sc, old);
273 }
274
275 static int
276 clmpcc_speed(sc, speed, cor, bpr)
277 struct clmpcc_softc *sc;
278 speed_t speed;
279 int *cor, *bpr;
280 {
281 int c, co, br;
282
283 for (co = 0, c = 8; c <= 2048; co++, c *= 4) {
284 br = ((sc->sc_clk / c) / speed) - 1;
285 if ( br < 0x100 ) {
286 *cor = co;
287 *bpr = br;
288 return 0;
289 }
290 }
291
292 return -1;
293 }
294
295 void
296 clmpcc_attach(sc)
297 struct clmpcc_softc *sc;
298 {
299 struct clmpcc_chan *ch;
300 struct tty *tp;
301 int chan;
302
303 if ( cons_sc != NULL &&
304 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh )
305 cons_sc = sc;
306
307 /* Initialise the chip */
308 clmpcc_init(sc);
309
310 printf(": Cirrus Logic CD240%c Serial Controller\n",
311 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '' : '1');
312
313 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
314 sc->sc_soft_running = 0;
315 #else
316 sc->sc_softintr_cookie =
317 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc);
318 #ifdef DEBUG
319 if (sc->sc_softintr_cookie == NULL)
320 panic("clmpcc_attach: softintr_establish");
321 #endif
322 #endif
323 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans));
324
325 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
326 ch = &sc->sc_chans[chan];
327
328 ch->ch_sc = sc;
329 ch->ch_car = chan;
330
331 tp = ttymalloc();
332 tp->t_oproc = clmpcc_start;
333 tp->t_param = clmpcc_param;
334
335 ch->ch_tty = tp;
336
337 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT);
338 if ( ch->ch_ibuf == NULL ) {
339 printf("%s(%d): unable to allocate ring buffer\n",
340 sc->sc_dev.dv_xname, chan);
341 return;
342 }
343
344 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]);
345 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
346
347 tty_attach(tp);
348 }
349
350 printf("%s: %d channels available", sc->sc_dev.dv_xname,
351 CLMPCC_NUM_CHANS);
352 if ( cons_sc == sc ) {
353 printf(", console on channel %d.\n", cons_chan);
354 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE);
355 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR);
356 } else
357 printf(".\n");
358 }
359
360 static int
361 clmpcc_init(sc)
362 struct clmpcc_softc *sc;
363 {
364 u_int tcor, tbpr;
365 u_int rcor, rbpr;
366 u_int msvr_rts, msvr_dtr;
367 u_int ccr;
368 int is_console;
369 int i;
370
371 /*
372 * All we're really concerned about here is putting the chip
373 * into a quiescent state so that it won't do anything until
374 * clmpccopen() is called. (Except the console channel.)
375 */
376
377 /*
378 * If the chip is acting as console, set all channels to the supplied
379 * console baud rate. Otherwise, plump for 9600.
380 */
381 if ( cons_sc &&
382 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) {
383 clmpcc_speed(sc, cons_rate, &tcor, &tbpr);
384 clmpcc_speed(sc, cons_rate, &rcor, &rbpr);
385 is_console = 1;
386 } else {
387 clmpcc_speed(sc, 9600, &tcor, &tbpr);
388 clmpcc_speed(sc, 9600, &rcor, &rbpr);
389 is_console = 0;
390 }
391
392 /* Allow any pending output to be sent */
393 delay(10000);
394
395 /* Send the Reset All command to channel 0 (resets all channels!) */
396 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL);
397
398 delay(1000);
399
400 /*
401 * The chip will set it's firmware revision register to a non-zero
402 * value to indicate completion of reset.
403 */
404 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--)
405 delay(1);
406
407 if ( i == 0 ) {
408 /*
409 * Watch out... If this chip is console, the message
410 * probably won't be sent since we just reset it!
411 */
412 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname);
413 return -1;
414 }
415
416 for (i = 0; i < CLMPCC_NUM_CHANS; i++) {
417 clmpcc_select_channel(sc, i);
418
419 /* All interrupts are disabled to begin with */
420 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0);
421
422 /* Make sure the channel interrupts on the correct vectors */
423 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base);
424 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr);
425 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr);
426 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr);
427
428 /* Receive timer prescaler set to 1ms */
429 clmpcc_wrreg(sc, CLMPCC_REG_TPR,
430 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1));
431
432 /* We support Async mode only */
433 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC);
434
435 /* Set the required baud rate */
436 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor));
437 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr);
438 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor));
439 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr);
440
441 /* Always default to 8N1 (XXX what about console?) */
442 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS |
443 CLMPCC_COR1_NO_PARITY |
444 CLMPCC_COR1_IGNORE_PAR);
445
446 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0);
447
448 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1);
449
450 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd |
451 CLMPCC_COR4_CDzd |
452 CLMPCC_COR4_CTSzd);
453
454 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod |
455 CLMPCC_COR5_CDod |
456 CLMPCC_COR5_CTSod |
457 CLMPCC_COR5_FLOW_NORM);
458
459 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0);
460 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0);
461
462 /* Set the receive FIFO timeout */
463 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT);
464 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0);
465
466 /* At this point, we set up the console differently */
467 if ( is_console && i == cons_chan ) {
468 msvr_rts = CLMPCC_MSVR_RTS;
469 msvr_dtr = CLMPCC_MSVR_DTR;
470 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN;
471 } else {
472 msvr_rts = 0;
473 msvr_dtr = 0;
474 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS;
475 }
476
477 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts);
478 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr);
479 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr);
480 delay(100);
481 }
482
483 return 0;
484 }
485
486 static void
487 clmpcc_shutdown(ch)
488 struct clmpcc_chan *ch;
489 {
490 int oldch;
491
492 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
493
494 /* Turn off interrupts. */
495 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0);
496
497 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
498 /* Disable the transmitter and receiver */
499 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS |
500 CLMPCC_CCR_T0_TX_DIS);
501
502 /* Drop RTS and DTR */
503 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
504 }
505
506 clmpcc_select_channel(ch->ch_sc, oldch);
507 }
508
509 int
510 clmpccopen(dev, flag, mode, p)
511 dev_t dev;
512 int flag, mode;
513 struct proc *p;
514 {
515 struct clmpcc_softc *sc;
516 struct clmpcc_chan *ch;
517 struct tty *tp;
518 int oldch;
519 int error;
520
521 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
522 if (sc == NULL)
523 return (ENXIO);
524
525 ch = &sc->sc_chans[CLMPCCCHAN(dev)];
526
527 tp = ch->ch_tty;
528
529 if ( ISSET(tp->t_state, TS_ISOPEN) &&
530 ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 )
531 return EBUSY;
532
533 /*
534 * Do the following iff this is a first open.
535 */
536 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
537
538 ttychars(tp);
539
540 tp->t_dev = dev;
541 tp->t_iflag = TTYDEF_IFLAG;
542 tp->t_oflag = TTYDEF_OFLAG;
543 tp->t_lflag = TTYDEF_LFLAG;
544 tp->t_cflag = TTYDEF_CFLAG;
545 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED;
546
547 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) )
548 SET(tp->t_cflag, CLOCAL);
549 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) )
550 SET(tp->t_cflag, CRTSCTS);
551 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) )
552 SET(tp->t_cflag, MDMBUF);
553
554 /*
555 * Override some settings if the channel is being
556 * used as the console.
557 */
558 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
559 tp->t_ospeed = tp->t_ispeed = cons_rate;
560 SET(tp->t_cflag, CLOCAL);
561 CLR(tp->t_cflag, CRTSCTS);
562 CLR(tp->t_cflag, HUPCL);
563 }
564
565 ch->ch_control = 0;
566
567 clmpcc_param(tp, &tp->t_termios);
568 ttsetwater(tp);
569
570 /* Clear the input ring */
571 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
572
573 /* Select the channel */
574 oldch = clmpcc_select_channel(sc, ch->ch_car);
575
576 /* Reset it */
577 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR |
578 CLMPCC_CCR_T0_RX_EN |
579 CLMPCC_CCR_T0_TX_EN);
580
581 /* Enable receiver and modem change interrupts. */
582 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM |
583 CLMPCC_IER_RET |
584 CLMPCC_IER_RX_FIFO);
585
586 /* Raise RTS and DTR */
587 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
588
589 clmpcc_select_channel(sc, oldch);
590 } else
591 if ( ISSET(tp->t_state, TS_XCLUDE) && p->p_ucred->cr_uid != 0 )
592 return EBUSY;
593
594 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK));
595 if (error)
596 goto bad;
597
598 error = (*tp->t_linesw->l_open)(dev, tp);
599 if (error)
600 goto bad;
601
602 return 0;
603
604 bad:
605 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
606 /*
607 * We failed to open the device, and nobody else had it opened.
608 * Clean up the state as appropriate.
609 */
610 clmpcc_shutdown(ch);
611 }
612
613 return error;
614 }
615
616 int
617 clmpccclose(dev, flag, mode, p)
618 dev_t dev;
619 int flag, mode;
620 struct proc *p;
621 {
622 struct clmpcc_softc *sc =
623 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
624 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
625 struct tty *tp = ch->ch_tty;
626 int s;
627
628 if ( ISCLR(tp->t_state, TS_ISOPEN) )
629 return 0;
630
631 (*tp->t_linesw->l_close)(tp, flag);
632
633 s = spltty();
634
635 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
636 /*
637 * Although we got a last close, the device may still be in
638 * use; e.g. if this was the dialout node, and there are still
639 * processes waiting for carrier on the non-dialout node.
640 */
641 clmpcc_shutdown(ch);
642 }
643
644 ttyclose(tp);
645
646 splx(s);
647
648 return 0;
649 }
650
651 int
652 clmpccread(dev, uio, flag)
653 dev_t dev;
654 struct uio *uio;
655 int flag;
656 {
657 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
658 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
659
660 return ((*tp->t_linesw->l_read)(tp, uio, flag));
661 }
662
663 int
664 clmpccwrite(dev, uio, flag)
665 dev_t dev;
666 struct uio *uio;
667 int flag;
668 {
669 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
670 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
671
672 return ((*tp->t_linesw->l_write)(tp, uio, flag));
673 }
674
675 int
676 clmpccpoll(dev, events, p)
677 dev_t dev;
678 int events;
679 struct proc *p;
680 {
681 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
682 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
683
684 return ((*tp->t_linesw->l_poll)(tp, events, p));
685 }
686
687 struct tty *
688 clmpcctty(dev)
689 dev_t dev;
690 {
691 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
692
693 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty);
694 }
695
696 int
697 clmpccioctl(dev, cmd, data, flag, p)
698 dev_t dev;
699 u_long cmd;
700 caddr_t data;
701 int flag;
702 struct proc *p;
703 {
704 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev));
705 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
706 struct tty *tp = ch->ch_tty;
707 int error;
708
709 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, p);
710 if (error != EPASSTHROUGH)
711 return error;
712
713 error = ttioctl(tp, cmd, data, flag, p);
714 if (error != EPASSTHROUGH)
715 return error;
716
717 error = 0;
718
719 switch (cmd) {
720 case TIOCSBRK:
721 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK);
722 clmpcc_enable_transmitter(ch);
723 break;
724
725 case TIOCCBRK:
726 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK);
727 clmpcc_enable_transmitter(ch);
728 break;
729
730 case TIOCSDTR:
731 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS);
732 break;
733
734 case TIOCCDTR:
735 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC);
736 break;
737
738 case TIOCMSET:
739 clmpcc_modem_control(ch, *((int *)data), DMSET);
740 break;
741
742 case TIOCMBIS:
743 clmpcc_modem_control(ch, *((int *)data), DMBIS);
744 break;
745
746 case TIOCMBIC:
747 clmpcc_modem_control(ch, *((int *)data), DMBIC);
748 break;
749
750 case TIOCMGET:
751 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET);
752 break;
753
754 case TIOCGFLAGS:
755 *((int *)data) = ch->ch_openflags;
756 break;
757
758 case TIOCSFLAGS:
759 error = suser(p->p_ucred, &p->p_acflag);
760 if ( error )
761 break;
762 ch->ch_openflags = *((int *)data) &
763 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
764 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
765 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) )
766 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR);
767 break;
768
769 default:
770 error = EPASSTHROUGH;
771 break;
772 }
773
774 return error;
775 }
776
777 int
778 clmpcc_modem_control(ch, bits, howto)
779 struct clmpcc_chan *ch;
780 int bits;
781 int howto;
782 {
783 struct clmpcc_softc *sc = ch->ch_sc;
784 struct tty *tp = ch->ch_tty;
785 int oldch;
786 int msvr;
787 int rbits = 0;
788
789 oldch = clmpcc_select_channel(sc, ch->ch_car);
790
791 switch ( howto ) {
792 case DMGET:
793 msvr = clmpcc_rd_msvr(sc);
794
795 if ( sc->sc_swaprtsdtr ) {
796 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0;
797 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0;
798 } else {
799 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0;
800 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0;
801 }
802
803 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0;
804 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0;
805 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0;
806 break;
807
808 case DMSET:
809 if ( sc->sc_swaprtsdtr ) {
810 if ( ISCLR(tp->t_cflag, CRTSCTS) )
811 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
812 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0);
813 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
814 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0);
815 } else {
816 if ( ISCLR(tp->t_cflag, CRTSCTS) )
817 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
818 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0);
819 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
820 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0);
821 }
822 break;
823
824 case DMBIS:
825 if ( sc->sc_swaprtsdtr ) {
826 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
827 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
828 if ( ISSET(bits, TIOCM_DTR) )
829 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
830 } else {
831 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
832 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
833 if ( ISSET(bits, TIOCM_DTR) )
834 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
835 }
836 break;
837
838 case DMBIC:
839 if ( sc->sc_swaprtsdtr ) {
840 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
841 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
842 if ( ISCLR(bits, TIOCM_DTR) )
843 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
844 } else {
845 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
846 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
847 if ( ISCLR(bits, TIOCM_DTR) )
848 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
849 }
850 break;
851 }
852
853 clmpcc_select_channel(sc, oldch);
854
855 return rbits;
856 }
857
858 static int
859 clmpcc_param(tp, t)
860 struct tty *tp;
861 struct termios *t;
862 {
863 struct clmpcc_softc *sc =
864 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
865 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
866 u_char cor;
867 u_char oldch;
868 int oclk, obpr;
869 int iclk, ibpr;
870 int s;
871
872 /* Check requested parameters. */
873 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 )
874 return EINVAL;
875
876 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 )
877 return EINVAL;
878
879 /*
880 * For the console, always force CLOCAL and !HUPCL, so that the port
881 * is always active.
882 */
883 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) ||
884 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
885 SET(t->c_cflag, CLOCAL);
886 CLR(t->c_cflag, HUPCL);
887 }
888
889 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
890
891 /* If ospeed it zero, hangup the line */
892 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS);
893
894 if ( t->c_ospeed ) {
895 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk);
896 ch->ch_tbpr = obpr;
897 } else {
898 ch->ch_tcor = 0;
899 ch->ch_tbpr = 0;
900 }
901
902 if ( t->c_ispeed ) {
903 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk);
904 ch->ch_rbpr = ibpr;
905 } else {
906 ch->ch_rcor = 0;
907 ch->ch_rbpr = 0;
908 }
909
910 /* Work out value to use for COR1 */
911 cor = 0;
912 if ( ISSET(t->c_cflag, PARENB) ) {
913 cor |= CLMPCC_COR1_NORM_PARITY;
914 if ( ISSET(t->c_cflag, PARODD) )
915 cor |= CLMPCC_COR1_ODD_PARITY;
916 }
917
918 if ( ISCLR(t->c_cflag, INPCK) )
919 cor |= CLMPCC_COR1_IGNORE_PAR;
920
921 switch ( t->c_cflag & CSIZE ) {
922 case CS5:
923 cor |= CLMPCC_COR1_CHAR_5BITS;
924 break;
925
926 case CS6:
927 cor |= CLMPCC_COR1_CHAR_6BITS;
928 break;
929
930 case CS7:
931 cor |= CLMPCC_COR1_CHAR_7BITS;
932 break;
933
934 case CS8:
935 cor |= CLMPCC_COR1_CHAR_8BITS;
936 break;
937 }
938
939 ch->ch_cor1 = cor;
940
941 /*
942 * The only interesting bit in COR2 is 'CTS Automatic Enable'
943 * when hardware flow control is in effect.
944 */
945 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0;
946
947 /* COR3 needs to be set to the number of stop bits... */
948 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 :
949 CLMPCC_COR3_STOP_1;
950
951 /*
952 * COR4 contains the FIFO threshold setting.
953 * We adjust the threshold depending on the input speed...
954 */
955 if ( t->c_ispeed <= 1200 )
956 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW;
957 else if ( t->c_ispeed <= 19200 )
958 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED;
959 else
960 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH;
961
962 /*
963 * If chip is used with CTS and DTR swapped, we can enable
964 * automatic hardware flow control.
965 */
966 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) )
967 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM;
968 else
969 ch->ch_cor5 = 0;
970
971 s = splserial();
972 oldch = clmpcc_select_channel(sc, ch->ch_car);
973
974 /*
975 * COR2 needs to be set immediately otherwise we might never get
976 * a Tx EMPTY interrupt to change the other parameters.
977 */
978 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 )
979 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
980
981 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) )
982 clmpcc_set_params(ch);
983 else
984 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
985
986 clmpcc_select_channel(sc, oldch);
987
988 splx(s);
989
990 return 0;
991 }
992
993 static void
994 clmpcc_set_params(ch)
995 struct clmpcc_chan *ch;
996 {
997 struct clmpcc_softc *sc = ch->ch_sc;
998 u_char r1;
999 u_char r2;
1000
1001 if ( ch->ch_tcor || ch->ch_tbpr ) {
1002 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR);
1003 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR);
1004 /* Only write Tx rate if it really has changed */
1005 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) {
1006 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor);
1007 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr);
1008 }
1009 }
1010
1011 if ( ch->ch_rcor || ch->ch_rbpr ) {
1012 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR);
1013 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR);
1014 /* Only write Rx rate if it really has changed */
1015 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) {
1016 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor);
1017 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr);
1018 }
1019 }
1020
1021 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) {
1022 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1);
1023 /* Any change to COR1 requires an INIT command */
1024 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
1025 }
1026
1027 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 )
1028 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3);
1029
1030 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1031 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) {
1032 /*
1033 * Note: If the FIFO has changed, we always set it to
1034 * zero here and disable the Receive Timeout interrupt.
1035 * It's up to the Rx Interrupt handler to pick the
1036 * appropriate moment to write the new FIFO length.
1037 */
1038 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK);
1039 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1040 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET);
1041 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1042 }
1043
1044 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5);
1045 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) {
1046 r1 &= ~CLMPCC_COR5_FLOW_MASK;
1047 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5);
1048 }
1049 }
1050
1051 static void
1052 clmpcc_start(tp)
1053 struct tty *tp;
1054 {
1055 struct clmpcc_softc *sc =
1056 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
1057 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
1058 u_int oldch;
1059 int s;
1060
1061 s = spltty();
1062
1063 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) {
1064 if ( tp->t_outq.c_cc <= tp->t_lowat ) {
1065 if ( ISSET(tp->t_state, TS_ASLEEP) ) {
1066 CLR(tp->t_state, TS_ASLEEP);
1067 wakeup(&tp->t_outq);
1068 }
1069 selwakeup(&tp->t_wsel);
1070 }
1071
1072 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK |
1073 CLMPCC_FLG_END_BREAK) ||
1074 tp->t_outq.c_cc > 0 ) {
1075
1076 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK |
1077 CLMPCC_FLG_END_BREAK) ) {
1078 ch->ch_obuf_addr = tp->t_outq.c_cf;
1079 ch->ch_obuf_size = ndqb(&tp->t_outq, 0);
1080 }
1081
1082 /* Enable TX empty interrupts */
1083 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
1084 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
1085 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) |
1086 CLMPCC_IER_TX_EMPTY);
1087 clmpcc_select_channel(ch->ch_sc, oldch);
1088 SET(tp->t_state, TS_BUSY);
1089 }
1090 }
1091
1092 splx(s);
1093 }
1094
1095 /*
1096 * Stop output on a line.
1097 */
1098 void
1099 clmpccstop(tp, flag)
1100 struct tty *tp;
1101 int flag;
1102 {
1103 struct clmpcc_softc *sc =
1104 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
1105 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
1106 int s;
1107
1108 s = splserial();
1109
1110 if ( ISSET(tp->t_state, TS_BUSY) ) {
1111 if ( ISCLR(tp->t_state, TS_TTSTOP) )
1112 SET(tp->t_state, TS_FLUSH);
1113 ch->ch_obuf_size = 0;
1114 }
1115 splx(s);
1116 }
1117
1118 /*
1119 * RX interrupt routine
1120 */
1121 int
1122 clmpcc_rxintr(arg)
1123 void *arg;
1124 {
1125 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1126 struct clmpcc_chan *ch;
1127 u_int8_t *put, *end, rxd;
1128 u_char errstat;
1129 u_char fc, tc;
1130 u_char risr;
1131 u_char rir;
1132 #ifdef DDB
1133 int saw_break = 0;
1134 #endif
1135
1136 /* Receive interrupt active? */
1137 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1138
1139 /*
1140 * If we're using auto-vectored interrupts, we have to
1141 * verify if the chip is generating the interrupt.
1142 */
1143 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 )
1144 return 0;
1145
1146 /* Get pointer to interrupting channel's data structure */
1147 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK];
1148
1149 /* Get the interrupt status register */
1150 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl);
1151 if ( risr & CLMPCC_RISR_TIMEOUT ) {
1152 u_char reg;
1153 /*
1154 * Set the FIFO threshold to zero, and disable
1155 * further receive timeout interrupts.
1156 */
1157 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1158 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK);
1159 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1160 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET);
1161 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1162 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1163 return 1;
1164 }
1165
1166 /* How many bytes are waiting in the FIFO? */
1167 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK;
1168
1169 #ifdef DDB
1170 /*
1171 * Allow BREAK on the console to drop to the debugger.
1172 */
1173 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) &&
1174 risr & CLMPCC_RISR_BREAK ) {
1175 saw_break = 1;
1176 }
1177 #endif
1178
1179 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) {
1180 /* Just get rid of the data */
1181 while ( fc-- )
1182 (void) clmpcc_rd_rxdata(sc);
1183 goto rx_done;
1184 }
1185
1186 put = ch->ch_ibuf_wr;
1187 end = ch->ch_ibuf_end;
1188
1189 /*
1190 * Note: The chip is completely hosed WRT these error
1191 * conditions; there seems to be no way to associate
1192 * the error with the correct character in the FIFO.
1193 * We compromise by tagging the first character we read
1194 * with the error. Not perfect, but there's no other way.
1195 */
1196 errstat = 0;
1197 if ( risr & CLMPCC_RISR_PARITY )
1198 errstat |= TTY_PE;
1199 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) )
1200 errstat |= TTY_FE;
1201
1202 /*
1203 * As long as there are characters in the FIFO, and we
1204 * have space for them...
1205 */
1206 while ( fc > 0 ) {
1207
1208 *put++ = rxd = clmpcc_rd_rxdata(sc);
1209 *put++ = errstat;
1210
1211 if ( put >= end )
1212 put = ch->ch_ibuf;
1213
1214 if ( put == ch->ch_ibuf_rd ) {
1215 put -= 2;
1216 if ( put < ch->ch_ibuf )
1217 put = end - 2;
1218 }
1219
1220 errstat = 0;
1221 fc--;
1222 }
1223
1224 ch->ch_ibuf_wr = put;
1225
1226 #if 0
1227 if ( sc->sc_swaprtsdtr == 0 &&
1228 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) {
1229 /*
1230 * If RTS/DTR are not physically swapped, we have to
1231 * do hardware flow control manually
1232 */
1233 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0);
1234 }
1235 #endif
1236
1237 rx_done:
1238 if ( fc != tc ) {
1239 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) {
1240 u_char reg;
1241 /*
1242 * Set the FIFO threshold to the preset value,
1243 * and enable receive timeout interrupts.
1244 */
1245 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1246 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4;
1247 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg);
1248 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1249 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET);
1250 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1251 }
1252
1253 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1254 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1255 if ( sc->sc_soft_running == 0 ) {
1256 sc->sc_soft_running = 1;
1257 (sc->sc_softhook)(sc);
1258 }
1259 #else
1260 softintr_schedule(sc->sc_softintr_cookie);
1261 #endif
1262 } else
1263 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1264
1265 #ifdef DDB
1266 /*
1267 * Only =after= we write REOIR is it safe to drop to the debugger.
1268 */
1269 if ( saw_break )
1270 Debugger();
1271 #endif
1272
1273 return 1;
1274 }
1275
1276 /*
1277 * Tx interrupt routine
1278 */
1279 int
1280 clmpcc_txintr(arg)
1281 void *arg;
1282 {
1283 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1284 struct clmpcc_chan *ch;
1285 struct tty *tp;
1286 u_char ftc, oftc;
1287 u_char tir, teoir;
1288 int etcmode = 0;
1289
1290 /* Tx interrupt active? */
1291 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR);
1292
1293 /*
1294 * If we're using auto-vectored interrupts, we have to
1295 * verify if the chip is generating the interrupt.
1296 */
1297 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 )
1298 return 0;
1299
1300 /* Get pointer to interrupting channel's data structure */
1301 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK];
1302 tp = ch->ch_tty;
1303
1304 /* Dummy read of the interrupt status register */
1305 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR);
1306
1307 /* Make sure embedded transmit commands are disabled */
1308 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
1309
1310 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC);
1311
1312 /* Handle a delayed parameter change */
1313 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) {
1314 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
1315 clmpcc_set_params(ch);
1316 }
1317
1318 if ( ch->ch_obuf_size > 0 ) {
1319 u_int n = min(ch->ch_obuf_size, ftc);
1320
1321 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n);
1322
1323 ftc -= n;
1324 ch->ch_obuf_size -= n;
1325 ch->ch_obuf_addr += n;
1326
1327 } else {
1328 /*
1329 * Check if we should start/stop a break
1330 */
1331 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) {
1332 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK);
1333 /* Enable embedded transmit commands */
1334 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1335 ch->ch_cor2 | CLMPCC_COR2_ETC);
1336 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1337 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK);
1338 ftc -= 2;
1339 etcmode = 1;
1340 }
1341
1342 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) {
1343 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK);
1344 /* Enable embedded transmit commands */
1345 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1346 ch->ch_cor2 | CLMPCC_COR2_ETC);
1347 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1348 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK);
1349 ftc -= 2;
1350 etcmode = 1;
1351 }
1352 }
1353
1354 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1355
1356 if ( ftc != oftc ) {
1357 /*
1358 * Enable/disable the Tx FIFO threshold interrupt
1359 * according to how much data is in the FIFO.
1360 * However, always disable the FIFO threshold if
1361 * we've left the channel in 'Embedded Transmit
1362 * Command' mode.
1363 */
1364 if ( etcmode || ftc >= ch->ch_cor4 )
1365 tir &= ~CLMPCC_IER_TX_FIFO;
1366 else
1367 tir |= CLMPCC_IER_TX_FIFO;
1368 teoir = 0;
1369 } else {
1370 /*
1371 * No data was sent.
1372 * Disable transmit interrupt.
1373 */
1374 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO);
1375 teoir = CLMPCC_TEOIR_NO_TRANS;
1376
1377 /*
1378 * Request Tx processing in the soft interrupt handler
1379 */
1380 ch->ch_tx_done = 1;
1381 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1382 if ( sc->sc_soft_running == 0 ) {
1383 sc->sc_soft_running = 1;
1384 (sc->sc_softhook)(sc);
1385 }
1386 #else
1387 softintr_schedule(sc->sc_softintr_cookie);
1388 #endif
1389 }
1390
1391 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir);
1392 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir);
1393
1394 return 1;
1395 }
1396
1397 /*
1398 * Modem change interrupt routine
1399 */
1400 int
1401 clmpcc_mdintr(arg)
1402 void *arg;
1403 {
1404 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1405 u_char mir;
1406
1407 /* Modem status interrupt active? */
1408 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR);
1409
1410 /*
1411 * If we're using auto-vectored interrupts, we have to
1412 * verify if the chip is generating the interrupt.
1413 */
1414 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 )
1415 return 0;
1416
1417 /* Dummy read of the interrupt status register */
1418 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR);
1419
1420 /* Retrieve current status of modem lines. */
1421 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |=
1422 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1423
1424 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0);
1425
1426 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1427 if ( sc->sc_soft_running == 0 ) {
1428 sc->sc_soft_running = 1;
1429 (sc->sc_softhook)(sc);
1430 }
1431 #else
1432 softintr_schedule(sc->sc_softintr_cookie);
1433 #endif
1434
1435 return 1;
1436 }
1437
1438 void
1439 clmpcc_softintr(arg)
1440 void *arg;
1441 {
1442 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1443 struct clmpcc_chan *ch;
1444 struct tty *tp;
1445 int (*rint)(int, struct tty *);
1446 u_char *get;
1447 u_char reg;
1448 u_int c;
1449 int chan;
1450
1451 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS
1452 sc->sc_soft_running = 0;
1453 #endif
1454
1455 /* Handle Modem state changes too... */
1456
1457 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
1458 ch = &sc->sc_chans[chan];
1459 tp = ch->ch_tty;
1460
1461 get = ch->ch_ibuf_rd;
1462 rint = tp->t_linesw->l_rint;
1463
1464 /* Squirt buffered incoming data into the tty layer */
1465 while ( get != ch->ch_ibuf_wr ) {
1466 c = get[0];
1467 c |= ((u_int)get[1]) << 8;
1468 if ( (rint)(c, tp) == -1 ) {
1469 ch->ch_ibuf_rd = ch->ch_ibuf_wr;
1470 break;
1471 }
1472
1473 get += 2;
1474 if ( get == ch->ch_ibuf_end )
1475 get = ch->ch_ibuf;
1476
1477 ch->ch_ibuf_rd = get;
1478 }
1479
1480 /*
1481 * Is the transmitter idle and in need of attention?
1482 */
1483 if ( ch->ch_tx_done ) {
1484 ch->ch_tx_done = 0;
1485
1486 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) {
1487 clmpcc_channel_cmd(sc, ch->ch_car,
1488 CLMPCC_CCR_T0_INIT |
1489 CLMPCC_CCR_T0_RX_EN |
1490 CLMPCC_CCR_T0_TX_EN);
1491 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
1492
1493 /*
1494 * Allow time for the channel to initialise.
1495 * (Empirically derived duration; there must
1496 * be another way to determine the command
1497 * has completed without busy-waiting...)
1498 */
1499 delay(800);
1500
1501 /*
1502 * Update the tty layer's idea of the carrier
1503 * bit, in case we changed CLOCAL or MDMBUF.
1504 * We don't hang up here; we only do that by
1505 * explicit request.
1506 */
1507 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1508 (*tp->t_linesw->l_modem)(tp, reg != 0);
1509 }
1510
1511 CLR(tp->t_state, TS_BUSY);
1512 if ( ISSET(tp->t_state, TS_FLUSH) )
1513 CLR(tp->t_state, TS_FLUSH);
1514 else
1515 ndflush(&tp->t_outq,
1516 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf));
1517
1518 (*tp->t_linesw->l_start)(tp);
1519 }
1520 }
1521 }
1522
1523
1524 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1525 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1526 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1527 /*
1528 * Following are all routines needed for a cd240x channel to act as console
1529 */
1530 int
1531 clmpcc_cnattach(sc, chan, rate)
1532 struct clmpcc_softc *sc;
1533 int chan;
1534 int rate;
1535 {
1536 cons_sc = sc;
1537 cons_chan = chan;
1538 cons_rate = rate;
1539
1540 return (clmpcc_init(sc));
1541 }
1542
1543 /*
1544 * The following functions are polled getc and putc routines, for console use.
1545 */
1546 static int
1547 clmpcc_common_getc(sc, chan)
1548 struct clmpcc_softc *sc;
1549 int chan;
1550 {
1551 u_char old_chan;
1552 u_char old_ier;
1553 u_char ch, rir, risr;
1554 int s;
1555
1556 s = splhigh();
1557
1558 /* Save the currently active channel */
1559 old_chan = clmpcc_select_channel(sc, chan);
1560
1561 /*
1562 * We have to put the channel into RX interrupt mode before
1563 * trying to read the Rx data register. So save the previous
1564 * interrupt mode.
1565 */
1566 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1567 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO);
1568
1569 /* Loop until we get a character */
1570 for (;;) {
1571 /*
1572 * The REN bit will be set in the Receive Interrupt Register
1573 * when the CD240x has a character to process. Remember,
1574 * the RACT bit won't be set until we generate an interrupt
1575 * acknowledge cycle via the MD front-end.
1576 */
1577 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1578 if ( (rir & CLMPCC_RIR_REN) == 0 )
1579 continue;
1580
1581 /* Acknowledge the request */
1582 if ( sc->sc_iackhook )
1583 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX);
1584
1585 /*
1586 * Determine if the interrupt is for the required channel
1587 * and if valid data is available.
1588 */
1589 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1590 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR);
1591 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan ||
1592 risr != 0 ) {
1593 /* Rx error, or BREAK */
1594 clmpcc_wrreg(sc, CLMPCC_REG_REOIR,
1595 CLMPCC_REOIR_NO_TRANS);
1596 } else {
1597 /* Dummy read of the FIFO count register */
1598 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC);
1599
1600 /* Fetch the received character */
1601 ch = clmpcc_rd_rxdata(sc);
1602
1603 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1604 break;
1605 }
1606 }
1607
1608 /* Restore the original IER and CAR register contents */
1609 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier);
1610 clmpcc_select_channel(sc, old_chan);
1611
1612 splx(s);
1613 return ch;
1614 }
1615
1616
1617 static void
1618 clmpcc_common_putc(sc, chan, c)
1619 struct clmpcc_softc *sc;
1620 int chan;
1621 int c;
1622 {
1623 u_char old_chan;
1624 int s = splhigh();
1625
1626 /* Save the currently active channel */
1627 old_chan = clmpcc_select_channel(sc, chan);
1628
1629 /*
1630 * Since we can only access the Tx Data register from within
1631 * the interrupt handler, the easiest way to get console data
1632 * onto the wire is using one of the Special Transmit Character
1633 * registers.
1634 */
1635 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c);
1636 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) |
1637 CLMPCC_STCR_SND_SPC);
1638
1639 /* Wait until the "Send Special Character" command is accepted */
1640 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 )
1641 ;
1642
1643 /* Restore the previous channel selected */
1644 clmpcc_select_channel(sc, old_chan);
1645
1646 splx(s);
1647 }
1648
1649 int
1650 clmpcccngetc(dev)
1651 dev_t dev;
1652 {
1653 return clmpcc_common_getc(cons_sc, cons_chan);
1654 }
1655
1656 /*
1657 * Console kernel output character routine.
1658 */
1659 void
1660 clmpcccnputc(dev, c)
1661 dev_t dev;
1662 int c;
1663 {
1664 if ( c == '\n' )
1665 clmpcc_common_putc(cons_sc, cons_chan, '\r');
1666
1667 clmpcc_common_putc(cons_sc, cons_chan, c);
1668 }
Cache object: f525ba860fa78201ca497949b9d29627
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