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sys/dev/ic/clmpcc.c
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1 /* $NetBSD: clmpcc.c,v 1.40 2008/06/17 16:27:30 he Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.40 2008/06/17 16:27:30 he Exp $"); 38 39 #include "opt_ddb.h" 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/ioctl.h> 44 #include <sys/select.h> 45 #include <sys/tty.h> 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/conf.h> 49 #include <sys/file.h> 50 #include <sys/uio.h> 51 #include <sys/kernel.h> 52 #include <sys/syslog.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/kauth.h> 56 #include <sys/intr.h> 57 58 #include <sys/bus.h> 59 #include <machine/param.h> 60 61 #include <dev/ic/clmpccreg.h> 62 #include <dev/ic/clmpccvar.h> 63 #include <dev/cons.h> 64 65 66 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 67 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 68 #endif 69 70 71 static int clmpcc_init(struct clmpcc_softc *sc); 72 static void clmpcc_shutdown(struct clmpcc_chan *); 73 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *); 74 static int clmpcc_param(struct tty *, struct termios *); 75 static void clmpcc_set_params(struct clmpcc_chan *); 76 static void clmpcc_start(struct tty *); 77 static int clmpcc_modem_control(struct clmpcc_chan *, int, int); 78 79 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 80 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 81 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 82 83 /* 84 * These should be in a header file somewhere... 85 */ 86 #define ISCLR(v, f) (((v) & (f)) == 0) 87 88 extern struct cfdriver clmpcc_cd; 89 90 dev_type_open(clmpccopen); 91 dev_type_close(clmpccclose); 92 dev_type_read(clmpccread); 93 dev_type_write(clmpccwrite); 94 dev_type_ioctl(clmpccioctl); 95 dev_type_stop(clmpccstop); 96 dev_type_tty(clmpcctty); 97 dev_type_poll(clmpccpoll); 98 99 const struct cdevsw clmpcc_cdevsw = { 100 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl, 101 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY 102 }; 103 104 /* 105 * Make this an option variable one can patch. 106 */ 107 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 108 109 110 /* 111 * Things needed when the device is used as a console 112 */ 113 static struct clmpcc_softc *cons_sc = NULL; 114 static int cons_chan; 115 static int cons_rate; 116 117 static int clmpcc_common_getc(struct clmpcc_softc *, int); 118 static void clmpcc_common_putc(struct clmpcc_softc *, int, int); 119 int clmpcccngetc(dev_t); 120 void clmpcccnputc(dev_t, int); 121 122 123 /* 124 * Convenience functions, inlined for speed 125 */ 126 #define integrate static inline 127 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int); 128 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int); 129 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int); 130 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int); 131 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *, 132 u_int); 133 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int); 134 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int); 135 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *); 136 137 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 138 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 139 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 140 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 141 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 142 143 144 integrate u_int8_t 145 clmpcc_rdreg(sc, offset) 146 struct clmpcc_softc *sc; 147 u_int offset; 148 { 149 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 150 offset ^= sc->sc_byteswap; 151 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 152 offset ^= CLMPCC_BYTESWAP_HIGH; 153 #endif 154 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 155 } 156 157 integrate void 158 clmpcc_wrreg(sc, offset, val) 159 struct clmpcc_softc *sc; 160 u_int offset; 161 u_int val; 162 { 163 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 164 offset ^= sc->sc_byteswap; 165 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 166 offset ^= CLMPCC_BYTESWAP_HIGH; 167 #endif 168 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 169 } 170 171 integrate u_int8_t 172 clmpcc_rdreg_odd(sc, offset) 173 struct clmpcc_softc *sc; 174 u_int offset; 175 { 176 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 177 offset ^= (sc->sc_byteswap & 2); 178 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 179 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 180 #endif 181 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 182 } 183 184 integrate void 185 clmpcc_wrreg_odd(sc, offset, val) 186 struct clmpcc_softc *sc; 187 u_int offset; 188 u_int val; 189 { 190 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 191 offset ^= (sc->sc_byteswap & 2); 192 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 193 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 194 #endif 195 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 196 } 197 198 integrate void 199 clmpcc_wrtx_multi(sc, buff, count) 200 struct clmpcc_softc *sc; 201 u_int8_t *buff; 202 u_int count; 203 { 204 u_int offset = CLMPCC_REG_TDR; 205 206 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 207 offset ^= (sc->sc_byteswap & 2); 208 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 209 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 210 #endif 211 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 212 } 213 214 integrate u_int8_t 215 clmpcc_select_channel(sc, new_chan) 216 struct clmpcc_softc *sc; 217 u_int new_chan; 218 { 219 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 220 221 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 222 223 return old_chan; 224 } 225 226 integrate void 227 clmpcc_channel_cmd(sc, chan, cmd) 228 struct clmpcc_softc *sc; 229 int chan; 230 int cmd; 231 { 232 int i; 233 234 for (i = 5000; i; i--) { 235 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 236 break; 237 delay(1); 238 } 239 240 if ( i == 0 ) 241 printf("%s: channel %d command timeout (idle)\n", 242 device_xname(&sc->sc_dev), chan); 243 244 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 245 } 246 247 integrate void 248 clmpcc_enable_transmitter(ch) 249 struct clmpcc_chan *ch; 250 { 251 u_int old; 252 int s; 253 254 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 255 256 s = splserial(); 257 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 258 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 259 SET(ch->ch_tty->t_state, TS_BUSY); 260 splx(s); 261 262 clmpcc_select_channel(ch->ch_sc, old); 263 } 264 265 static int 266 clmpcc_speed(sc, speed, cor, bpr) 267 struct clmpcc_softc *sc; 268 speed_t speed; 269 int *cor, *bpr; 270 { 271 int c, co, br; 272 273 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 274 br = ((sc->sc_clk / c) / speed) - 1; 275 if ( br < 0x100 ) { 276 *cor = co; 277 *bpr = br; 278 return 0; 279 } 280 } 281 282 return -1; 283 } 284 285 void 286 clmpcc_attach(sc) 287 struct clmpcc_softc *sc; 288 { 289 struct clmpcc_chan *ch; 290 struct tty *tp; 291 int chan; 292 293 if ( cons_sc != NULL && 294 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 295 cons_sc = sc; 296 297 /* Initialise the chip */ 298 clmpcc_init(sc); 299 300 printf(": Cirrus Logic CD240%c Serial Controller\n", 301 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '' : '1'); 302 303 sc->sc_softintr_cookie = 304 softint_establish(SOFTINT_SERIAL, clmpcc_softintr, sc); 305 if (sc->sc_softintr_cookie == NULL) 306 panic("clmpcc_attach: softintr_establish"); 307 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 308 309 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 310 ch = &sc->sc_chans[chan]; 311 312 ch->ch_sc = sc; 313 ch->ch_car = chan; 314 315 tp = ttymalloc(); 316 tp->t_oproc = clmpcc_start; 317 tp->t_param = clmpcc_param; 318 319 ch->ch_tty = tp; 320 321 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 322 if ( ch->ch_ibuf == NULL ) { 323 aprint_error_dev(&sc->sc_dev, "(%d): unable to allocate ring buffer\n", 324 chan); 325 return; 326 } 327 328 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 329 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 330 331 tty_attach(tp); 332 } 333 334 aprint_error_dev(&sc->sc_dev, "%d channels available", 335 CLMPCC_NUM_CHANS); 336 if ( cons_sc == sc ) { 337 printf(", console on channel %d.\n", cons_chan); 338 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 339 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 340 } else 341 printf(".\n"); 342 } 343 344 static int 345 clmpcc_init(sc) 346 struct clmpcc_softc *sc; 347 { 348 u_int tcor, tbpr; 349 u_int rcor, rbpr; 350 u_int msvr_rts, msvr_dtr; 351 u_int ccr; 352 int is_console; 353 int i; 354 355 /* 356 * All we're really concerned about here is putting the chip 357 * into a quiescent state so that it won't do anything until 358 * clmpccopen() is called. (Except the console channel.) 359 */ 360 361 /* 362 * If the chip is acting as console, set all channels to the supplied 363 * console baud rate. Otherwise, plump for 9600. 364 */ 365 if ( cons_sc && 366 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 367 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 368 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 369 is_console = 1; 370 } else { 371 clmpcc_speed(sc, 9600, &tcor, &tbpr); 372 clmpcc_speed(sc, 9600, &rcor, &rbpr); 373 is_console = 0; 374 } 375 376 /* Allow any pending output to be sent */ 377 delay(10000); 378 379 /* Send the Reset All command to channel 0 (resets all channels!) */ 380 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 381 382 delay(1000); 383 384 /* 385 * The chip will set it's firmware revision register to a non-zero 386 * value to indicate completion of reset. 387 */ 388 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 389 delay(1); 390 391 if ( i == 0 ) { 392 /* 393 * Watch out... If this chip is console, the message 394 * probably won't be sent since we just reset it! 395 */ 396 aprint_error_dev(&sc->sc_dev, "Failed to reset chip\n"); 397 return -1; 398 } 399 400 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 401 clmpcc_select_channel(sc, i); 402 403 /* All interrupts are disabled to begin with */ 404 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 405 406 /* Make sure the channel interrupts on the correct vectors */ 407 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 408 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 409 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 410 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 411 412 /* Receive timer prescaler set to 1ms */ 413 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 414 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 415 416 /* We support Async mode only */ 417 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 418 419 /* Set the required baud rate */ 420 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 421 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 422 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 423 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 424 425 /* Always default to 8N1 (XXX what about console?) */ 426 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 427 CLMPCC_COR1_NO_PARITY | 428 CLMPCC_COR1_IGNORE_PAR); 429 430 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 431 432 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 433 434 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 435 CLMPCC_COR4_CDzd | 436 CLMPCC_COR4_CTSzd); 437 438 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 439 CLMPCC_COR5_CDod | 440 CLMPCC_COR5_CTSod | 441 CLMPCC_COR5_FLOW_NORM); 442 443 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 444 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 445 446 /* Set the receive FIFO timeout */ 447 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 448 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 449 450 /* At this point, we set up the console differently */ 451 if ( is_console && i == cons_chan ) { 452 msvr_rts = CLMPCC_MSVR_RTS; 453 msvr_dtr = CLMPCC_MSVR_DTR; 454 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 455 } else { 456 msvr_rts = 0; 457 msvr_dtr = 0; 458 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 459 } 460 461 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 462 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 463 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 464 delay(100); 465 } 466 467 return 0; 468 } 469 470 static void 471 clmpcc_shutdown(ch) 472 struct clmpcc_chan *ch; 473 { 474 int oldch; 475 476 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 477 478 /* Turn off interrupts. */ 479 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 480 481 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 482 /* Disable the transmitter and receiver */ 483 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 484 CLMPCC_CCR_T0_TX_DIS); 485 486 /* Drop RTS and DTR */ 487 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 488 } 489 490 clmpcc_select_channel(ch->ch_sc, oldch); 491 } 492 493 int 494 clmpccopen(dev_t dev, int flag, int mode, struct lwp *l) 495 { 496 struct clmpcc_softc *sc; 497 struct clmpcc_chan *ch; 498 struct tty *tp; 499 int oldch; 500 int error; 501 502 sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 503 if (sc == NULL) 504 return (ENXIO); 505 506 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 507 508 tp = ch->ch_tty; 509 510 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 511 return EBUSY; 512 513 /* 514 * Do the following iff this is a first open. 515 */ 516 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 517 518 ttychars(tp); 519 520 tp->t_dev = dev; 521 tp->t_iflag = TTYDEF_IFLAG; 522 tp->t_oflag = TTYDEF_OFLAG; 523 tp->t_lflag = TTYDEF_LFLAG; 524 tp->t_cflag = TTYDEF_CFLAG; 525 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 526 527 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 528 SET(tp->t_cflag, CLOCAL); 529 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 530 SET(tp->t_cflag, CRTSCTS); 531 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 532 SET(tp->t_cflag, MDMBUF); 533 534 /* 535 * Override some settings if the channel is being 536 * used as the console. 537 */ 538 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 539 tp->t_ospeed = tp->t_ispeed = cons_rate; 540 SET(tp->t_cflag, CLOCAL); 541 CLR(tp->t_cflag, CRTSCTS); 542 CLR(tp->t_cflag, HUPCL); 543 } 544 545 ch->ch_control = 0; 546 547 clmpcc_param(tp, &tp->t_termios); 548 ttsetwater(tp); 549 550 /* Clear the input ring */ 551 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 552 553 /* Select the channel */ 554 oldch = clmpcc_select_channel(sc, ch->ch_car); 555 556 /* Reset it */ 557 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 558 CLMPCC_CCR_T0_RX_EN | 559 CLMPCC_CCR_T0_TX_EN); 560 561 /* Enable receiver and modem change interrupts. */ 562 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 563 CLMPCC_IER_RET | 564 CLMPCC_IER_RX_FIFO); 565 566 /* Raise RTS and DTR */ 567 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 568 569 clmpcc_select_channel(sc, oldch); 570 } 571 572 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 573 if (error) 574 goto bad; 575 576 error = (*tp->t_linesw->l_open)(dev, tp); 577 if (error) 578 goto bad; 579 580 return 0; 581 582 bad: 583 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 584 /* 585 * We failed to open the device, and nobody else had it opened. 586 * Clean up the state as appropriate. 587 */ 588 clmpcc_shutdown(ch); 589 } 590 591 return error; 592 } 593 594 int 595 clmpccclose(dev_t dev, int flag, int mode, struct lwp *l) 596 { 597 struct clmpcc_softc *sc = 598 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 599 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 600 struct tty *tp = ch->ch_tty; 601 int s; 602 603 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 604 return 0; 605 606 (*tp->t_linesw->l_close)(tp, flag); 607 608 s = spltty(); 609 610 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 611 /* 612 * Although we got a last close, the device may still be in 613 * use; e.g. if this was the dialout node, and there are still 614 * processes waiting for carrier on the non-dialout node. 615 */ 616 clmpcc_shutdown(ch); 617 } 618 619 ttyclose(tp); 620 621 splx(s); 622 623 return 0; 624 } 625 626 int 627 clmpccread(dev_t dev, struct uio *uio, int flag) 628 { 629 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 630 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 631 632 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 633 } 634 635 int 636 clmpccwrite(dev_t dev, struct uio *uio, int flag) 637 { 638 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 639 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 640 641 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 642 } 643 644 int 645 clmpccpoll(dev_t dev, int events, struct lwp *l) 646 { 647 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 648 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 649 650 return ((*tp->t_linesw->l_poll)(tp, events, l)); 651 } 652 653 struct tty * 654 clmpcctty(dev_t dev) 655 { 656 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 657 658 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 659 } 660 661 int 662 clmpccioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l) 663 { 664 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev)); 665 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 666 struct tty *tp = ch->ch_tty; 667 int error; 668 669 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 670 if (error != EPASSTHROUGH) 671 return error; 672 673 error = ttioctl(tp, cmd, data, flag, l); 674 if (error != EPASSTHROUGH) 675 return error; 676 677 error = 0; 678 679 switch (cmd) { 680 case TIOCSBRK: 681 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 682 clmpcc_enable_transmitter(ch); 683 break; 684 685 case TIOCCBRK: 686 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 687 clmpcc_enable_transmitter(ch); 688 break; 689 690 case TIOCSDTR: 691 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 692 break; 693 694 case TIOCCDTR: 695 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 696 break; 697 698 case TIOCMSET: 699 clmpcc_modem_control(ch, *((int *)data), DMSET); 700 break; 701 702 case TIOCMBIS: 703 clmpcc_modem_control(ch, *((int *)data), DMBIS); 704 break; 705 706 case TIOCMBIC: 707 clmpcc_modem_control(ch, *((int *)data), DMBIC); 708 break; 709 710 case TIOCMGET: 711 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 712 break; 713 714 case TIOCGFLAGS: 715 *((int *)data) = ch->ch_openflags; 716 break; 717 718 case TIOCSFLAGS: 719 error = kauth_authorize_device_tty(l->l_cred, 720 KAUTH_DEVICE_TTY_PRIVSET, tp); 721 if ( error ) 722 break; 723 ch->ch_openflags = *((int *)data) & 724 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 725 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 726 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 727 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 728 break; 729 730 default: 731 error = EPASSTHROUGH; 732 break; 733 } 734 735 return error; 736 } 737 738 int 739 clmpcc_modem_control(ch, bits, howto) 740 struct clmpcc_chan *ch; 741 int bits; 742 int howto; 743 { 744 struct clmpcc_softc *sc = ch->ch_sc; 745 struct tty *tp = ch->ch_tty; 746 int oldch; 747 int msvr; 748 int rbits = 0; 749 750 oldch = clmpcc_select_channel(sc, ch->ch_car); 751 752 switch ( howto ) { 753 case DMGET: 754 msvr = clmpcc_rd_msvr(sc); 755 756 if ( sc->sc_swaprtsdtr ) { 757 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 758 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 759 } else { 760 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 761 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 762 } 763 764 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 765 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 766 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 767 break; 768 769 case DMSET: 770 if ( sc->sc_swaprtsdtr ) { 771 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 772 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 773 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 774 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 775 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 776 } else { 777 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 778 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 779 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 780 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 781 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 782 } 783 break; 784 785 case DMBIS: 786 if ( sc->sc_swaprtsdtr ) { 787 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 788 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 789 if ( ISSET(bits, TIOCM_DTR) ) 790 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 791 } else { 792 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 793 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 794 if ( ISSET(bits, TIOCM_DTR) ) 795 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 796 } 797 break; 798 799 case DMBIC: 800 if ( sc->sc_swaprtsdtr ) { 801 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 802 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 803 if ( ISCLR(bits, TIOCM_DTR) ) 804 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 805 } else { 806 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 807 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 808 if ( ISCLR(bits, TIOCM_DTR) ) 809 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 810 } 811 break; 812 } 813 814 clmpcc_select_channel(sc, oldch); 815 816 return rbits; 817 } 818 819 static int 820 clmpcc_param(struct tty *tp, struct termios *t) 821 { 822 struct clmpcc_softc *sc = 823 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 824 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 825 u_char cor; 826 u_char oldch; 827 int oclk, obpr; 828 int iclk, ibpr; 829 int s; 830 831 /* Check requested parameters. */ 832 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 833 return EINVAL; 834 835 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 836 return EINVAL; 837 838 /* 839 * For the console, always force CLOCAL and !HUPCL, so that the port 840 * is always active. 841 */ 842 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 843 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 844 SET(t->c_cflag, CLOCAL); 845 CLR(t->c_cflag, HUPCL); 846 } 847 848 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 849 850 /* If ospeed it zero, hangup the line */ 851 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 852 853 if ( t->c_ospeed ) { 854 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 855 ch->ch_tbpr = obpr; 856 } else { 857 ch->ch_tcor = 0; 858 ch->ch_tbpr = 0; 859 } 860 861 if ( t->c_ispeed ) { 862 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 863 ch->ch_rbpr = ibpr; 864 } else { 865 ch->ch_rcor = 0; 866 ch->ch_rbpr = 0; 867 } 868 869 /* Work out value to use for COR1 */ 870 cor = 0; 871 if ( ISSET(t->c_cflag, PARENB) ) { 872 cor |= CLMPCC_COR1_NORM_PARITY; 873 if ( ISSET(t->c_cflag, PARODD) ) 874 cor |= CLMPCC_COR1_ODD_PARITY; 875 } 876 877 if ( ISCLR(t->c_cflag, INPCK) ) 878 cor |= CLMPCC_COR1_IGNORE_PAR; 879 880 switch ( t->c_cflag & CSIZE ) { 881 case CS5: 882 cor |= CLMPCC_COR1_CHAR_5BITS; 883 break; 884 885 case CS6: 886 cor |= CLMPCC_COR1_CHAR_6BITS; 887 break; 888 889 case CS7: 890 cor |= CLMPCC_COR1_CHAR_7BITS; 891 break; 892 893 case CS8: 894 cor |= CLMPCC_COR1_CHAR_8BITS; 895 break; 896 } 897 898 ch->ch_cor1 = cor; 899 900 /* 901 * The only interesting bit in COR2 is 'CTS Automatic Enable' 902 * when hardware flow control is in effect. 903 */ 904 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 905 906 /* COR3 needs to be set to the number of stop bits... */ 907 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 908 CLMPCC_COR3_STOP_1; 909 910 /* 911 * COR4 contains the FIFO threshold setting. 912 * We adjust the threshold depending on the input speed... 913 */ 914 if ( t->c_ispeed <= 1200 ) 915 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 916 else if ( t->c_ispeed <= 19200 ) 917 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 918 else 919 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 920 921 /* 922 * If chip is used with CTS and DTR swapped, we can enable 923 * automatic hardware flow control. 924 */ 925 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 926 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 927 else 928 ch->ch_cor5 = 0; 929 930 s = splserial(); 931 oldch = clmpcc_select_channel(sc, ch->ch_car); 932 933 /* 934 * COR2 needs to be set immediately otherwise we might never get 935 * a Tx EMPTY interrupt to change the other parameters. 936 */ 937 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 938 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 939 940 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 941 clmpcc_set_params(ch); 942 else 943 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 944 945 clmpcc_select_channel(sc, oldch); 946 947 splx(s); 948 949 return 0; 950 } 951 952 static void 953 clmpcc_set_params(ch) 954 struct clmpcc_chan *ch; 955 { 956 struct clmpcc_softc *sc = ch->ch_sc; 957 u_char r1; 958 u_char r2; 959 960 if ( ch->ch_tcor || ch->ch_tbpr ) { 961 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 962 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 963 /* Only write Tx rate if it really has changed */ 964 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 965 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 966 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 967 } 968 } 969 970 if ( ch->ch_rcor || ch->ch_rbpr ) { 971 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 972 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 973 /* Only write Rx rate if it really has changed */ 974 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 975 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 976 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 977 } 978 } 979 980 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 981 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 982 /* Any change to COR1 requires an INIT command */ 983 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 984 } 985 986 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 987 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 988 989 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 990 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 991 /* 992 * Note: If the FIFO has changed, we always set it to 993 * zero here and disable the Receive Timeout interrupt. 994 * It's up to the Rx Interrupt handler to pick the 995 * appropriate moment to write the new FIFO length. 996 */ 997 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 998 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 999 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1000 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1001 } 1002 1003 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1004 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1005 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1006 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1007 } 1008 } 1009 1010 static void 1011 clmpcc_start(struct tty *tp) 1012 { 1013 struct clmpcc_softc *sc = 1014 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1015 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1016 u_int oldch; 1017 int s; 1018 1019 s = spltty(); 1020 1021 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1022 ttypull(tp); 1023 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1024 CLMPCC_FLG_END_BREAK) || 1025 tp->t_outq.c_cc > 0 ) { 1026 1027 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1028 CLMPCC_FLG_END_BREAK) ) { 1029 ch->ch_obuf_addr = tp->t_outq.c_cf; 1030 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1031 } 1032 1033 /* Enable TX empty interrupts */ 1034 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1035 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1036 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1037 CLMPCC_IER_TX_EMPTY); 1038 clmpcc_select_channel(ch->ch_sc, oldch); 1039 SET(tp->t_state, TS_BUSY); 1040 } 1041 } 1042 1043 splx(s); 1044 } 1045 1046 /* 1047 * Stop output on a line. 1048 */ 1049 void 1050 clmpccstop(struct tty *tp, int flag) 1051 { 1052 struct clmpcc_softc *sc = 1053 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1054 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1055 int s; 1056 1057 s = splserial(); 1058 1059 if ( ISSET(tp->t_state, TS_BUSY) ) { 1060 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1061 SET(tp->t_state, TS_FLUSH); 1062 ch->ch_obuf_size = 0; 1063 } 1064 splx(s); 1065 } 1066 1067 /* 1068 * RX interrupt routine 1069 */ 1070 int 1071 clmpcc_rxintr(arg) 1072 void *arg; 1073 { 1074 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1075 struct clmpcc_chan *ch; 1076 u_int8_t *put, *end, rxd; 1077 u_char errstat; 1078 u_char fc, tc; 1079 u_char risr; 1080 u_char rir; 1081 #ifdef DDB 1082 int saw_break = 0; 1083 #endif 1084 1085 /* Receive interrupt active? */ 1086 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1087 1088 /* 1089 * If we're using auto-vectored interrupts, we have to 1090 * verify if the chip is generating the interrupt. 1091 */ 1092 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1093 return 0; 1094 1095 /* Get pointer to interrupting channel's data structure */ 1096 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1097 1098 /* Get the interrupt status register */ 1099 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1100 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1101 u_char reg; 1102 /* 1103 * Set the FIFO threshold to zero, and disable 1104 * further receive timeout interrupts. 1105 */ 1106 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1107 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1108 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1109 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1110 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1111 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1112 return 1; 1113 } 1114 1115 /* How many bytes are waiting in the FIFO? */ 1116 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1117 1118 #ifdef DDB 1119 /* 1120 * Allow BREAK on the console to drop to the debugger. 1121 */ 1122 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1123 risr & CLMPCC_RISR_BREAK ) { 1124 saw_break = 1; 1125 } 1126 #endif 1127 1128 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1129 /* Just get rid of the data */ 1130 while ( fc-- ) 1131 (void) clmpcc_rd_rxdata(sc); 1132 goto rx_done; 1133 } 1134 1135 put = ch->ch_ibuf_wr; 1136 end = ch->ch_ibuf_end; 1137 1138 /* 1139 * Note: The chip is completely hosed WRT these error 1140 * conditions; there seems to be no way to associate 1141 * the error with the correct character in the FIFO. 1142 * We compromise by tagging the first character we read 1143 * with the error. Not perfect, but there's no other way. 1144 */ 1145 errstat = 0; 1146 if ( risr & CLMPCC_RISR_PARITY ) 1147 errstat |= TTY_PE; 1148 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1149 errstat |= TTY_FE; 1150 1151 /* 1152 * As long as there are characters in the FIFO, and we 1153 * have space for them... 1154 */ 1155 while ( fc > 0 ) { 1156 1157 *put++ = rxd = clmpcc_rd_rxdata(sc); 1158 *put++ = errstat; 1159 1160 if ( put >= end ) 1161 put = ch->ch_ibuf; 1162 1163 if ( put == ch->ch_ibuf_rd ) { 1164 put -= 2; 1165 if ( put < ch->ch_ibuf ) 1166 put = end - 2; 1167 } 1168 1169 errstat = 0; 1170 fc--; 1171 } 1172 1173 ch->ch_ibuf_wr = put; 1174 1175 #if 0 1176 if ( sc->sc_swaprtsdtr == 0 && 1177 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1178 /* 1179 * If RTS/DTR are not physically swapped, we have to 1180 * do hardware flow control manually 1181 */ 1182 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1183 } 1184 #endif 1185 1186 rx_done: 1187 if ( fc != tc ) { 1188 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1189 u_char reg; 1190 /* 1191 * Set the FIFO threshold to the preset value, 1192 * and enable receive timeout interrupts. 1193 */ 1194 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1195 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1196 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1197 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1198 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1199 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1200 } 1201 1202 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1203 softint_schedule(sc->sc_softintr_cookie); 1204 } else 1205 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1206 1207 #ifdef DDB 1208 /* 1209 * Only =after= we write REOIR is it safe to drop to the debugger. 1210 */ 1211 if ( saw_break ) 1212 Debugger(); 1213 #endif 1214 1215 return 1; 1216 } 1217 1218 /* 1219 * Tx interrupt routine 1220 */ 1221 int 1222 clmpcc_txintr(arg) 1223 void *arg; 1224 { 1225 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1226 struct clmpcc_chan *ch; 1227 struct tty *tp; 1228 u_char ftc, oftc; 1229 u_char tir, teoir; 1230 int etcmode = 0; 1231 1232 /* Tx interrupt active? */ 1233 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1234 1235 /* 1236 * If we're using auto-vectored interrupts, we have to 1237 * verify if the chip is generating the interrupt. 1238 */ 1239 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1240 return 0; 1241 1242 /* Get pointer to interrupting channel's data structure */ 1243 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1244 tp = ch->ch_tty; 1245 1246 /* Dummy read of the interrupt status register */ 1247 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1248 1249 /* Make sure embedded transmit commands are disabled */ 1250 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1251 1252 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1253 1254 /* Handle a delayed parameter change */ 1255 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1256 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1257 clmpcc_set_params(ch); 1258 } 1259 1260 if ( ch->ch_obuf_size > 0 ) { 1261 u_int n = min(ch->ch_obuf_size, ftc); 1262 1263 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1264 1265 ftc -= n; 1266 ch->ch_obuf_size -= n; 1267 ch->ch_obuf_addr += n; 1268 1269 } else { 1270 /* 1271 * Check if we should start/stop a break 1272 */ 1273 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1274 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1275 /* Enable embedded transmit commands */ 1276 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1277 ch->ch_cor2 | CLMPCC_COR2_ETC); 1278 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1279 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1280 ftc -= 2; 1281 etcmode = 1; 1282 } 1283 1284 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1285 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1286 /* Enable embedded transmit commands */ 1287 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1288 ch->ch_cor2 | CLMPCC_COR2_ETC); 1289 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1290 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1291 ftc -= 2; 1292 etcmode = 1; 1293 } 1294 } 1295 1296 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1297 1298 if ( ftc != oftc ) { 1299 /* 1300 * Enable/disable the Tx FIFO threshold interrupt 1301 * according to how much data is in the FIFO. 1302 * However, always disable the FIFO threshold if 1303 * we've left the channel in 'Embedded Transmit 1304 * Command' mode. 1305 */ 1306 if ( etcmode || ftc >= ch->ch_cor4 ) 1307 tir &= ~CLMPCC_IER_TX_FIFO; 1308 else 1309 tir |= CLMPCC_IER_TX_FIFO; 1310 teoir = 0; 1311 } else { 1312 /* 1313 * No data was sent. 1314 * Disable transmit interrupt. 1315 */ 1316 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1317 teoir = CLMPCC_TEOIR_NO_TRANS; 1318 1319 /* 1320 * Request Tx processing in the soft interrupt handler 1321 */ 1322 ch->ch_tx_done = 1; 1323 softint_schedule(sc->sc_softintr_cookie); 1324 } 1325 1326 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1327 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1328 1329 return 1; 1330 } 1331 1332 /* 1333 * Modem change interrupt routine 1334 */ 1335 int 1336 clmpcc_mdintr(arg) 1337 void *arg; 1338 { 1339 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1340 u_char mir; 1341 1342 /* Modem status interrupt active? */ 1343 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1344 1345 /* 1346 * If we're using auto-vectored interrupts, we have to 1347 * verify if the chip is generating the interrupt. 1348 */ 1349 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1350 return 0; 1351 1352 /* Dummy read of the interrupt status register */ 1353 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1354 1355 /* Retrieve current status of modem lines. */ 1356 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1357 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1358 1359 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1360 softint_schedule(sc->sc_softintr_cookie); 1361 1362 return 1; 1363 } 1364 1365 void 1366 clmpcc_softintr(arg) 1367 void *arg; 1368 { 1369 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1370 struct clmpcc_chan *ch; 1371 struct tty *tp; 1372 int (*rint)(int, struct tty *); 1373 u_char *get; 1374 u_char reg; 1375 u_int c; 1376 int chan; 1377 1378 /* Handle Modem state changes too... */ 1379 1380 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1381 ch = &sc->sc_chans[chan]; 1382 tp = ch->ch_tty; 1383 1384 get = ch->ch_ibuf_rd; 1385 rint = tp->t_linesw->l_rint; 1386 1387 /* Squirt buffered incoming data into the tty layer */ 1388 while ( get != ch->ch_ibuf_wr ) { 1389 c = get[0]; 1390 c |= ((u_int)get[1]) << 8; 1391 if ( (rint)(c, tp) == -1 ) { 1392 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1393 break; 1394 } 1395 1396 get += 2; 1397 if ( get == ch->ch_ibuf_end ) 1398 get = ch->ch_ibuf; 1399 1400 ch->ch_ibuf_rd = get; 1401 } 1402 1403 /* 1404 * Is the transmitter idle and in need of attention? 1405 */ 1406 if ( ch->ch_tx_done ) { 1407 ch->ch_tx_done = 0; 1408 1409 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1410 clmpcc_channel_cmd(sc, ch->ch_car, 1411 CLMPCC_CCR_T0_INIT | 1412 CLMPCC_CCR_T0_RX_EN | 1413 CLMPCC_CCR_T0_TX_EN); 1414 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1415 1416 /* 1417 * Allow time for the channel to initialise. 1418 * (Empirically derived duration; there must 1419 * be another way to determine the command 1420 * has completed without busy-waiting...) 1421 */ 1422 delay(800); 1423 1424 /* 1425 * Update the tty layer's idea of the carrier 1426 * bit, in case we changed CLOCAL or MDMBUF. 1427 * We don't hang up here; we only do that by 1428 * explicit request. 1429 */ 1430 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1431 (*tp->t_linesw->l_modem)(tp, reg != 0); 1432 } 1433 1434 CLR(tp->t_state, TS_BUSY); 1435 if ( ISSET(tp->t_state, TS_FLUSH) ) 1436 CLR(tp->t_state, TS_FLUSH); 1437 else 1438 ndflush(&tp->t_outq, 1439 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1440 1441 (*tp->t_linesw->l_start)(tp); 1442 } 1443 } 1444 } 1445 1446 1447 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1448 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1449 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1450 /* 1451 * Following are all routines needed for a cd240x channel to act as console 1452 */ 1453 int 1454 clmpcc_cnattach(sc, chan, rate) 1455 struct clmpcc_softc *sc; 1456 int chan; 1457 int rate; 1458 { 1459 cons_sc = sc; 1460 cons_chan = chan; 1461 cons_rate = rate; 1462 1463 return (clmpcc_init(sc)); 1464 } 1465 1466 /* 1467 * The following functions are polled getc and putc routines, for console use. 1468 */ 1469 static int 1470 clmpcc_common_getc(sc, chan) 1471 struct clmpcc_softc *sc; 1472 int chan; 1473 { 1474 u_char old_chan; 1475 u_char old_ier; 1476 u_char ch, rir, risr; 1477 int s; 1478 1479 s = splhigh(); 1480 1481 /* Save the currently active channel */ 1482 old_chan = clmpcc_select_channel(sc, chan); 1483 1484 /* 1485 * We have to put the channel into RX interrupt mode before 1486 * trying to read the Rx data register. So save the previous 1487 * interrupt mode. 1488 */ 1489 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1490 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1491 1492 /* Loop until we get a character */ 1493 for (;;) { 1494 /* 1495 * The REN bit will be set in the Receive Interrupt Register 1496 * when the CD240x has a character to process. Remember, 1497 * the RACT bit won't be set until we generate an interrupt 1498 * acknowledge cycle via the MD front-end. 1499 */ 1500 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1501 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1502 continue; 1503 1504 /* Acknowledge the request */ 1505 if ( sc->sc_iackhook ) 1506 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1507 1508 /* 1509 * Determine if the interrupt is for the required channel 1510 * and if valid data is available. 1511 */ 1512 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1513 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1514 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1515 risr != 0 ) { 1516 /* Rx error, or BREAK */ 1517 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1518 CLMPCC_REOIR_NO_TRANS); 1519 } else { 1520 /* Dummy read of the FIFO count register */ 1521 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1522 1523 /* Fetch the received character */ 1524 ch = clmpcc_rd_rxdata(sc); 1525 1526 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1527 break; 1528 } 1529 } 1530 1531 /* Restore the original IER and CAR register contents */ 1532 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1533 clmpcc_select_channel(sc, old_chan); 1534 1535 splx(s); 1536 return ch; 1537 } 1538 1539 1540 static void 1541 clmpcc_common_putc(sc, chan, c) 1542 struct clmpcc_softc *sc; 1543 int chan; 1544 int c; 1545 { 1546 u_char old_chan; 1547 int s = splhigh(); 1548 1549 /* Save the currently active channel */ 1550 old_chan = clmpcc_select_channel(sc, chan); 1551 1552 /* 1553 * Since we can only access the Tx Data register from within 1554 * the interrupt handler, the easiest way to get console data 1555 * onto the wire is using one of the Special Transmit Character 1556 * registers. 1557 */ 1558 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1559 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1560 CLMPCC_STCR_SND_SPC); 1561 1562 /* Wait until the "Send Special Character" command is accepted */ 1563 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1564 ; 1565 1566 /* Restore the previous channel selected */ 1567 clmpcc_select_channel(sc, old_chan); 1568 1569 splx(s); 1570 } 1571 1572 int 1573 clmpcccngetc(dev) 1574 dev_t dev; 1575 { 1576 return clmpcc_common_getc(cons_sc, cons_chan); 1577 } 1578 1579 /* 1580 * Console kernel output character routine. 1581 */ 1582 void 1583 clmpcccnputc(dev, c) 1584 dev_t dev; 1585 int c; 1586 { 1587 if ( c == '\n' ) 1588 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1589 1590 clmpcc_common_putc(cons_sc, cons_chan, c); 1591 }
Cache object: 6281f25ac7a929e0b76ccb975b0887e9
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