FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/com.c
1 /* $NetBSD: com.c,v 1.286 2008/10/25 17:50:29 matt Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999, 2004, 2008 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Copyright (c) 1991 The Regents of the University of California.
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 * 1. Redistributions of source code must retain the above copyright
40 * notice, this list of conditions and the following disclaimer.
41 * 2. Redistributions in binary form must reproduce the above copyright
42 * notice, this list of conditions and the following disclaimer in the
43 * documentation and/or other materials provided with the distribution.
44 * 3. Neither the name of the University nor the names of its contributors
45 * may be used to endorse or promote products derived from this software
46 * without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
49 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
51 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
54 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
55 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
56 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
57 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
58 * SUCH DAMAGE.
59 *
60 * @(#)com.c 7.5 (Berkeley) 5/16/91
61 */
62
63 /*
64 * COM driver, uses National Semiconductor NS16450/NS16550AF UART
65 * Supports automatic hardware flow control on StarTech ST16C650A UART
66 */
67
68 #include <sys/cdefs.h>
69 __KERNEL_RCSID(0, "$NetBSD: com.c,v 1.286 2008/10/25 17:50:29 matt Exp $");
70
71 #include "opt_com.h"
72 #include "opt_ddb.h"
73 #include "opt_kgdb.h"
74 #include "opt_lockdebug.h"
75 #include "opt_multiprocessor.h"
76 #include "opt_ntp.h"
77
78 #include "rnd.h"
79 #if NRND > 0 && defined(RND_COM)
80 #include <sys/rnd.h>
81 #endif
82
83 /* The COM16650 option was renamed to COM_16650. */
84 #ifdef COM16650
85 #error Obsolete COM16650 option; use COM_16650 instead.
86 #endif
87
88 /*
89 * Override cnmagic(9) macro before including <sys/systm.h>.
90 * We need to know if cn_check_magic triggered debugger, so set a flag.
91 * Callers of cn_check_magic must declare int cn_trapped = 0;
92 * XXX: this is *ugly*!
93 */
94 #define cn_trap() \
95 do { \
96 console_debugger(); \
97 cn_trapped = 1; \
98 } while (/* CONSTCOND */ 0)
99
100 #include <sys/param.h>
101 #include <sys/systm.h>
102 #include <sys/ioctl.h>
103 #include <sys/select.h>
104 #include <sys/poll.h>
105 #include <sys/tty.h>
106 #include <sys/proc.h>
107 #include <sys/user.h>
108 #include <sys/conf.h>
109 #include <sys/file.h>
110 #include <sys/uio.h>
111 #include <sys/kernel.h>
112 #include <sys/syslog.h>
113 #include <sys/device.h>
114 #include <sys/malloc.h>
115 #include <sys/timepps.h>
116 #include <sys/vnode.h>
117 #include <sys/kauth.h>
118 #include <sys/intr.h>
119
120 #include <sys/bus.h>
121
122 #include <dev/ic/comreg.h>
123 #include <dev/ic/comvar.h>
124 #include <dev/ic/ns16550reg.h>
125 #include <dev/ic/st16650reg.h>
126 #ifdef COM_HAYESP
127 #include <dev/ic/hayespreg.h>
128 #endif
129 #define com_lcr com_cfcr
130 #include <dev/cons.h>
131
132 #ifdef COM_REGMAP
133 #define CSR_WRITE_1(r, o, v) \
134 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v)
135 #define CSR_READ_1(r, o) \
136 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o])
137 #define CSR_WRITE_2(r, o, v) \
138 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], v)
139 #define CSR_READ_2(r, o) \
140 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o])
141 #define CSR_WRITE_MULTI(r, o, p, n) \
142 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, (r)->cr_map[o], p, n)
143 #else
144 #define CSR_WRITE_1(r, o, v) \
145 bus_space_write_1((r)->cr_iot, (r)->cr_ioh, o, v)
146 #define CSR_READ_1(r, o) \
147 bus_space_read_1((r)->cr_iot, (r)->cr_ioh, o)
148 #define CSR_WRITE_2(r, o, v) \
149 bus_space_write_2((r)->cr_iot, (r)->cr_ioh, o, v)
150 #define CSR_READ_2(r, o) \
151 bus_space_read_2((r)->cr_iot, (r)->cr_ioh, o)
152 #define CSR_WRITE_MULTI(r, o, p, n) \
153 bus_space_write_multi_1((r)->cr_iot, (r)->cr_ioh, o, p, n)
154 #endif
155
156
157 static void com_enable_debugport(struct com_softc *);
158
159 void com_config(struct com_softc *);
160 void com_shutdown(struct com_softc *);
161 int comspeed(long, long, int);
162 static u_char cflag2lcr(tcflag_t);
163 int comparam(struct tty *, struct termios *);
164 void comstart(struct tty *);
165 int comhwiflow(struct tty *, int);
166
167 void com_loadchannelregs(struct com_softc *);
168 void com_hwiflow(struct com_softc *);
169 void com_break(struct com_softc *, int);
170 void com_modem(struct com_softc *, int);
171 void tiocm_to_com(struct com_softc *, u_long, int);
172 int com_to_tiocm(struct com_softc *);
173 void com_iflush(struct com_softc *);
174
175 int com_common_getc(dev_t, struct com_regs *);
176 void com_common_putc(dev_t, struct com_regs *, int);
177
178 int cominit(struct com_regs *, int, int, int, tcflag_t);
179
180 int comcngetc(dev_t);
181 void comcnputc(dev_t, int);
182 void comcnpollc(dev_t, int);
183
184 #define integrate static inline
185 void comsoft(void *);
186 integrate void com_rxsoft(struct com_softc *, struct tty *);
187 integrate void com_txsoft(struct com_softc *, struct tty *);
188 integrate void com_stsoft(struct com_softc *, struct tty *);
189 integrate void com_schedrx(struct com_softc *);
190 void comdiag(void *);
191
192 extern struct cfdriver com_cd;
193
194 dev_type_open(comopen);
195 dev_type_close(comclose);
196 dev_type_read(comread);
197 dev_type_write(comwrite);
198 dev_type_ioctl(comioctl);
199 dev_type_stop(comstop);
200 dev_type_tty(comtty);
201 dev_type_poll(compoll);
202
203 const struct cdevsw com_cdevsw = {
204 comopen, comclose, comread, comwrite, comioctl,
205 comstop, comtty, compoll, nommap, ttykqfilter, D_TTY
206 };
207
208 /*
209 * Make this an option variable one can patch.
210 * But be warned: this must be a power of 2!
211 */
212 u_int com_rbuf_size = COM_RING_SIZE;
213
214 /* Stop input when 3/4 of the ring is full; restart when only 1/4 is full. */
215 u_int com_rbuf_hiwat = (COM_RING_SIZE * 1) / 4;
216 u_int com_rbuf_lowat = (COM_RING_SIZE * 3) / 4;
217
218 static struct com_regs comconsregs;
219 static int comconsattached;
220 static int comconsrate;
221 static tcflag_t comconscflag;
222 static struct cnm_state com_cnm_state;
223
224 #ifdef KGDB
225 #include <sys/kgdb.h>
226
227 static struct com_regs comkgdbregs;
228 static int com_kgdb_attached;
229
230 int com_kgdb_getc(void *);
231 void com_kgdb_putc(void *, int);
232 #endif /* KGDB */
233
234 #ifdef COM_REGMAP
235 /* initializer for typical 16550-ish hardware */
236 #define COM_REG_16550 { \
237 com_data, com_data, com_dlbl, com_dlbh, com_ier, com_iir, com_fifo, \
238 com_efr, com_lcr, com_mcr, com_lsr, com_msr }
239
240 const bus_size_t com_std_map[16] = COM_REG_16550;
241 #endif /* COM_REGMAP */
242
243 #define COMUNIT_MASK 0x7ffff
244 #define COMDIALOUT_MASK 0x80000
245
246 #define COMUNIT(x) (minor(x) & COMUNIT_MASK)
247 #define COMDIALOUT(x) (minor(x) & COMDIALOUT_MASK)
248
249 #define COM_ISALIVE(sc) ((sc)->enabled != 0 && \
250 device_is_active((sc)->sc_dev))
251
252 #define BR BUS_SPACE_BARRIER_READ
253 #define BW BUS_SPACE_BARRIER_WRITE
254 #define COM_BARRIER(r, f) \
255 bus_space_barrier((r)->cr_iot, (r)->cr_ioh, 0, (r)->cr_nports, (f))
256
257 /*ARGSUSED*/
258 int
259 comspeed(long speed, long frequency, int type)
260 {
261 #define divrnd(n, q) (((n)*2/(q)+1)/2) /* divide and round off */
262
263 int x, err;
264 int divisor = 16;
265
266 if ((type == COM_TYPE_OMAP) && (speed > 230400)) {
267 divisor = 13;
268 }
269
270 #if 0
271 if (speed == 0)
272 return (0);
273 #endif
274 if (speed <= 0)
275 return (-1);
276 x = divrnd(frequency / divisor, speed);
277 if (x <= 0)
278 return (-1);
279 err = divrnd(((quad_t)frequency) * 1000 / divisor, speed * x) - 1000;
280 if (err < 0)
281 err = -err;
282 if (err > COM_TOLERANCE)
283 return (-1);
284 return (x);
285
286 #undef divrnd
287 }
288
289 #ifdef COM_DEBUG
290 int com_debug = 0;
291
292 void comstatus(struct com_softc *, const char *);
293 void
294 comstatus(struct com_softc *sc, const char *str)
295 {
296 struct tty *tp = sc->sc_tty;
297
298 aprint_normal_dev(sc->sc_dev,
299 "%s %cclocal %cdcd %cts_carr_on %cdtr %ctx_stopped\n",
300 str,
301 ISSET(tp->t_cflag, CLOCAL) ? '+' : '-',
302 ISSET(sc->sc_msr, MSR_DCD) ? '+' : '-',
303 ISSET(tp->t_state, TS_CARR_ON) ? '+' : '-',
304 ISSET(sc->sc_mcr, MCR_DTR) ? '+' : '-',
305 sc->sc_tx_stopped ? '+' : '-');
306
307 aprint_normal_dev(sc->sc_dev,
308 "%s %ccrtscts %ccts %cts_ttstop %crts rx_flags=0x%x\n",
309 str,
310 ISSET(tp->t_cflag, CRTSCTS) ? '+' : '-',
311 ISSET(sc->sc_msr, MSR_CTS) ? '+' : '-',
312 ISSET(tp->t_state, TS_TTSTOP) ? '+' : '-',
313 ISSET(sc->sc_mcr, MCR_RTS) ? '+' : '-',
314 sc->sc_rx_flags);
315 }
316 #endif
317
318 int
319 com_probe_subr(struct com_regs *regs)
320 {
321
322 /* force access to id reg */
323 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS);
324 CSR_WRITE_1(regs, COM_REG_IIR, 0);
325 if ((CSR_READ_1(regs, COM_REG_LCR) != LCR_8BITS) ||
326 (CSR_READ_1(regs, COM_REG_IIR) & 0x38))
327 return (0);
328
329 return (1);
330 }
331
332 int
333 comprobe1(bus_space_tag_t iot, bus_space_handle_t ioh)
334 {
335 struct com_regs regs;
336
337 regs.cr_iot = iot;
338 regs.cr_ioh = ioh;
339 #ifdef COM_REGMAP
340 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));;
341 #endif
342
343 return com_probe_subr(®s);
344 }
345
346 /*
347 * No locking in this routine; it is only called during attach,
348 * or with the port already locked.
349 */
350 static void
351 com_enable_debugport(struct com_softc *sc)
352 {
353
354 /* Turn on line break interrupt, set carrier. */
355 sc->sc_ier = IER_ERXRDY;
356 if (sc->sc_type == COM_TYPE_PXA2x0)
357 sc->sc_ier |= IER_EUART | IER_ERXTOUT;
358 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
359 SET(sc->sc_mcr, MCR_DTR | MCR_RTS);
360 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr);
361 }
362
363 void
364 com_attach_subr(struct com_softc *sc)
365 {
366 struct com_regs *regsp = &sc->sc_regs;
367 struct tty *tp;
368 #ifdef COM_16650
369 u_int8_t lcr;
370 #endif
371 const char *fifo_msg = NULL;
372
373 aprint_naive("\n");
374
375 callout_init(&sc->sc_diag_callout, 0);
376 mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_HIGH);
377
378 /* Disable interrupts before configuring the device. */
379 if (sc->sc_type == COM_TYPE_PXA2x0)
380 sc->sc_ier = IER_EUART;
381 else
382 sc->sc_ier = 0;
383
384 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
385
386 if (regsp->cr_iot == comconsregs.cr_iot &&
387 regsp->cr_iobase == comconsregs.cr_iobase) {
388 comconsattached = 1;
389
390 /* Make sure the console is always "hardwired". */
391 delay(10000); /* wait for output to finish */
392 SET(sc->sc_hwflags, COM_HW_CONSOLE);
393 SET(sc->sc_swflags, TIOCFLAG_SOFTCAR);
394 }
395
396 /* Probe for FIFO */
397 switch (sc->sc_type) {
398 case COM_TYPE_HAYESP:
399 goto fifodone;
400
401 case COM_TYPE_AU1x00:
402 sc->sc_fifolen = 16;
403 fifo_msg = "Au1X00 UART, working fifo";
404 SET(sc->sc_hwflags, COM_HW_FIFO);
405 goto fifodelay;
406
407 case COM_TYPE_16550_NOERS:
408 sc->sc_fifolen = 16;
409 fifo_msg = "ns16650, no ERS, working fifo";
410 SET(sc->sc_hwflags, COM_HW_FIFO);
411 goto fifodelay;
412
413 case COM_TYPE_OMAP:
414 sc->sc_fifolen = 64;
415 fifo_msg = "OMAP UART, working fifo";
416 SET(sc->sc_hwflags, COM_HW_FIFO);
417 goto fifodelay;
418 }
419
420 sc->sc_fifolen = 1;
421 /* look for a NS 16550AF UART with FIFOs */
422 CSR_WRITE_1(regsp, COM_REG_FIFO,
423 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_14);
424 delay(100);
425 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
426 == IIR_FIFO_MASK)
427 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)
428 == FIFO_TRIGGER_14) {
429 SET(sc->sc_hwflags, COM_HW_FIFO);
430
431 #ifdef COM_16650
432 /*
433 * IIR changes into the EFR if LCR is set to LCR_EERS
434 * on 16650s. We also know IIR != 0 at this point.
435 * Write 0 into the EFR, and read it. If the result
436 * is 0, we have a 16650.
437 *
438 * Older 16650s were broken; the test to detect them
439 * is taken from the Linux driver. Apparently
440 * setting DLAB enable gives access to the EFR on
441 * these chips.
442 */
443 lcr = CSR_READ_1(regsp, COM_REG_LCR);
444 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
445 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
446 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
447 CSR_WRITE_1(regsp, COM_REG_LCR,
448 lcr | LCR_DLAB);
449 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
450 CLR(sc->sc_hwflags, COM_HW_FIFO);
451 sc->sc_fifolen = 0;
452 } else {
453 SET(sc->sc_hwflags, COM_HW_FLOW);
454 sc->sc_fifolen = 32;
455 }
456 } else
457 #endif
458 sc->sc_fifolen = 16;
459
460 #ifdef COM_16650
461 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
462 if (sc->sc_fifolen == 0)
463 fifo_msg = "st16650, broken fifo";
464 else if (sc->sc_fifolen == 32)
465 fifo_msg = "st16650a, working fifo";
466 else
467 #endif
468 fifo_msg = "ns16550a, working fifo";
469 } else
470 fifo_msg = "ns16550, broken fifo";
471 else
472 fifo_msg = "ns8250 or ns16450, no fifo";
473 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
474 fifodelay:
475 /*
476 * Some chips will clear down both Tx and Rx FIFOs when zero is
477 * written to com_fifo. If this chip is the console, writing zero
478 * results in some of the chip/FIFO description being lost, so delay
479 * printing it until now.
480 */
481 delay(10);
482 aprint_normal(": %s\n", fifo_msg);
483 if (ISSET(sc->sc_hwflags, COM_HW_TXFIFO_DISABLE)) {
484 sc->sc_fifolen = 1;
485 aprint_normal_dev(sc->sc_dev, "txfifo disabled\n");
486 }
487
488 fifodone:
489
490 tp = ttymalloc();
491 tp->t_oproc = comstart;
492 tp->t_param = comparam;
493 tp->t_hwiflow = comhwiflow;
494
495 sc->sc_tty = tp;
496 sc->sc_rbuf = malloc(com_rbuf_size << 1, M_DEVBUF, M_NOWAIT);
497 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
498 sc->sc_rbavail = com_rbuf_size;
499 if (sc->sc_rbuf == NULL) {
500 aprint_error_dev(sc->sc_dev,
501 "unable to allocate ring buffer\n");
502 return;
503 }
504 sc->sc_ebuf = sc->sc_rbuf + (com_rbuf_size << 1);
505
506 tty_attach(tp);
507
508 if (!ISSET(sc->sc_hwflags, COM_HW_NOIEN))
509 SET(sc->sc_mcr, MCR_IENABLE);
510
511 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
512 int maj;
513
514 /* locate the major number */
515 maj = cdevsw_lookup_major(&com_cdevsw);
516
517 tp->t_dev = cn_tab->cn_dev = makedev(maj,
518 device_unit(sc->sc_dev));
519
520 aprint_normal_dev(sc->sc_dev, "console\n");
521 }
522
523 #ifdef KGDB
524 /*
525 * Allow kgdb to "take over" this port. If this is
526 * not the console and is the kgdb device, it has
527 * exclusive use. If it's the console _and_ the
528 * kgdb device, it doesn't.
529 */
530 if (regsp->cr_iot == comkgdbregs.cr_iot &&
531 regsp->cr_iobase == comkgdbregs.cr_iobase) {
532 if (!ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
533 com_kgdb_attached = 1;
534
535 SET(sc->sc_hwflags, COM_HW_KGDB);
536 }
537 aprint_normal_dev(sc->sc_dev, "kgdb\n");
538 }
539 #endif
540
541 sc->sc_si = softint_establish(SOFTINT_SERIAL, comsoft, sc);
542
543 #if NRND > 0 && defined(RND_COM)
544 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
545 RND_TYPE_TTY, 0);
546 #endif
547
548 /* if there are no enable/disable functions, assume the device
549 is always enabled */
550 if (!sc->enable)
551 sc->enabled = 1;
552
553 com_config(sc);
554
555 SET(sc->sc_hwflags, COM_HW_DEV_OK);
556 }
557
558 void
559 com_config(struct com_softc *sc)
560 {
561 struct com_regs *regsp = &sc->sc_regs;
562
563 /* Disable interrupts before configuring the device. */
564 if (sc->sc_type == COM_TYPE_PXA2x0)
565 sc->sc_ier = IER_EUART;
566 else
567 sc->sc_ier = 0;
568 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
569 (void) CSR_READ_1(regsp, COM_REG_IIR);
570
571 #ifdef COM_HAYESP
572 /* Look for a Hayes ESP board. */
573 if (sc->sc_type == COM_TYPE_HAYESP) {
574
575 /* Set 16550 compatibility mode */
576 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
577 HAYESP_SETMODE);
578 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
579 HAYESP_MODE_FIFO|HAYESP_MODE_RTS|
580 HAYESP_MODE_SCALE);
581
582 /* Set RTS/CTS flow control */
583 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
584 HAYESP_SETFLOWTYPE);
585 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
586 HAYESP_FLOW_RTS);
587 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
588 HAYESP_FLOW_CTS);
589
590 /* Set flow control levels */
591 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
592 HAYESP_SETRXFLOW);
593 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
594 HAYESP_HIBYTE(HAYESP_RXHIWMARK));
595 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
596 HAYESP_LOBYTE(HAYESP_RXHIWMARK));
597 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
598 HAYESP_HIBYTE(HAYESP_RXLOWMARK));
599 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
600 HAYESP_LOBYTE(HAYESP_RXLOWMARK));
601 }
602 #endif
603
604 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE|COM_HW_KGDB))
605 com_enable_debugport(sc);
606 }
607
608 int
609 com_detach(device_t self, int flags)
610 {
611 struct com_softc *sc = device_private(self);
612 int maj, mn;
613
614 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE))
615 return EBUSY;
616
617 /* locate the major number */
618 maj = cdevsw_lookup_major(&com_cdevsw);
619
620 /* Nuke the vnodes for any open instances. */
621 mn = device_unit(self);
622 vdevgone(maj, mn, mn, VCHR);
623
624 mn |= COMDIALOUT_MASK;
625 vdevgone(maj, mn, mn, VCHR);
626
627 if (sc->sc_rbuf == NULL) {
628 /*
629 * Ring buffer allocation failed in the com_attach_subr,
630 * only the tty is allocated, and nothing else.
631 */
632 ttyfree(sc->sc_tty);
633 return 0;
634 }
635
636 /* Free the receive buffer. */
637 free(sc->sc_rbuf, M_DEVBUF);
638
639 /* Detach and free the tty. */
640 tty_detach(sc->sc_tty);
641 ttyfree(sc->sc_tty);
642
643 /* Unhook the soft interrupt handler. */
644 softint_disestablish(sc->sc_si);
645
646 #if NRND > 0 && defined(RND_COM)
647 /* Unhook the entropy source. */
648 rnd_detach_source(&sc->rnd_source);
649 #endif
650 callout_destroy(&sc->sc_diag_callout);
651
652 /* Destroy the lock. */
653 mutex_destroy(&sc->sc_lock);
654
655 return (0);
656 }
657
658 int
659 com_activate(device_t self, enum devact act)
660 {
661 struct com_softc *sc = device_private(self);
662 int rv = 0;
663
664 switch (act) {
665 case DVACT_ACTIVATE:
666 rv = EOPNOTSUPP;
667 break;
668
669 case DVACT_DEACTIVATE:
670 if (sc->sc_hwflags & (COM_HW_CONSOLE|COM_HW_KGDB)) {
671 rv = EBUSY;
672 break;
673 }
674
675 if (sc->disable != NULL && sc->enabled != 0) {
676 (*sc->disable)(sc);
677 sc->enabled = 0;
678 }
679 break;
680 }
681
682 return (rv);
683 }
684
685 void
686 com_shutdown(struct com_softc *sc)
687 {
688 struct tty *tp = sc->sc_tty;
689
690 mutex_spin_enter(&sc->sc_lock);
691
692 /* If we were asserting flow control, then deassert it. */
693 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
694 com_hwiflow(sc);
695
696 /* Clear any break condition set with TIOCSBRK. */
697 com_break(sc, 0);
698
699 /*
700 * Hang up if necessary. Wait a bit, so the other side has time to
701 * notice even if we immediately open the port again.
702 * Avoid tsleeping above splhigh().
703 */
704 if (ISSET(tp->t_cflag, HUPCL)) {
705 com_modem(sc, 0);
706 mutex_spin_exit(&sc->sc_lock);
707 /* XXX will only timeout */
708 (void) kpause(ttclos, false, hz, NULL);
709 mutex_spin_enter(&sc->sc_lock);
710 }
711
712 /* Turn off interrupts. */
713 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
714 sc->sc_ier = IER_ERXRDY; /* interrupt on break */
715 if (sc->sc_type == COM_TYPE_PXA2x0)
716 sc->sc_ier |= IER_ERXTOUT;
717 } else
718 sc->sc_ier = 0;
719
720 if (sc->sc_type == COM_TYPE_PXA2x0)
721 sc->sc_ier |= IER_EUART;
722
723 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
724
725 mutex_spin_exit(&sc->sc_lock);
726
727 if (sc->disable) {
728 #ifdef DIAGNOSTIC
729 if (!sc->enabled)
730 panic("com_shutdown: not enabled?");
731 #endif
732 (*sc->disable)(sc);
733 sc->enabled = 0;
734 }
735 }
736
737 int
738 comopen(dev_t dev, int flag, int mode, struct lwp *l)
739 {
740 struct com_softc *sc;
741 struct tty *tp;
742 int s;
743 int error;
744
745 sc = device_lookup_private(&com_cd, COMUNIT(dev));
746 if (sc == NULL || !ISSET(sc->sc_hwflags, COM_HW_DEV_OK) ||
747 sc->sc_rbuf == NULL)
748 return (ENXIO);
749
750 if (!device_is_active(sc->sc_dev))
751 return (ENXIO);
752
753 #ifdef KGDB
754 /*
755 * If this is the kgdb port, no other use is permitted.
756 */
757 if (ISSET(sc->sc_hwflags, COM_HW_KGDB))
758 return (EBUSY);
759 #endif
760
761 tp = sc->sc_tty;
762
763 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
764 return (EBUSY);
765
766 s = spltty();
767
768 /*
769 * Do the following iff this is a first open.
770 */
771 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
772 struct termios t;
773
774 tp->t_dev = dev;
775
776
777 if (sc->enable) {
778 if ((*sc->enable)(sc)) {
779 splx(s);
780 aprint_error_dev(sc->sc_dev,
781 "device enable failed\n");
782 return (EIO);
783 }
784 mutex_spin_enter(&sc->sc_lock);
785 sc->enabled = 1;
786 com_config(sc);
787 } else {
788 mutex_spin_enter(&sc->sc_lock);
789 }
790
791 /* Turn on interrupts. */
792 sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
793 if (sc->sc_type == COM_TYPE_PXA2x0)
794 sc->sc_ier |= IER_EUART | IER_ERXTOUT;
795 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
796
797 /* Fetch the current modem control status, needed later. */
798 sc->sc_msr = CSR_READ_1(&sc->sc_regs, COM_REG_MSR);
799
800 /* Clear PPS capture state on first open. */
801 mutex_spin_enter(&timecounter_lock);
802 memset(&sc->sc_pps_state, 0, sizeof(sc->sc_pps_state));
803 sc->sc_pps_state.ppscap = PPS_CAPTUREASSERT | PPS_CAPTURECLEAR;
804 pps_init(&sc->sc_pps_state);
805 mutex_spin_exit(&timecounter_lock);
806
807 mutex_spin_exit(&sc->sc_lock);
808
809 /*
810 * Initialize the termios status to the defaults. Add in the
811 * sticky bits from TIOCSFLAGS.
812 */
813 if (ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
814 t.c_ospeed = comconsrate;
815 t.c_cflag = comconscflag;
816 } else {
817 t.c_ospeed = TTYDEF_SPEED;
818 t.c_cflag = TTYDEF_CFLAG;
819 }
820 t.c_ispeed = t.c_ospeed;
821 if (ISSET(sc->sc_swflags, TIOCFLAG_CLOCAL))
822 SET(t.c_cflag, CLOCAL);
823 if (ISSET(sc->sc_swflags, TIOCFLAG_CRTSCTS))
824 SET(t.c_cflag, CRTSCTS);
825 if (ISSET(sc->sc_swflags, TIOCFLAG_MDMBUF))
826 SET(t.c_cflag, MDMBUF);
827 /* Make sure comparam() will do something. */
828 tp->t_ospeed = 0;
829 (void) comparam(tp, &t);
830 tp->t_iflag = TTYDEF_IFLAG;
831 tp->t_oflag = TTYDEF_OFLAG;
832 tp->t_lflag = TTYDEF_LFLAG;
833 ttychars(tp);
834 ttsetwater(tp);
835
836 mutex_spin_enter(&sc->sc_lock);
837
838 /*
839 * Turn on DTR. We must always do this, even if carrier is not
840 * present, because otherwise we'd have to use TIOCSDTR
841 * immediately after setting CLOCAL, which applications do not
842 * expect. We always assert DTR while the device is open
843 * unless explicitly requested to deassert it.
844 */
845 com_modem(sc, 1);
846
847 /* Clear the input ring, and unblock. */
848 sc->sc_rbput = sc->sc_rbget = sc->sc_rbuf;
849 sc->sc_rbavail = com_rbuf_size;
850 com_iflush(sc);
851 CLR(sc->sc_rx_flags, RX_ANY_BLOCK);
852 com_hwiflow(sc);
853
854 #ifdef COM_DEBUG
855 if (com_debug)
856 comstatus(sc, "comopen ");
857 #endif
858
859 mutex_spin_exit(&sc->sc_lock);
860 }
861
862 splx(s);
863
864 error = ttyopen(tp, COMDIALOUT(dev), ISSET(flag, O_NONBLOCK));
865 if (error)
866 goto bad;
867
868 error = (*tp->t_linesw->l_open)(dev, tp);
869 if (error)
870 goto bad;
871
872 return (0);
873
874 bad:
875 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
876 /*
877 * We failed to open the device, and nobody else had it opened.
878 * Clean up the state as appropriate.
879 */
880 com_shutdown(sc);
881 }
882
883 return (error);
884 }
885
886 int
887 comclose(dev_t dev, int flag, int mode, struct lwp *l)
888 {
889 struct com_softc *sc =
890 device_lookup_private(&com_cd, COMUNIT(dev));
891 struct tty *tp = sc->sc_tty;
892
893 /* XXX This is for cons.c. */
894 if (!ISSET(tp->t_state, TS_ISOPEN))
895 return (0);
896
897 (*tp->t_linesw->l_close)(tp, flag);
898 ttyclose(tp);
899
900 if (COM_ISALIVE(sc) == 0)
901 return (0);
902
903 if (!ISSET(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0) {
904 /*
905 * Although we got a last close, the device may still be in
906 * use; e.g. if this was the dialout node, and there are still
907 * processes waiting for carrier on the non-dialout node.
908 */
909 com_shutdown(sc);
910 }
911
912 return (0);
913 }
914
915 int
916 comread(dev_t dev, struct uio *uio, int flag)
917 {
918 struct com_softc *sc =
919 device_lookup_private(&com_cd, COMUNIT(dev));
920 struct tty *tp = sc->sc_tty;
921
922 if (COM_ISALIVE(sc) == 0)
923 return (EIO);
924
925 return ((*tp->t_linesw->l_read)(tp, uio, flag));
926 }
927
928 int
929 comwrite(dev_t dev, struct uio *uio, int flag)
930 {
931 struct com_softc *sc =
932 device_lookup_private(&com_cd, COMUNIT(dev));
933 struct tty *tp = sc->sc_tty;
934
935 if (COM_ISALIVE(sc) == 0)
936 return (EIO);
937
938 return ((*tp->t_linesw->l_write)(tp, uio, flag));
939 }
940
941 int
942 compoll(dev_t dev, int events, struct lwp *l)
943 {
944 struct com_softc *sc =
945 device_lookup_private(&com_cd, COMUNIT(dev));
946 struct tty *tp = sc->sc_tty;
947
948 if (COM_ISALIVE(sc) == 0)
949 return (POLLHUP);
950
951 return ((*tp->t_linesw->l_poll)(tp, events, l));
952 }
953
954 struct tty *
955 comtty(dev_t dev)
956 {
957 struct com_softc *sc =
958 device_lookup_private(&com_cd, COMUNIT(dev));
959 struct tty *tp = sc->sc_tty;
960
961 return (tp);
962 }
963
964 int
965 comioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
966 {
967 struct com_softc *sc;
968 struct tty *tp;
969 int error;
970
971 sc = device_lookup_private(&com_cd, COMUNIT(dev));
972 if (sc == NULL)
973 return ENXIO;
974 if (COM_ISALIVE(sc) == 0)
975 return (EIO);
976
977 tp = sc->sc_tty;
978
979 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
980 if (error != EPASSTHROUGH)
981 return (error);
982
983 error = ttioctl(tp, cmd, data, flag, l);
984 if (error != EPASSTHROUGH)
985 return (error);
986
987 error = 0;
988 switch (cmd) {
989 case TIOCSFLAGS:
990 error = kauth_authorize_device_tty(l->l_cred,
991 KAUTH_DEVICE_TTY_PRIVSET, tp);
992 break;
993 default:
994 /* nothing */
995 break;
996 }
997 if (error) {
998 return error;
999 }
1000
1001 mutex_spin_enter(&sc->sc_lock);
1002
1003 switch (cmd) {
1004 case TIOCSBRK:
1005 com_break(sc, 1);
1006 break;
1007
1008 case TIOCCBRK:
1009 com_break(sc, 0);
1010 break;
1011
1012 case TIOCSDTR:
1013 com_modem(sc, 1);
1014 break;
1015
1016 case TIOCCDTR:
1017 com_modem(sc, 0);
1018 break;
1019
1020 case TIOCGFLAGS:
1021 *(int *)data = sc->sc_swflags;
1022 break;
1023
1024 case TIOCSFLAGS:
1025 sc->sc_swflags = *(int *)data;
1026 break;
1027
1028 case TIOCMSET:
1029 case TIOCMBIS:
1030 case TIOCMBIC:
1031 tiocm_to_com(sc, cmd, *(int *)data);
1032 break;
1033
1034 case TIOCMGET:
1035 *(int *)data = com_to_tiocm(sc);
1036 break;
1037
1038 case PPS_IOC_CREATE:
1039 case PPS_IOC_DESTROY:
1040 case PPS_IOC_GETPARAMS:
1041 case PPS_IOC_SETPARAMS:
1042 case PPS_IOC_GETCAP:
1043 case PPS_IOC_FETCH:
1044 #ifdef PPS_SYNC
1045 case PPS_IOC_KCBIND:
1046 #endif
1047 mutex_spin_enter(&timecounter_lock);
1048 error = pps_ioctl(cmd, data, &sc->sc_pps_state);
1049 mutex_spin_exit(&timecounter_lock);
1050 break;
1051
1052 case TIOCDCDTIMESTAMP: /* XXX old, overloaded API used by xntpd v3 */
1053 mutex_spin_enter(&timecounter_lock);
1054 #ifndef PPS_TRAILING_EDGE
1055 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
1056 &sc->sc_pps_state.ppsinfo.assert_timestamp);
1057 #else
1058 TIMESPEC_TO_TIMEVAL((struct timeval *)data,
1059 &sc->sc_pps_state.ppsinfo.clear_timestamp);
1060 #endif
1061 mutex_spin_exit(&timecounter_lock);
1062 break;
1063
1064 default:
1065 error = EPASSTHROUGH;
1066 break;
1067 }
1068
1069 mutex_spin_exit(&sc->sc_lock);
1070
1071 #ifdef COM_DEBUG
1072 if (com_debug)
1073 comstatus(sc, "comioctl ");
1074 #endif
1075
1076 return (error);
1077 }
1078
1079 integrate void
1080 com_schedrx(struct com_softc *sc)
1081 {
1082
1083 sc->sc_rx_ready = 1;
1084
1085 /* Wake up the poller. */
1086 softint_schedule(sc->sc_si);
1087 }
1088
1089 void
1090 com_break(struct com_softc *sc, int onoff)
1091 {
1092
1093 if (onoff)
1094 SET(sc->sc_lcr, LCR_SBREAK);
1095 else
1096 CLR(sc->sc_lcr, LCR_SBREAK);
1097
1098 if (!sc->sc_heldchange) {
1099 if (sc->sc_tx_busy) {
1100 sc->sc_heldtbc = sc->sc_tbc;
1101 sc->sc_tbc = 0;
1102 sc->sc_heldchange = 1;
1103 } else
1104 com_loadchannelregs(sc);
1105 }
1106 }
1107
1108 void
1109 com_modem(struct com_softc *sc, int onoff)
1110 {
1111
1112 if (sc->sc_mcr_dtr == 0)
1113 return;
1114
1115 if (onoff)
1116 SET(sc->sc_mcr, sc->sc_mcr_dtr);
1117 else
1118 CLR(sc->sc_mcr, sc->sc_mcr_dtr);
1119
1120 if (!sc->sc_heldchange) {
1121 if (sc->sc_tx_busy) {
1122 sc->sc_heldtbc = sc->sc_tbc;
1123 sc->sc_tbc = 0;
1124 sc->sc_heldchange = 1;
1125 } else
1126 com_loadchannelregs(sc);
1127 }
1128 }
1129
1130 void
1131 tiocm_to_com(struct com_softc *sc, u_long how, int ttybits)
1132 {
1133 u_char combits;
1134
1135 combits = 0;
1136 if (ISSET(ttybits, TIOCM_DTR))
1137 SET(combits, MCR_DTR);
1138 if (ISSET(ttybits, TIOCM_RTS))
1139 SET(combits, MCR_RTS);
1140
1141 switch (how) {
1142 case TIOCMBIC:
1143 CLR(sc->sc_mcr, combits);
1144 break;
1145
1146 case TIOCMBIS:
1147 SET(sc->sc_mcr, combits);
1148 break;
1149
1150 case TIOCMSET:
1151 CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
1152 SET(sc->sc_mcr, combits);
1153 break;
1154 }
1155
1156 if (!sc->sc_heldchange) {
1157 if (sc->sc_tx_busy) {
1158 sc->sc_heldtbc = sc->sc_tbc;
1159 sc->sc_tbc = 0;
1160 sc->sc_heldchange = 1;
1161 } else
1162 com_loadchannelregs(sc);
1163 }
1164 }
1165
1166 int
1167 com_to_tiocm(struct com_softc *sc)
1168 {
1169 u_char combits;
1170 int ttybits = 0;
1171
1172 combits = sc->sc_mcr;
1173 if (ISSET(combits, MCR_DTR))
1174 SET(ttybits, TIOCM_DTR);
1175 if (ISSET(combits, MCR_RTS))
1176 SET(ttybits, TIOCM_RTS);
1177
1178 combits = sc->sc_msr;
1179 if (ISSET(combits, MSR_DCD))
1180 SET(ttybits, TIOCM_CD);
1181 if (ISSET(combits, MSR_CTS))
1182 SET(ttybits, TIOCM_CTS);
1183 if (ISSET(combits, MSR_DSR))
1184 SET(ttybits, TIOCM_DSR);
1185 if (ISSET(combits, MSR_RI | MSR_TERI))
1186 SET(ttybits, TIOCM_RI);
1187
1188 if (ISSET(sc->sc_ier, IER_ERXRDY | IER_ETXRDY | IER_ERLS | IER_EMSC))
1189 SET(ttybits, TIOCM_LE);
1190
1191 return (ttybits);
1192 }
1193
1194 static u_char
1195 cflag2lcr(tcflag_t cflag)
1196 {
1197 u_char lcr = 0;
1198
1199 switch (ISSET(cflag, CSIZE)) {
1200 case CS5:
1201 SET(lcr, LCR_5BITS);
1202 break;
1203 case CS6:
1204 SET(lcr, LCR_6BITS);
1205 break;
1206 case CS7:
1207 SET(lcr, LCR_7BITS);
1208 break;
1209 case CS8:
1210 SET(lcr, LCR_8BITS);
1211 break;
1212 }
1213 if (ISSET(cflag, PARENB)) {
1214 SET(lcr, LCR_PENAB);
1215 if (!ISSET(cflag, PARODD))
1216 SET(lcr, LCR_PEVEN);
1217 }
1218 if (ISSET(cflag, CSTOPB))
1219 SET(lcr, LCR_STOPB);
1220
1221 return (lcr);
1222 }
1223
1224 int
1225 comparam(struct tty *tp, struct termios *t)
1226 {
1227 struct com_softc *sc =
1228 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1229 int ospeed;
1230 u_char lcr;
1231
1232 if (COM_ISALIVE(sc) == 0)
1233 return (EIO);
1234
1235 #ifdef COM_HAYESP
1236 if (sc->sc_type == COM_TYPE_HAYESP) {
1237 int prescaler, speed;
1238
1239 /*
1240 * Calculate UART clock prescaler. It should be in
1241 * range of 0 .. 3.
1242 */
1243 for (prescaler = 0, speed = t->c_ospeed; prescaler < 4;
1244 prescaler++, speed /= 2)
1245 if ((ospeed = comspeed(speed, sc->sc_frequency,
1246 sc->sc_type)) > 0)
1247 break;
1248
1249 if (prescaler == 4)
1250 return (EINVAL);
1251 sc->sc_prescaler = prescaler;
1252 } else
1253 #endif
1254 ospeed = comspeed(t->c_ospeed, sc->sc_frequency, sc->sc_type);
1255
1256 /* Check requested parameters. */
1257 if (ospeed < 0)
1258 return (EINVAL);
1259 if (t->c_ispeed && t->c_ispeed != t->c_ospeed)
1260 return (EINVAL);
1261
1262 /*
1263 * For the console, always force CLOCAL and !HUPCL, so that the port
1264 * is always active.
1265 */
1266 if (ISSET(sc->sc_swflags, TIOCFLAG_SOFTCAR) ||
1267 ISSET(sc->sc_hwflags, COM_HW_CONSOLE)) {
1268 SET(t->c_cflag, CLOCAL);
1269 CLR(t->c_cflag, HUPCL);
1270 }
1271
1272 /*
1273 * If there were no changes, don't do anything. This avoids dropping
1274 * input and improves performance when all we did was frob things like
1275 * VMIN and VTIME.
1276 */
1277 if (tp->t_ospeed == t->c_ospeed &&
1278 tp->t_cflag == t->c_cflag)
1279 return (0);
1280
1281 lcr = ISSET(sc->sc_lcr, LCR_SBREAK) | cflag2lcr(t->c_cflag);
1282
1283 mutex_spin_enter(&sc->sc_lock);
1284
1285 sc->sc_lcr = lcr;
1286
1287 /*
1288 * If we're not in a mode that assumes a connection is present, then
1289 * ignore carrier changes.
1290 */
1291 if (ISSET(t->c_cflag, CLOCAL | MDMBUF))
1292 sc->sc_msr_dcd = 0;
1293 else
1294 sc->sc_msr_dcd = MSR_DCD;
1295 /*
1296 * Set the flow control pins depending on the current flow control
1297 * mode.
1298 */
1299 if (ISSET(t->c_cflag, CRTSCTS)) {
1300 sc->sc_mcr_dtr = MCR_DTR;
1301 sc->sc_mcr_rts = MCR_RTS;
1302 sc->sc_msr_cts = MSR_CTS;
1303 sc->sc_efr = EFR_AUTORTS | EFR_AUTOCTS;
1304 } else if (ISSET(t->c_cflag, MDMBUF)) {
1305 /*
1306 * For DTR/DCD flow control, make sure we don't toggle DTR for
1307 * carrier detection.
1308 */
1309 sc->sc_mcr_dtr = 0;
1310 sc->sc_mcr_rts = MCR_DTR;
1311 sc->sc_msr_cts = MSR_DCD;
1312 sc->sc_efr = 0;
1313 } else {
1314 /*
1315 * If no flow control, then always set RTS. This will make
1316 * the other side happy if it mistakenly thinks we're doing
1317 * RTS/CTS flow control.
1318 */
1319 sc->sc_mcr_dtr = MCR_DTR | MCR_RTS;
1320 sc->sc_mcr_rts = 0;
1321 sc->sc_msr_cts = 0;
1322 sc->sc_efr = 0;
1323 if (ISSET(sc->sc_mcr, MCR_DTR))
1324 SET(sc->sc_mcr, MCR_RTS);
1325 else
1326 CLR(sc->sc_mcr, MCR_RTS);
1327 }
1328 sc->sc_msr_mask = sc->sc_msr_cts | sc->sc_msr_dcd;
1329
1330 #if 0
1331 if (ospeed == 0)
1332 CLR(sc->sc_mcr, sc->sc_mcr_dtr);
1333 else
1334 SET(sc->sc_mcr, sc->sc_mcr_dtr);
1335 #endif
1336
1337 sc->sc_dlbl = ospeed;
1338 sc->sc_dlbh = ospeed >> 8;
1339
1340 /*
1341 * Set the FIFO threshold based on the receive speed.
1342 *
1343 * * If it's a low speed, it's probably a mouse or some other
1344 * interactive device, so set the threshold low.
1345 * * If it's a high speed, trim the trigger level down to prevent
1346 * overflows.
1347 * * Otherwise set it a bit higher.
1348 */
1349 if (sc->sc_type == COM_TYPE_HAYESP)
1350 sc->sc_fifo = FIFO_DMA_MODE | FIFO_ENABLE | FIFO_TRIGGER_8;
1351 else if (ISSET(sc->sc_hwflags, COM_HW_FIFO)) {
1352 if (t->c_ospeed <= 1200)
1353 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_1;
1354 else if (t->c_ospeed <= 38400)
1355 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_8;
1356 else
1357 sc->sc_fifo = FIFO_ENABLE | FIFO_TRIGGER_4;
1358 } else
1359 sc->sc_fifo = 0;
1360
1361 /* And copy to tty. */
1362 tp->t_ispeed = t->c_ospeed;
1363 tp->t_ospeed = t->c_ospeed;
1364 tp->t_cflag = t->c_cflag;
1365
1366 if (!sc->sc_heldchange) {
1367 if (sc->sc_tx_busy) {
1368 sc->sc_heldtbc = sc->sc_tbc;
1369 sc->sc_tbc = 0;
1370 sc->sc_heldchange = 1;
1371 } else
1372 com_loadchannelregs(sc);
1373 }
1374
1375 if (!ISSET(t->c_cflag, CHWFLOW)) {
1376 /* Disable the high water mark. */
1377 sc->sc_r_hiwat = 0;
1378 sc->sc_r_lowat = 0;
1379 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1380 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1381 com_schedrx(sc);
1382 }
1383 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED)) {
1384 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED|RX_IBUF_BLOCKED);
1385 com_hwiflow(sc);
1386 }
1387 } else {
1388 sc->sc_r_hiwat = com_rbuf_hiwat;
1389 sc->sc_r_lowat = com_rbuf_lowat;
1390 }
1391
1392 mutex_spin_exit(&sc->sc_lock);
1393
1394 /*
1395 * Update the tty layer's idea of the carrier bit, in case we changed
1396 * CLOCAL or MDMBUF. We don't hang up here; we only do that by
1397 * explicit request.
1398 */
1399 (void) (*tp->t_linesw->l_modem)(tp, ISSET(sc->sc_msr, MSR_DCD));
1400
1401 #ifdef COM_DEBUG
1402 if (com_debug)
1403 comstatus(sc, "comparam ");
1404 #endif
1405
1406 if (!ISSET(t->c_cflag, CHWFLOW)) {
1407 if (sc->sc_tx_stopped) {
1408 sc->sc_tx_stopped = 0;
1409 comstart(tp);
1410 }
1411 }
1412
1413 return (0);
1414 }
1415
1416 void
1417 com_iflush(struct com_softc *sc)
1418 {
1419 struct com_regs *regsp = &sc->sc_regs;
1420 #ifdef DIAGNOSTIC
1421 int reg;
1422 #endif
1423 int timo;
1424
1425 #ifdef DIAGNOSTIC
1426 reg = 0xffff;
1427 #endif
1428 timo = 50000;
1429 /* flush any pending I/O */
1430 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)
1431 && --timo)
1432 #ifdef DIAGNOSTIC
1433 reg =
1434 #else
1435 (void)
1436 #endif
1437 CSR_READ_1(regsp, COM_REG_RXDATA);
1438 #ifdef DIAGNOSTIC
1439 if (!timo)
1440 aprint_error_dev(sc->sc_dev, "com_iflush timeout %02x\n", reg);
1441 #endif
1442 }
1443
1444 void
1445 com_loadchannelregs(struct com_softc *sc)
1446 {
1447 struct com_regs *regsp = &sc->sc_regs;
1448
1449 /* XXXXX necessary? */
1450 com_iflush(sc);
1451
1452 if (sc->sc_type == COM_TYPE_PXA2x0)
1453 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
1454 else
1455 CSR_WRITE_1(regsp, COM_REG_IER, 0);
1456
1457 if (sc->sc_type == COM_TYPE_OMAP) {
1458 /* disable before changing settings */
1459 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
1460 }
1461
1462 if (ISSET(sc->sc_hwflags, COM_HW_FLOW)) {
1463 KASSERT(sc->sc_type != COM_TYPE_AU1x00);
1464 KASSERT(sc->sc_type != COM_TYPE_16550_NOERS);
1465 /* no EFR on alchemy */
1466 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1467 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1468 }
1469 if (sc->sc_type == COM_TYPE_AU1x00) {
1470 /* alchemy has single separate 16-bit clock divisor register */
1471 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
1472 (sc->sc_dlbh << 8));
1473 } else {
1474 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
1475 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
1476 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
1477 }
1478 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1479 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
1480 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
1481 #ifdef COM_HAYESP
1482 if (sc->sc_type == COM_TYPE_HAYESP) {
1483 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
1484 HAYESP_SETPRESCALER);
1485 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1486 sc->sc_prescaler);
1487 }
1488 #endif
1489 if (sc->sc_type == COM_TYPE_OMAP) {
1490 /* setup the fifos. the FCR value is not used as long
1491 as SCR[6] and SCR[7] are 0, which they are at reset
1492 and we never touch the SCR register */
1493 uint8_t rx_fifo_trig = 40;
1494 uint8_t tx_fifo_trig = 60;
1495 uint8_t rx_start = 8;
1496 uint8_t rx_halt = 60;
1497 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2);
1498 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2);
1499
1500 /* enable access to TCR & TLR */
1501 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);
1502
1503 /* write tcr and tlr values */
1504 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
1505 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
1506
1507 /* disable access to TCR & TLR */
1508 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);
1509
1510 /* enable again, but mode is based on speed */
1511 if (sc->sc_tty->t_termios.c_ospeed > 230400) {
1512 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
1513 } else {
1514 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
1515 }
1516 }
1517
1518 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1519 }
1520
1521 int
1522 comhwiflow(struct tty *tp, int block)
1523 {
1524 struct com_softc *sc =
1525 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1526
1527 if (COM_ISALIVE(sc) == 0)
1528 return (0);
1529
1530 if (sc->sc_mcr_rts == 0)
1531 return (0);
1532
1533 mutex_spin_enter(&sc->sc_lock);
1534
1535 if (block) {
1536 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1537 SET(sc->sc_rx_flags, RX_TTY_BLOCKED);
1538 com_hwiflow(sc);
1539 }
1540 } else {
1541 if (ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED)) {
1542 CLR(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1543 com_schedrx(sc);
1544 }
1545 if (ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1546 CLR(sc->sc_rx_flags, RX_TTY_BLOCKED);
1547 com_hwiflow(sc);
1548 }
1549 }
1550
1551 mutex_spin_exit(&sc->sc_lock);
1552 return (1);
1553 }
1554
1555 /*
1556 * (un)block input via hw flowcontrol
1557 */
1558 void
1559 com_hwiflow(struct com_softc *sc)
1560 {
1561 struct com_regs *regsp= &sc->sc_regs;
1562
1563 if (sc->sc_mcr_rts == 0)
1564 return;
1565
1566 if (ISSET(sc->sc_rx_flags, RX_ANY_BLOCK)) {
1567 CLR(sc->sc_mcr, sc->sc_mcr_rts);
1568 CLR(sc->sc_mcr_active, sc->sc_mcr_rts);
1569 } else {
1570 SET(sc->sc_mcr, sc->sc_mcr_rts);
1571 SET(sc->sc_mcr_active, sc->sc_mcr_rts);
1572 }
1573 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);
1574 }
1575
1576
1577 void
1578 comstart(struct tty *tp)
1579 {
1580 struct com_softc *sc =
1581 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1582 struct com_regs *regsp = &sc->sc_regs;
1583 int s;
1584
1585 if (COM_ISALIVE(sc) == 0)
1586 return;
1587
1588 s = spltty();
1589 if (ISSET(tp->t_state, TS_BUSY | TS_TIMEOUT | TS_TTSTOP))
1590 goto out;
1591 if (sc->sc_tx_stopped)
1592 goto out;
1593 if (!ttypull(tp))
1594 goto out;
1595
1596 /* Grab the first contiguous region of buffer space. */
1597 {
1598 u_char *tba;
1599 int tbc;
1600
1601 tba = tp->t_outq.c_cf;
1602 tbc = ndqb(&tp->t_outq, 0);
1603
1604 mutex_spin_enter(&sc->sc_lock);
1605
1606 sc->sc_tba = tba;
1607 sc->sc_tbc = tbc;
1608 }
1609
1610 SET(tp->t_state, TS_BUSY);
1611 sc->sc_tx_busy = 1;
1612
1613 /* Enable transmit completion interrupts if necessary. */
1614 if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
1615 SET(sc->sc_ier, IER_ETXRDY);
1616 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1617 }
1618
1619 /* Output the first chunk of the contiguous buffer. */
1620 if (!ISSET(sc->sc_hwflags, COM_HW_NO_TXPRELOAD)) {
1621 u_int n;
1622
1623 n = sc->sc_tbc;
1624 if (n > sc->sc_fifolen)
1625 n = sc->sc_fifolen;
1626 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
1627 sc->sc_tbc -= n;
1628 sc->sc_tba += n;
1629 }
1630
1631 mutex_spin_exit(&sc->sc_lock);
1632 out:
1633 splx(s);
1634 return;
1635 }
1636
1637 /*
1638 * Stop output on a line.
1639 */
1640 void
1641 comstop(struct tty *tp, int flag)
1642 {
1643 struct com_softc *sc =
1644 device_lookup_private(&com_cd, COMUNIT(tp->t_dev));
1645
1646 mutex_spin_enter(&sc->sc_lock);
1647 if (ISSET(tp->t_state, TS_BUSY)) {
1648 /* Stop transmitting at the next chunk. */
1649 sc->sc_tbc = 0;
1650 sc->sc_heldtbc = 0;
1651 if (!ISSET(tp->t_state, TS_TTSTOP))
1652 SET(tp->t_state, TS_FLUSH);
1653 }
1654 mutex_spin_exit(&sc->sc_lock);
1655 }
1656
1657 void
1658 comdiag(void *arg)
1659 {
1660 struct com_softc *sc = arg;
1661 int overflows, floods;
1662
1663 mutex_spin_enter(&sc->sc_lock);
1664 overflows = sc->sc_overflows;
1665 sc->sc_overflows = 0;
1666 floods = sc->sc_floods;
1667 sc->sc_floods = 0;
1668 sc->sc_errors = 0;
1669 mutex_spin_exit(&sc->sc_lock);
1670
1671 log(LOG_WARNING, "%s: %d silo overflow%s, %d ibuf flood%s\n",
1672 device_xname(sc->sc_dev),
1673 overflows, overflows == 1 ? "" : "s",
1674 floods, floods == 1 ? "" : "s");
1675 }
1676
1677 integrate void
1678 com_rxsoft(struct com_softc *sc, struct tty *tp)
1679 {
1680 int (*rint)(int, struct tty *) = tp->t_linesw->l_rint;
1681 u_char *get, *end;
1682 u_int cc, scc;
1683 u_char lsr;
1684 int code;
1685
1686 end = sc->sc_ebuf;
1687 get = sc->sc_rbget;
1688 scc = cc = com_rbuf_size - sc->sc_rbavail;
1689
1690 if (cc == com_rbuf_size) {
1691 sc->sc_floods++;
1692 if (sc->sc_errors++ == 0)
1693 callout_reset(&sc->sc_diag_callout, 60 * hz,
1694 comdiag, sc);
1695 }
1696
1697 /* If not yet open, drop the entire buffer content here */
1698 if (!ISSET(tp->t_state, TS_ISOPEN)) {
1699 get += cc << 1;
1700 if (get >= end)
1701 get -= com_rbuf_size << 1;
1702 cc = 0;
1703 }
1704 while (cc) {
1705 code = get[0];
1706 lsr = get[1];
1707 if (ISSET(lsr, LSR_OE | LSR_BI | LSR_FE | LSR_PE)) {
1708 if (ISSET(lsr, LSR_OE)) {
1709 sc->sc_overflows++;
1710 if (sc->sc_errors++ == 0)
1711 callout_reset(&sc->sc_diag_callout,
1712 60 * hz, comdiag, sc);
1713 }
1714 if (ISSET(lsr, LSR_BI | LSR_FE))
1715 SET(code, TTY_FE);
1716 if (ISSET(lsr, LSR_PE))
1717 SET(code, TTY_PE);
1718 }
1719 if ((*rint)(code, tp) == -1) {
1720 /*
1721 * The line discipline's buffer is out of space.
1722 */
1723 if (!ISSET(sc->sc_rx_flags, RX_TTY_BLOCKED)) {
1724 /*
1725 * We're either not using flow control, or the
1726 * line discipline didn't tell us to block for
1727 * some reason. Either way, we have no way to
1728 * know when there's more space available, so
1729 * just drop the rest of the data.
1730 */
1731 get += cc << 1;
1732 if (get >= end)
1733 get -= com_rbuf_size << 1;
1734 cc = 0;
1735 } else {
1736 /*
1737 * Don't schedule any more receive processing
1738 * until the line discipline tells us there's
1739 * space available (through comhwiflow()).
1740 * Leave the rest of the data in the input
1741 * buffer.
1742 */
1743 SET(sc->sc_rx_flags, RX_TTY_OVERFLOWED);
1744 }
1745 break;
1746 }
1747 get += 2;
1748 if (get >= end)
1749 get = sc->sc_rbuf;
1750 cc--;
1751 }
1752
1753 if (cc != scc) {
1754 sc->sc_rbget = get;
1755 mutex_spin_enter(&sc->sc_lock);
1756
1757 cc = sc->sc_rbavail += scc - cc;
1758 /* Buffers should be ok again, release possible block. */
1759 if (cc >= sc->sc_r_lowat) {
1760 if (ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
1761 CLR(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1762 SET(sc->sc_ier, IER_ERXRDY);
1763 #ifdef COM_PXA2X0
1764 if (sc->sc_type == COM_TYPE_PXA2x0)
1765 SET(sc->sc_ier, IER_ERXTOUT);
1766 #endif
1767 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
1768 }
1769 if (ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED)) {
1770 CLR(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1771 com_hwiflow(sc);
1772 }
1773 }
1774 mutex_spin_exit(&sc->sc_lock);
1775 }
1776 }
1777
1778 integrate void
1779 com_txsoft(struct com_softc *sc, struct tty *tp)
1780 {
1781
1782 CLR(tp->t_state, TS_BUSY);
1783 if (ISSET(tp->t_state, TS_FLUSH))
1784 CLR(tp->t_state, TS_FLUSH);
1785 else
1786 ndflush(&tp->t_outq, (int)(sc->sc_tba - tp->t_outq.c_cf));
1787 (*tp->t_linesw->l_start)(tp);
1788 }
1789
1790 integrate void
1791 com_stsoft(struct com_softc *sc, struct tty *tp)
1792 {
1793 u_char msr, delta;
1794
1795 mutex_spin_enter(&sc->sc_lock);
1796 msr = sc->sc_msr;
1797 delta = sc->sc_msr_delta;
1798 sc->sc_msr_delta = 0;
1799 mutex_spin_exit(&sc->sc_lock);
1800
1801 if (ISSET(delta, sc->sc_msr_dcd)) {
1802 /*
1803 * Inform the tty layer that carrier detect changed.
1804 */
1805 (void) (*tp->t_linesw->l_modem)(tp, ISSET(msr, MSR_DCD));
1806 }
1807
1808 if (ISSET(delta, sc->sc_msr_cts)) {
1809 /* Block or unblock output according to flow control. */
1810 if (ISSET(msr, sc->sc_msr_cts)) {
1811 sc->sc_tx_stopped = 0;
1812 (*tp->t_linesw->l_start)(tp);
1813 } else {
1814 sc->sc_tx_stopped = 1;
1815 }
1816 }
1817
1818 #ifdef COM_DEBUG
1819 if (com_debug)
1820 comstatus(sc, "com_stsoft");
1821 #endif
1822 }
1823
1824 void
1825 comsoft(void *arg)
1826 {
1827 struct com_softc *sc = arg;
1828 struct tty *tp;
1829
1830 if (COM_ISALIVE(sc) == 0)
1831 return;
1832
1833 tp = sc->sc_tty;
1834
1835 if (sc->sc_rx_ready) {
1836 sc->sc_rx_ready = 0;
1837 com_rxsoft(sc, tp);
1838 }
1839
1840 if (sc->sc_st_check) {
1841 sc->sc_st_check = 0;
1842 com_stsoft(sc, tp);
1843 }
1844
1845 if (sc->sc_tx_done) {
1846 sc->sc_tx_done = 0;
1847 com_txsoft(sc, tp);
1848 }
1849 }
1850
1851 int
1852 comintr(void *arg)
1853 {
1854 struct com_softc *sc = arg;
1855 struct com_regs *regsp = &sc->sc_regs;
1856
1857 u_char *put, *end;
1858 u_int cc;
1859 u_char lsr, iir;
1860
1861 if (COM_ISALIVE(sc) == 0)
1862 return (0);
1863
1864 mutex_spin_enter(&sc->sc_lock);
1865 iir = CSR_READ_1(regsp, COM_REG_IIR);
1866 if (ISSET(iir, IIR_NOPEND)) {
1867 mutex_spin_exit(&sc->sc_lock);
1868 return (0);
1869 }
1870
1871 end = sc->sc_ebuf;
1872 put = sc->sc_rbput;
1873 cc = sc->sc_rbavail;
1874
1875 again: do {
1876 u_char msr, delta;
1877
1878 lsr = CSR_READ_1(regsp, COM_REG_LSR);
1879 if (ISSET(lsr, LSR_BI)) {
1880 int cn_trapped = 0;
1881
1882 cn_check_magic(sc->sc_tty->t_dev,
1883 CNC_BREAK, com_cnm_state);
1884 if (cn_trapped)
1885 continue;
1886 #if defined(KGDB) && !defined(DDB)
1887 if (ISSET(sc->sc_hwflags, COM_HW_KGDB)) {
1888 kgdb_connect(1);
1889 continue;
1890 }
1891 #endif
1892 }
1893
1894 if (ISSET(lsr, LSR_RCV_MASK) &&
1895 !ISSET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED)) {
1896 while (cc > 0) {
1897 int cn_trapped = 0;
1898 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA);
1899 put[1] = lsr;
1900 cn_check_magic(sc->sc_tty->t_dev,
1901 put[0], com_cnm_state);
1902 if (cn_trapped)
1903 goto next;
1904 put += 2;
1905 if (put >= end)
1906 put = sc->sc_rbuf;
1907 cc--;
1908 next:
1909 lsr = CSR_READ_1(regsp, COM_REG_LSR);
1910 if (!ISSET(lsr, LSR_RCV_MASK))
1911 break;
1912 }
1913
1914 /*
1915 * Current string of incoming characters ended because
1916 * no more data was available or we ran out of space.
1917 * Schedule a receive event if any data was received.
1918 * If we're out of space, turn off receive interrupts.
1919 */
1920 sc->sc_rbput = put;
1921 sc->sc_rbavail = cc;
1922 if (!ISSET(sc->sc_rx_flags, RX_TTY_OVERFLOWED))
1923 sc->sc_rx_ready = 1;
1924
1925 /*
1926 * See if we are in danger of overflowing a buffer. If
1927 * so, use hardware flow control to ease the pressure.
1928 */
1929 if (!ISSET(sc->sc_rx_flags, RX_IBUF_BLOCKED) &&
1930 cc < sc->sc_r_hiwat) {
1931 SET(sc->sc_rx_flags, RX_IBUF_BLOCKED);
1932 com_hwiflow(sc);
1933 }
1934
1935 /*
1936 * If we're out of space, disable receive interrupts
1937 * until the queue has drained a bit.
1938 */
1939 if (!cc) {
1940 SET(sc->sc_rx_flags, RX_IBUF_OVERFLOWED);
1941 #ifdef COM_PXA2X0
1942 if (sc->sc_type == COM_TYPE_PXA2x0)
1943 CLR(sc->sc_ier, IER_ERXRDY|IER_ERXTOUT);
1944 else
1945 #endif
1946 CLR(sc->sc_ier, IER_ERXRDY);
1947 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1948 }
1949 } else {
1950 if ((iir & (IIR_RXRDY|IIR_TXRDY)) == IIR_RXRDY) {
1951 (void) CSR_READ_1(regsp, COM_REG_RXDATA);
1952 continue;
1953 }
1954 }
1955
1956 msr = CSR_READ_1(regsp, COM_REG_MSR);
1957 delta = msr ^ sc->sc_msr;
1958 sc->sc_msr = msr;
1959 if ((sc->sc_pps_state.ppsparam.mode & PPS_CAPTUREBOTH) &&
1960 (delta & MSR_DCD)) {
1961 mutex_spin_enter(&timecounter_lock);
1962 pps_capture(&sc->sc_pps_state);
1963 pps_event(&sc->sc_pps_state,
1964 (msr & MSR_DCD) ?
1965 PPS_CAPTUREASSERT :
1966 PPS_CAPTURECLEAR);
1967 mutex_spin_exit(&timecounter_lock);
1968 }
1969
1970 /*
1971 * Process normal status changes
1972 */
1973 if (ISSET(delta, sc->sc_msr_mask)) {
1974 SET(sc->sc_msr_delta, delta);
1975
1976 /*
1977 * Stop output immediately if we lose the output
1978 * flow control signal or carrier detect.
1979 */
1980 if (ISSET(~msr, sc->sc_msr_mask)) {
1981 sc->sc_tbc = 0;
1982 sc->sc_heldtbc = 0;
1983 #ifdef COM_DEBUG
1984 if (com_debug)
1985 comstatus(sc, "comintr ");
1986 #endif
1987 }
1988
1989 sc->sc_st_check = 1;
1990 }
1991 } while (!ISSET((iir =
1992 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) &&
1993 /*
1994 * Since some device (e.g., ST16C1550) doesn't clear IIR_TXRDY
1995 * by IIR read, so we can't do this way: `process all interrupts,
1996 * then do TX if possble'.
1997 */
1998 (iir & IIR_IMASK) != IIR_TXRDY);
1999
2000 /*
2001 * Read LSR again, since there may be an interrupt between
2002 * the last LSR read and IIR read above.
2003 */
2004 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2005
2006 /*
2007 * See if data can be transmitted as well.
2008 * Schedule tx done event if no data left
2009 * and tty was marked busy.
2010 */
2011 if (ISSET(lsr, LSR_TXRDY)) {
2012 /*
2013 * If we've delayed a parameter change, do it now, and restart
2014 * output.
2015 */
2016 if (sc->sc_heldchange) {
2017 com_loadchannelregs(sc);
2018 sc->sc_heldchange = 0;
2019 sc->sc_tbc = sc->sc_heldtbc;
2020 sc->sc_heldtbc = 0;
2021 }
2022
2023 /* Output the next chunk of the contiguous buffer, if any. */
2024 if (sc->sc_tbc > 0) {
2025 u_int n;
2026
2027 n = sc->sc_tbc;
2028 if (n > sc->sc_fifolen)
2029 n = sc->sc_fifolen;
2030 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2031 sc->sc_tbc -= n;
2032 sc->sc_tba += n;
2033 } else {
2034 /* Disable transmit completion interrupts if necessary. */
2035 if (ISSET(sc->sc_ier, IER_ETXRDY)) {
2036 CLR(sc->sc_ier, IER_ETXRDY);
2037 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2038 }
2039 if (sc->sc_tx_busy) {
2040 sc->sc_tx_busy = 0;
2041 sc->sc_tx_done = 1;
2042 }
2043 }
2044 }
2045
2046 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND))
2047 goto again;
2048
2049 mutex_spin_exit(&sc->sc_lock);
2050
2051 /* Wake up the poller. */
2052 softint_schedule(sc->sc_si);
2053
2054 #if NRND > 0 && defined(RND_COM)
2055 rnd_add_uint32(&sc->rnd_source, iir | lsr);
2056 #endif
2057
2058 return (1);
2059 }
2060
2061 /*
2062 * The following functions are polled getc and putc routines, shared
2063 * by the console and kgdb glue.
2064 *
2065 * The read-ahead code is so that you can detect pending in-band
2066 * cn_magic in polled mode while doing output rather than having to
2067 * wait until the kernel decides it needs input.
2068 */
2069
2070 #define MAX_READAHEAD 20
2071 static int com_readahead[MAX_READAHEAD];
2072 static int com_readaheadcount = 0;
2073
2074 int
2075 com_common_getc(dev_t dev, struct com_regs *regsp)
2076 {
2077 int s = splserial();
2078 u_char stat, c;
2079
2080 /* got a character from reading things earlier */
2081 if (com_readaheadcount > 0) {
2082 int i;
2083
2084 c = com_readahead[0];
2085 for (i = 1; i < com_readaheadcount; i++) {
2086 com_readahead[i-1] = com_readahead[i];
2087 }
2088 com_readaheadcount--;
2089 splx(s);
2090 return (c);
2091 }
2092
2093 /* block until a character becomes available */
2094 while (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY))
2095 ;
2096
2097 c = CSR_READ_1(regsp, COM_REG_RXDATA);
2098 stat = CSR_READ_1(regsp, COM_REG_IIR);
2099 {
2100 int cn_trapped = 0; /* unused */
2101 #ifdef DDB
2102 extern int db_active;
2103 if (!db_active)
2104 #endif
2105 cn_check_magic(dev, c, com_cnm_state);
2106 }
2107 splx(s);
2108 return (c);
2109 }
2110
2111 void
2112 com_common_putc(dev_t dev, struct com_regs *regsp, int c)
2113 {
2114 int s = splserial();
2115 int cin, stat, timo;
2116
2117 if (com_readaheadcount < MAX_READAHEAD
2118 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2119 int cn_trapped = 0;
2120 cin = CSR_READ_1(regsp, COM_REG_RXDATA);
2121 stat = CSR_READ_1(regsp, COM_REG_IIR);
2122 cn_check_magic(dev, cin, com_cnm_state);
2123 com_readahead[com_readaheadcount++] = cin;
2124 }
2125
2126 /* wait for any pending transmission to finish */
2127 timo = 150000;
2128 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo)
2129 continue;
2130
2131 CSR_WRITE_1(regsp, COM_REG_TXDATA, c);
2132 COM_BARRIER(regsp, BR | BW);
2133
2134 splx(s);
2135 }
2136
2137 /*
2138 * Initialize UART for use as console or KGDB line.
2139 */
2140 int
2141 cominit(struct com_regs *regsp, int rate, int frequency, int type,
2142 tcflag_t cflag)
2143 {
2144
2145 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0,
2146 ®sp->cr_ioh))
2147 return (ENOMEM); /* ??? */
2148
2149 if (type == COM_TYPE_OMAP) {
2150 /* disable before changing settings */
2151 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
2152 }
2153
2154 rate = comspeed(rate, frequency, type);
2155 if (type != COM_TYPE_AU1x00) {
2156 /* no EFR on alchemy */
2157 if (type != COM_TYPE_16550_NOERS) {
2158 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
2159 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
2160 }
2161 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
2162 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
2163 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
2164 } else {
2165 CSR_WRITE_1(regsp, COM_REG_DLBL, rate);
2166 }
2167 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
2168 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2169 CSR_WRITE_1(regsp, COM_REG_FIFO,
2170 FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST | FIFO_TRIGGER_1);
2171
2172 if (type == COM_TYPE_OMAP) {
2173 /* setup the fifos. the FCR value is not used as long
2174 as SCR[6] and SCR[7] are 0, which they are at reset
2175 and we never touch the SCR register */
2176 uint8_t rx_fifo_trig = 40;
2177 uint8_t tx_fifo_trig = 60;
2178 uint8_t rx_start = 8;
2179 uint8_t rx_halt = 60;
2180 uint8_t tlr_value = ((rx_fifo_trig>>2) << 4) | (tx_fifo_trig>>2);
2181 uint8_t tcr_value = ((rx_start>>2) << 4) | (rx_halt>>2);
2182
2183 /* enable access to TCR & TLR */
2184 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
2185
2186 /* write tcr and tlr values */
2187 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
2188 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
2189
2190 /* disable access to TCR & TLR */
2191 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2192
2193 /* enable again, but mode is based on speed */
2194 if (rate > 230400) {
2195 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
2196 } else {
2197 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
2198 }
2199 }
2200
2201 #ifdef COM_PXA2X0
2202 if (type == COM_TYPE_PXA2x0)
2203 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
2204 else
2205 #endif
2206 CSR_WRITE_1(regsp, COM_REG_IER, 0);
2207
2208 return (0);
2209 }
2210
2211 /*
2212 * Following are all routines needed for COM to act as console
2213 */
2214 struct consdev comcons = {
2215 NULL, NULL, comcngetc, comcnputc, comcnpollc, NULL, NULL, NULL,
2216 NODEV, CN_NORMAL
2217 };
2218
2219
2220 int
2221 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type,
2222 tcflag_t cflag)
2223 {
2224 int res;
2225
2226 comconsregs = *regsp;
2227
2228 res = cominit(&comconsregs, rate, frequency, type, cflag);
2229 if (res)
2230 return (res);
2231
2232 cn_tab = &comcons;
2233 cn_init_magic(&com_cnm_state);
2234 cn_set_magic("\047\001"); /* default magic is BREAK */
2235
2236 comconsrate = rate;
2237 comconscflag = cflag;
2238
2239 return (0);
2240 }
2241
2242 int
2243 comcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, int frequency,
2244 int type, tcflag_t cflag)
2245 {
2246 struct com_regs regs;
2247
2248 memset(®s, 0, sizeof regs);
2249 regs.cr_iot = iot;
2250 regs.cr_iobase = iobase;
2251 regs.cr_nports = COM_NPORTS;
2252 #ifdef COM_REGMAP
2253 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));
2254 #endif
2255
2256 return comcnattach1(®s, rate, frequency, type, cflag);
2257 }
2258
2259 int
2260 comcngetc(dev_t dev)
2261 {
2262
2263 return (com_common_getc(dev, &comconsregs));
2264 }
2265
2266 /*
2267 * Console kernel output character routine.
2268 */
2269 void
2270 comcnputc(dev_t dev, int c)
2271 {
2272
2273 com_common_putc(dev, &comconsregs, c);
2274 }
2275
2276 void
2277 comcnpollc(dev_t dev, int on)
2278 {
2279
2280 }
2281
2282 #ifdef KGDB
2283 int
2284 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type,
2285 tcflag_t cflag)
2286 {
2287 int res;
2288
2289 if (regsp->cr_iot == comconsregs.cr_iot &&
2290 regsp->cr_iobase == comconsregs.cr_iobase) {
2291 #if !defined(DDB)
2292 return (EBUSY); /* cannot share with console */
2293 #else
2294 comkgdbregs = *regsp;
2295 comkgdbregs.cr_ioh = comconsregs.cr_ioh;
2296 #endif
2297 } else {
2298 comkgdbregs = *regsp;
2299 res = cominit(&comkgdbregs, rate, frequency, type, cflag);
2300 if (res)
2301 return (res);
2302
2303 /*
2304 * XXXfvdl this shouldn't be needed, but the cn_magic goo
2305 * expects this to be initialized
2306 */
2307 cn_init_magic(&com_cnm_state);
2308 cn_set_magic("\047\001");
2309 }
2310
2311 kgdb_attach(com_kgdb_getc, com_kgdb_putc, NULL);
2312 kgdb_dev = 123; /* unneeded, only to satisfy some tests */
2313
2314 return (0);
2315 }
2316
2317 int
2318 com_kgdb_attach(bus_space_tag_t iot, bus_addr_t iobase, int rate,
2319 int frequency, int type, tcflag_t cflag)
2320 {
2321 struct com_regs regs;
2322
2323 regs.cr_iot = iot;
2324 regs.cr_nports = COM_NPORTS;
2325 regs.cr_iobase = iobase;
2326 #ifdef COM_REGMAP
2327 memcpy(regs.cr_map, com_std_map, sizeof (regs.cr_map));
2328 #endif
2329
2330 return com_kgdb_attach1(®s, rate, frequency, type, cflag);
2331 }
2332
2333 /* ARGSUSED */
2334 int
2335 com_kgdb_getc(void *arg)
2336 {
2337
2338 return (com_common_getc(NODEV, &comkgdbregs));
2339 }
2340
2341 /* ARGSUSED */
2342 void
2343 com_kgdb_putc(void *arg, int c)
2344 {
2345
2346 com_common_putc(NODEV, &comkgdbregs, c);
2347 }
2348 #endif /* KGDB */
2349
2350 /* helper function to identify the com ports used by
2351 console or KGDB (and not yet autoconf attached) */
2352 int
2353 com_is_console(bus_space_tag_t iot, bus_addr_t iobase, bus_space_handle_t *ioh)
2354 {
2355 bus_space_handle_t help;
2356
2357 if (!comconsattached &&
2358 iot == comconsregs.cr_iot && iobase == comconsregs.cr_iobase)
2359 help = comconsregs.cr_ioh;
2360 #ifdef KGDB
2361 else if (!com_kgdb_attached &&
2362 iot == comkgdbregs.cr_iot && iobase == comkgdbregs.cr_iobase)
2363 help = comkgdbregs.cr_ioh;
2364 #endif
2365 else
2366 return (0);
2367
2368 if (ioh)
2369 *ioh = help;
2370 return (1);
2371 }
2372
2373 /*
2374 * this routine exists to serve as a shutdown hook for systems that
2375 * have firmware which doesn't interact properly with a com device in
2376 * FIFO mode.
2377 */
2378 bool
2379 com_cleanup(device_t self, int how)
2380 {
2381 struct com_softc *sc = device_private(self);
2382
2383 if (ISSET(sc->sc_hwflags, COM_HW_FIFO))
2384 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0);
2385
2386 return true;
2387 }
2388
2389 bool
2390 com_suspend(device_t self PMF_FN_ARGS)
2391 {
2392 struct com_softc *sc = device_private(self);
2393
2394 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0);
2395 (void)CSR_READ_1(&sc->sc_regs, COM_REG_IIR);
2396
2397 return true;
2398 }
2399
2400 bool
2401 com_resume(device_t self PMF_FN_ARGS)
2402 {
2403 struct com_softc *sc = device_private(self);
2404
2405 mutex_spin_enter(&sc->sc_lock);
2406 com_loadchannelregs(sc);
2407 mutex_spin_exit(&sc->sc_lock);
2408
2409 return true;
2410 }
Cache object: 74aed6fd3283308267b11f9cd6e316a1
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