The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/comreg.h

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    1 /*      $NetBSD: comreg.h,v 1.15 2008/04/28 22:00:01 matt Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 1991 The Regents of the University of California.
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. Neither the name of the University nor the names of its contributors
   16  *    may be used to endorse or promote products derived from this software
   17  *    without specific prior written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   29  * SUCH DAMAGE.
   30  *
   31  *      @(#)comreg.h    7.2 (Berkeley) 5/9/91
   32  */
   33 
   34 #include <dev/ic/ns16550reg.h>
   35 
   36 #define COM_FREQ        1843200 /* 16-bit baud rate divisor */
   37 #define COM_TOLERANCE   30      /* baud rate tolerance, in 0.1% units */
   38 
   39 /* interrupt enable register */
   40 #define IER_ERXRDY      0x1     /* Enable receiver interrupt */
   41 #define IER_ETXRDY      0x2     /* Enable transmitter empty interrupt */
   42 #define IER_ERLS        0x4     /* Enable line status interrupt */
   43 #define IER_EMSC        0x8     /* Enable modem status interrupt */
   44 #define IER_ERTS        0x40    /* Enable RTS interrupt */
   45 #define IER_ECTS        0x80    /* Enable CTS interrupt */
   46 /* PXA2X0's ns16550 ports have extra bits in this register */
   47 #define IER_ERXTOUT     0x10    /* Enable rx timeout interrupt */
   48 #define IER_EUART       0x40    /* Enable UART */
   49 
   50 /* interrupt identification register */
   51 #define IIR_IMASK       0xf
   52 #define IIR_RXTOUT      0xc
   53 #define IIR_RLS         0x6     /* Line status change */
   54 #define IIR_RXRDY       0x4     /* Receiver ready */
   55 #define IIR_TXRDY       0x2     /* Transmitter ready */
   56 #define IIR_MLSC        0x0     /* Modem status */
   57 #define IIR_NOPEND      0x1     /* No pending interrupts */
   58 #define IIR_FIFO_MASK   0xc0    /* set if FIFOs are enabled */
   59 
   60 /* fifo control register */
   61 #define FIFO_ENABLE     0x01    /* Turn the FIFO on */
   62 #define FIFO_RCV_RST    0x02    /* Reset RX FIFO */
   63 #define FIFO_XMT_RST    0x04    /* Reset TX FIFO */
   64 #define FIFO_DMA_MODE   0x08
   65 #define FIFO_TRIGGER_1  0x00    /* Trigger RXRDY intr on 1 character */
   66 #define FIFO_TRIGGER_4  0x40    /* ibid 4 */
   67 #define FIFO_TRIGGER_8  0x80    /* ibid 8 */
   68 #define FIFO_TRIGGER_14 0xc0    /* ibid 14 */
   69 
   70 /* enhanced feature register */
   71 #define EFR_AUTOCTS     0x80    /* Automatic CTS flow control */
   72 #define EFR_AUTORTS     0x40    /* Automatic RTS flow control */
   73 #define EFR_SPECIAL     0x20    /* Special char detect */
   74 #define EFR_EFCR        0x10    /* Enhanced function control bit */
   75 #define EFR_TXFLOWBOTH  0x0c    /* Automatic transmit XON/XOFF 1 and 2 */
   76 #define EFR_TXFLOW1     0x08    /* Automatic transmit XON/XOFF 1 */
   77 #define EFR_TXFLOW2     0x04    /* Automatic transmit XON/XOFF 2 */
   78 #define EFR_TXFLOWNONE  0x00    /* No automatic XON/XOFF transmit */
   79 #define EFR_RXFLOWBOTH  0x03    /* Automatic receive XON/XOFF 1 and 2 */
   80 #define EFR_RXFLOW1     0x02    /* Automatic receive XON/XOFF 1 */
   81 #define EFR_RXFLOW2     0x01    /* Automatic receive XON/XOFF 2 */
   82 #define EFR_RXFLOWNONE  0x00    /* No automatic XON/XOFF receive */
   83 
   84 /* line control register */
   85 #define LCR_EERS        0xBF    /* Enable access to Enhanced Register Set */
   86 #define LCR_DLAB        0x80    /* Divisor latch access enable */
   87 #define LCR_SBREAK      0x40    /* Break Control */
   88 #define LCR_PZERO       0x38    /* Space parity */
   89 #define LCR_PONE        0x28    /* Mark parity */
   90 #define LCR_PEVEN       0x18    /* Even parity */
   91 #define LCR_PODD        0x08    /* Odd parity */
   92 #define LCR_PNONE       0x00    /* No parity */
   93 #define LCR_PENAB       0x08    /* XXX - low order bit of all parity */
   94 #define LCR_STOPB       0x04    /* 2 stop bits per serial word */
   95 #define LCR_8BITS       0x03    /* 8 bits per serial word */
   96 #define LCR_7BITS       0x02    /* 7 bits */
   97 #define LCR_6BITS       0x01    /* 6 bits */
   98 #define LCR_5BITS       0x00    /* 5 bits */
   99 
  100 /* modem control register */
  101 #define MCR_TCR_TLR     0x40    /* OMAP: enables access to the TCR & TLR regs */
  102 #define MCR_XONENABLE   0x20    /* OMAP XON_EN */
  103 #define MCR_LOOPBACK    0x10    /* Loop test: echos from TX to RX */
  104 #define MCR_IENABLE     0x08    /* Out2: enables UART interrupts */
  105 #define MCR_DRS         0x04    /* Out1: resets some internal modems */
  106 #define MCR_RTS         0x02    /* Request To Send */
  107 #define MCR_DTR         0x01    /* Data Terminal Ready */
  108 
  109 /* line status register */
  110 #define LSR_RCV_FIFO    0x80
  111 #define LSR_TSRE        0x40    /* Transmitter empty: byte sent */
  112 #define LSR_TXRDY       0x20    /* Transmitter buffer empty */
  113 #define LSR_BI          0x10    /* Break detected */
  114 #define LSR_FE          0x08    /* Framing error: bad stop bit */
  115 #define LSR_PE          0x04    /* Parity error */
  116 #define LSR_OE          0x02    /* Overrun, lost incoming byte */
  117 #define LSR_RXRDY       0x01    /* Byte ready in Receive Buffer */
  118 #define LSR_RCV_MASK    0x1f    /* Mask for incoming data or error */
  119 
  120 /* modem status register */
  121 /* All deltas are from the last read of the MSR. */
  122 #define MSR_DCD         0x80    /* Current Data Carrier Detect */
  123 #define MSR_RI          0x40    /* Current Ring Indicator */
  124 #define MSR_DSR         0x20    /* Current Data Set Ready */
  125 #define MSR_CTS         0x10    /* Current Clear to Send */
  126 #define MSR_DDCD        0x08    /* DCD has changed state */
  127 #define MSR_TERI        0x04    /* RI has toggled low to high */
  128 #define MSR_DDSR        0x02    /* DSR has changed state */
  129 #define MSR_DCTS        0x01    /* CTS has changed state */
  130 
  131 /* OMAP mode definition register 1 */
  132 #define MDR1_FRAME_END_MODE             0x80
  133 #define MDR1_SIP_MODE                   0x40
  134 #define MDR1_SCT                        0x20
  135 #define MDR1_SET_TXIR                   0x10
  136 #define MDR1_IR_SLEEP                   0x08
  137 #define MDR1_MODE_DISABLE               0x07
  138 #define MDR1_MODE_FIR                   0x05
  139 #define MDR1_MODE_MIR                   0x04
  140 #define MDR1_MODE_UART_13X              0x03
  141 #define MDR1_MODE_UART_16X_AUTOBAUD     0x02
  142 #define MDR1_MODE_SIR                   0x01
  143 #define MDR1_MODE_UART_16X              0x00
  144 #define MDR1_MODE_MASK                  0x07
  145 
  146 
  147 /* XXX ISA-specific. */
  148 #define COM_NPORTS      8

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