FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/comreg.h
1 /* $NetBSD: comreg.h,v 1.28 2022/10/06 19:59:55 riastradh Exp $ */
2
3 /*-
4 * Copyright (c) 1991 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the University nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * @(#)comreg.h 7.2 (Berkeley) 5/9/91
32 */
33
34 #ifndef _SYS_DEV_IC_COMREG_H_
35 #define _SYS_DEV_IC_COMREG_H_
36
37 #include <dev/ic/ns16550reg.h>
38
39 #ifdef _KERNEL_OPT
40 #include "opt_com.h"
41 #endif
42
43 #define COM_FREQ 1843200 /* 16-bit baud rate divisor */
44 #ifndef COM_TOLERANCE
45 #define COM_TOLERANCE 30 /* baud rate tolerance, in 0.1% units */
46 #endif
47
48 /* interrupt enable register */
49 #define IER_ERXRDY 0x1 /* Enable receiver interrupt */
50 #define IER_ETXRDY 0x2 /* Enable transmitter empty interrupt */
51 #define IER_ERLS 0x4 /* Enable line status interrupt */
52 #define IER_EMSC 0x8 /* Enable modem status interrupt */
53 #define IER_ERTS 0x40 /* Enable RTS interrupt */
54 #define IER_ECTS 0x80 /* Enable CTS interrupt */
55 /* PXA2X0's ns16550 ports have extra bits in this register */
56 /* Ingenic's got this one too */
57 #define IER_ERXTOUT 0x10 /* Enable rx timeout interrupt */
58 #define IER_EUART 0x40 /* Enable UART */
59
60 /* interrupt identification register */
61 #define IIR_IMASK 0xf
62 #define IIR_RXTOUT 0xc
63 #define IIR_RLS 0x6 /* Line status change */
64 #define IIR_RXRDY 0x4 /* Receiver ready */
65 #define IIR_TXRDY 0x2 /* Transmitter ready */
66 #define IIR_MLSC 0x0 /* Modem status */
67 #define IIR_NOPEND 0x1 /* No pending interrupts */
68 #define IIR_64B_FIFO 0x20 /* 64byte FIFO Enabled (16750) */
69 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
70 #define IIR_BUSY 0x7 /* Busy indicator (16750/SUNXI) */
71
72 /* fifo control register */
73 #define FIFO_ENABLE 0x01 /* Turn the FIFO on */
74 #define FIFO_RCV_RST 0x02 /* Reset RX FIFO */
75 #define FIFO_XMT_RST 0x04 /* Reset TX FIFO */
76 #define FIFO_DMA_MODE 0x08
77 #define FIFO_UART_ON 0x10 /* JZ47xx only */
78 #define FIFO_64B_ENABLE 0x20 /* 64byte FIFO Enable (16750) */
79 #define FIFO_TRIGGER_1 0x00 /* Trigger RXRDY intr on 1 character */
80 #define FIFO_TRIGGER_4 0x40 /* ibid 4 */
81 #define FIFO_TRIGGER_8 0x80 /* ibid 8 */
82 #define FIFO_TRIGGER_14 0xc0 /* ibid 14 */
83
84 /* enhanced feature register */
85 #define EFR_AUTOCTS 0x80 /* Automatic CTS flow control */
86 #define EFR_AUTORTS 0x40 /* Automatic RTS flow control */
87 #define EFR_SPECIAL 0x20 /* Special char detect */
88 #define EFR_EFCR 0x10 /* Enhanced function control bit */
89 #define EFR_TXFLOWBOTH 0x0c /* Automatic transmit XON/XOFF 1 and 2 */
90 #define EFR_TXFLOW1 0x08 /* Automatic transmit XON/XOFF 1 */
91 #define EFR_TXFLOW2 0x04 /* Automatic transmit XON/XOFF 2 */
92 #define EFR_TXFLOWNONE 0x00 /* No automatic XON/XOFF transmit */
93 #define EFR_RXFLOWBOTH 0x03 /* Automatic receive XON/XOFF 1 and 2 */
94 #define EFR_RXFLOW1 0x02 /* Automatic receive XON/XOFF 1 */
95 #define EFR_RXFLOW2 0x01 /* Automatic receive XON/XOFF 2 */
96 #define EFR_RXFLOWNONE 0x00 /* No automatic XON/XOFF receive */
97
98 /* line control register */
99 #define LCR_EERS 0xBF /* Enable access to Enhanced Register Set */
100 #define LCR_DLAB 0x80 /* Divisor latch access enable */
101 #define LCR_SBREAK 0x40 /* Break Control */
102 #define LCR_PZERO 0x38 /* Space parity */
103 #define LCR_PONE 0x28 /* Mark parity */
104 #define LCR_PEVEN 0x18 /* Even parity */
105 #define LCR_PODD 0x08 /* Odd parity */
106 #define LCR_PNONE 0x00 /* No parity */
107 #define LCR_PENAB 0x08 /* XXX - low order bit of all parity */
108 #define LCR_STOPB 0x04 /* 2 stop bits per serial word */
109 #define LCR_8BITS 0x03 /* 8 bits per serial word */
110 #define LCR_7BITS 0x02 /* 7 bits */
111 #define LCR_6BITS 0x01 /* 6 bits */
112 #define LCR_5BITS 0x00 /* 5 bits */
113
114 /* modem control register */
115 #define MCR_PRESCALE 0x80 /* 16650/16950: Baud rate prescaler select */
116 #define MCR_MDCE 0x80 /* Ingenic: modem control enable */
117 #define MCR_TCR_TLR 0x40 /* OMAP: enables access to the TCR & TLR regs */
118 #define MCR_FCM 0x40 /* Ingenic: 1 - hardware flow control */
119 #define MCR_XONENABLE 0x20 /* OMAP XON_EN */
120 #define MCR_AFE 0x20 /* tl16c750: Flow Control Enable */
121 #define MCR_LOOPBACK 0x10 /* Loop test: echos from TX to RX */
122 #define MCR_IENABLE 0x08 /* Out2: enables UART interrupts */
123 #define MCR_DRS 0x04 /* Out1: resets some internal modems */
124 #define MCR_RTS 0x02 /* Request To Send */
125 #define MCR_DTR 0x01 /* Data Terminal Ready */
126
127 /* line status register */
128 #define LSR_RCV_FIFO 0x80
129 #define LSR_TSRE 0x40 /* Transmitter empty: byte sent */
130 #define LSR_TXRDY 0x20 /* Transmitter buffer empty */
131 #define LSR_BI 0x10 /* Break detected */
132 #define LSR_FE 0x08 /* Framing error: bad stop bit */
133 #define LSR_PE 0x04 /* Parity error */
134 #define LSR_OE 0x02 /* Overrun, lost incoming byte */
135 #define LSR_RXRDY 0x01 /* Byte ready in Receive Buffer */
136 #define LSR_RCV_MASK 0x1f /* Mask for incoming data or error */
137
138 /* modem status register */
139 /* All deltas are from the last read of the MSR. */
140 #define MSR_DCD 0x80 /* Current Data Carrier Detect */
141 #define MSR_RI 0x40 /* Current Ring Indicator */
142 #define MSR_DSR 0x20 /* Current Data Set Ready */
143 #define MSR_CTS 0x10 /* Current Clear to Send */
144 #define MSR_DDCD 0x08 /* DCD has changed state */
145 #define MSR_TERI 0x04 /* RI has toggled low to high */
146 #define MSR_DDSR 0x02 /* DSR has changed state */
147 #define MSR_DCTS 0x01 /* CTS has changed state */
148
149 /* OMAP mode definition register 1 */
150 #define MDR1_FRAME_END_MODE 0x80
151 #define MDR1_SIP_MODE 0x40
152 #define MDR1_SCT 0x20
153 #define MDR1_SET_TXIR 0x10
154 #define MDR1_IR_SLEEP 0x08
155 #define MDR1_MODE_DISABLE 0x07
156 #define MDR1_MODE_FIR 0x05
157 #define MDR1_MODE_MIR 0x04
158 #define MDR1_MODE_UART_13X 0x03
159 #define MDR1_MODE_UART_16X_AUTOBAUD 0x02
160 #define MDR1_MODE_SIR 0x01
161 #define MDR1_MODE_UART_16X 0x00
162 #define MDR1_MODE_MASK 0x07
163
164 /* SUNXI-specific registers */
165 #define HALT_CHCFG_UD 0x04 /* apply updates to LCR/dividors */
166 #define HALT_CHCFG_EN 0x02 /* enable change while busy */
167
168 /* DesignWare-specific registers */
169 #define DW_APB_UART_CPR 0xf4
170 #define UART_CPR_FIFO_MODE __BITS(23,16)
171
172 /* XXX ISA-specific. */
173 #define COM_NPORTS 8
174
175 #endif /* _SYS_DEV_IC_COMREG_H_ */
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