FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/cpc700reg.h
1 /* $NetBSD: cpc700reg.h,v 1.3 2003/11/07 17:03:42 augustss Exp $ */
2
3 /*
4 * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Lennart Augustsson (lennart@augustsson.net) at Sandburst Corp.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 /* PCI memory space */
40 #define CPC_PCI_MEM_BASE 0x80000000
41 #define CPC_PCI_MEM_END 0xf7ffffff
42
43 /* PCI IO space */
44 #define CPC_PCI_IO_BASE 0xf8000000
45 #define CPC_PCI_IO_START 0xf8800000 /* for allocation */
46 #define CPC_PCI_IO_END 0xfbffffff
47
48 /* PCI config space */
49 #define CPC_PCICFGADR 0xfec00000
50 #define CPC_PCI_CONFIG_ENABLE 0x80000000
51 #define CPC_PCICFGDATA 0xfec00004
52
53 /* Config space regs */
54 #define CPC_PCI_BRDGERR 0x48
55 #define CPC_PCI_CLEARERR 0x0000ff00
56
57 #define CPC_BRIDGE_OPTIONS2 0x60
58 #define CPC_BRIDGE_O2_ILAT_MASK 0x00f8
59 #define CPC_BRIDGE_O2_ILAT_SHIFT 3
60 #define CPC_BRIDGE_O2_ILAT_PRIM_ASYNC 18
61 #define CPC_BRIDGE_O2_SLAT_MASK 0x0f00
62 #define CPC_BRIDGE_O2_SLAT_SHIFT 8
63 #define CPC_BRIDGE_O2_2LAT_PRIM_ASYNC 2
64
65 /* PCI interrupt acknowledge & special cycle */
66 #define CPC_INTR_ACK 0xfed00000
67
68 #define CPC_PMM0_LOCAL 0xff400000
69 #define CPC_PMM0_MASK_ATTR 0xff400004
70 #define CPC_PMM0_PCI_LOW 0xff400008
71 #define CPC_PMM0_PCI_HIGH 0xff40000c
72 #define CPC_PMM1_LOCAL 0xff400010
73 #define CPC_PMM1_MASK_ATTR 0xff400014
74 #define CPC_PMM1_PCI_LOW 0xff400018
75 #define CPC_PMM1_PCI_HIGH 0xff40001c
76 #define CPC_PMM2_LOCAL 0xff400020
77 #define CPC_PMM2_MASK_ATTR 0xff400024
78 #define CPC_PMM2_PCI_LOW 0xff400028
79 #define CPC_PMM2_PCI_HIGH 0xff40002c
80 #define CPC_PTM1_LOCAL 0xff400030
81 #define CPC_PTM1_MEMSIZE 0xff400034
82 #define CPC_PTM2_LOCAL 0xff400038
83 #define CPC_PTM2_MEMSIZE 0xff40003c
84
85 /* serial ports */
86 #define CPC_COM0 0xff600300
87 #define CPC_COM1 0xff600400
88 #define CPC_COM_SPEED(bus) ((bus) / (2 * 4))
89
90 /* processor interface registers */
91 #define CPC_PIF_CFGADR 0xff500000
92 #define CPC_PIF_CFG_PRIFOPT1 0x00
93 #define CPC_PIF_CFG_ERRDET1 0x04
94 #define CPC_PIF_CFG_ERREN1 0x08
95 #define CPC_PIF_CFG_CPUERAD 0x0c
96 #define CPC_PIF_CFG_CPUERAT 0x10
97 #define CPC_PIF_CFG_PLBMIFOPT 0x18
98 #define CPC_PIF_CFG_PLBMTLSA1 0x20
99 #define CPC_PIF_CFG_PLBMTLEA1 0x24
100 #define CPC_PIF_CFG_PLBMTLSA2 0x28
101 #define CPC_PIF_CFG_PLBMTLEA2 0x2c
102 #define CPC_PIF_CFG_PLBMTLSA3 0x30
103 #define CPC_PIF_CFG_PLBMTLEA3 0x34
104 #define CPC_PIF_CFG_PLBSNSSA0 0x38
105 #define CPC_PIF_CFG_PLBSNSEA0 0x3c
106 #define CPC_PIF_CFG_BESR 0x40
107 #define CPC_PIF_CFG_BESRSET 0x44
108 #define CPC_PIF_CFG_BEAR 0x4c
109 #define CPC_PIF_CFG_PLBSWRINT 0x80
110 #define CPC_PIF_CFGDATA 0xff500004
111
112 /* interrupt controller */
113 #define CPC_UIC_BASE 0xff500880
114 #define CPC_UIC_SIZE 0x00000024
115 #define CPC_UIC_SR 0x00000000 /* UIC status (read/clear) */
116 #define CPC_UIC_SRS 0x00000004 /* UIC status (set) */
117 #define CPC_UIC_ER 0x00000008 /* UIC enable */
118 #define CPC_UIC_CR 0x0000000c /* UIC critical */
119 #define CPC_UIC_PR 0x00000010 /* UIC polarity 0=low, 1=high*/
120 #define CPC_UIC_TR 0x00000014 /* UIC trigger 0=level; 1=edge */
121 #define CPC_UIC_MSR 0x00000018 /* UIC masked status */
122 #define CPC_UIC_VR 0x0000001c /* UIC vector */
123 #define CPC_UIC_VCR 0x00000020 /* UIC vector configuration */
124 #define CPC_UIC_CVR_PRI 0x00000001 /* 0=intr31 high, 1=intr0 high */
125 /*
126 * if intr0 high then interrupt vector at (vcr&~3) + N*512
127 * if intr31 high then interrupt vector at (vcr&~3) + (31-N)*512
128 */
129
130 /* UIC interrupt bits. Note, MSB is bit 0 */
131 /* Internal */
132 #define CPC_IB_ECC 0
133 #define CPC_IB_PCI_WR_RANGE 1
134 #define CPC_IB_PCI_WR_CMD 2
135 #define CPC_IB_UART_0 3
136 #define CPC_IB_UART_1 4
137 #define CPC_IB_IIC_0 5
138 #define CPC_IB_IIC_1 6
139 /* 6-16 GPT compare&capture */
140 /* 20-31 external */
141 #define CPC_IB_EXT0 20
142 #define CPC_IB_EXT1 21
143 #define CPC_IB_EXT2 22
144 #define CPC_IB_EXT3 23
145 #define CPC_IB_EXT4 24
146 #define CPC_IB_EXT5 25
147 #define CPC_IB_EXT6 26
148 #define CPC_IB_EXT7 27
149 #define CPC_IB_EXT8 28
150 #define CPC_IB_EXT9 29
151 #define CPC_IB_EXT10 30
152 #define CPC_IB_EXT11 31
153
154 #define CPC_INTR_MASK(irq) (0x80000000 >> (irq))
155
156
157 /* IIC */
158 #define CPC_IIC0 0xff620000
159 #define CPC_IIC1 0xff630000
160 #define CPC_IIC_SIZE 0x00000014
161 /* offsets from base */
162 #define CPC_IIC_MDBUF 0x00000000
163 #define CPC_IIC_SDBUF 0x00000002
164 #define CPC_IIC_LMADR 0x00000004
165 #define CPC_IIC_HNADR 0x00000005
166 #define CPC_IIC_CNTL 0x00000006
167 #define CPC_IIC_MDCNTL 0x00000007
168 #define CPC_IIC_STS 0x00000008
169 #define CPC_IIC_EXTSTS 0x00000009
170 #define CPC_IIC_LSADR 0x0000000a
171 #define CPC_IIC_HSADR 0x0000000b
172 #define CPC_IIC_CLKDIV 0x0000000c
173 #define CPC_IIC_INTRMSK 0x0000000d
174 #define CPC_IIC_FRCNT 0x0000000e
175 #define CPC_IIC_TCNTLSS 0x0000000f
176 #define CPC_IIC_DIRECTCNTL 0x00000010
177
178 /* timer */
179 #define CPC_TIMER 0xff650000
180 #define CPC_GPTTBC 0x00000000
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