FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/cs89x0.c
1 /* $NetBSD: cs89x0.c,v 1.12.2.1 2004/07/07 17:03:14 tron Exp $ */
2
3 /*
4 * Copyright 1997
5 * Digital Equipment Corporation. All rights reserved.
6 *
7 * This software is furnished under license and may be used and
8 * copied only in accordance with the following terms and conditions.
9 * Subject to these conditions, you may download, copy, install,
10 * use, modify and distribute this software in source and/or binary
11 * form. No title or ownership is transferred hereby.
12 *
13 * 1) Any source code used, modified or distributed must reproduce
14 * and retain this copyright notice and list of conditions as
15 * they appear in the source file.
16 *
17 * 2) No right is granted to use any trade name, trademark, or logo of
18 * Digital Equipment Corporation. Neither the "Digital Equipment
19 * Corporation" name nor any trademark or logo of Digital Equipment
20 * Corporation may be used to endorse or promote products derived
21 * from this software without the prior written permission of
22 * Digital Equipment Corporation.
23 *
24 * 3) This software is provided "AS-IS" and any express or implied
25 * warranties, including but not limited to, any implied warranties
26 * of merchantability, fitness for a particular purpose, or
27 * non-infringement are disclaimed. In no event shall DIGITAL be
28 * liable for any damages whatsoever, and in particular, DIGITAL
29 * shall not be liable for special, indirect, consequential, or
30 * incidental damages or damages for lost profits, loss of
31 * revenue or loss of use, whether such damages arise in contract,
32 * negligence, tort, under statute, in equity, at law or otherwise,
33 * even if advised of the possibility of such damage.
34 */
35
36 /*
37 **++
38 ** FACILITY
39 **
40 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller.
41 **
42 ** ABSTRACT
43 **
44 ** This module provides standard ethernet access for INET protocols
45 ** only.
46 **
47 ** AUTHORS
48 **
49 ** Peter Dettori SEA - Software Engineering.
50 **
51 ** CREATION DATE:
52 **
53 ** 13-Feb-1997.
54 **
55 ** MODIFICATION HISTORY (Digital):
56 **
57 ** Revision 1.27 1998/01/20 17:59:40 cgd
58 ** update for moved headers
59 **
60 ** Revision 1.26 1998/01/12 19:29:36 cgd
61 ** use arm32/isa versions of isadma code.
62 **
63 ** Revision 1.25 1997/12/12 01:35:27 cgd
64 ** convert to use new arp code (from Brini)
65 **
66 ** Revision 1.24 1997/12/10 22:31:56 cgd
67 ** trim some fat (get rid of ability to explicitly supply enet addr, since
68 ** it was never used and added a bunch of code which really doesn't belong in
69 ** an enet driver), and clean up slightly.
70 **
71 ** Revision 1.23 1997/10/06 16:42:12 cgd
72 ** copyright notices
73 **
74 ** Revision 1.22 1997/06/20 19:38:01 chaiken
75 ** fixes some smartcard problems
76 **
77 ** Revision 1.21 1997/06/10 02:56:20 grohn
78 ** Added call to ledNetActive
79 **
80 ** Revision 1.20 1997/06/05 00:47:06 dettori
81 ** Changed cs_process_rx_dma to reset and re-initialise the
82 ** ethernet chip when DMA gets out of sync, or mbufs
83 ** can't be allocated.
84 **
85 ** Revision 1.19 1997/06/03 03:09:58 dettori
86 ** Turn off sc_txbusy flag when a transmit underrun
87 ** occurs.
88 **
89 ** Revision 1.18 1997/06/02 00:04:35 dettori
90 ** redefined the transmit table to get around the nfs_timer bug while we are
91 ** looking into it further.
92 **
93 ** Also changed interrupts from EDGE to LEVEL.
94 **
95 ** Revision 1.17 1997/05/27 23:31:01 dettori
96 ** Pulled out changes to DMAMODE defines.
97 **
98 ** Revision 1.16 1997/05/23 04:25:16 cgd
99 ** reformat log so it fits in 80cols
100 **
101 ** Revision 1.15 1997/05/23 04:22:18 cgd
102 ** remove the existing copyright notice (which Peter Dettori indicated
103 ** was incorrect, copied from an existing NetBSD file only so that the
104 ** file would have a copyright notice on it, and which he'd intended to
105 ** replace). Replace it with a Digital copyright notice, cloned from
106 ** ess.c. It's not really correct either (it indicates that the source
107 ** is Digital confidential!), but is better than nothing and more
108 ** correct than what was there before.
109 **
110 ** Revision 1.14 1997/05/23 04:12:50 cgd
111 ** use an adaptive transmit start algorithm: start by telling the chip
112 ** to start transmitting after 381 bytes have been fed to it. if that
113 ** gets transmit underruns, ramp down to 1021 bytes then "whole
114 ** packet." If successful at a given level for a while, try the next
115 ** more agressive level. This code doesn't ever try to start
116 ** transmitting after 5 bytes have been sent to the NIC, because
117 ** that underruns rather regularly. The back-off and ramp-up mechanism
118 ** could probably be tuned a little bit, but this works well enough to
119 ** support > 1MB/s transmit rates on a clear ethernet (which is about
120 ** 20-25% better than the driver had previously been getting).
121 **
122 ** Revision 1.13 1997/05/22 21:06:54 cgd
123 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly
124 ** casting from u_int8_t * to u_int16_t * without worrying about alignment
125 ** issues. This would cause bogus data to be spit out for mbufs with
126 ** misaligned data. For instance, it caused the following bits to appear
127 ** on the wire:
128 ** ... etBND 1S2C .SHA(K) R ...
129 ** 11112222333344445555
130 ** which should have appeared as:
131 ** ... NetBSD 1.2C (SHARK) ...
132 ** 11112222333344445555
133 ** Note the apparent 'rotate' of the bytes in the word, which was due to
134 ** incorrect unaligned accesses. This data corruption was the cause of
135 ** incoming telnet/rlogin hangs.
136 **
137 ** Revision 1.12 1997/05/22 01:55:32 cgd
138 ** reformat log so it fits in 80cols
139 **
140 ** Revision 1.11 1997/05/22 01:50:27 cgd
141 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case,
142 ** so packets aimed at other hosts don't get sent to ether_input().
143 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that
144 ** you can easily tell (`strings`) what version of the driver is in your
145 ** kernel binary.
146 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily
147 ** safe, and not really a performance win anyway. (It was only used when
148 ** setting up the multicast logical address filter, which is an
149 ** infrequent event. It could have been used in the IFF_PROMISCUOUS
150 ** address check above, but the benefit of it vs. memcmp would be
151 ** inconsequential, there.) Use memcmp() instead.
152 ** * restructure csStartOuput to avoid the following bugs in the case where
153 ** txWait was being set:
154 ** * it would accidentally drop the outgoing packet if told to wait
155 ** but the outgoing packet queue was empty.
156 ** * it would bpf_mtap() the outgoing packet multiple times (once for
157 ** each time it was told to wait), and would also recalculate
158 ** the length of the outgoing packet each time it was told to
159 ** wait.
160 ** While there, rename txWait to txLoop, since with the new structure of
161 ** the code, the latter name makes more sense.
162 **
163 ** Revision 1.10 1997/05/19 02:03:20 cgd
164 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip()
165 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this
166 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC
167 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave
168 ** as before.
169 **
170 ** Revision 1.9 1997/05/19 01:45:37 cgd
171 ** create a new function, cs_ether_input(), which does received-packet
172 ** BPF and ether_input processing. This code used to be in three places,
173 ** and centralizing it will make adding IFF_PROMISC support much easier.
174 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to
175 ** do copies with bus_space_write_region_2(). It's more correct, and
176 ** potentially more efficient. That function needs to be gutted (to
177 ** deal properly with alignment issues, which it currently does wrong),
178 ** however, and the change doesn't gain much, so there's no point in
179 ** enabling it now.
180 **
181 ** Revision 1.8 1997/05/19 01:17:10 cgd
182 ** fix a comment re: the setting of the TxConfig register. Clean up
183 ** interface counter maintenance (make it use standard idiom).
184 **
185 **--
186 */
187
188 #include <sys/cdefs.h>
189 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.12.2.1 2004/07/07 17:03:14 tron Exp $");
190
191 #include "opt_inet.h"
192
193 #include <sys/param.h>
194 #include <sys/systm.h>
195 #include <sys/mbuf.h>
196 #include <sys/syslog.h>
197 #include <sys/socket.h>
198 #include <sys/device.h>
199 #include <sys/malloc.h>
200 #include <sys/ioctl.h>
201 #include <sys/errno.h>
202
203 #include "rnd.h"
204 #if NRND > 0
205 #include <sys/rnd.h>
206 #endif
207
208 #include <net/if.h>
209 #include <net/if_ether.h>
210 #include <net/if_media.h>
211 #ifdef INET
212 #include <netinet/in.h>
213 #include <netinet/if_inarp.h>
214 #endif
215
216 #include "bpfilter.h"
217 #if NBPFILTER > 0
218 #include <net/bpf.h>
219 #include <net/bpfdesc.h>
220 #endif
221
222 #include <uvm/uvm_extern.h>
223
224 #include <machine/bus.h>
225 #include <machine/intr.h>
226
227 #include <dev/ic/cs89x0reg.h>
228 #include <dev/ic/cs89x0var.h>
229
230 #ifdef SHARK
231 #include <shark/shark/sequoia.h>
232 #endif
233
234 /*
235 * MACRO DEFINITIONS
236 */
237 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */
238
239 /*
240 * FUNCTION PROTOTYPES
241 */
242 void cs_get_default_media(struct cs_softc *);
243 int cs_get_params(struct cs_softc *);
244 int cs_get_enaddr(struct cs_softc *);
245 int cs_reset_chip(struct cs_softc *);
246 void cs_reset(void *);
247 int cs_ioctl(struct ifnet *, u_long, caddr_t);
248 void cs_initChip(struct cs_softc *);
249 void cs_buffer_event(struct cs_softc *, u_int16_t);
250 void cs_transmit_event(struct cs_softc *, u_int16_t);
251 void cs_receive_event(struct cs_softc *, u_int16_t);
252 void cs_process_receive(struct cs_softc *);
253 void cs_process_rx_early(struct cs_softc *);
254 void cs_start_output(struct ifnet *);
255 void cs_copy_tx_frame(struct cs_softc *, struct mbuf *);
256 void cs_set_ladr_filt(struct cs_softc *, struct ethercom *);
257 u_int16_t cs_hash_index(char *);
258 void cs_counter_event(struct cs_softc *, u_int16_t);
259
260 int cs_mediachange(struct ifnet *);
261 void cs_mediastatus(struct ifnet *, struct ifmediareq *);
262
263 static int cs_enable(struct cs_softc *);
264 static void cs_disable(struct cs_softc *);
265 static void cs_stop(struct ifnet *, int);
266 static void cs_power(int, void *);
267
268 /*
269 * GLOBAL DECLARATIONS
270 */
271
272 /*
273 * Xmit-early table.
274 *
275 * To get better performance, we tell the chip to start packet
276 * transmission before the whole packet is copied to the chip.
277 * However, this can fail under load. When it fails, we back off
278 * to a safer setting for a little while.
279 *
280 * txcmd is the value of txcmd used to indicate when to start transmission.
281 * better is the next 'better' state in the table.
282 * better_count is the number of output packets before transition to the
283 * better state.
284 * worse is the next 'worse' state in the table.
285 *
286 * Transition to the next worse state happens automatically when a
287 * transmittion underrun occurs.
288 */
289 struct cs_xmit_early {
290 u_int16_t txcmd;
291 int better;
292 int better_count;
293 int worse;
294 } cs_xmit_early_table[3] = {
295 { TX_CMD_START_381, 0, INT_MAX, 1, },
296 { TX_CMD_START_1021, 0, 50000, 2, },
297 { TX_CMD_START_ALL, 1, 5000, 2, },
298 };
299
300 int cs_default_media[] = {
301 IFM_ETHER|IFM_10_2,
302 IFM_ETHER|IFM_10_5,
303 IFM_ETHER|IFM_10_T,
304 IFM_ETHER|IFM_10_T|IFM_FDX,
305 };
306 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]);
307
308 int
309 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media,
310 int nmedia, int defmedia)
311 {
312 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
313 const char *chipname, *medname;
314 u_int16_t reg;
315 int i;
316
317 /* Start out in IO mode */
318 sc->sc_memorymode = FALSE;
319
320 /* make sure we're right */
321 for (i = 0; i < 10000; i++) {
322 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
323 if (reg == EISA_NUM_CRYSTAL) {
324 break;
325 }
326 }
327 if (i == 10000) {
328 printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg);
329 return 1; /* XXX should panic? */
330 }
331
332 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID);
333 sc->sc_prodid = reg & PROD_ID_MASK;
334 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8;
335
336 switch (sc->sc_prodid) {
337 case PROD_ID_CS8900:
338 chipname = "CS8900";
339 break;
340 case PROD_ID_CS8920:
341 chipname = "CS8920";
342 break;
343 case PROD_ID_CS8920M:
344 chipname = "CS8920M";
345 break;
346 default:
347 panic("cs_attach: impossible");
348 }
349
350 /*
351 * the first thing to do is check that the mbuf cluster size is
352 * greater than the MTU for an ethernet frame. The code depends on
353 * this and to port this to a OS where this was not the case would
354 * not be straightforward.
355 *
356 * we need 1 byte spare because our
357 * packet read loop can overrun.
358 * and we may need pad bytes to align ip header.
359 */
360 if (MCLBYTES < ETHER_MAX_LEN + 1 +
361 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) {
362 printf("%s: MCLBYTES too small for Ethernet frame\n",
363 sc->sc_dev.dv_xname);
364 return 1;
365 }
366
367 /* Start out not transmitting */
368 sc->sc_txbusy = FALSE;
369
370 /* Set up early transmit threshhold */
371 sc->sc_xe_ent = 0;
372 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count;
373
374 /* Initialize ifnet structure. */
375 strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
376 ifp->if_softc = sc;
377 ifp->if_start = cs_start_output;
378 ifp->if_init = cs_init;
379 ifp->if_ioctl = cs_ioctl;
380 ifp->if_stop = cs_stop;
381 ifp->if_watchdog = NULL; /* no watchdog at this stage */
382 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS |
383 IFF_BROADCAST | IFF_MULTICAST;
384 IFQ_SET_READY(&ifp->if_snd);
385
386 /* Initialize ifmedia structures. */
387 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus);
388
389 if (media != NULL) {
390 for (i = 0; i < nmedia; i++)
391 ifmedia_add(&sc->sc_media, media[i], 0, NULL);
392 ifmedia_set(&sc->sc_media, defmedia);
393 } else {
394 for (i = 0; i < cs_default_nmedia; i++)
395 ifmedia_add(&sc->sc_media, cs_default_media[i],
396 0, NULL);
397 cs_get_default_media(sc);
398 }
399
400 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
401 /* Get parameters from the EEPROM */
402 if (cs_get_params(sc) == CS_ERROR) {
403 printf("%s: unable to get settings from EEPROM\n",
404 sc->sc_dev.dv_xname);
405 return 1;
406 }
407 }
408
409 if (enaddr != NULL)
410 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr));
411 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) {
412 /* Get and store the Ethernet address */
413 if (cs_get_enaddr(sc) == CS_ERROR) {
414 printf("%s: unable to read Ethernet address\n",
415 sc->sc_dev.dv_xname);
416 return 1;
417 }
418 } else {
419 #if 1
420 int i;
421 uint v;
422
423 for (i = 0; i < 6; i += 2) {
424 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + i);
425 sc->sc_enaddr[i + 0] = v;
426 sc->sc_enaddr[i + 1] = v >> 8;
427 }
428 #else
429 printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname);
430 return 1;
431 #endif
432 }
433
434 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) {
435 case IFM_10_2:
436 medname = "BNC";
437 break;
438 case IFM_10_5:
439 medname = "AUI";
440 break;
441 case IFM_10_T:
442 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
443 medname = "UTP <full-duplex>";
444 else
445 medname = "UTP";
446 break;
447 default:
448 panic("cs_attach: impossible");
449 }
450 printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname,
451 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr),
452 medname);
453
454 if (sc->sc_dma_attach)
455 (*sc->sc_dma_attach)(sc);
456
457 sc->sc_sh = shutdownhook_establish(cs_reset, sc);
458 if (sc->sc_sh == NULL) {
459 printf("%s: unable to establish shutdownhook\n",
460 sc->sc_dev.dv_xname);
461 cs_detach(sc);
462 return 1;
463 }
464
465 /* Attach the interface. */
466 if_attach(ifp);
467 ether_ifattach(ifp, sc->sc_enaddr);
468
469 #if NRND > 0
470 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
471 RND_TYPE_NET, 0);
472 #endif
473 sc->sc_cfgflags |= CFGFLG_ATTACHED;
474
475 /* Reset the chip */
476 if (cs_reset_chip(sc) == CS_ERROR) {
477 printf("%s: reset failed\n", sc->sc_dev.dv_xname);
478 cs_detach(sc);
479 return 1;
480 }
481
482 sc->sc_powerhook = powerhook_establish(cs_power, sc);
483 if (sc->sc_powerhook == 0)
484 printf("%s: warning: powerhook_establish failed\n",
485 sc->sc_dev.dv_xname);
486
487 return 0;
488 }
489
490 int
491 cs_detach(struct cs_softc *sc)
492 {
493 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
494
495 if (sc->sc_powerhook) {
496 powerhook_disestablish(sc->sc_powerhook);
497 sc->sc_powerhook = 0;
498 }
499
500 if (sc->sc_cfgflags & CFGFLG_ATTACHED) {
501 #if NRND > 0
502 rnd_detach_source(&sc->rnd_source);
503 #endif
504 ether_ifdetach(ifp);
505 if_detach(ifp);
506 sc->sc_cfgflags &= ~CFGFLG_ATTACHED;
507 }
508
509 if (sc->sc_sh != NULL)
510 shutdownhook_disestablish(sc->sc_sh);
511
512 #if 0
513 /*
514 * XXX not necessary
515 */
516 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) {
517 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize);
518 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize);
519 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq);
520 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE;
521 }
522 #endif
523
524 return 0;
525 }
526
527 void
528 cs_get_default_media(struct cs_softc *sc)
529 {
530 u_int16_t adp_cfg, xmit_ctl;
531
532 if (cs_verify_eeprom(sc) == CS_ERROR) {
533 printf("%s: cs_get_default_media: EEPROM missing or bad\n",
534 sc->sc_dev.dv_xname);
535 goto fakeit;
536 }
537
538 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) {
539 printf("%s: unable to read adapter config from EEPROM\n",
540 sc->sc_dev.dv_xname);
541 goto fakeit;
542 }
543
544 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) {
545 printf("%s: unable to read transmit control from EEPROM\n",
546 sc->sc_dev.dv_xname);
547 goto fakeit;
548 }
549
550 switch (adp_cfg & ADPTR_CFG_MEDIA) {
551 case ADPTR_CFG_AUI:
552 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5);
553 break;
554 case ADPTR_CFG_10BASE2:
555 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2);
556 break;
557 case ADPTR_CFG_10BASET:
558 default:
559 if (xmit_ctl & XMIT_CTL_FDX)
560 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX);
561 else
562 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T);
563 break;
564 }
565 return;
566
567 fakeit:
568 printf("%s: WARNING: default media setting may be inaccurate\n",
569 sc->sc_dev.dv_xname);
570 /* XXX Arbitrary... */
571 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T);
572 }
573
574 int
575 cs_get_params(struct cs_softc *sc)
576 {
577 u_int16_t isaConfig;
578 u_int16_t adapterConfig;
579
580 if (cs_verify_eeprom(sc) == CS_ERROR) {
581 printf("%s: cs_get_params: EEPROM missing or bad\n",
582 sc->sc_dev.dv_xname);
583 return (CS_ERROR);
584 }
585
586 /* Get ISA configuration from the EEPROM */
587 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR)
588 goto eeprom_bad;
589
590 /* Get adapter configuration from the EEPROM */
591 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR)
592 goto eeprom_bad;
593
594 /* Copy the USE_SA flag */
595 if (isaConfig & ISA_CFG_USE_SA)
596 sc->sc_cfgflags |= CFGFLG_USE_SA;
597
598 /* Copy the IO Channel Ready flag */
599 if (isaConfig & ISA_CFG_IOCHRDY)
600 sc->sc_cfgflags |= CFGFLG_IOCHRDY;
601
602 /* Copy the DC/DC Polarity flag */
603 if (adapterConfig & ADPTR_CFG_DCDC_POL)
604 sc->sc_cfgflags |= CFGFLG_DCDC_POL;
605
606 return (CS_OK);
607
608 eeprom_bad:
609 printf("%s: cs_get_params: unable to read from EEPROM\n",
610 sc->sc_dev.dv_xname);
611 return (CS_ERROR);
612 }
613
614 int
615 cs_get_enaddr(struct cs_softc *sc)
616 {
617 u_int16_t *myea;
618
619 if (cs_verify_eeprom(sc) == CS_ERROR) {
620 printf("%s: cs_get_enaddr: EEPROM missing or bad\n",
621 sc->sc_dev.dv_xname);
622 return (CS_ERROR);
623 }
624
625 myea = (u_int16_t *)sc->sc_enaddr;
626
627 /* Get Ethernet address from the EEPROM */
628 /* XXX this will likely lose on a big-endian machine. -- cgd */
629 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR)
630 goto eeprom_bad;
631 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR)
632 goto eeprom_bad;
633 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR)
634 goto eeprom_bad;
635
636 return (CS_OK);
637
638 eeprom_bad:
639 printf("%s: cs_get_enaddr: unable to read from EEPROM\n",
640 sc->sc_dev.dv_xname);
641 return (CS_ERROR);
642 }
643
644 int
645 cs_reset_chip(struct cs_softc *sc)
646 {
647 int intState;
648 int x;
649
650 /* Disable interrupts at the CPU so reset command is atomic */
651 intState = splnet();
652
653 /*
654 * We are now resetting the chip
655 *
656 * A spurious interrupt is generated by the chip when it is reset. This
657 * variable informs the interrupt handler to ignore this interrupt.
658 */
659 sc->sc_resetting = TRUE;
660
661 /* Issue a reset command to the chip */
662 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET);
663
664 /* Re-enable interrupts at the CPU */
665 splx(intState);
666
667 /* The chip is always in IO mode after a reset */
668 sc->sc_memorymode = FALSE;
669
670 /* If transmission was in progress, it is not now */
671 sc->sc_txbusy = FALSE;
672
673 /*
674 * there was a delay(125); here, but it seems uneccesary 125 usec is
675 * 1/8000 of a second, not 1/8 of a second. the data sheet advises
676 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below
677 * should be sufficient.
678 */
679
680 /* Transition SBHE to switch chip from 8-bit to 16-bit */
681 IO_READ_1(sc, PORT_PKTPG_PTR + 0);
682 IO_READ_1(sc, PORT_PKTPG_PTR + 1);
683 IO_READ_1(sc, PORT_PKTPG_PTR + 0);
684 IO_READ_1(sc, PORT_PKTPG_PTR + 1);
685
686 /* Wait until the EEPROM is not busy */
687 for (x = 0; x < MAXLOOP; x++) {
688 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY))
689 break;
690 }
691
692 if (x == MAXLOOP)
693 return CS_ERROR;
694
695 /* Wait until initialization is done */
696 for (x = 0; x < MAXLOOP; x++) {
697 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE)
698 break;
699 }
700
701 if (x == MAXLOOP)
702 return CS_ERROR;
703
704 /* Reset is no longer in progress */
705 sc->sc_resetting = FALSE;
706
707 return CS_OK;
708 }
709
710 int
711 cs_verify_eeprom(struct cs_softc *sc)
712 {
713 u_int16_t self_status;
714
715 /* Verify that the EEPROM is present and OK */
716 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST);
717 if (((self_status & SELF_ST_EEP_PRES) &&
718 (self_status & SELF_ST_EEP_OK)) == 0)
719 return (CS_ERROR);
720
721 return (CS_OK);
722 }
723
724 int
725 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue)
726 {
727 int x;
728
729 /* Ensure that the EEPROM is not busy */
730 for (x = 0; x < MAXLOOP; x++) {
731 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
732 SELF_ST_SI_BUSY))
733 break;
734 }
735
736 if (x == MAXLOOP)
737 return (CS_ERROR);
738
739 /* Issue the command to read the offset within the EEPROM */
740 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD,
741 offset | EEPROM_CMD_READ);
742
743 /* Wait until the command is completed */
744 for (x = 0; x < MAXLOOP; x++) {
745 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) &
746 SELF_ST_SI_BUSY))
747 break;
748 }
749
750 if (x == MAXLOOP)
751 return (CS_ERROR);
752
753 /* Get the EEPROM data from the EEPROM Data register */
754 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA);
755
756 return (CS_OK);
757 }
758
759 void
760 cs_initChip(struct cs_softc *sc)
761 {
762 u_int16_t busCtl;
763 u_int16_t selfCtl;
764 u_int16_t v;
765 u_int16_t isaId;
766 int i;
767 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media);
768
769 /* Disable reception and transmission of frames */
770 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
771 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) &
772 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON);
773
774 /* Disable interrupt at the chip */
775 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
776 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL);
777
778 /* If IOCHRDY is enabled then clear the bit in the busCtl register */
779 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL);
780 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) {
781 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
782 busCtl & ~BUS_CTL_IOCHRDY);
783 } else {
784 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
785 busCtl | BUS_CTL_IOCHRDY);
786 }
787
788 /* Set the Line Control register to match the media type */
789 if (media == IFM_10_T)
790 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET);
791 else
792 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY);
793
794 /*
795 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to
796 * enable the DC/DC converter
797 */
798 selfCtl = SELF_CTL_HC1E;
799
800 /* If the media type is 10Base2 */
801 if (media == IFM_10_2) {
802 /*
803 * Enable the DC/DC converter if it has a low enable.
804 */
805 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0)
806 /*
807 * Set the HCB1 bit, which causes the HC1 pin to go
808 * low.
809 */
810 selfCtl |= SELF_CTL_HCB1;
811 } else { /* Media type is 10BaseT or AUI */
812 /*
813 * Disable the DC/DC converter if it has a high enable.
814 */
815 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) {
816 /*
817 * Set the HCB1 bit, which causes the HC1 pin to go
818 * low.
819 */
820 selfCtl |= SELF_CTL_HCB1;
821 }
822 }
823 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl);
824
825 /* enable normal link pulse */
826 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M)
827 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE);
828
829 /* Enable full-duplex, if appropriate */
830 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX)
831 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX);
832
833 /* RX_CTL set in cs_set_ladr_filt(), below */
834
835 /* enable all transmission interrupts */
836 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE);
837
838 /* Accept all receive interrupts */
839 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE);
840
841 /*
842 * Configure Operational Modes
843 *
844 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is
845 * a better way to do it because the card has a counter which can be
846 * read to update the RX_MISS counter. This saves many interrupts.
847 *
848 * I have turned on the tx and rx overflow interrupts to counter using
849 * the receive miss interrupt. This is a better estimate of errors
850 * and requires lower system overhead.
851 */
852 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE |
853 BUF_CFG_RX_DMA_IE);
854
855 if (sc->sc_dma_chipinit)
856 (*sc->sc_dma_chipinit)(sc);
857
858 /* If memory mode is enabled */
859 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) {
860 /* If external logic is present for address decoding */
861 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) {
862 /*
863 * Program the external logic to decode address bits
864 * SA20-SA23
865 */
866 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD,
867 ((sc->sc_pktpgaddr & 0xffffff) >> 20) |
868 EEPROM_CMD_ELSEL);
869 }
870
871 /*
872 * Write the packet page base physical address to the memory
873 * base register.
874 */
875 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0,
876 sc->sc_pktpgaddr & 0xFFFF);
877 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2,
878 sc->sc_pktpgaddr >> 16);
879 busCtl = BUS_CTL_MEM_MODE;
880
881 /* tell the chip to read the addresses off the SA pins */
882 if (sc->sc_cfgflags & CFGFLG_USE_SA) {
883 busCtl |= BUS_CTL_USE_SA;
884 }
885 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
886 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl);
887
888 /* We are in memory mode now! */
889 sc->sc_memorymode = TRUE;
890
891 /*
892 * wait here (10ms) for the chip to swap over. this is the
893 * maximum time that this could take.
894 */
895 delay(10000);
896
897 /* Verify that we can read from the chip */
898 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM);
899
900 /*
901 * As a last minute sanity check before actually using mapped
902 * memory we verify that we can read the isa number from the
903 * chip in memory mode.
904 */
905 if (isaId != EISA_NUM_CRYSTAL) {
906 printf("%s: failed to enable memory mode\n",
907 sc->sc_dev.dv_xname);
908 sc->sc_memorymode = FALSE;
909 } else {
910 /*
911 * we are in memory mode so if we aren't using DMA,
912 * then program the chip to interrupt early.
913 */
914 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) {
915 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG,
916 BUF_CFG_RX_DEST_IE |
917 BUF_CFG_RX_MISS_OVER_IE |
918 BUF_CFG_TX_COL_OVER_IE);
919 }
920 }
921
922 }
923
924 /* Put Ethernet address into the Individual Address register */
925 for (i = 0; i < 6; i += 2) {
926 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8;
927 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v);
928 }
929
930 if (sc->sc_irq != -1) {
931 /* Set the interrupt level in the chip */
932 if (sc->sc_prodid == PROD_ID_CS8900) {
933 if (sc->sc_irq == 5) {
934 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3);
935 } else {
936 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10);
937 }
938 }
939 else { /* CS8920 */
940 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq);
941 }
942 }
943
944 /* write the multicast mask to the address filter register */
945 cs_set_ladr_filt(sc, &sc->sc_ethercom);
946
947 /* Enable reception and transmission of frames */
948 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL,
949 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) |
950 LINE_CTL_RX_ON | LINE_CTL_TX_ON);
951
952 /* Enable interrupt at the chip */
953 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL,
954 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL);
955 }
956
957 int
958 cs_init(struct ifnet *ifp)
959 {
960 int intState;
961 int error = CS_OK;
962 struct cs_softc *sc = ifp->if_softc;
963
964 if (cs_enable(sc))
965 goto out;
966
967 cs_stop(ifp, 0);
968
969 intState = splnet();
970
971 #if 0
972 /* Mark the interface as down */
973 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING);
974 #endif
975
976 #ifdef CS_DEBUG
977 /* Enable debugging */
978 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG;
979 #endif
980
981 /* Reset the chip */
982 if ((error = cs_reset_chip(sc)) == CS_OK) {
983 /* Initialize the chip */
984 cs_initChip(sc);
985
986 /* Mark the interface as running */
987 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING;
988 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE;
989 sc->sc_ethercom.ec_if.if_timer = 0;
990
991 /* Assume we have carrier until we are told otherwise. */
992 sc->sc_carrier = 1;
993 } else {
994 printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname);
995 }
996
997 splx(intState);
998 out:
999 if (error == CS_OK)
1000 return 0;
1001 return EIO;
1002 }
1003
1004 void
1005 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec)
1006 {
1007 struct ifnet *ifp = &ec->ec_if;
1008 struct ether_multi *enm;
1009 struct ether_multistep step;
1010 u_int16_t af[4];
1011 u_int16_t port, mask, index;
1012
1013 /*
1014 * Set up multicast address filter by passing all multicast addresses
1015 * through a crc generator, and then using the high order 6 bits as an
1016 * index into the 64 bit logical address filter. The high order bit
1017 * selects the word, while the rest of the bits select the bit within
1018 * the word.
1019 */
1020 if (ifp->if_flags & IFF_PROMISC) {
1021 /* accept all valid frames. */
1022 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
1023 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A |
1024 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
1025 ifp->if_flags |= IFF_ALLMULTI;
1026 return;
1027 }
1028
1029 /*
1030 * accept frames if a. crc valid, b. individual address match c.
1031 * broadcast address,and d. multicast addresses matched in the hash
1032 * filter
1033 */
1034 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL,
1035 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A);
1036
1037
1038 /*
1039 * start off with all multicast flag clear, set it if we need to
1040 * later, otherwise we will leave it.
1041 */
1042 ifp->if_flags &= ~IFF_ALLMULTI;
1043 af[0] = af[1] = af[2] = af[3] = 0x0000;
1044
1045 /*
1046 * Loop through all the multicast addresses unless we get a range of
1047 * addresses, in which case we will just accept all packets.
1048 * Justification for this is given in the next comment.
1049 */
1050 ETHER_FIRST_MULTI(step, ec, enm);
1051 while (enm != NULL) {
1052 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
1053 sizeof enm->enm_addrlo)) {
1054 /*
1055 * We must listen to a range of multicast addresses.
1056 * For now, just accept all multicasts, rather than
1057 * trying to set only those filter bits needed to match
1058 * the range. (At this time, the only use of address
1059 * ranges is for IP multicast routing, for which the
1060 * range is big enough to require all bits set.)
1061 */
1062 ifp->if_flags |= IFF_ALLMULTI;
1063 af[0] = af[1] = af[2] = af[3] = 0xffff;
1064 break;
1065 } else {
1066 /*
1067 * we have got an individual address so just set that
1068 * bit.
1069 */
1070 index = cs_hash_index(enm->enm_addrlo);
1071
1072 /* Set the bit the Logical address filter. */
1073 port = (u_int16_t) (index >> 4);
1074 mask = (u_int16_t) (1 << (index & 0xf));
1075 af[port] |= mask;
1076
1077 ETHER_NEXT_MULTI(step, enm);
1078 }
1079 }
1080
1081 /* now program the chip with the addresses */
1082 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]);
1083 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]);
1084 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]);
1085 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]);
1086 return;
1087 }
1088
1089 u_int16_t
1090 cs_hash_index(char *addr)
1091 {
1092 uint32_t crc;
1093 uint16_t hash_code;
1094
1095 crc = ether_crc32_le(addr, ETHER_ADDR_LEN);
1096
1097 hash_code = crc >> 26;
1098 return (hash_code);
1099 }
1100
1101 void
1102 cs_reset(void *arg)
1103 {
1104 struct cs_softc *sc = arg;
1105
1106 /* Mark the interface as down */
1107 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING;
1108
1109 /* Reset the chip */
1110 cs_reset_chip(sc);
1111 }
1112
1113 int
1114 cs_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1115 {
1116 struct cs_softc *sc = ifp->if_softc;
1117 struct ifreq *ifr = (struct ifreq *) data;
1118 int state;
1119 int result;
1120
1121 state = splnet();
1122
1123 result = 0; /* only set if something goes wrong */
1124
1125 switch (cmd) {
1126 case SIOCGIFMEDIA:
1127 case SIOCSIFMEDIA:
1128 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
1129 break;
1130
1131 default:
1132 result = ether_ioctl(ifp, cmd, data);
1133 if (result == ENETRESET) {
1134 if (CS_IS_ENABLED(sc)) {
1135 /*
1136 * Multicast list has changed. Set the
1137 * hardware filter accordingly.
1138 */
1139 cs_set_ladr_filt(sc, &sc->sc_ethercom);
1140 }
1141 result = 0;
1142 }
1143 break;
1144 }
1145
1146 splx(state);
1147
1148 return result;
1149 }
1150
1151 int
1152 cs_mediachange(struct ifnet *ifp)
1153 {
1154
1155 /*
1156 * Current media is already set up. Just reset the interface
1157 * to let the new value take hold.
1158 */
1159 cs_init(ifp);
1160 return (0);
1161 }
1162
1163 void
1164 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1165 {
1166 struct cs_softc *sc = ifp->if_softc;
1167
1168 /*
1169 * The currently selected media is always the active media.
1170 */
1171 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media;
1172
1173 if (ifp->if_flags & IFF_UP) {
1174 /* Interface up, status is valid. */
1175 ifmr->ifm_status = IFM_AVALID |
1176 (sc->sc_carrier ? IFM_ACTIVE : 0);
1177 }
1178 else ifmr->ifm_status = 0;
1179 }
1180
1181 int
1182 cs_intr(void *arg)
1183 {
1184 struct cs_softc *sc = arg;
1185 u_int16_t Event;
1186 #if NRND > 0
1187 u_int16_t rndEvent;
1188 #endif
1189
1190 /*printf("cs_intr %p\n", sc);*/
1191 /* Ignore any interrupts that happen while the chip is being reset */
1192 if (sc->sc_resetting) {
1193 printf("%s: cs_intr: reset in progress\n",
1194 sc->sc_dev.dv_xname);
1195 return 1;
1196 }
1197
1198 /* Read an event from the Interrupt Status Queue */
1199 if (sc->sc_memorymode)
1200 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
1201 else
1202 Event = CS_READ_PORT(sc, PORT_ISQ);
1203
1204 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff)
1205 return 0; /* not ours */
1206
1207 #if NRND > 0
1208 rndEvent = Event;
1209 #endif
1210
1211 /* Process all the events in the Interrupt Status Queue */
1212 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) {
1213 /* Dispatch to an event handler based on the register number */
1214 switch (Event & REG_NUM_MASK) {
1215 case REG_NUM_RX_EVENT:
1216 cs_receive_event(sc, Event);
1217 break;
1218 case REG_NUM_TX_EVENT:
1219 cs_transmit_event(sc, Event);
1220 break;
1221 case REG_NUM_BUF_EVENT:
1222 cs_buffer_event(sc, Event);
1223 break;
1224 case REG_NUM_TX_COL:
1225 case REG_NUM_RX_MISS:
1226 cs_counter_event(sc, Event);
1227 break;
1228 default:
1229 printf("%s: unknown interrupt event 0x%x\n",
1230 sc->sc_dev.dv_xname, Event);
1231 break;
1232 }
1233
1234 /* Read another event from the Interrupt Status Queue */
1235 if (sc->sc_memorymode)
1236 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ);
1237 else
1238 Event = CS_READ_PORT(sc, PORT_ISQ);
1239 }
1240
1241 /* have handled the interrupt */
1242 #if NRND > 0
1243 rnd_add_uint32(&sc->rnd_source, rndEvent);
1244 #endif
1245 return 1;
1246 }
1247
1248 void
1249 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent)
1250 {
1251 struct ifnet *ifp;
1252 u_int16_t errorCount;
1253
1254 ifp = &sc->sc_ethercom.ec_if;
1255
1256 switch (cntEvent & REG_NUM_MASK) {
1257 case REG_NUM_TX_COL:
1258 /*
1259 * the count should be read before an overflow occurs.
1260 */
1261 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL);
1262 /*
1263 * the tramsit event routine always checks the number of
1264 * collisions for any packet so we don't increment any
1265 * counters here, as they should already have been
1266 * considered.
1267 */
1268 break;
1269 case REG_NUM_RX_MISS:
1270 /*
1271 * the count should be read before an overflow occurs.
1272 */
1273 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS);
1274 /*
1275 * Increment the input error count, the first 6bits are the
1276 * register id.
1277 */
1278 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6);
1279 break;
1280 default:
1281 /* do nothing */
1282 break;
1283 }
1284 }
1285
1286 void
1287 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent)
1288 {
1289
1290 /*
1291 * multiple events can be in the buffer event register at one time so
1292 * a standard switch statement will not suffice, here every event
1293 * must be checked.
1294 */
1295
1296 /*
1297 * if 128 bits have been rxed by the time we get here, the dest event
1298 * will be cleared and 128 event will be set.
1299 */
1300 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) {
1301 cs_process_rx_early(sc);
1302 }
1303
1304 if (bufEvent & BUF_EVENT_RX_DMA) {
1305 /* process the receive data */
1306 if (sc->sc_dma_process_rx)
1307 (*sc->sc_dma_process_rx)(sc);
1308 else
1309 /* should panic? */
1310 printf("%s: unexpected DMA event\n", sc->sc_dev.dv_xname);
1311 }
1312
1313 if (bufEvent & BUF_EVENT_TX_UNDR) {
1314 #if 0
1315 /*
1316 * This can happen occasionally, and it's not worth worrying
1317 * about.
1318 */
1319 printf("%s: transmit underrun (%d -> %d)\n",
1320 sc->sc_dev.dv_xname, sc->sc_xe_ent,
1321 cs_xmit_early_table[sc->sc_xe_ent].worse);
1322 #endif
1323 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse;
1324 sc->sc_xe_togo =
1325 cs_xmit_early_table[sc->sc_xe_ent].better_count;
1326
1327 /* had an underrun, transmit is finished */
1328 sc->sc_txbusy = FALSE;
1329 }
1330
1331 if (bufEvent & BUF_EVENT_SW_INT) {
1332 printf("%s: software initiated interrupt\n",
1333 sc->sc_dev.dv_xname);
1334 }
1335 }
1336
1337 void
1338 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent)
1339 {
1340 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1341
1342 /* If there were any errors transmitting this frame */
1343 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN |
1344 TX_EVENT_JABBER | TX_EVENT_16_COLL)) {
1345 /* Increment the output error count */
1346 ifp->if_oerrors++;
1347
1348 /* Note carrier loss. */
1349 if (txEvent & TX_EVENT_LOSS_CRS)
1350 sc->sc_carrier = 0;
1351
1352 /* If debugging is enabled then log error messages */
1353 if (ifp->if_flags & IFF_DEBUG) {
1354 if (txEvent & TX_EVENT_LOSS_CRS) {
1355 printf("%s: lost carrier\n",
1356 sc->sc_dev.dv_xname);
1357 }
1358 if (txEvent & TX_EVENT_SQE_ERR) {
1359 printf("%s: SQE error\n",
1360 sc->sc_dev.dv_xname);
1361 }
1362 if (txEvent & TX_EVENT_OUT_WIN) {
1363 printf("%s: out-of-window collision\n",
1364 sc->sc_dev.dv_xname);
1365 }
1366 if (txEvent & TX_EVENT_JABBER) {
1367 printf("%s: jabber\n", sc->sc_dev.dv_xname);
1368 }
1369 if (txEvent & TX_EVENT_16_COLL) {
1370 printf("%s: 16 collisions\n",
1371 sc->sc_dev.dv_xname);
1372 }
1373 }
1374 }
1375 else {
1376 /* Transmission successful, carrier is up. */
1377 sc->sc_carrier = 1;
1378 #ifdef SHARK
1379 ledNetActive();
1380 #endif
1381 }
1382
1383 /* Add the number of collisions for this frame */
1384 if (txEvent & TX_EVENT_16_COLL) {
1385 ifp->if_collisions += 16;
1386 } else {
1387 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11);
1388 }
1389
1390 ifp->if_opackets++;
1391
1392 /* Transmission is no longer in progress */
1393 sc->sc_txbusy = FALSE;
1394
1395 /* If there is more to transmit */
1396 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) {
1397 /* Start the next transmission */
1398 cs_start_output(ifp);
1399 }
1400 }
1401
1402 void
1403 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent)
1404 {
1405
1406 if (rxEvent & RX_EVENT_RUNT)
1407 printf("%s: runt\n", sc->sc_dev.dv_xname);
1408
1409 if (rxEvent & RX_EVENT_X_DATA)
1410 printf("%s: extra data\n", sc->sc_dev.dv_xname);
1411
1412 if (rxEvent & RX_EVENT_CRC_ERR) {
1413 if (rxEvent & RX_EVENT_DRIBBLE)
1414 printf("%s: alignment error\n", sc->sc_dev.dv_xname);
1415 else
1416 printf("%s: CRC error\n", sc->sc_dev.dv_xname);
1417 } else {
1418 if (rxEvent & RX_EVENT_DRIBBLE)
1419 printf("%s: dribble bits\n", sc->sc_dev.dv_xname);
1420 }
1421 }
1422
1423 void
1424 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent)
1425 {
1426 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1427
1428 /* If the frame was not received OK */
1429 if (!(rxEvent & RX_EVENT_RX_OK)) {
1430 /* Increment the input error count */
1431 ifp->if_ierrors++;
1432
1433 /*
1434 * If debugging is enabled then log error messages.
1435 */
1436 if (ifp->if_flags & IFF_DEBUG) {
1437 if (rxEvent != REG_NUM_RX_EVENT) {
1438 cs_print_rx_errors(sc, rxEvent);
1439
1440 /*
1441 * Must read the length of all received
1442 * frames
1443 */
1444 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
1445
1446 /* Skip the received frame */
1447 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1448 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) |
1449 RX_CFG_SKIP);
1450 } else {
1451 printf("%s: implied skip\n",
1452 sc->sc_dev.dv_xname);
1453 }
1454 }
1455 } else {
1456 /*
1457 * process the received frame and pass it up to the upper
1458 * layers.
1459 */
1460 cs_process_receive(sc);
1461 }
1462 }
1463
1464 void
1465 cs_ether_input(struct cs_softc *sc, struct mbuf *m)
1466 {
1467 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1468
1469 ifp->if_ipackets++;
1470
1471 #if NBPFILTER > 0
1472 /*
1473 * Check if there's a BPF listener on this interface.
1474 * If so, hand off the raw packet to BPF.
1475 */
1476 if (ifp->if_bpf)
1477 bpf_mtap(ifp->if_bpf, m);
1478 #endif
1479
1480 /* Pass the packet up. */
1481 (*ifp->if_input)(ifp, m);
1482 }
1483
1484 void
1485 cs_process_receive(struct cs_softc *sc)
1486 {
1487 struct ifnet *ifp;
1488 struct mbuf *m;
1489 int totlen;
1490 u_int16_t *pBuff, *pBuffLimit;
1491 int pad;
1492 unsigned int frameOffset = 0; /* XXX: gcc */
1493
1494 #ifdef SHARK
1495 ledNetActive();
1496 #endif
1497
1498 ifp = &sc->sc_ethercom.ec_if;
1499
1500 /* Received a packet; carrier is up. */
1501 sc->sc_carrier = 1;
1502
1503 if (sc->sc_memorymode) {
1504 /* Initialize the frame offset */
1505 frameOffset = PKTPG_RX_LENGTH;
1506
1507 /* Get the length of the received frame */
1508 totlen = CS_READ_PACKET_PAGE(sc, frameOffset);
1509 frameOffset += 2;
1510 }
1511 else {
1512 /* drop status */
1513 CS_READ_PORT(sc, PORT_RXTX_DATA);
1514
1515 /* Get the length of the received frame */
1516 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA);
1517 }
1518
1519 if (totlen > ETHER_MAX_LEN) {
1520 printf("%s: invalid packet length %d\n",
1521 sc->sc_dev.dv_xname, totlen);
1522
1523 /* skip the received frame */
1524 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1525 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1526 return;
1527 }
1528
1529 MGETHDR(m, M_DONTWAIT, MT_DATA);
1530 if (m == 0) {
1531 printf("%s: cs_process_receive: unable to allocate mbuf\n",
1532 sc->sc_dev.dv_xname);
1533 ifp->if_ierrors++;
1534 /*
1535 * couldn't allocate an mbuf so things are not good, may as
1536 * well drop the packet I think.
1537 *
1538 * have already read the length so we should be right to skip
1539 * the packet.
1540 */
1541 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1542 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1543 return;
1544 }
1545 m->m_pkthdr.rcvif = ifp;
1546 m->m_pkthdr.len = totlen;
1547
1548 /* number of bytes to align ip header on word boundary for ipintr */
1549 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
1550
1551 /*
1552 * alloc mbuf cluster if we need.
1553 * we need 1 byte spare because following
1554 * packet read loop can overrun.
1555 */
1556 if (totlen + pad + 1 > MHLEN) {
1557 MCLGET(m, M_DONTWAIT);
1558 if ((m->m_flags & M_EXT) == 0) {
1559 /* couldn't allocate an mbuf cluster */
1560 printf("%s: cs_process_receive: unable to allocate a cluster\n",
1561 sc->sc_dev.dv_xname);
1562 m_freem(m);
1563
1564 /* skip the received frame */
1565 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1566 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1567 return;
1568 }
1569 }
1570
1571 /* align ip header on word boundary for ipintr */
1572 m->m_data += pad;
1573
1574 m->m_len = totlen;
1575 pBuff = mtod(m, u_int16_t *);
1576
1577 /* now read the data from the chip */
1578 if (sc->sc_memorymode) {
1579 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */
1580 while (pBuff < pBuffLimit) {
1581 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
1582 frameOffset += 2;
1583 }
1584 }
1585 else {
1586 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1);
1587 }
1588
1589 cs_ether_input(sc, m);
1590 }
1591
1592 void
1593 cs_process_rx_early(struct cs_softc *sc)
1594 {
1595 struct ifnet *ifp;
1596 struct mbuf *m;
1597 u_int16_t frameCount, oldFrameCount;
1598 u_int16_t rxEvent;
1599 u_int16_t *pBuff;
1600 int pad;
1601 unsigned int frameOffset;
1602
1603
1604 ifp = &sc->sc_ethercom.ec_if;
1605
1606 /* Initialize the frame offset */
1607 frameOffset = PKTPG_RX_FRAME;
1608 frameCount = 0;
1609
1610 MGETHDR(m, M_DONTWAIT, MT_DATA);
1611 if (m == 0) {
1612 printf("%s: cs_process_rx_early: unable to allocate mbuf\n",
1613 sc->sc_dev.dv_xname);
1614 ifp->if_ierrors++;
1615 /*
1616 * couldn't allocate an mbuf so things are not good, may as
1617 * well drop the packet I think.
1618 *
1619 * have already read the length so we should be right to skip
1620 * the packet.
1621 */
1622 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1623 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1624 return;
1625 }
1626 m->m_pkthdr.rcvif = ifp;
1627 /*
1628 * save processing by always using a mbuf cluster, guaranteed to fit
1629 * packet
1630 */
1631 MCLGET(m, M_DONTWAIT);
1632 if ((m->m_flags & M_EXT) == 0) {
1633 /* couldn't allocate an mbuf cluster */
1634 printf("%s: cs_process_rx_early: unable to allocate a cluster\n",
1635 sc->sc_dev.dv_xname);
1636 m_freem(m);
1637 /* skip the frame */
1638 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG,
1639 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP);
1640 return;
1641 }
1642
1643 /* align ip header on word boundary for ipintr */
1644 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
1645 m->m_data += pad;
1646
1647 /* set up the buffer pointer to point to the data area */
1648 pBuff = mtod(m, u_int16_t *);
1649
1650 /*
1651 * now read the frame byte counter until we have finished reading the
1652 * frame
1653 */
1654 oldFrameCount = 0;
1655 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
1656 while ((frameCount != 0) && (frameCount < MCLBYTES)) {
1657 for (; oldFrameCount < frameCount; oldFrameCount += 2) {
1658 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset);
1659 frameOffset += 2;
1660 }
1661
1662 /* read the new count from the chip */
1663 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT);
1664 }
1665
1666 /* update the mbuf counts */
1667 m->m_len = oldFrameCount;
1668 m->m_pkthdr.len = oldFrameCount;
1669
1670 /* now check the Rx Event register */
1671 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
1672
1673 if ((rxEvent & RX_EVENT_RX_OK) != 0) {
1674 /*
1675 * do an implied skip, it seems to be more reliable than a
1676 * forced skip.
1677 */
1678 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS);
1679 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH);
1680
1681 /*
1682 * now read the RX_EVENT register to perform an implied skip.
1683 */
1684 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT);
1685
1686 cs_ether_input(sc, m);
1687 } else {
1688 m_freem(m);
1689 ifp->if_ierrors++;
1690 }
1691 }
1692
1693 void
1694 cs_start_output(struct ifnet *ifp)
1695 {
1696 struct cs_softc *sc;
1697 struct mbuf *pMbuf;
1698 struct mbuf *pMbufChain;
1699 u_int16_t BusStatus;
1700 u_int16_t Length;
1701 int txLoop = 0;
1702 int dropout = 0;
1703
1704 sc = ifp->if_softc;
1705
1706 /* check that the interface is up and running */
1707 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) {
1708 return;
1709 }
1710
1711 /* Don't interrupt a transmission in progress */
1712 if (sc->sc_txbusy) {
1713 return;
1714 }
1715
1716 /* this loop will only run through once if transmission is successful */
1717 /*
1718 * While there are packets to transmit and a transmit is not in
1719 * progress
1720 */
1721 while (sc->sc_txbusy == 0 && dropout == 0) {
1722 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain);
1723 if (pMbufChain == NULL)
1724 break;
1725
1726 #if NBPFILTER > 0
1727 /*
1728 * If BPF is listening on this interface, let it see the packet
1729 * before we commit it to the wire.
1730 */
1731 if (ifp->if_bpf)
1732 bpf_mtap(ifp->if_bpf, pMbufChain);
1733 #endif
1734
1735 /* Find the total length of the data to transmit */
1736 Length = 0;
1737 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next)
1738 Length += pMbuf->m_len;
1739
1740 do {
1741 /*
1742 * Request that the transmit be started after all
1743 * data has been copied
1744 *
1745 * In IO mode must write to the IO port not the packet
1746 * page address
1747 *
1748 * If this is changed to start transmission after a
1749 * small amount of data has been copied you tend to
1750 * get packet missed errors i think because the ISA
1751 * bus is too slow. Or possibly the copy routine is
1752 * not streamlined enough.
1753 */
1754 if (sc->sc_memorymode) {
1755 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD,
1756 cs_xmit_early_table[sc->sc_xe_ent].txcmd);
1757 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length);
1758 }
1759 else {
1760 CS_WRITE_PORT(sc, PORT_TX_CMD,
1761 cs_xmit_early_table[sc->sc_xe_ent].txcmd);
1762 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length);
1763 }
1764
1765 /*
1766 * Adjust early-transmit machinery.
1767 */
1768 if (--sc->sc_xe_togo == 0) {
1769 sc->sc_xe_ent =
1770 cs_xmit_early_table[sc->sc_xe_ent].better;
1771 sc->sc_xe_togo =
1772 cs_xmit_early_table[sc->sc_xe_ent].better_count;
1773 }
1774 /*
1775 * Read the BusStatus register which indicates
1776 * success of the request
1777 */
1778 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST);
1779
1780 /*
1781 * If there was an error in the transmit bid free the
1782 * mbuf and go on. This is presuming that mbuf is
1783 * corrupt.
1784 */
1785 if (BusStatus & BUS_ST_TX_BID_ERR) {
1786 printf("%s: transmit bid error (too big)",
1787 sc->sc_dev.dv_xname);
1788
1789 /* Discard the bad mbuf chain */
1790 m_freem(pMbufChain);
1791 sc->sc_ethercom.ec_if.if_oerrors++;
1792
1793 /* Loop up to transmit the next chain */
1794 txLoop = 0;
1795 } else {
1796 if (BusStatus & BUS_ST_RDY4TXNOW) {
1797 /*
1798 * The chip is ready for transmission
1799 * now
1800 */
1801 /*
1802 * Copy the frame to the chip to
1803 * start transmission
1804 */
1805 cs_copy_tx_frame(sc, pMbufChain);
1806
1807 /* Free the mbuf chain */
1808 m_freem(pMbufChain);
1809
1810 /* Transmission is now in progress */
1811 sc->sc_txbusy = TRUE;
1812 txLoop = 0;
1813 } else {
1814 /*
1815 * if we get here we want to try
1816 * again with the same mbuf, until
1817 * the chip lets us transmit.
1818 */
1819 txLoop++;
1820 if (txLoop > CS_OUTPUT_LOOP_MAX) {
1821 /* Free the mbuf chain */
1822 m_freem(pMbufChain);
1823 /*
1824 * Transmission is not in
1825 * progress
1826 */
1827 sc->sc_txbusy = FALSE;
1828 /*
1829 * Increment the output error
1830 * count
1831 */
1832 ifp->if_oerrors++;
1833 /*
1834 * exit the routine and drop
1835 * the packet.
1836 */
1837 txLoop = 0;
1838 dropout = 1;
1839 }
1840 }
1841 }
1842 } while (txLoop);
1843 }
1844 }
1845
1846 void
1847 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0)
1848 {
1849 struct mbuf *m;
1850 int len, leftover, frameoff;
1851 u_int16_t dbuf;
1852 u_int8_t *p;
1853 #ifdef DIAGNOSTIC
1854 u_int8_t *lim;
1855 #endif
1856
1857 /* Initialize frame pointer and data port address */
1858 frameoff = PKTPG_TX_FRAME;
1859
1860 /* start out with no leftover data */
1861 leftover = 0;
1862 dbuf = 0;
1863
1864 /* Process the chain of mbufs */
1865 for (m = m0; m != NULL; m = m->m_next) {
1866 /*
1867 * Process all of the data in a single mbuf.
1868 */
1869 p = mtod(m, u_int8_t *);
1870 len = m->m_len;
1871 #ifdef DIAGNOSTIC
1872 lim = p + len;
1873 #endif
1874
1875 while (len > 0) {
1876 if (leftover) {
1877 /*
1878 * Data left over (from mbuf or realignment).
1879 * Buffer the next byte, and write it and
1880 * the leftover data out.
1881 */
1882 dbuf |= *p++ << 8;
1883 len--;
1884 if (sc->sc_memorymode) {
1885 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
1886 frameoff += 2;
1887 }
1888 else {
1889 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
1890 }
1891 leftover = 0;
1892 } else if ((long) p & 1) {
1893 /*
1894 * Misaligned data. Buffer the next byte.
1895 */
1896 dbuf = *p++;
1897 len--;
1898 leftover = 1;
1899 } else {
1900 /*
1901 * Aligned data. This is the case we like.
1902 *
1903 * Write-region out as much as we can, then
1904 * buffer the remaining byte (if any).
1905 */
1906 leftover = len & 1;
1907 len &= ~1;
1908 if (sc->sc_memorymode) {
1909 MEM_WRITE_REGION_2(sc, frameoff,
1910 (u_int16_t *) p, len >> 1);
1911 frameoff += len;
1912 }
1913 else {
1914 IO_WRITE_MULTI_2(sc,
1915 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1);
1916 }
1917 p += len;
1918
1919 if (leftover)
1920 dbuf = *p++;
1921 len = 0;
1922 }
1923 }
1924 if (len < 0)
1925 panic("cs_copy_tx_frame: negative len");
1926 #ifdef DIAGNOSTIC
1927 if (p != lim)
1928 panic("cs_copy_tx_frame: p != lim");
1929 #endif
1930 }
1931 if (leftover) {
1932 if (sc->sc_memorymode) {
1933 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf);
1934 }
1935 else {
1936 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf);
1937 }
1938 }
1939 }
1940
1941 static int
1942 cs_enable(struct cs_softc *sc)
1943 {
1944
1945 if (CS_IS_ENABLED(sc) == 0) {
1946 if (sc->sc_enable != NULL) {
1947 int error;
1948
1949 error = (*sc->sc_enable)(sc);
1950 if (error)
1951 return (error);
1952 }
1953 sc->sc_cfgflags |= CFGFLG_ENABLED;
1954 }
1955
1956 return (0);
1957 }
1958
1959 static void
1960 cs_disable(struct cs_softc *sc)
1961 {
1962
1963 if (CS_IS_ENABLED(sc)) {
1964 if (sc->sc_disable != NULL)
1965 (*sc->sc_disable)(sc);
1966
1967 sc->sc_cfgflags &= ~CFGFLG_ENABLED;
1968 }
1969 }
1970
1971 static void
1972 cs_stop(struct ifnet *ifp, int disable)
1973 {
1974 struct cs_softc *sc = ifp->if_softc;
1975
1976 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0);
1977 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0);
1978 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0);
1979 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0);
1980
1981 if (disable) {
1982 cs_disable(sc);
1983 }
1984
1985 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1986 }
1987
1988 int
1989 cs_activate(struct device *self, enum devact act)
1990 {
1991 struct cs_softc *sc = (void *)self;
1992 int s, error = 0;
1993
1994 s = splnet();
1995 switch (act) {
1996 case DVACT_ACTIVATE:
1997 error = EOPNOTSUPP;
1998 break;
1999
2000 case DVACT_DEACTIVATE:
2001 if_deactivate(&sc->sc_ethercom.ec_if);
2002 break;
2003 }
2004 splx(s);
2005
2006 return error;
2007 }
2008
2009 static void
2010 cs_power(int why, void *arg)
2011 {
2012 struct cs_softc *sc = arg;
2013 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
2014 int s;
2015
2016 s = splnet();
2017 switch (why) {
2018 case PWR_STANDBY:
2019 case PWR_SUSPEND:
2020 cs_stop(ifp, 0);
2021 break;
2022 case PWR_RESUME:
2023 if (ifp->if_flags & IFF_UP) {
2024 cs_init(ifp);
2025 }
2026 break;
2027 case PWR_SOFTSUSPEND:
2028 case PWR_SOFTSTANDBY:
2029 case PWR_SOFTRESUME:
2030 break;
2031 }
2032 splx(s);
2033 }
Cache object: ba886c65ea7d00d653cd4770a6be5b50
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