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sys/dev/ic/cs89x0.c
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1 /* $NetBSD: cs89x0.c,v 1.16 2005/02/27 00:27:01 perry Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher Gilbert 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1997 31 * Digital Equipment Corporation. All rights reserved. 32 * 33 * This software is furnished under license and may be used and 34 * copied only in accordance with the following terms and conditions. 35 * Subject to these conditions, you may download, copy, install, 36 * use, modify and distribute this software in source and/or binary 37 * form. No title or ownership is transferred hereby. 38 * 39 * 1) Any source code used, modified or distributed must reproduce 40 * and retain this copyright notice and list of conditions as 41 * they appear in the source file. 42 * 43 * 2) No right is granted to use any trade name, trademark, or logo of 44 * Digital Equipment Corporation. Neither the "Digital Equipment 45 * Corporation" name nor any trademark or logo of Digital Equipment 46 * Corporation may be used to endorse or promote products derived 47 * from this software without the prior written permission of 48 * Digital Equipment Corporation. 49 * 50 * 3) This software is provided "AS-IS" and any express or implied 51 * warranties, including but not limited to, any implied warranties 52 * of merchantability, fitness for a particular purpose, or 53 * non-infringement are disclaimed. In no event shall DIGITAL be 54 * liable for any damages whatsoever, and in particular, DIGITAL 55 * shall not be liable for special, indirect, consequential, or 56 * incidental damages or damages for lost profits, loss of 57 * revenue or loss of use, whether such damages arise in contract, 58 * negligence, tort, under statute, in equity, at law or otherwise, 59 * even if advised of the possibility of such damage. 60 */ 61 62 /* 63 **++ 64 ** FACILITY 65 ** 66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 67 ** 68 ** ABSTRACT 69 ** 70 ** This module provides standard ethernet access for INET protocols 71 ** only. 72 ** 73 ** AUTHORS 74 ** 75 ** Peter Dettori SEA - Software Engineering. 76 ** 77 ** CREATION DATE: 78 ** 79 ** 13-Feb-1997. 80 ** 81 ** MODIFICATION HISTORY (Digital): 82 ** 83 ** Revision 1.27 1998/01/20 17:59:40 cgd 84 ** update for moved headers 85 ** 86 ** Revision 1.26 1998/01/12 19:29:36 cgd 87 ** use arm32/isa versions of isadma code. 88 ** 89 ** Revision 1.25 1997/12/12 01:35:27 cgd 90 ** convert to use new arp code (from Brini) 91 ** 92 ** Revision 1.24 1997/12/10 22:31:56 cgd 93 ** trim some fat (get rid of ability to explicitly supply enet addr, since 94 ** it was never used and added a bunch of code which really doesn't belong in 95 ** an enet driver), and clean up slightly. 96 ** 97 ** Revision 1.23 1997/10/06 16:42:12 cgd 98 ** copyright notices 99 ** 100 ** Revision 1.22 1997/06/20 19:38:01 chaiken 101 ** fixes some smartcard problems 102 ** 103 ** Revision 1.21 1997/06/10 02:56:20 grohn 104 ** Added call to ledNetActive 105 ** 106 ** Revision 1.20 1997/06/05 00:47:06 dettori 107 ** Changed cs_process_rx_dma to reset and re-initialise the 108 ** ethernet chip when DMA gets out of sync, or mbufs 109 ** can't be allocated. 110 ** 111 ** Revision 1.19 1997/06/03 03:09:58 dettori 112 ** Turn off sc_txbusy flag when a transmit underrun 113 ** occurs. 114 ** 115 ** Revision 1.18 1997/06/02 00:04:35 dettori 116 ** redefined the transmit table to get around the nfs_timer bug while we are 117 ** looking into it further. 118 ** 119 ** Also changed interrupts from EDGE to LEVEL. 120 ** 121 ** Revision 1.17 1997/05/27 23:31:01 dettori 122 ** Pulled out changes to DMAMODE defines. 123 ** 124 ** Revision 1.16 1997/05/23 04:25:16 cgd 125 ** reformat log so it fits in 80cols 126 ** 127 ** Revision 1.15 1997/05/23 04:22:18 cgd 128 ** remove the existing copyright notice (which Peter Dettori indicated 129 ** was incorrect, copied from an existing NetBSD file only so that the 130 ** file would have a copyright notice on it, and which he'd intended to 131 ** replace). Replace it with a Digital copyright notice, cloned from 132 ** ess.c. It's not really correct either (it indicates that the source 133 ** is Digital confidential!), but is better than nothing and more 134 ** correct than what was there before. 135 ** 136 ** Revision 1.14 1997/05/23 04:12:50 cgd 137 ** use an adaptive transmit start algorithm: start by telling the chip 138 ** to start transmitting after 381 bytes have been fed to it. if that 139 ** gets transmit underruns, ramp down to 1021 bytes then "whole 140 ** packet." If successful at a given level for a while, try the next 141 ** more agressive level. This code doesn't ever try to start 142 ** transmitting after 5 bytes have been sent to the NIC, because 143 ** that underruns rather regularly. The back-off and ramp-up mechanism 144 ** could probably be tuned a little bit, but this works well enough to 145 ** support > 1MB/s transmit rates on a clear ethernet (which is about 146 ** 20-25% better than the driver had previously been getting). 147 ** 148 ** Revision 1.13 1997/05/22 21:06:54 cgd 149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 150 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 151 ** issues. This would cause bogus data to be spit out for mbufs with 152 ** misaligned data. For instance, it caused the following bits to appear 153 ** on the wire: 154 ** ... etBND 1S2C .SHA(K) R ... 155 ** 11112222333344445555 156 ** which should have appeared as: 157 ** ... NetBSD 1.2C (SHARK) ... 158 ** 11112222333344445555 159 ** Note the apparent 'rotate' of the bytes in the word, which was due to 160 ** incorrect unaligned accesses. This data corruption was the cause of 161 ** incoming telnet/rlogin hangs. 162 ** 163 ** Revision 1.12 1997/05/22 01:55:32 cgd 164 ** reformat log so it fits in 80cols 165 ** 166 ** Revision 1.11 1997/05/22 01:50:27 cgd 167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 168 ** so packets aimed at other hosts don't get sent to ether_input(). 169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 170 ** you can easily tell (`strings`) what version of the driver is in your 171 ** kernel binary. 172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 173 ** safe, and not really a performance win anyway. (It was only used when 174 ** setting up the multicast logical address filter, which is an 175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 176 ** address check above, but the benefit of it vs. memcmp would be 177 ** inconsequential, there.) Use memcmp() instead. 178 ** * restructure csStartOuput to avoid the following bugs in the case where 179 ** txWait was being set: 180 ** * it would accidentally drop the outgoing packet if told to wait 181 ** but the outgoing packet queue was empty. 182 ** * it would bpf_mtap() the outgoing packet multiple times (once for 183 ** each time it was told to wait), and would also recalculate 184 ** the length of the outgoing packet each time it was told to 185 ** wait. 186 ** While there, rename txWait to txLoop, since with the new structure of 187 ** the code, the latter name makes more sense. 188 ** 189 ** Revision 1.10 1997/05/19 02:03:20 cgd 190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 194 ** as before. 195 ** 196 ** Revision 1.9 1997/05/19 01:45:37 cgd 197 ** create a new function, cs_ether_input(), which does received-packet 198 ** BPF and ether_input processing. This code used to be in three places, 199 ** and centralizing it will make adding IFF_PROMISC support much easier. 200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 201 ** do copies with bus_space_write_region_2(). It's more correct, and 202 ** potentially more efficient. That function needs to be gutted (to 203 ** deal properly with alignment issues, which it currently does wrong), 204 ** however, and the change doesn't gain much, so there's no point in 205 ** enabling it now. 206 ** 207 ** Revision 1.8 1997/05/19 01:17:10 cgd 208 ** fix a comment re: the setting of the TxConfig register. Clean up 209 ** interface counter maintenance (make it use standard idiom). 210 ** 211 **-- 212 */ 213 214 #include <sys/cdefs.h> 215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.16 2005/02/27 00:27:01 perry Exp $"); 216 217 #include "opt_inet.h" 218 219 #include <sys/param.h> 220 #include <sys/systm.h> 221 #include <sys/mbuf.h> 222 #include <sys/syslog.h> 223 #include <sys/socket.h> 224 #include <sys/device.h> 225 #include <sys/malloc.h> 226 #include <sys/ioctl.h> 227 #include <sys/errno.h> 228 229 #include "rnd.h" 230 #if NRND > 0 231 #include <sys/rnd.h> 232 #endif 233 234 #include <net/if.h> 235 #include <net/if_ether.h> 236 #include <net/if_media.h> 237 #ifdef INET 238 #include <netinet/in.h> 239 #include <netinet/if_inarp.h> 240 #endif 241 242 #include "bpfilter.h" 243 #if NBPFILTER > 0 244 #include <net/bpf.h> 245 #include <net/bpfdesc.h> 246 #endif 247 248 #include <uvm/uvm_extern.h> 249 250 #include <machine/bus.h> 251 #include <machine/intr.h> 252 253 #include <dev/ic/cs89x0reg.h> 254 #include <dev/ic/cs89x0var.h> 255 256 #ifdef SHARK 257 #include <shark/shark/sequoia.h> 258 #endif 259 260 /* 261 * MACRO DEFINITIONS 262 */ 263 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 264 265 /* 266 * FUNCTION PROTOTYPES 267 */ 268 void cs_get_default_media(struct cs_softc *); 269 int cs_get_params(struct cs_softc *); 270 int cs_get_enaddr(struct cs_softc *); 271 int cs_reset_chip(struct cs_softc *); 272 void cs_reset(void *); 273 int cs_ioctl(struct ifnet *, u_long, caddr_t); 274 void cs_initChip(struct cs_softc *); 275 void cs_buffer_event(struct cs_softc *, u_int16_t); 276 void cs_transmit_event(struct cs_softc *, u_int16_t); 277 void cs_receive_event(struct cs_softc *, u_int16_t); 278 void cs_process_receive(struct cs_softc *); 279 void cs_process_rx_early(struct cs_softc *); 280 void cs_start_output(struct ifnet *); 281 void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 282 void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 283 u_int16_t cs_hash_index(char *); 284 void cs_counter_event(struct cs_softc *, u_int16_t); 285 286 int cs_mediachange(struct ifnet *); 287 void cs_mediastatus(struct ifnet *, struct ifmediareq *); 288 289 static int cs_enable(struct cs_softc *); 290 static void cs_disable(struct cs_softc *); 291 static void cs_stop(struct ifnet *, int); 292 static void cs_power(int, void *); 293 static int cs_scan_eeprom(struct cs_softc *); 294 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, u_int16_t *); 295 296 297 /* 298 * GLOBAL DECLARATIONS 299 */ 300 301 /* 302 * Xmit-early table. 303 * 304 * To get better performance, we tell the chip to start packet 305 * transmission before the whole packet is copied to the chip. 306 * However, this can fail under load. When it fails, we back off 307 * to a safer setting for a little while. 308 * 309 * txcmd is the value of txcmd used to indicate when to start transmission. 310 * better is the next 'better' state in the table. 311 * better_count is the number of output packets before transition to the 312 * better state. 313 * worse is the next 'worse' state in the table. 314 * 315 * Transition to the next worse state happens automatically when a 316 * transmittion underrun occurs. 317 */ 318 struct cs_xmit_early { 319 u_int16_t txcmd; 320 int better; 321 int better_count; 322 int worse; 323 } cs_xmit_early_table[3] = { 324 { TX_CMD_START_381, 0, INT_MAX, 1, }, 325 { TX_CMD_START_1021, 0, 50000, 2, }, 326 { TX_CMD_START_ALL, 1, 5000, 2, }, 327 }; 328 329 int cs_default_media[] = { 330 IFM_ETHER|IFM_10_2, 331 IFM_ETHER|IFM_10_5, 332 IFM_ETHER|IFM_10_T, 333 IFM_ETHER|IFM_10_T|IFM_FDX, 334 }; 335 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 336 337 int 338 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media, 339 int nmedia, int defmedia) 340 { 341 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 342 const char *chipname, *medname; 343 u_int16_t reg; 344 int i; 345 346 /* Start out in IO mode */ 347 sc->sc_memorymode = FALSE; 348 349 /* make sure we're right */ 350 for (i = 0; i < 10000; i++) { 351 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 352 if (reg == EISA_NUM_CRYSTAL) { 353 break; 354 } 355 } 356 if (i == 10000) { 357 printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg); 358 return 1; /* XXX should panic? */ 359 } 360 361 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 362 sc->sc_prodid = reg & PROD_ID_MASK; 363 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 364 365 switch (sc->sc_prodid) { 366 case PROD_ID_CS8900: 367 chipname = "CS8900"; 368 break; 369 case PROD_ID_CS8920: 370 chipname = "CS8920"; 371 break; 372 case PROD_ID_CS8920M: 373 chipname = "CS8920M"; 374 break; 375 default: 376 panic("cs_attach: impossible"); 377 } 378 379 /* 380 * the first thing to do is check that the mbuf cluster size is 381 * greater than the MTU for an ethernet frame. The code depends on 382 * this and to port this to a OS where this was not the case would 383 * not be straightforward. 384 * 385 * we need 1 byte spare because our 386 * packet read loop can overrun. 387 * and we may need pad bytes to align ip header. 388 */ 389 if (MCLBYTES < ETHER_MAX_LEN + 1 + 390 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 391 printf("%s: MCLBYTES too small for Ethernet frame\n", 392 sc->sc_dev.dv_xname); 393 return 1; 394 } 395 396 /* Start out not transmitting */ 397 sc->sc_txbusy = FALSE; 398 399 /* Set up early transmit threshhold */ 400 sc->sc_xe_ent = 0; 401 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 402 403 /* Initialize ifnet structure. */ 404 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 405 ifp->if_softc = sc; 406 ifp->if_start = cs_start_output; 407 ifp->if_init = cs_init; 408 ifp->if_ioctl = cs_ioctl; 409 ifp->if_stop = cs_stop; 410 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 411 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 412 IFF_BROADCAST | IFF_MULTICAST; 413 IFQ_SET_READY(&ifp->if_snd); 414 415 /* Initialize ifmedia structures. */ 416 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 417 418 if (media != NULL) { 419 for (i = 0; i < nmedia; i++) 420 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 421 ifmedia_set(&sc->sc_media, defmedia); 422 } else { 423 for (i = 0; i < cs_default_nmedia; i++) 424 ifmedia_add(&sc->sc_media, cs_default_media[i], 425 0, NULL); 426 cs_get_default_media(sc); 427 } 428 429 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 430 if (cs_scan_eeprom(sc) == CS_ERROR) { 431 /* failed to scan the eeprom, pretend there isn't an eeprom */ 432 printf("%s: unable to scan EEPROM\n", 433 sc->sc_dev.dv_xname); 434 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM; 435 } 436 } 437 438 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 439 /* Get parameters from the EEPROM */ 440 if (cs_get_params(sc) == CS_ERROR) { 441 printf("%s: unable to get settings from EEPROM\n", 442 sc->sc_dev.dv_xname); 443 return 1; 444 } 445 } 446 447 if (enaddr != NULL) 448 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 449 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 450 /* Get and store the Ethernet address */ 451 if (cs_get_enaddr(sc) == CS_ERROR) { 452 printf("%s: unable to read Ethernet address\n", 453 sc->sc_dev.dv_xname); 454 return 1; 455 } 456 } else { 457 #if 1 458 int i; 459 uint v; 460 461 for (i = 0; i < 6; i += 2) { 462 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + i); 463 sc->sc_enaddr[i + 0] = v; 464 sc->sc_enaddr[i + 1] = v >> 8; 465 } 466 #else 467 printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname); 468 return 1; 469 #endif 470 } 471 472 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 473 case IFM_10_2: 474 medname = "BNC"; 475 break; 476 case IFM_10_5: 477 medname = "AUI"; 478 break; 479 case IFM_10_T: 480 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 481 medname = "UTP <full-duplex>"; 482 else 483 medname = "UTP"; 484 break; 485 default: 486 panic("cs_attach: impossible"); 487 } 488 printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname, 489 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 490 medname); 491 492 if (sc->sc_dma_attach) 493 (*sc->sc_dma_attach)(sc); 494 495 sc->sc_sh = shutdownhook_establish(cs_reset, sc); 496 if (sc->sc_sh == NULL) { 497 printf("%s: unable to establish shutdownhook\n", 498 sc->sc_dev.dv_xname); 499 cs_detach(sc); 500 return 1; 501 } 502 503 /* Attach the interface. */ 504 if_attach(ifp); 505 ether_ifattach(ifp, sc->sc_enaddr); 506 507 #if NRND > 0 508 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 509 RND_TYPE_NET, 0); 510 #endif 511 sc->sc_cfgflags |= CFGFLG_ATTACHED; 512 513 /* Reset the chip */ 514 if (cs_reset_chip(sc) == CS_ERROR) { 515 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 516 cs_detach(sc); 517 return 1; 518 } 519 520 sc->sc_powerhook = powerhook_establish(cs_power, sc); 521 if (sc->sc_powerhook == 0) 522 printf("%s: warning: powerhook_establish failed\n", 523 sc->sc_dev.dv_xname); 524 525 return 0; 526 } 527 528 int 529 cs_detach(struct cs_softc *sc) 530 { 531 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 532 533 if (sc->sc_powerhook) { 534 powerhook_disestablish(sc->sc_powerhook); 535 sc->sc_powerhook = 0; 536 } 537 538 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 539 #if NRND > 0 540 rnd_detach_source(&sc->rnd_source); 541 #endif 542 ether_ifdetach(ifp); 543 if_detach(ifp); 544 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 545 } 546 547 if (sc->sc_sh != NULL) 548 shutdownhook_disestablish(sc->sc_sh); 549 550 #if 0 551 /* 552 * XXX not necessary 553 */ 554 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 555 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 556 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 557 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 558 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 559 } 560 #endif 561 562 return 0; 563 } 564 565 void 566 cs_get_default_media(struct cs_softc *sc) 567 { 568 u_int16_t adp_cfg, xmit_ctl; 569 570 if (cs_verify_eeprom(sc) == CS_ERROR) { 571 printf("%s: cs_get_default_media: EEPROM missing or bad\n", 572 sc->sc_dev.dv_xname); 573 goto fakeit; 574 } 575 576 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) { 577 printf("%s: unable to read adapter config from EEPROM\n", 578 sc->sc_dev.dv_xname); 579 goto fakeit; 580 } 581 582 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) { 583 printf("%s: unable to read transmit control from EEPROM\n", 584 sc->sc_dev.dv_xname); 585 goto fakeit; 586 } 587 588 switch (adp_cfg & ADPTR_CFG_MEDIA) { 589 case ADPTR_CFG_AUI: 590 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 591 break; 592 case ADPTR_CFG_10BASE2: 593 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 594 break; 595 case ADPTR_CFG_10BASET: 596 default: 597 if (xmit_ctl & XMIT_CTL_FDX) 598 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 599 else 600 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 601 break; 602 } 603 return; 604 605 fakeit: 606 printf("%s: WARNING: default media setting may be inaccurate\n", 607 sc->sc_dev.dv_xname); 608 /* XXX Arbitrary... */ 609 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 610 } 611 612 /* 613 * cs_scan_eeprom 614 * 615 * Attempt to take a complete copy of the eeprom into main memory. 616 * this will allow faster parsing of the eeprom data. 617 * 618 * Only tested against a 8920M's eeprom, but the data sheet for the 619 * 8920A indicates that is uses the same layout. 620 */ 621 int 622 cs_scan_eeprom(struct cs_softc *sc) 623 { 624 u_int16_t result; 625 int i; 626 int eeprom_size; 627 u_int8_t checksum = 0; 628 629 if (cs_verify_eeprom(sc) == CS_ERROR) { 630 printf("%s: cs_scan_params: EEPROM missing or bad\n", 631 sc->sc_dev.dv_xname); 632 return (CS_ERROR); 633 } 634 635 /* 636 * read the 0th word from the eeprom, it will tell us the length 637 * and if the eeprom is valid 638 */ 639 cs_read_eeprom(sc, 0, &result); 640 641 /* check the eeprom signature */ 642 if ((result & 0xE000) != 0xA000) { 643 /* empty eeprom */ 644 return (CS_ERROR); 645 } 646 647 /* 648 * take the eeprom size (note the read value doesn't include the header 649 * word) 650 */ 651 eeprom_size = (result & 0xff) + 2; 652 653 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK); 654 if (sc->eeprom_data == NULL) { 655 /* no memory, treat this as if there's no eeprom */ 656 return (CS_ERROR); 657 } 658 659 sc->eeprom_size = eeprom_size; 660 661 /* read the eeprom into the buffer, also calculate the checksum */ 662 for (i = 0; i < (eeprom_size >> 1); i++) { 663 cs_read_eeprom(sc, i, &(sc->eeprom_data[i])); 664 checksum += (sc->eeprom_data[i] & 0xff00) >> 8; 665 checksum += (sc->eeprom_data[i] & 0x00ff); 666 } 667 668 /* 669 * validate checksum calculation, the sum of all the bytes should be 0, 670 * as the high byte of the last word is the 2's complement of the 671 * sum to that point. 672 */ 673 if (checksum != 0) { 674 printf("%s: eeprom checksum failure\n", sc->sc_dev.dv_xname); 675 return (CS_ERROR); 676 } 677 678 return (CS_OK); 679 } 680 681 static int 682 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, u_int16_t *pValue) 683 { 684 int x, maxword; 685 686 /* Check that we have eeprom data */ 687 if (sc->eeprom_data == NULL && (sc->eeprom_size > 2)) 688 return (CS_ERROR); 689 690 /* 691 * We only want to read the data words, the last word contains the 692 * checksum 693 */ 694 maxword = (sc->eeprom_size - 2) >> 1; 695 696 /* start 1 word in, as the first word is the length and signature */ 697 x = 1; 698 699 while ( x < (maxword)) { 700 u_int16_t header; 701 int group_size; 702 int offset; 703 int offset_max; 704 705 /* read in the group header word */ 706 header = sc->eeprom_data[x]; 707 x++; /* skip group header */ 708 709 /* 710 * size of group in words is in the top 4 bits, note that it 711 * is one less than the number of words 712 */ 713 group_size = header & 0xF000; 714 715 /* 716 * CS8900 Data sheet says this should be 0x01ff, 717 * but my cs8920 eeprom has higher offsets, 718 * perhaps the 8920 allows higher offsets, otherwise 719 * it's writing to places that it shouldn't 720 */ 721 /* work out the offsets this group covers */ 722 offset = header & 0x0FFF; 723 offset_max = offset + (group_size << 1); 724 725 /* check if the pkgpg we're after is in this group */ 726 if ((offset <= pktpg) && (pktpg <= offset_max)) { 727 /* the pkgpg value we want is in here */ 728 int eeprom_location; 729 730 eeprom_location = ((pktpg - offset) >> 1) ; 731 732 *pValue = sc->eeprom_data[x + eeprom_location]; 733 return (CS_OK); 734 } else { 735 /* skip this group (+ 1 for first entry) */ 736 x += group_size + 1; 737 } 738 } 739 740 /* 741 * if we've fallen out here then we don't have a value in the EEPROM 742 * for this pktpg so return an error 743 */ 744 return (CS_ERROR); 745 } 746 747 int 748 cs_get_params(struct cs_softc *sc) 749 { 750 u_int16_t isaConfig; 751 u_int16_t adapterConfig; 752 753 if (cs_verify_eeprom(sc) == CS_ERROR) { 754 printf("%s: cs_get_params: EEPROM missing or bad\n", 755 sc->sc_dev.dv_xname); 756 return (CS_ERROR); 757 } 758 759 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 760 /* Get ISA configuration from the EEPROM */ 761 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig) 762 == CS_ERROR) { 763 /* eeprom doesn't have this value, use data sheet default */ 764 isaConfig = 0x0017; 765 } 766 767 /* Get adapter configuration from the EEPROM */ 768 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, &adapterConfig) 769 == CS_ERROR) { 770 /* eeprom doesn't have this value, use data sheet default */ 771 adapterConfig = 0x0015; 772 } 773 774 /* Copy the USE_SA flag */ 775 if (isaConfig & BUS_CTL_USE_SA) 776 sc->sc_cfgflags |= CFGFLG_USE_SA; 777 778 /* Copy the IO Channel Ready flag */ 779 if (isaConfig & BUS_CTL_IOCHRDY) 780 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 781 782 /* Copy the DC/DC Polarity flag */ 783 if (adapterConfig & SELF_CTL_HCB1) 784 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 785 } else { 786 /* Get ISA configuration from the EEPROM */ 787 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR) 788 goto eeprom_bad; 789 790 /* Get adapter configuration from the EEPROM */ 791 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR) 792 goto eeprom_bad; 793 794 /* Copy the USE_SA flag */ 795 if (isaConfig & ISA_CFG_USE_SA) 796 sc->sc_cfgflags |= CFGFLG_USE_SA; 797 798 /* Copy the IO Channel Ready flag */ 799 if (isaConfig & ISA_CFG_IOCHRDY) 800 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 801 802 /* Copy the DC/DC Polarity flag */ 803 if (adapterConfig & ADPTR_CFG_DCDC_POL) 804 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 805 } 806 807 return (CS_OK); 808 eeprom_bad: 809 printf("%s: cs_get_params: unable to read from EEPROM\n", 810 sc->sc_dev.dv_xname); 811 return (CS_ERROR); 812 } 813 814 int 815 cs_get_enaddr(struct cs_softc *sc) 816 { 817 u_int16_t *myea; 818 819 if (cs_verify_eeprom(sc) == CS_ERROR) { 820 printf("%s: cs_get_enaddr: EEPROM missing or bad\n", 821 sc->sc_dev.dv_xname); 822 return (CS_ERROR); 823 } 824 825 myea = (u_int16_t *)sc->sc_enaddr; 826 827 /* Get Ethernet address from the EEPROM */ 828 /* XXX this will likely lose on a big-endian machine. -- cgd */ 829 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 830 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0]) 831 == CS_ERROR) 832 goto eeprom_bad; 833 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1]) 834 == CS_ERROR) 835 goto eeprom_bad; 836 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2]) 837 == CS_ERROR) 838 goto eeprom_bad; 839 } else { 840 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR) 841 goto eeprom_bad; 842 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR) 843 goto eeprom_bad; 844 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR) 845 goto eeprom_bad; 846 } 847 848 return (CS_OK); 849 850 eeprom_bad: 851 printf("%s: cs_get_enaddr: unable to read from EEPROM\n", 852 sc->sc_dev.dv_xname); 853 return (CS_ERROR); 854 } 855 856 int 857 cs_reset_chip(struct cs_softc *sc) 858 { 859 int intState; 860 int x; 861 862 /* Disable interrupts at the CPU so reset command is atomic */ 863 intState = splnet(); 864 865 /* 866 * We are now resetting the chip 867 * 868 * A spurious interrupt is generated by the chip when it is reset. This 869 * variable informs the interrupt handler to ignore this interrupt. 870 */ 871 sc->sc_resetting = TRUE; 872 873 /* Issue a reset command to the chip */ 874 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 875 876 /* Re-enable interrupts at the CPU */ 877 splx(intState); 878 879 /* The chip is always in IO mode after a reset */ 880 sc->sc_memorymode = FALSE; 881 882 /* If transmission was in progress, it is not now */ 883 sc->sc_txbusy = FALSE; 884 885 /* 886 * there was a delay(125); here, but it seems uneccesary 125 usec is 887 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 888 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 889 * should be sufficient. 890 */ 891 892 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 893 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 894 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 895 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 896 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 897 898 /* Wait until the EEPROM is not busy */ 899 for (x = 0; x < MAXLOOP; x++) { 900 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 901 break; 902 } 903 904 if (x == MAXLOOP) 905 return CS_ERROR; 906 907 /* Wait until initialization is done */ 908 for (x = 0; x < MAXLOOP; x++) { 909 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 910 break; 911 } 912 913 if (x == MAXLOOP) 914 return CS_ERROR; 915 916 /* Reset is no longer in progress */ 917 sc->sc_resetting = FALSE; 918 919 return CS_OK; 920 } 921 922 int 923 cs_verify_eeprom(struct cs_softc *sc) 924 { 925 u_int16_t self_status; 926 927 /* Verify that the EEPROM is present and OK */ 928 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST); 929 if (((self_status & SELF_ST_EEP_PRES) && 930 (self_status & SELF_ST_EEP_OK)) == 0) 931 return (CS_ERROR); 932 933 return (CS_OK); 934 } 935 936 int 937 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue) 938 { 939 int x; 940 941 /* Ensure that the EEPROM is not busy */ 942 for (x = 0; x < MAXLOOP; x++) { 943 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 944 SELF_ST_SI_BUSY)) 945 break; 946 } 947 948 if (x == MAXLOOP) 949 return (CS_ERROR); 950 951 /* Issue the command to read the offset within the EEPROM */ 952 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD, 953 offset | EEPROM_CMD_READ); 954 955 /* Wait until the command is completed */ 956 for (x = 0; x < MAXLOOP; x++) { 957 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 958 SELF_ST_SI_BUSY)) 959 break; 960 } 961 962 if (x == MAXLOOP) 963 return (CS_ERROR); 964 965 /* Get the EEPROM data from the EEPROM Data register */ 966 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA); 967 968 return (CS_OK); 969 } 970 971 void 972 cs_initChip(struct cs_softc *sc) 973 { 974 u_int16_t busCtl; 975 u_int16_t selfCtl; 976 u_int16_t v; 977 u_int16_t isaId; 978 int i; 979 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 980 981 /* Disable reception and transmission of frames */ 982 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 983 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 984 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 985 986 /* Disable interrupt at the chip */ 987 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 988 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 989 990 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 991 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 992 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 993 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 994 busCtl & ~BUS_CTL_IOCHRDY); 995 } else { 996 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 997 busCtl | BUS_CTL_IOCHRDY); 998 } 999 1000 /* Set the Line Control register to match the media type */ 1001 if (media == IFM_10_T) 1002 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 1003 else 1004 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 1005 1006 /* 1007 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 1008 * enable the DC/DC converter 1009 */ 1010 selfCtl = SELF_CTL_HC1E; 1011 1012 /* If the media type is 10Base2 */ 1013 if (media == IFM_10_2) { 1014 /* 1015 * Enable the DC/DC converter if it has a low enable. 1016 */ 1017 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 1018 /* 1019 * Set the HCB1 bit, which causes the HC1 pin to go 1020 * low. 1021 */ 1022 selfCtl |= SELF_CTL_HCB1; 1023 } else { /* Media type is 10BaseT or AUI */ 1024 /* 1025 * Disable the DC/DC converter if it has a high enable. 1026 */ 1027 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 1028 /* 1029 * Set the HCB1 bit, which causes the HC1 pin to go 1030 * low. 1031 */ 1032 selfCtl |= SELF_CTL_HCB1; 1033 } 1034 } 1035 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 1036 1037 /* enable normal link pulse */ 1038 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 1039 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 1040 1041 /* Enable full-duplex, if appropriate */ 1042 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 1043 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 1044 1045 /* RX_CTL set in cs_set_ladr_filt(), below */ 1046 1047 /* enable all transmission interrupts */ 1048 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 1049 1050 /* Accept all receive interrupts */ 1051 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 1052 1053 /* 1054 * Configure Operational Modes 1055 * 1056 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 1057 * a better way to do it because the card has a counter which can be 1058 * read to update the RX_MISS counter. This saves many interrupts. 1059 * 1060 * I have turned on the tx and rx overflow interrupts to counter using 1061 * the receive miss interrupt. This is a better estimate of errors 1062 * and requires lower system overhead. 1063 */ 1064 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 1065 BUF_CFG_RX_DMA_IE); 1066 1067 if (sc->sc_dma_chipinit) 1068 (*sc->sc_dma_chipinit)(sc); 1069 1070 /* If memory mode is enabled */ 1071 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 1072 /* If external logic is present for address decoding */ 1073 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 1074 /* 1075 * Program the external logic to decode address bits 1076 * SA20-SA23 1077 */ 1078 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 1079 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 1080 EEPROM_CMD_ELSEL); 1081 } 1082 1083 /* 1084 * Write the packet page base physical address to the memory 1085 * base register. 1086 */ 1087 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 1088 sc->sc_pktpgaddr & 0xFFFF); 1089 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 1090 sc->sc_pktpgaddr >> 16); 1091 busCtl = BUS_CTL_MEM_MODE; 1092 1093 /* tell the chip to read the addresses off the SA pins */ 1094 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 1095 busCtl |= BUS_CTL_USE_SA; 1096 } 1097 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1098 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 1099 1100 /* We are in memory mode now! */ 1101 sc->sc_memorymode = TRUE; 1102 1103 /* 1104 * wait here (10ms) for the chip to swap over. this is the 1105 * maximum time that this could take. 1106 */ 1107 delay(10000); 1108 1109 /* Verify that we can read from the chip */ 1110 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 1111 1112 /* 1113 * As a last minute sanity check before actually using mapped 1114 * memory we verify that we can read the isa number from the 1115 * chip in memory mode. 1116 */ 1117 if (isaId != EISA_NUM_CRYSTAL) { 1118 printf("%s: failed to enable memory mode\n", 1119 sc->sc_dev.dv_xname); 1120 sc->sc_memorymode = FALSE; 1121 } else { 1122 /* 1123 * we are in memory mode so if we aren't using DMA, 1124 * then program the chip to interrupt early. 1125 */ 1126 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 1127 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 1128 BUF_CFG_RX_DEST_IE | 1129 BUF_CFG_RX_MISS_OVER_IE | 1130 BUF_CFG_TX_COL_OVER_IE); 1131 } 1132 } 1133 1134 } 1135 1136 /* Put Ethernet address into the Individual Address register */ 1137 for (i = 0; i < 6; i += 2) { 1138 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8; 1139 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v); 1140 } 1141 1142 if (sc->sc_irq != -1) { 1143 /* Set the interrupt level in the chip */ 1144 if (sc->sc_prodid == PROD_ID_CS8900) { 1145 if (sc->sc_irq == 5) { 1146 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 1147 } else { 1148 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 1149 } 1150 } 1151 else { /* CS8920 */ 1152 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 1153 } 1154 } 1155 1156 /* write the multicast mask to the address filter register */ 1157 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1158 1159 /* Enable reception and transmission of frames */ 1160 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 1161 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 1162 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 1163 1164 /* Enable interrupt at the chip */ 1165 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1166 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 1167 } 1168 1169 int 1170 cs_init(struct ifnet *ifp) 1171 { 1172 int intState; 1173 int error = CS_OK; 1174 struct cs_softc *sc = ifp->if_softc; 1175 1176 if (cs_enable(sc)) 1177 goto out; 1178 1179 cs_stop(ifp, 0); 1180 1181 intState = splnet(); 1182 1183 #if 0 1184 /* Mark the interface as down */ 1185 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 1186 #endif 1187 1188 #ifdef CS_DEBUG 1189 /* Enable debugging */ 1190 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 1191 #endif 1192 1193 /* Reset the chip */ 1194 if ((error = cs_reset_chip(sc)) == CS_OK) { 1195 /* Initialize the chip */ 1196 cs_initChip(sc); 1197 1198 /* Mark the interface as running */ 1199 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1200 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1201 sc->sc_ethercom.ec_if.if_timer = 0; 1202 1203 /* Assume we have carrier until we are told otherwise. */ 1204 sc->sc_carrier = 1; 1205 } else { 1206 printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname); 1207 } 1208 1209 splx(intState); 1210 out: 1211 if (error == CS_OK) 1212 return 0; 1213 return EIO; 1214 } 1215 1216 void 1217 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1218 { 1219 struct ifnet *ifp = &ec->ec_if; 1220 struct ether_multi *enm; 1221 struct ether_multistep step; 1222 u_int16_t af[4]; 1223 u_int16_t port, mask, index; 1224 1225 /* 1226 * Set up multicast address filter by passing all multicast addresses 1227 * through a crc generator, and then using the high order 6 bits as an 1228 * index into the 64 bit logical address filter. The high order bit 1229 * selects the word, while the rest of the bits select the bit within 1230 * the word. 1231 */ 1232 if (ifp->if_flags & IFF_PROMISC) { 1233 /* accept all valid frames. */ 1234 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1235 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1236 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1237 ifp->if_flags |= IFF_ALLMULTI; 1238 return; 1239 } 1240 1241 /* 1242 * accept frames if a. crc valid, b. individual address match c. 1243 * broadcast address,and d. multicast addresses matched in the hash 1244 * filter 1245 */ 1246 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1247 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1248 1249 1250 /* 1251 * start off with all multicast flag clear, set it if we need to 1252 * later, otherwise we will leave it. 1253 */ 1254 ifp->if_flags &= ~IFF_ALLMULTI; 1255 af[0] = af[1] = af[2] = af[3] = 0x0000; 1256 1257 /* 1258 * Loop through all the multicast addresses unless we get a range of 1259 * addresses, in which case we will just accept all packets. 1260 * Justification for this is given in the next comment. 1261 */ 1262 ETHER_FIRST_MULTI(step, ec, enm); 1263 while (enm != NULL) { 1264 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1265 sizeof enm->enm_addrlo)) { 1266 /* 1267 * We must listen to a range of multicast addresses. 1268 * For now, just accept all multicasts, rather than 1269 * trying to set only those filter bits needed to match 1270 * the range. (At this time, the only use of address 1271 * ranges is for IP multicast routing, for which the 1272 * range is big enough to require all bits set.) 1273 */ 1274 ifp->if_flags |= IFF_ALLMULTI; 1275 af[0] = af[1] = af[2] = af[3] = 0xffff; 1276 break; 1277 } else { 1278 /* 1279 * we have got an individual address so just set that 1280 * bit. 1281 */ 1282 index = cs_hash_index(enm->enm_addrlo); 1283 1284 /* Set the bit the Logical address filter. */ 1285 port = (u_int16_t) (index >> 4); 1286 mask = (u_int16_t) (1 << (index & 0xf)); 1287 af[port] |= mask; 1288 1289 ETHER_NEXT_MULTI(step, enm); 1290 } 1291 } 1292 1293 /* now program the chip with the addresses */ 1294 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1295 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1296 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1297 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1298 return; 1299 } 1300 1301 u_int16_t 1302 cs_hash_index(char *addr) 1303 { 1304 uint32_t crc; 1305 uint16_t hash_code; 1306 1307 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1308 1309 hash_code = crc >> 26; 1310 return (hash_code); 1311 } 1312 1313 void 1314 cs_reset(void *arg) 1315 { 1316 struct cs_softc *sc = arg; 1317 1318 /* Mark the interface as down */ 1319 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1320 1321 /* Reset the chip */ 1322 cs_reset_chip(sc); 1323 } 1324 1325 int 1326 cs_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1327 { 1328 struct cs_softc *sc = ifp->if_softc; 1329 struct ifreq *ifr = (struct ifreq *) data; 1330 int state; 1331 int result; 1332 1333 state = splnet(); 1334 1335 result = 0; /* only set if something goes wrong */ 1336 1337 switch (cmd) { 1338 case SIOCGIFMEDIA: 1339 case SIOCSIFMEDIA: 1340 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1341 break; 1342 1343 default: 1344 result = ether_ioctl(ifp, cmd, data); 1345 if (result == ENETRESET) { 1346 if (ifp->if_flags & IFF_RUNNING) { 1347 /* 1348 * Multicast list has changed. Set the 1349 * hardware filter accordingly. 1350 */ 1351 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1352 } 1353 result = 0; 1354 } 1355 break; 1356 } 1357 1358 splx(state); 1359 1360 return result; 1361 } 1362 1363 int 1364 cs_mediachange(struct ifnet *ifp) 1365 { 1366 1367 /* 1368 * Current media is already set up. Just reset the interface 1369 * to let the new value take hold. 1370 */ 1371 cs_init(ifp); 1372 return (0); 1373 } 1374 1375 void 1376 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1377 { 1378 struct cs_softc *sc = ifp->if_softc; 1379 1380 /* 1381 * The currently selected media is always the active media. 1382 */ 1383 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1384 1385 if (ifp->if_flags & IFF_UP) { 1386 /* Interface up, status is valid. */ 1387 ifmr->ifm_status = IFM_AVALID | 1388 (sc->sc_carrier ? IFM_ACTIVE : 0); 1389 } 1390 else ifmr->ifm_status = 0; 1391 } 1392 1393 int 1394 cs_intr(void *arg) 1395 { 1396 struct cs_softc *sc = arg; 1397 u_int16_t Event; 1398 #if NRND > 0 1399 u_int16_t rndEvent; 1400 #endif 1401 1402 /*printf("cs_intr %p\n", sc);*/ 1403 /* Ignore any interrupts that happen while the chip is being reset */ 1404 if (sc->sc_resetting) { 1405 printf("%s: cs_intr: reset in progress\n", 1406 sc->sc_dev.dv_xname); 1407 return 1; 1408 } 1409 1410 /* Read an event from the Interrupt Status Queue */ 1411 if (sc->sc_memorymode) 1412 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1413 else 1414 Event = CS_READ_PORT(sc, PORT_ISQ); 1415 1416 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1417 return 0; /* not ours */ 1418 1419 #if NRND > 0 1420 rndEvent = Event; 1421 #endif 1422 1423 /* Process all the events in the Interrupt Status Queue */ 1424 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1425 /* Dispatch to an event handler based on the register number */ 1426 switch (Event & REG_NUM_MASK) { 1427 case REG_NUM_RX_EVENT: 1428 cs_receive_event(sc, Event); 1429 break; 1430 case REG_NUM_TX_EVENT: 1431 cs_transmit_event(sc, Event); 1432 break; 1433 case REG_NUM_BUF_EVENT: 1434 cs_buffer_event(sc, Event); 1435 break; 1436 case REG_NUM_TX_COL: 1437 case REG_NUM_RX_MISS: 1438 cs_counter_event(sc, Event); 1439 break; 1440 default: 1441 printf("%s: unknown interrupt event 0x%x\n", 1442 sc->sc_dev.dv_xname, Event); 1443 break; 1444 } 1445 1446 /* Read another event from the Interrupt Status Queue */ 1447 if (sc->sc_memorymode) 1448 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1449 else 1450 Event = CS_READ_PORT(sc, PORT_ISQ); 1451 } 1452 1453 /* have handled the interrupt */ 1454 #if NRND > 0 1455 rnd_add_uint32(&sc->rnd_source, rndEvent); 1456 #endif 1457 return 1; 1458 } 1459 1460 void 1461 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent) 1462 { 1463 struct ifnet *ifp; 1464 u_int16_t errorCount; 1465 1466 ifp = &sc->sc_ethercom.ec_if; 1467 1468 switch (cntEvent & REG_NUM_MASK) { 1469 case REG_NUM_TX_COL: 1470 /* 1471 * the count should be read before an overflow occurs. 1472 */ 1473 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1474 /* 1475 * the tramsit event routine always checks the number of 1476 * collisions for any packet so we don't increment any 1477 * counters here, as they should already have been 1478 * considered. 1479 */ 1480 break; 1481 case REG_NUM_RX_MISS: 1482 /* 1483 * the count should be read before an overflow occurs. 1484 */ 1485 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1486 /* 1487 * Increment the input error count, the first 6bits are the 1488 * register id. 1489 */ 1490 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1491 break; 1492 default: 1493 /* do nothing */ 1494 break; 1495 } 1496 } 1497 1498 void 1499 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent) 1500 { 1501 1502 /* 1503 * multiple events can be in the buffer event register at one time so 1504 * a standard switch statement will not suffice, here every event 1505 * must be checked. 1506 */ 1507 1508 /* 1509 * if 128 bits have been rxed by the time we get here, the dest event 1510 * will be cleared and 128 event will be set. 1511 */ 1512 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1513 cs_process_rx_early(sc); 1514 } 1515 1516 if (bufEvent & BUF_EVENT_RX_DMA) { 1517 /* process the receive data */ 1518 if (sc->sc_dma_process_rx) 1519 (*sc->sc_dma_process_rx)(sc); 1520 else 1521 /* should panic? */ 1522 printf("%s: unexpected DMA event\n", sc->sc_dev.dv_xname); 1523 } 1524 1525 if (bufEvent & BUF_EVENT_TX_UNDR) { 1526 #if 0 1527 /* 1528 * This can happen occasionally, and it's not worth worrying 1529 * about. 1530 */ 1531 printf("%s: transmit underrun (%d -> %d)\n", 1532 sc->sc_dev.dv_xname, sc->sc_xe_ent, 1533 cs_xmit_early_table[sc->sc_xe_ent].worse); 1534 #endif 1535 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1536 sc->sc_xe_togo = 1537 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1538 1539 /* had an underrun, transmit is finished */ 1540 sc->sc_txbusy = FALSE; 1541 } 1542 1543 if (bufEvent & BUF_EVENT_SW_INT) { 1544 printf("%s: software initiated interrupt\n", 1545 sc->sc_dev.dv_xname); 1546 } 1547 } 1548 1549 void 1550 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent) 1551 { 1552 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1553 1554 /* If there were any errors transmitting this frame */ 1555 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1556 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1557 /* Increment the output error count */ 1558 ifp->if_oerrors++; 1559 1560 /* Note carrier loss. */ 1561 if (txEvent & TX_EVENT_LOSS_CRS) 1562 sc->sc_carrier = 0; 1563 1564 /* If debugging is enabled then log error messages */ 1565 if (ifp->if_flags & IFF_DEBUG) { 1566 if (txEvent & TX_EVENT_LOSS_CRS) { 1567 printf("%s: lost carrier\n", 1568 sc->sc_dev.dv_xname); 1569 } 1570 if (txEvent & TX_EVENT_SQE_ERR) { 1571 printf("%s: SQE error\n", 1572 sc->sc_dev.dv_xname); 1573 } 1574 if (txEvent & TX_EVENT_OUT_WIN) { 1575 printf("%s: out-of-window collision\n", 1576 sc->sc_dev.dv_xname); 1577 } 1578 if (txEvent & TX_EVENT_JABBER) { 1579 printf("%s: jabber\n", sc->sc_dev.dv_xname); 1580 } 1581 if (txEvent & TX_EVENT_16_COLL) { 1582 printf("%s: 16 collisions\n", 1583 sc->sc_dev.dv_xname); 1584 } 1585 } 1586 } 1587 else { 1588 /* Transmission successful, carrier is up. */ 1589 sc->sc_carrier = 1; 1590 #ifdef SHARK 1591 ledNetActive(); 1592 #endif 1593 } 1594 1595 /* Add the number of collisions for this frame */ 1596 if (txEvent & TX_EVENT_16_COLL) { 1597 ifp->if_collisions += 16; 1598 } else { 1599 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1600 } 1601 1602 ifp->if_opackets++; 1603 1604 /* Transmission is no longer in progress */ 1605 sc->sc_txbusy = FALSE; 1606 1607 /* If there is more to transmit */ 1608 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1609 /* Start the next transmission */ 1610 cs_start_output(ifp); 1611 } 1612 } 1613 1614 void 1615 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent) 1616 { 1617 1618 if (rxEvent & RX_EVENT_RUNT) 1619 printf("%s: runt\n", sc->sc_dev.dv_xname); 1620 1621 if (rxEvent & RX_EVENT_X_DATA) 1622 printf("%s: extra data\n", sc->sc_dev.dv_xname); 1623 1624 if (rxEvent & RX_EVENT_CRC_ERR) { 1625 if (rxEvent & RX_EVENT_DRIBBLE) 1626 printf("%s: alignment error\n", sc->sc_dev.dv_xname); 1627 else 1628 printf("%s: CRC error\n", sc->sc_dev.dv_xname); 1629 } else { 1630 if (rxEvent & RX_EVENT_DRIBBLE) 1631 printf("%s: dribble bits\n", sc->sc_dev.dv_xname); 1632 } 1633 } 1634 1635 void 1636 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent) 1637 { 1638 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1639 1640 /* If the frame was not received OK */ 1641 if (!(rxEvent & RX_EVENT_RX_OK)) { 1642 /* Increment the input error count */ 1643 ifp->if_ierrors++; 1644 1645 /* 1646 * If debugging is enabled then log error messages. 1647 */ 1648 if (ifp->if_flags & IFF_DEBUG) { 1649 if (rxEvent != REG_NUM_RX_EVENT) { 1650 cs_print_rx_errors(sc, rxEvent); 1651 1652 /* 1653 * Must read the length of all received 1654 * frames 1655 */ 1656 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1657 1658 /* Skip the received frame */ 1659 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1660 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1661 RX_CFG_SKIP); 1662 } else { 1663 printf("%s: implied skip\n", 1664 sc->sc_dev.dv_xname); 1665 } 1666 } 1667 } else { 1668 /* 1669 * process the received frame and pass it up to the upper 1670 * layers. 1671 */ 1672 cs_process_receive(sc); 1673 } 1674 } 1675 1676 void 1677 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1678 { 1679 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1680 1681 ifp->if_ipackets++; 1682 1683 #if NBPFILTER > 0 1684 /* 1685 * Check if there's a BPF listener on this interface. 1686 * If so, hand off the raw packet to BPF. 1687 */ 1688 if (ifp->if_bpf) 1689 bpf_mtap(ifp->if_bpf, m); 1690 #endif 1691 1692 /* Pass the packet up. */ 1693 (*ifp->if_input)(ifp, m); 1694 } 1695 1696 void 1697 cs_process_receive(struct cs_softc *sc) 1698 { 1699 struct ifnet *ifp; 1700 struct mbuf *m; 1701 int totlen; 1702 u_int16_t *pBuff, *pBuffLimit; 1703 int pad; 1704 unsigned int frameOffset = 0; /* XXX: gcc */ 1705 1706 #ifdef SHARK 1707 ledNetActive(); 1708 #endif 1709 1710 ifp = &sc->sc_ethercom.ec_if; 1711 1712 /* Received a packet; carrier is up. */ 1713 sc->sc_carrier = 1; 1714 1715 if (sc->sc_memorymode) { 1716 /* Initialize the frame offset */ 1717 frameOffset = PKTPG_RX_LENGTH; 1718 1719 /* Get the length of the received frame */ 1720 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1721 frameOffset += 2; 1722 } 1723 else { 1724 /* drop status */ 1725 CS_READ_PORT(sc, PORT_RXTX_DATA); 1726 1727 /* Get the length of the received frame */ 1728 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1729 } 1730 1731 if (totlen > ETHER_MAX_LEN) { 1732 printf("%s: invalid packet length %d\n", 1733 sc->sc_dev.dv_xname, totlen); 1734 1735 /* skip the received frame */ 1736 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1737 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1738 return; 1739 } 1740 1741 MGETHDR(m, M_DONTWAIT, MT_DATA); 1742 if (m == 0) { 1743 printf("%s: cs_process_receive: unable to allocate mbuf\n", 1744 sc->sc_dev.dv_xname); 1745 ifp->if_ierrors++; 1746 /* 1747 * couldn't allocate an mbuf so things are not good, may as 1748 * well drop the packet I think. 1749 * 1750 * have already read the length so we should be right to skip 1751 * the packet. 1752 */ 1753 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1754 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1755 return; 1756 } 1757 m->m_pkthdr.rcvif = ifp; 1758 m->m_pkthdr.len = totlen; 1759 1760 /* number of bytes to align ip header on word boundary for ipintr */ 1761 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1762 1763 /* 1764 * alloc mbuf cluster if we need. 1765 * we need 1 byte spare because following 1766 * packet read loop can overrun. 1767 */ 1768 if (totlen + pad + 1 > MHLEN) { 1769 MCLGET(m, M_DONTWAIT); 1770 if ((m->m_flags & M_EXT) == 0) { 1771 /* couldn't allocate an mbuf cluster */ 1772 printf("%s: cs_process_receive: unable to allocate a cluster\n", 1773 sc->sc_dev.dv_xname); 1774 m_freem(m); 1775 1776 /* skip the received frame */ 1777 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1778 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1779 return; 1780 } 1781 } 1782 1783 /* align ip header on word boundary for ipintr */ 1784 m->m_data += pad; 1785 1786 m->m_len = totlen; 1787 pBuff = mtod(m, u_int16_t *); 1788 1789 /* now read the data from the chip */ 1790 if (sc->sc_memorymode) { 1791 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1792 while (pBuff < pBuffLimit) { 1793 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1794 frameOffset += 2; 1795 } 1796 } 1797 else { 1798 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1); 1799 } 1800 1801 cs_ether_input(sc, m); 1802 } 1803 1804 void 1805 cs_process_rx_early(struct cs_softc *sc) 1806 { 1807 struct ifnet *ifp; 1808 struct mbuf *m; 1809 u_int16_t frameCount, oldFrameCount; 1810 u_int16_t rxEvent; 1811 u_int16_t *pBuff; 1812 int pad; 1813 unsigned int frameOffset; 1814 1815 1816 ifp = &sc->sc_ethercom.ec_if; 1817 1818 /* Initialize the frame offset */ 1819 frameOffset = PKTPG_RX_FRAME; 1820 frameCount = 0; 1821 1822 MGETHDR(m, M_DONTWAIT, MT_DATA); 1823 if (m == 0) { 1824 printf("%s: cs_process_rx_early: unable to allocate mbuf\n", 1825 sc->sc_dev.dv_xname); 1826 ifp->if_ierrors++; 1827 /* 1828 * couldn't allocate an mbuf so things are not good, may as 1829 * well drop the packet I think. 1830 * 1831 * have already read the length so we should be right to skip 1832 * the packet. 1833 */ 1834 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1835 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1836 return; 1837 } 1838 m->m_pkthdr.rcvif = ifp; 1839 /* 1840 * save processing by always using a mbuf cluster, guaranteed to fit 1841 * packet 1842 */ 1843 MCLGET(m, M_DONTWAIT); 1844 if ((m->m_flags & M_EXT) == 0) { 1845 /* couldn't allocate an mbuf cluster */ 1846 printf("%s: cs_process_rx_early: unable to allocate a cluster\n", 1847 sc->sc_dev.dv_xname); 1848 m_freem(m); 1849 /* skip the frame */ 1850 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1851 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1852 return; 1853 } 1854 1855 /* align ip header on word boundary for ipintr */ 1856 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1857 m->m_data += pad; 1858 1859 /* set up the buffer pointer to point to the data area */ 1860 pBuff = mtod(m, u_int16_t *); 1861 1862 /* 1863 * now read the frame byte counter until we have finished reading the 1864 * frame 1865 */ 1866 oldFrameCount = 0; 1867 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1868 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1869 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1870 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1871 frameOffset += 2; 1872 } 1873 1874 /* read the new count from the chip */ 1875 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1876 } 1877 1878 /* update the mbuf counts */ 1879 m->m_len = oldFrameCount; 1880 m->m_pkthdr.len = oldFrameCount; 1881 1882 /* now check the Rx Event register */ 1883 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1884 1885 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1886 /* 1887 * do an implied skip, it seems to be more reliable than a 1888 * forced skip. 1889 */ 1890 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1891 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1892 1893 /* 1894 * now read the RX_EVENT register to perform an implied skip. 1895 */ 1896 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1897 1898 cs_ether_input(sc, m); 1899 } else { 1900 m_freem(m); 1901 ifp->if_ierrors++; 1902 } 1903 } 1904 1905 void 1906 cs_start_output(struct ifnet *ifp) 1907 { 1908 struct cs_softc *sc; 1909 struct mbuf *pMbuf; 1910 struct mbuf *pMbufChain; 1911 u_int16_t BusStatus; 1912 u_int16_t Length; 1913 int txLoop = 0; 1914 int dropout = 0; 1915 1916 sc = ifp->if_softc; 1917 1918 /* check that the interface is up and running */ 1919 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1920 return; 1921 } 1922 1923 /* Don't interrupt a transmission in progress */ 1924 if (sc->sc_txbusy) { 1925 return; 1926 } 1927 1928 /* this loop will only run through once if transmission is successful */ 1929 /* 1930 * While there are packets to transmit and a transmit is not in 1931 * progress 1932 */ 1933 while (sc->sc_txbusy == 0 && dropout == 0) { 1934 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1935 if (pMbufChain == NULL) 1936 break; 1937 1938 #if NBPFILTER > 0 1939 /* 1940 * If BPF is listening on this interface, let it see the packet 1941 * before we commit it to the wire. 1942 */ 1943 if (ifp->if_bpf) 1944 bpf_mtap(ifp->if_bpf, pMbufChain); 1945 #endif 1946 1947 /* Find the total length of the data to transmit */ 1948 Length = 0; 1949 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1950 Length += pMbuf->m_len; 1951 1952 do { 1953 /* 1954 * Request that the transmit be started after all 1955 * data has been copied 1956 * 1957 * In IO mode must write to the IO port not the packet 1958 * page address 1959 * 1960 * If this is changed to start transmission after a 1961 * small amount of data has been copied you tend to 1962 * get packet missed errors i think because the ISA 1963 * bus is too slow. Or possibly the copy routine is 1964 * not streamlined enough. 1965 */ 1966 if (sc->sc_memorymode) { 1967 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1968 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1969 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1970 } 1971 else { 1972 CS_WRITE_PORT(sc, PORT_TX_CMD, 1973 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1974 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1975 } 1976 1977 /* 1978 * Adjust early-transmit machinery. 1979 */ 1980 if (--sc->sc_xe_togo == 0) { 1981 sc->sc_xe_ent = 1982 cs_xmit_early_table[sc->sc_xe_ent].better; 1983 sc->sc_xe_togo = 1984 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1985 } 1986 /* 1987 * Read the BusStatus register which indicates 1988 * success of the request 1989 */ 1990 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1991 1992 /* 1993 * If there was an error in the transmit bid free the 1994 * mbuf and go on. This is presuming that mbuf is 1995 * corrupt. 1996 */ 1997 if (BusStatus & BUS_ST_TX_BID_ERR) { 1998 printf("%s: transmit bid error (too big)", 1999 sc->sc_dev.dv_xname); 2000 2001 /* Discard the bad mbuf chain */ 2002 m_freem(pMbufChain); 2003 sc->sc_ethercom.ec_if.if_oerrors++; 2004 2005 /* Loop up to transmit the next chain */ 2006 txLoop = 0; 2007 } else { 2008 if (BusStatus & BUS_ST_RDY4TXNOW) { 2009 /* 2010 * The chip is ready for transmission 2011 * now 2012 */ 2013 /* 2014 * Copy the frame to the chip to 2015 * start transmission 2016 */ 2017 cs_copy_tx_frame(sc, pMbufChain); 2018 2019 /* Free the mbuf chain */ 2020 m_freem(pMbufChain); 2021 2022 /* Transmission is now in progress */ 2023 sc->sc_txbusy = TRUE; 2024 txLoop = 0; 2025 } else { 2026 /* 2027 * if we get here we want to try 2028 * again with the same mbuf, until 2029 * the chip lets us transmit. 2030 */ 2031 txLoop++; 2032 if (txLoop > CS_OUTPUT_LOOP_MAX) { 2033 /* Free the mbuf chain */ 2034 m_freem(pMbufChain); 2035 /* 2036 * Transmission is not in 2037 * progress 2038 */ 2039 sc->sc_txbusy = FALSE; 2040 /* 2041 * Increment the output error 2042 * count 2043 */ 2044 ifp->if_oerrors++; 2045 /* 2046 * exit the routine and drop 2047 * the packet. 2048 */ 2049 txLoop = 0; 2050 dropout = 1; 2051 } 2052 } 2053 } 2054 } while (txLoop); 2055 } 2056 } 2057 2058 void 2059 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 2060 { 2061 struct mbuf *m; 2062 int len, leftover, frameoff; 2063 u_int16_t dbuf; 2064 u_int8_t *p; 2065 #ifdef DIAGNOSTIC 2066 u_int8_t *lim; 2067 #endif 2068 2069 /* Initialize frame pointer and data port address */ 2070 frameoff = PKTPG_TX_FRAME; 2071 2072 /* start out with no leftover data */ 2073 leftover = 0; 2074 dbuf = 0; 2075 2076 /* Process the chain of mbufs */ 2077 for (m = m0; m != NULL; m = m->m_next) { 2078 /* 2079 * Process all of the data in a single mbuf. 2080 */ 2081 p = mtod(m, u_int8_t *); 2082 len = m->m_len; 2083 #ifdef DIAGNOSTIC 2084 lim = p + len; 2085 #endif 2086 2087 while (len > 0) { 2088 if (leftover) { 2089 /* 2090 * Data left over (from mbuf or realignment). 2091 * Buffer the next byte, and write it and 2092 * the leftover data out. 2093 */ 2094 dbuf |= *p++ << 8; 2095 len--; 2096 if (sc->sc_memorymode) { 2097 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2098 frameoff += 2; 2099 } 2100 else { 2101 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2102 } 2103 leftover = 0; 2104 } else if ((long) p & 1) { 2105 /* 2106 * Misaligned data. Buffer the next byte. 2107 */ 2108 dbuf = *p++; 2109 len--; 2110 leftover = 1; 2111 } else { 2112 /* 2113 * Aligned data. This is the case we like. 2114 * 2115 * Write-region out as much as we can, then 2116 * buffer the remaining byte (if any). 2117 */ 2118 leftover = len & 1; 2119 len &= ~1; 2120 if (sc->sc_memorymode) { 2121 MEM_WRITE_REGION_2(sc, frameoff, 2122 (u_int16_t *) p, len >> 1); 2123 frameoff += len; 2124 } 2125 else { 2126 IO_WRITE_MULTI_2(sc, 2127 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 2128 } 2129 p += len; 2130 2131 if (leftover) 2132 dbuf = *p++; 2133 len = 0; 2134 } 2135 } 2136 if (len < 0) 2137 panic("cs_copy_tx_frame: negative len"); 2138 #ifdef DIAGNOSTIC 2139 if (p != lim) 2140 panic("cs_copy_tx_frame: p != lim"); 2141 #endif 2142 } 2143 if (leftover) { 2144 if (sc->sc_memorymode) { 2145 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2146 } 2147 else { 2148 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2149 } 2150 } 2151 } 2152 2153 static int 2154 cs_enable(struct cs_softc *sc) 2155 { 2156 2157 if (CS_IS_ENABLED(sc) == 0) { 2158 if (sc->sc_enable != NULL) { 2159 int error; 2160 2161 error = (*sc->sc_enable)(sc); 2162 if (error) 2163 return (error); 2164 } 2165 sc->sc_cfgflags |= CFGFLG_ENABLED; 2166 } 2167 2168 return (0); 2169 } 2170 2171 static void 2172 cs_disable(struct cs_softc *sc) 2173 { 2174 2175 if (CS_IS_ENABLED(sc)) { 2176 if (sc->sc_disable != NULL) 2177 (*sc->sc_disable)(sc); 2178 2179 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2180 } 2181 } 2182 2183 static void 2184 cs_stop(struct ifnet *ifp, int disable) 2185 { 2186 struct cs_softc *sc = ifp->if_softc; 2187 2188 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2189 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2190 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2191 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2192 2193 if (disable) { 2194 cs_disable(sc); 2195 } 2196 2197 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2198 } 2199 2200 int 2201 cs_activate(struct device *self, enum devact act) 2202 { 2203 struct cs_softc *sc = (void *)self; 2204 int s, error = 0; 2205 2206 s = splnet(); 2207 switch (act) { 2208 case DVACT_ACTIVATE: 2209 error = EOPNOTSUPP; 2210 break; 2211 2212 case DVACT_DEACTIVATE: 2213 if_deactivate(&sc->sc_ethercom.ec_if); 2214 break; 2215 } 2216 splx(s); 2217 2218 return error; 2219 } 2220 2221 static void 2222 cs_power(int why, void *arg) 2223 { 2224 struct cs_softc *sc = arg; 2225 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2226 int s; 2227 2228 s = splnet(); 2229 switch (why) { 2230 case PWR_STANDBY: 2231 case PWR_SUSPEND: 2232 cs_stop(ifp, 0); 2233 break; 2234 case PWR_RESUME: 2235 if (ifp->if_flags & IFF_UP) { 2236 cs_init(ifp); 2237 } 2238 break; 2239 case PWR_SOFTSUSPEND: 2240 case PWR_SOFTSTANDBY: 2241 case PWR_SOFTRESUME: 2242 break; 2243 } 2244 splx(s); 2245 }
Cache object: 81b9e17477400c05b7ab3e8b9e0b0b1a
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