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sys/dev/ic/cs89x0.c
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1 /* $NetBSD: cs89x0.c,v 1.20 2006/09/24 03:53:08 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher Gilbert 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1997 31 * Digital Equipment Corporation. All rights reserved. 32 * 33 * This software is furnished under license and may be used and 34 * copied only in accordance with the following terms and conditions. 35 * Subject to these conditions, you may download, copy, install, 36 * use, modify and distribute this software in source and/or binary 37 * form. No title or ownership is transferred hereby. 38 * 39 * 1) Any source code used, modified or distributed must reproduce 40 * and retain this copyright notice and list of conditions as 41 * they appear in the source file. 42 * 43 * 2) No right is granted to use any trade name, trademark, or logo of 44 * Digital Equipment Corporation. Neither the "Digital Equipment 45 * Corporation" name nor any trademark or logo of Digital Equipment 46 * Corporation may be used to endorse or promote products derived 47 * from this software without the prior written permission of 48 * Digital Equipment Corporation. 49 * 50 * 3) This software is provided "AS-IS" and any express or implied 51 * warranties, including but not limited to, any implied warranties 52 * of merchantability, fitness for a particular purpose, or 53 * non-infringement are disclaimed. In no event shall DIGITAL be 54 * liable for any damages whatsoever, and in particular, DIGITAL 55 * shall not be liable for special, indirect, consequential, or 56 * incidental damages or damages for lost profits, loss of 57 * revenue or loss of use, whether such damages arise in contract, 58 * negligence, tort, under statute, in equity, at law or otherwise, 59 * even if advised of the possibility of such damage. 60 */ 61 62 /* 63 **++ 64 ** FACILITY 65 ** 66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 67 ** 68 ** ABSTRACT 69 ** 70 ** This module provides standard ethernet access for INET protocols 71 ** only. 72 ** 73 ** AUTHORS 74 ** 75 ** Peter Dettori SEA - Software Engineering. 76 ** 77 ** CREATION DATE: 78 ** 79 ** 13-Feb-1997. 80 ** 81 ** MODIFICATION HISTORY (Digital): 82 ** 83 ** Revision 1.27 1998/01/20 17:59:40 cgd 84 ** update for moved headers 85 ** 86 ** Revision 1.26 1998/01/12 19:29:36 cgd 87 ** use arm32/isa versions of isadma code. 88 ** 89 ** Revision 1.25 1997/12/12 01:35:27 cgd 90 ** convert to use new arp code (from Brini) 91 ** 92 ** Revision 1.24 1997/12/10 22:31:56 cgd 93 ** trim some fat (get rid of ability to explicitly supply enet addr, since 94 ** it was never used and added a bunch of code which really doesn't belong in 95 ** an enet driver), and clean up slightly. 96 ** 97 ** Revision 1.23 1997/10/06 16:42:12 cgd 98 ** copyright notices 99 ** 100 ** Revision 1.22 1997/06/20 19:38:01 chaiken 101 ** fixes some smartcard problems 102 ** 103 ** Revision 1.21 1997/06/10 02:56:20 grohn 104 ** Added call to ledNetActive 105 ** 106 ** Revision 1.20 1997/06/05 00:47:06 dettori 107 ** Changed cs_process_rx_dma to reset and re-initialise the 108 ** ethernet chip when DMA gets out of sync, or mbufs 109 ** can't be allocated. 110 ** 111 ** Revision 1.19 1997/06/03 03:09:58 dettori 112 ** Turn off sc_txbusy flag when a transmit underrun 113 ** occurs. 114 ** 115 ** Revision 1.18 1997/06/02 00:04:35 dettori 116 ** redefined the transmit table to get around the nfs_timer bug while we are 117 ** looking into it further. 118 ** 119 ** Also changed interrupts from EDGE to LEVEL. 120 ** 121 ** Revision 1.17 1997/05/27 23:31:01 dettori 122 ** Pulled out changes to DMAMODE defines. 123 ** 124 ** Revision 1.16 1997/05/23 04:25:16 cgd 125 ** reformat log so it fits in 80cols 126 ** 127 ** Revision 1.15 1997/05/23 04:22:18 cgd 128 ** remove the existing copyright notice (which Peter Dettori indicated 129 ** was incorrect, copied from an existing NetBSD file only so that the 130 ** file would have a copyright notice on it, and which he'd intended to 131 ** replace). Replace it with a Digital copyright notice, cloned from 132 ** ess.c. It's not really correct either (it indicates that the source 133 ** is Digital confidential!), but is better than nothing and more 134 ** correct than what was there before. 135 ** 136 ** Revision 1.14 1997/05/23 04:12:50 cgd 137 ** use an adaptive transmit start algorithm: start by telling the chip 138 ** to start transmitting after 381 bytes have been fed to it. if that 139 ** gets transmit underruns, ramp down to 1021 bytes then "whole 140 ** packet." If successful at a given level for a while, try the next 141 ** more agressive level. This code doesn't ever try to start 142 ** transmitting after 5 bytes have been sent to the NIC, because 143 ** that underruns rather regularly. The back-off and ramp-up mechanism 144 ** could probably be tuned a little bit, but this works well enough to 145 ** support > 1MB/s transmit rates on a clear ethernet (which is about 146 ** 20-25% better than the driver had previously been getting). 147 ** 148 ** Revision 1.13 1997/05/22 21:06:54 cgd 149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 150 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 151 ** issues. This would cause bogus data to be spit out for mbufs with 152 ** misaligned data. For instance, it caused the following bits to appear 153 ** on the wire: 154 ** ... etBND 1S2C .SHA(K) R ... 155 ** 11112222333344445555 156 ** which should have appeared as: 157 ** ... NetBSD 1.2C (SHARK) ... 158 ** 11112222333344445555 159 ** Note the apparent 'rotate' of the bytes in the word, which was due to 160 ** incorrect unaligned accesses. This data corruption was the cause of 161 ** incoming telnet/rlogin hangs. 162 ** 163 ** Revision 1.12 1997/05/22 01:55:32 cgd 164 ** reformat log so it fits in 80cols 165 ** 166 ** Revision 1.11 1997/05/22 01:50:27 cgd 167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 168 ** so packets aimed at other hosts don't get sent to ether_input(). 169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 170 ** you can easily tell (`strings`) what version of the driver is in your 171 ** kernel binary. 172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 173 ** safe, and not really a performance win anyway. (It was only used when 174 ** setting up the multicast logical address filter, which is an 175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 176 ** address check above, but the benefit of it vs. memcmp would be 177 ** inconsequential, there.) Use memcmp() instead. 178 ** * restructure csStartOuput to avoid the following bugs in the case where 179 ** txWait was being set: 180 ** * it would accidentally drop the outgoing packet if told to wait 181 ** but the outgoing packet queue was empty. 182 ** * it would bpf_mtap() the outgoing packet multiple times (once for 183 ** each time it was told to wait), and would also recalculate 184 ** the length of the outgoing packet each time it was told to 185 ** wait. 186 ** While there, rename txWait to txLoop, since with the new structure of 187 ** the code, the latter name makes more sense. 188 ** 189 ** Revision 1.10 1997/05/19 02:03:20 cgd 190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 194 ** as before. 195 ** 196 ** Revision 1.9 1997/05/19 01:45:37 cgd 197 ** create a new function, cs_ether_input(), which does received-packet 198 ** BPF and ether_input processing. This code used to be in three places, 199 ** and centralizing it will make adding IFF_PROMISC support much easier. 200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 201 ** do copies with bus_space_write_region_2(). It's more correct, and 202 ** potentially more efficient. That function needs to be gutted (to 203 ** deal properly with alignment issues, which it currently does wrong), 204 ** however, and the change doesn't gain much, so there's no point in 205 ** enabling it now. 206 ** 207 ** Revision 1.8 1997/05/19 01:17:10 cgd 208 ** fix a comment re: the setting of the TxConfig register. Clean up 209 ** interface counter maintenance (make it use standard idiom). 210 ** 211 **-- 212 */ 213 214 #include <sys/cdefs.h> 215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.20 2006/09/24 03:53:08 jmcneill Exp $"); 216 217 #include "opt_inet.h" 218 219 #include <sys/param.h> 220 #include <sys/systm.h> 221 #include <sys/mbuf.h> 222 #include <sys/syslog.h> 223 #include <sys/socket.h> 224 #include <sys/device.h> 225 #include <sys/malloc.h> 226 #include <sys/ioctl.h> 227 #include <sys/errno.h> 228 229 #include "rnd.h" 230 #if NRND > 0 231 #include <sys/rnd.h> 232 #endif 233 234 #include <net/if.h> 235 #include <net/if_ether.h> 236 #include <net/if_media.h> 237 #ifdef INET 238 #include <netinet/in.h> 239 #include <netinet/if_inarp.h> 240 #endif 241 242 #include "bpfilter.h" 243 #if NBPFILTER > 0 244 #include <net/bpf.h> 245 #include <net/bpfdesc.h> 246 #endif 247 248 #include <uvm/uvm_extern.h> 249 250 #include <machine/bus.h> 251 #include <machine/intr.h> 252 253 #include <dev/ic/cs89x0reg.h> 254 #include <dev/ic/cs89x0var.h> 255 256 #ifdef SHARK 257 #include <shark/shark/sequoia.h> 258 #endif 259 260 /* 261 * MACRO DEFINITIONS 262 */ 263 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 264 265 /* 266 * FUNCTION PROTOTYPES 267 */ 268 void cs_get_default_media(struct cs_softc *); 269 int cs_get_params(struct cs_softc *); 270 int cs_get_enaddr(struct cs_softc *); 271 int cs_reset_chip(struct cs_softc *); 272 void cs_reset(void *); 273 int cs_ioctl(struct ifnet *, u_long, caddr_t); 274 void cs_initChip(struct cs_softc *); 275 void cs_buffer_event(struct cs_softc *, u_int16_t); 276 void cs_transmit_event(struct cs_softc *, u_int16_t); 277 void cs_receive_event(struct cs_softc *, u_int16_t); 278 void cs_process_receive(struct cs_softc *); 279 void cs_process_rx_early(struct cs_softc *); 280 void cs_start_output(struct ifnet *); 281 void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 282 void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 283 u_int16_t cs_hash_index(char *); 284 void cs_counter_event(struct cs_softc *, u_int16_t); 285 286 int cs_mediachange(struct ifnet *); 287 void cs_mediastatus(struct ifnet *, struct ifmediareq *); 288 289 static int cs_enable(struct cs_softc *); 290 static void cs_disable(struct cs_softc *); 291 static void cs_stop(struct ifnet *, int); 292 static void cs_power(int, void *); 293 static int cs_scan_eeprom(struct cs_softc *); 294 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, u_int16_t *); 295 296 297 /* 298 * GLOBAL DECLARATIONS 299 */ 300 301 /* 302 * Xmit-early table. 303 * 304 * To get better performance, we tell the chip to start packet 305 * transmission before the whole packet is copied to the chip. 306 * However, this can fail under load. When it fails, we back off 307 * to a safer setting for a little while. 308 * 309 * txcmd is the value of txcmd used to indicate when to start transmission. 310 * better is the next 'better' state in the table. 311 * better_count is the number of output packets before transition to the 312 * better state. 313 * worse is the next 'worse' state in the table. 314 * 315 * Transition to the next worse state happens automatically when a 316 * transmittion underrun occurs. 317 */ 318 struct cs_xmit_early { 319 u_int16_t txcmd; 320 int better; 321 int better_count; 322 int worse; 323 } cs_xmit_early_table[3] = { 324 { TX_CMD_START_381, 0, INT_MAX, 1, }, 325 { TX_CMD_START_1021, 0, 50000, 2, }, 326 { TX_CMD_START_ALL, 1, 5000, 2, }, 327 }; 328 329 int cs_default_media[] = { 330 IFM_ETHER|IFM_10_2, 331 IFM_ETHER|IFM_10_5, 332 IFM_ETHER|IFM_10_T, 333 IFM_ETHER|IFM_10_T|IFM_FDX, 334 }; 335 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 336 337 int 338 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media, 339 int nmedia, int defmedia) 340 { 341 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 342 const char *chipname, *medname; 343 u_int16_t reg; 344 int i; 345 346 /* Start out in IO mode */ 347 sc->sc_memorymode = FALSE; 348 349 /* make sure we're right */ 350 for (i = 0; i < 10000; i++) { 351 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 352 if (reg == EISA_NUM_CRYSTAL) { 353 break; 354 } 355 } 356 if (i == 10000) { 357 printf("%s: wrong id(0x%x)\n", sc->sc_dev.dv_xname, reg); 358 return 1; /* XXX should panic? */ 359 } 360 361 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 362 sc->sc_prodid = reg & PROD_ID_MASK; 363 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 364 365 switch (sc->sc_prodid) { 366 case PROD_ID_CS8900: 367 chipname = "CS8900"; 368 break; 369 case PROD_ID_CS8920: 370 chipname = "CS8920"; 371 break; 372 case PROD_ID_CS8920M: 373 chipname = "CS8920M"; 374 break; 375 default: 376 panic("cs_attach: impossible"); 377 } 378 379 /* 380 * the first thing to do is check that the mbuf cluster size is 381 * greater than the MTU for an ethernet frame. The code depends on 382 * this and to port this to a OS where this was not the case would 383 * not be straightforward. 384 * 385 * we need 1 byte spare because our 386 * packet read loop can overrun. 387 * and we may need pad bytes to align ip header. 388 */ 389 if (MCLBYTES < ETHER_MAX_LEN + 1 + 390 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 391 printf("%s: MCLBYTES too small for Ethernet frame\n", 392 sc->sc_dev.dv_xname); 393 return 1; 394 } 395 396 /* Start out not transmitting */ 397 sc->sc_txbusy = FALSE; 398 399 /* Set up early transmit threshhold */ 400 sc->sc_xe_ent = 0; 401 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 402 403 /* Initialize ifnet structure. */ 404 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 405 ifp->if_softc = sc; 406 ifp->if_start = cs_start_output; 407 ifp->if_init = cs_init; 408 ifp->if_ioctl = cs_ioctl; 409 ifp->if_stop = cs_stop; 410 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 411 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 412 IFF_BROADCAST | IFF_MULTICAST; 413 IFQ_SET_READY(&ifp->if_snd); 414 415 /* Initialize ifmedia structures. */ 416 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 417 418 if (media != NULL) { 419 for (i = 0; i < nmedia; i++) 420 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 421 ifmedia_set(&sc->sc_media, defmedia); 422 } else { 423 for (i = 0; i < cs_default_nmedia; i++) 424 ifmedia_add(&sc->sc_media, cs_default_media[i], 425 0, NULL); 426 cs_get_default_media(sc); 427 } 428 429 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 430 if (cs_scan_eeprom(sc) == CS_ERROR) { 431 /* failed to scan the eeprom, pretend there isn't an eeprom */ 432 printf("%s: unable to scan EEPROM\n", 433 sc->sc_dev.dv_xname); 434 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM; 435 } 436 } 437 438 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 439 /* Get parameters from the EEPROM */ 440 if (cs_get_params(sc) == CS_ERROR) { 441 printf("%s: unable to get settings from EEPROM\n", 442 sc->sc_dev.dv_xname); 443 return 1; 444 } 445 } 446 447 if (enaddr != NULL) 448 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 449 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 450 /* Get and store the Ethernet address */ 451 if (cs_get_enaddr(sc) == CS_ERROR) { 452 printf("%s: unable to read Ethernet address\n", 453 sc->sc_dev.dv_xname); 454 return 1; 455 } 456 } else { 457 #if 1 458 int j; 459 uint v; 460 461 for (j = 0; j < 6; j += 2) { 462 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j); 463 sc->sc_enaddr[j + 0] = v; 464 sc->sc_enaddr[j + 1] = v >> 8; 465 } 466 #else 467 printf("%s: no Ethernet address!\n", sc->sc_dev.dv_xname); 468 return 1; 469 #endif 470 } 471 472 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 473 case IFM_10_2: 474 medname = "BNC"; 475 break; 476 case IFM_10_5: 477 medname = "AUI"; 478 break; 479 case IFM_10_T: 480 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 481 medname = "UTP <full-duplex>"; 482 else 483 medname = "UTP"; 484 break; 485 default: 486 panic("cs_attach: impossible"); 487 } 488 printf("%s: %s rev. %c, address %s, media %s\n", sc->sc_dev.dv_xname, 489 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 490 medname); 491 492 if (sc->sc_dma_attach) 493 (*sc->sc_dma_attach)(sc); 494 495 sc->sc_sh = shutdownhook_establish(cs_reset, sc); 496 if (sc->sc_sh == NULL) { 497 printf("%s: unable to establish shutdownhook\n", 498 sc->sc_dev.dv_xname); 499 cs_detach(sc); 500 return 1; 501 } 502 503 /* Attach the interface. */ 504 if_attach(ifp); 505 ether_ifattach(ifp, sc->sc_enaddr); 506 507 #if NRND > 0 508 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 509 RND_TYPE_NET, 0); 510 #endif 511 sc->sc_cfgflags |= CFGFLG_ATTACHED; 512 513 /* Reset the chip */ 514 if (cs_reset_chip(sc) == CS_ERROR) { 515 printf("%s: reset failed\n", sc->sc_dev.dv_xname); 516 cs_detach(sc); 517 return 1; 518 } 519 520 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 521 cs_power, sc); 522 if (sc->sc_powerhook == 0) 523 printf("%s: warning: powerhook_establish failed\n", 524 sc->sc_dev.dv_xname); 525 526 return 0; 527 } 528 529 int 530 cs_detach(struct cs_softc *sc) 531 { 532 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 533 534 if (sc->sc_powerhook) { 535 powerhook_disestablish(sc->sc_powerhook); 536 sc->sc_powerhook = 0; 537 } 538 539 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 540 #if NRND > 0 541 rnd_detach_source(&sc->rnd_source); 542 #endif 543 ether_ifdetach(ifp); 544 if_detach(ifp); 545 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 546 } 547 548 if (sc->sc_sh != NULL) 549 shutdownhook_disestablish(sc->sc_sh); 550 551 #if 0 552 /* 553 * XXX not necessary 554 */ 555 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 556 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 557 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 558 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 559 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 560 } 561 #endif 562 563 return 0; 564 } 565 566 void 567 cs_get_default_media(struct cs_softc *sc) 568 { 569 u_int16_t adp_cfg, xmit_ctl; 570 571 if (cs_verify_eeprom(sc) == CS_ERROR) { 572 printf("%s: cs_get_default_media: EEPROM missing or bad\n", 573 sc->sc_dev.dv_xname); 574 goto fakeit; 575 } 576 577 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) { 578 printf("%s: unable to read adapter config from EEPROM\n", 579 sc->sc_dev.dv_xname); 580 goto fakeit; 581 } 582 583 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) { 584 printf("%s: unable to read transmit control from EEPROM\n", 585 sc->sc_dev.dv_xname); 586 goto fakeit; 587 } 588 589 switch (adp_cfg & ADPTR_CFG_MEDIA) { 590 case ADPTR_CFG_AUI: 591 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 592 break; 593 case ADPTR_CFG_10BASE2: 594 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 595 break; 596 case ADPTR_CFG_10BASET: 597 default: 598 if (xmit_ctl & XMIT_CTL_FDX) 599 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 600 else 601 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 602 break; 603 } 604 return; 605 606 fakeit: 607 printf("%s: WARNING: default media setting may be inaccurate\n", 608 sc->sc_dev.dv_xname); 609 /* XXX Arbitrary... */ 610 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 611 } 612 613 /* 614 * cs_scan_eeprom 615 * 616 * Attempt to take a complete copy of the eeprom into main memory. 617 * this will allow faster parsing of the eeprom data. 618 * 619 * Only tested against a 8920M's eeprom, but the data sheet for the 620 * 8920A indicates that is uses the same layout. 621 */ 622 int 623 cs_scan_eeprom(struct cs_softc *sc) 624 { 625 u_int16_t result; 626 int i; 627 int eeprom_size; 628 u_int8_t checksum = 0; 629 630 if (cs_verify_eeprom(sc) == CS_ERROR) { 631 printf("%s: cs_scan_params: EEPROM missing or bad\n", 632 sc->sc_dev.dv_xname); 633 return (CS_ERROR); 634 } 635 636 /* 637 * read the 0th word from the eeprom, it will tell us the length 638 * and if the eeprom is valid 639 */ 640 cs_read_eeprom(sc, 0, &result); 641 642 /* check the eeprom signature */ 643 if ((result & 0xE000) != 0xA000) { 644 /* empty eeprom */ 645 return (CS_ERROR); 646 } 647 648 /* 649 * take the eeprom size (note the read value doesn't include the header 650 * word) 651 */ 652 eeprom_size = (result & 0xff) + 2; 653 654 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK); 655 if (sc->eeprom_data == NULL) { 656 /* no memory, treat this as if there's no eeprom */ 657 return (CS_ERROR); 658 } 659 660 sc->eeprom_size = eeprom_size; 661 662 /* read the eeprom into the buffer, also calculate the checksum */ 663 for (i = 0; i < (eeprom_size >> 1); i++) { 664 cs_read_eeprom(sc, i, &(sc->eeprom_data[i])); 665 checksum += (sc->eeprom_data[i] & 0xff00) >> 8; 666 checksum += (sc->eeprom_data[i] & 0x00ff); 667 } 668 669 /* 670 * validate checksum calculation, the sum of all the bytes should be 0, 671 * as the high byte of the last word is the 2's complement of the 672 * sum to that point. 673 */ 674 if (checksum != 0) { 675 printf("%s: eeprom checksum failure\n", sc->sc_dev.dv_xname); 676 return (CS_ERROR); 677 } 678 679 return (CS_OK); 680 } 681 682 static int 683 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, u_int16_t *pValue) 684 { 685 int x, maxword; 686 687 /* Check that we have eeprom data */ 688 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2)) 689 return (CS_ERROR); 690 691 /* 692 * We only want to read the data words, the last word contains the 693 * checksum 694 */ 695 maxword = (sc->eeprom_size - 2) >> 1; 696 697 /* start 1 word in, as the first word is the length and signature */ 698 x = 1; 699 700 while ( x < (maxword)) { 701 u_int16_t header; 702 int group_size; 703 int offset; 704 int offset_max; 705 706 /* read in the group header word */ 707 header = sc->eeprom_data[x]; 708 x++; /* skip group header */ 709 710 /* 711 * size of group in words is in the top 4 bits, note that it 712 * is one less than the number of words 713 */ 714 group_size = header & 0xF000; 715 716 /* 717 * CS8900 Data sheet says this should be 0x01ff, 718 * but my cs8920 eeprom has higher offsets, 719 * perhaps the 8920 allows higher offsets, otherwise 720 * it's writing to places that it shouldn't 721 */ 722 /* work out the offsets this group covers */ 723 offset = header & 0x0FFF; 724 offset_max = offset + (group_size << 1); 725 726 /* check if the pkgpg we're after is in this group */ 727 if ((offset <= pktpg) && (pktpg <= offset_max)) { 728 /* the pkgpg value we want is in here */ 729 int eeprom_location; 730 731 eeprom_location = ((pktpg - offset) >> 1) ; 732 733 *pValue = sc->eeprom_data[x + eeprom_location]; 734 return (CS_OK); 735 } else { 736 /* skip this group (+ 1 for first entry) */ 737 x += group_size + 1; 738 } 739 } 740 741 /* 742 * if we've fallen out here then we don't have a value in the EEPROM 743 * for this pktpg so return an error 744 */ 745 return (CS_ERROR); 746 } 747 748 int 749 cs_get_params(struct cs_softc *sc) 750 { 751 u_int16_t isaConfig; 752 u_int16_t adapterConfig; 753 754 if (cs_verify_eeprom(sc) == CS_ERROR) { 755 printf("%s: cs_get_params: EEPROM missing or bad\n", 756 sc->sc_dev.dv_xname); 757 return (CS_ERROR); 758 } 759 760 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 761 /* Get ISA configuration from the EEPROM */ 762 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig) 763 == CS_ERROR) { 764 /* eeprom doesn't have this value, use data sheet default */ 765 isaConfig = 0x0017; 766 } 767 768 /* Get adapter configuration from the EEPROM */ 769 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, &adapterConfig) 770 == CS_ERROR) { 771 /* eeprom doesn't have this value, use data sheet default */ 772 adapterConfig = 0x0015; 773 } 774 775 /* Copy the USE_SA flag */ 776 if (isaConfig & BUS_CTL_USE_SA) 777 sc->sc_cfgflags |= CFGFLG_USE_SA; 778 779 /* Copy the IO Channel Ready flag */ 780 if (isaConfig & BUS_CTL_IOCHRDY) 781 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 782 783 /* Copy the DC/DC Polarity flag */ 784 if (adapterConfig & SELF_CTL_HCB1) 785 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 786 } else { 787 /* Get ISA configuration from the EEPROM */ 788 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR) 789 goto eeprom_bad; 790 791 /* Get adapter configuration from the EEPROM */ 792 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR) 793 goto eeprom_bad; 794 795 /* Copy the USE_SA flag */ 796 if (isaConfig & ISA_CFG_USE_SA) 797 sc->sc_cfgflags |= CFGFLG_USE_SA; 798 799 /* Copy the IO Channel Ready flag */ 800 if (isaConfig & ISA_CFG_IOCHRDY) 801 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 802 803 /* Copy the DC/DC Polarity flag */ 804 if (adapterConfig & ADPTR_CFG_DCDC_POL) 805 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 806 } 807 808 return (CS_OK); 809 eeprom_bad: 810 printf("%s: cs_get_params: unable to read from EEPROM\n", 811 sc->sc_dev.dv_xname); 812 return (CS_ERROR); 813 } 814 815 int 816 cs_get_enaddr(struct cs_softc *sc) 817 { 818 u_int16_t *myea; 819 820 if (cs_verify_eeprom(sc) == CS_ERROR) { 821 printf("%s: cs_get_enaddr: EEPROM missing or bad\n", 822 sc->sc_dev.dv_xname); 823 return (CS_ERROR); 824 } 825 826 myea = (u_int16_t *)sc->sc_enaddr; 827 828 /* Get Ethernet address from the EEPROM */ 829 /* XXX this will likely lose on a big-endian machine. -- cgd */ 830 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 831 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0]) 832 == CS_ERROR) 833 goto eeprom_bad; 834 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1]) 835 == CS_ERROR) 836 goto eeprom_bad; 837 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2]) 838 == CS_ERROR) 839 goto eeprom_bad; 840 } else { 841 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR) 842 goto eeprom_bad; 843 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR) 844 goto eeprom_bad; 845 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR) 846 goto eeprom_bad; 847 } 848 849 return (CS_OK); 850 851 eeprom_bad: 852 printf("%s: cs_get_enaddr: unable to read from EEPROM\n", 853 sc->sc_dev.dv_xname); 854 return (CS_ERROR); 855 } 856 857 int 858 cs_reset_chip(struct cs_softc *sc) 859 { 860 int intState; 861 int x; 862 863 /* Disable interrupts at the CPU so reset command is atomic */ 864 intState = splnet(); 865 866 /* 867 * We are now resetting the chip 868 * 869 * A spurious interrupt is generated by the chip when it is reset. This 870 * variable informs the interrupt handler to ignore this interrupt. 871 */ 872 sc->sc_resetting = TRUE; 873 874 /* Issue a reset command to the chip */ 875 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 876 877 /* Re-enable interrupts at the CPU */ 878 splx(intState); 879 880 /* The chip is always in IO mode after a reset */ 881 sc->sc_memorymode = FALSE; 882 883 /* If transmission was in progress, it is not now */ 884 sc->sc_txbusy = FALSE; 885 886 /* 887 * there was a delay(125); here, but it seems uneccesary 125 usec is 888 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 889 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 890 * should be sufficient. 891 */ 892 893 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 894 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 895 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 896 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 897 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 898 899 /* Wait until the EEPROM is not busy */ 900 for (x = 0; x < MAXLOOP; x++) { 901 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 902 break; 903 } 904 905 if (x == MAXLOOP) 906 return CS_ERROR; 907 908 /* Wait until initialization is done */ 909 for (x = 0; x < MAXLOOP; x++) { 910 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 911 break; 912 } 913 914 if (x == MAXLOOP) 915 return CS_ERROR; 916 917 /* Reset is no longer in progress */ 918 sc->sc_resetting = FALSE; 919 920 return CS_OK; 921 } 922 923 int 924 cs_verify_eeprom(struct cs_softc *sc) 925 { 926 u_int16_t self_status; 927 928 /* Verify that the EEPROM is present and OK */ 929 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST); 930 if (((self_status & SELF_ST_EEP_PRES) && 931 (self_status & SELF_ST_EEP_OK)) == 0) 932 return (CS_ERROR); 933 934 return (CS_OK); 935 } 936 937 int 938 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue) 939 { 940 int x; 941 942 /* Ensure that the EEPROM is not busy */ 943 for (x = 0; x < MAXLOOP; x++) { 944 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 945 SELF_ST_SI_BUSY)) 946 break; 947 } 948 949 if (x == MAXLOOP) 950 return (CS_ERROR); 951 952 /* Issue the command to read the offset within the EEPROM */ 953 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD, 954 offset | EEPROM_CMD_READ); 955 956 /* Wait until the command is completed */ 957 for (x = 0; x < MAXLOOP; x++) { 958 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 959 SELF_ST_SI_BUSY)) 960 break; 961 } 962 963 if (x == MAXLOOP) 964 return (CS_ERROR); 965 966 /* Get the EEPROM data from the EEPROM Data register */ 967 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA); 968 969 return (CS_OK); 970 } 971 972 void 973 cs_initChip(struct cs_softc *sc) 974 { 975 u_int16_t busCtl; 976 u_int16_t selfCtl; 977 u_int16_t v; 978 u_int16_t isaId; 979 int i; 980 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 981 982 /* Disable reception and transmission of frames */ 983 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 984 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 985 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 986 987 /* Disable interrupt at the chip */ 988 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 989 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 990 991 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 992 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 993 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 994 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 995 busCtl & ~BUS_CTL_IOCHRDY); 996 } else { 997 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 998 busCtl | BUS_CTL_IOCHRDY); 999 } 1000 1001 /* Set the Line Control register to match the media type */ 1002 if (media == IFM_10_T) 1003 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 1004 else 1005 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 1006 1007 /* 1008 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 1009 * enable the DC/DC converter 1010 */ 1011 selfCtl = SELF_CTL_HC1E; 1012 1013 /* If the media type is 10Base2 */ 1014 if (media == IFM_10_2) { 1015 /* 1016 * Enable the DC/DC converter if it has a low enable. 1017 */ 1018 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 1019 /* 1020 * Set the HCB1 bit, which causes the HC1 pin to go 1021 * low. 1022 */ 1023 selfCtl |= SELF_CTL_HCB1; 1024 } else { /* Media type is 10BaseT or AUI */ 1025 /* 1026 * Disable the DC/DC converter if it has a high enable. 1027 */ 1028 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 1029 /* 1030 * Set the HCB1 bit, which causes the HC1 pin to go 1031 * low. 1032 */ 1033 selfCtl |= SELF_CTL_HCB1; 1034 } 1035 } 1036 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 1037 1038 /* enable normal link pulse */ 1039 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 1040 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 1041 1042 /* Enable full-duplex, if appropriate */ 1043 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 1044 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 1045 1046 /* RX_CTL set in cs_set_ladr_filt(), below */ 1047 1048 /* enable all transmission interrupts */ 1049 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 1050 1051 /* Accept all receive interrupts */ 1052 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 1053 1054 /* 1055 * Configure Operational Modes 1056 * 1057 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 1058 * a better way to do it because the card has a counter which can be 1059 * read to update the RX_MISS counter. This saves many interrupts. 1060 * 1061 * I have turned on the tx and rx overflow interrupts to counter using 1062 * the receive miss interrupt. This is a better estimate of errors 1063 * and requires lower system overhead. 1064 */ 1065 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 1066 BUF_CFG_RX_DMA_IE); 1067 1068 if (sc->sc_dma_chipinit) 1069 (*sc->sc_dma_chipinit)(sc); 1070 1071 /* If memory mode is enabled */ 1072 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 1073 /* If external logic is present for address decoding */ 1074 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 1075 /* 1076 * Program the external logic to decode address bits 1077 * SA20-SA23 1078 */ 1079 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 1080 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 1081 EEPROM_CMD_ELSEL); 1082 } 1083 1084 /* 1085 * Write the packet page base physical address to the memory 1086 * base register. 1087 */ 1088 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 1089 sc->sc_pktpgaddr & 0xFFFF); 1090 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 1091 sc->sc_pktpgaddr >> 16); 1092 busCtl = BUS_CTL_MEM_MODE; 1093 1094 /* tell the chip to read the addresses off the SA pins */ 1095 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 1096 busCtl |= BUS_CTL_USE_SA; 1097 } 1098 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1099 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 1100 1101 /* We are in memory mode now! */ 1102 sc->sc_memorymode = TRUE; 1103 1104 /* 1105 * wait here (10ms) for the chip to swap over. this is the 1106 * maximum time that this could take. 1107 */ 1108 delay(10000); 1109 1110 /* Verify that we can read from the chip */ 1111 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 1112 1113 /* 1114 * As a last minute sanity check before actually using mapped 1115 * memory we verify that we can read the isa number from the 1116 * chip in memory mode. 1117 */ 1118 if (isaId != EISA_NUM_CRYSTAL) { 1119 printf("%s: failed to enable memory mode\n", 1120 sc->sc_dev.dv_xname); 1121 sc->sc_memorymode = FALSE; 1122 } else { 1123 /* 1124 * we are in memory mode so if we aren't using DMA, 1125 * then program the chip to interrupt early. 1126 */ 1127 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 1128 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 1129 BUF_CFG_RX_DEST_IE | 1130 BUF_CFG_RX_MISS_OVER_IE | 1131 BUF_CFG_TX_COL_OVER_IE); 1132 } 1133 } 1134 1135 } 1136 1137 /* Put Ethernet address into the Individual Address register */ 1138 for (i = 0; i < 6; i += 2) { 1139 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8; 1140 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v); 1141 } 1142 1143 if (sc->sc_irq != -1) { 1144 /* Set the interrupt level in the chip */ 1145 if (sc->sc_prodid == PROD_ID_CS8900) { 1146 if (sc->sc_irq == 5) { 1147 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 1148 } else { 1149 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 1150 } 1151 } 1152 else { /* CS8920 */ 1153 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 1154 } 1155 } 1156 1157 /* write the multicast mask to the address filter register */ 1158 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1159 1160 /* Enable reception and transmission of frames */ 1161 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 1162 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 1163 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 1164 1165 /* Enable interrupt at the chip */ 1166 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1167 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 1168 } 1169 1170 int 1171 cs_init(struct ifnet *ifp) 1172 { 1173 int intState; 1174 int error = CS_OK; 1175 struct cs_softc *sc = ifp->if_softc; 1176 1177 if (cs_enable(sc)) 1178 goto out; 1179 1180 cs_stop(ifp, 0); 1181 1182 intState = splnet(); 1183 1184 #if 0 1185 /* Mark the interface as down */ 1186 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 1187 #endif 1188 1189 #ifdef CS_DEBUG 1190 /* Enable debugging */ 1191 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 1192 #endif 1193 1194 /* Reset the chip */ 1195 if ((error = cs_reset_chip(sc)) == CS_OK) { 1196 /* Initialize the chip */ 1197 cs_initChip(sc); 1198 1199 /* Mark the interface as running */ 1200 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1201 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1202 sc->sc_ethercom.ec_if.if_timer = 0; 1203 1204 /* Assume we have carrier until we are told otherwise. */ 1205 sc->sc_carrier = 1; 1206 } else { 1207 printf("%s: unable to reset chip\n", sc->sc_dev.dv_xname); 1208 } 1209 1210 splx(intState); 1211 out: 1212 if (error == CS_OK) 1213 return 0; 1214 return EIO; 1215 } 1216 1217 void 1218 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1219 { 1220 struct ifnet *ifp = &ec->ec_if; 1221 struct ether_multi *enm; 1222 struct ether_multistep step; 1223 u_int16_t af[4]; 1224 u_int16_t port, mask, index; 1225 1226 /* 1227 * Set up multicast address filter by passing all multicast addresses 1228 * through a crc generator, and then using the high order 6 bits as an 1229 * index into the 64 bit logical address filter. The high order bit 1230 * selects the word, while the rest of the bits select the bit within 1231 * the word. 1232 */ 1233 if (ifp->if_flags & IFF_PROMISC) { 1234 /* accept all valid frames. */ 1235 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1236 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1237 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1238 ifp->if_flags |= IFF_ALLMULTI; 1239 return; 1240 } 1241 1242 /* 1243 * accept frames if a. crc valid, b. individual address match c. 1244 * broadcast address,and d. multicast addresses matched in the hash 1245 * filter 1246 */ 1247 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1248 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1249 1250 1251 /* 1252 * start off with all multicast flag clear, set it if we need to 1253 * later, otherwise we will leave it. 1254 */ 1255 ifp->if_flags &= ~IFF_ALLMULTI; 1256 af[0] = af[1] = af[2] = af[3] = 0x0000; 1257 1258 /* 1259 * Loop through all the multicast addresses unless we get a range of 1260 * addresses, in which case we will just accept all packets. 1261 * Justification for this is given in the next comment. 1262 */ 1263 ETHER_FIRST_MULTI(step, ec, enm); 1264 while (enm != NULL) { 1265 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1266 sizeof enm->enm_addrlo)) { 1267 /* 1268 * We must listen to a range of multicast addresses. 1269 * For now, just accept all multicasts, rather than 1270 * trying to set only those filter bits needed to match 1271 * the range. (At this time, the only use of address 1272 * ranges is for IP multicast routing, for which the 1273 * range is big enough to require all bits set.) 1274 */ 1275 ifp->if_flags |= IFF_ALLMULTI; 1276 af[0] = af[1] = af[2] = af[3] = 0xffff; 1277 break; 1278 } else { 1279 /* 1280 * we have got an individual address so just set that 1281 * bit. 1282 */ 1283 index = cs_hash_index(enm->enm_addrlo); 1284 1285 /* Set the bit the Logical address filter. */ 1286 port = (u_int16_t) (index >> 4); 1287 mask = (u_int16_t) (1 << (index & 0xf)); 1288 af[port] |= mask; 1289 1290 ETHER_NEXT_MULTI(step, enm); 1291 } 1292 } 1293 1294 /* now program the chip with the addresses */ 1295 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1296 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1297 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1298 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1299 return; 1300 } 1301 1302 u_int16_t 1303 cs_hash_index(char *addr) 1304 { 1305 uint32_t crc; 1306 uint16_t hash_code; 1307 1308 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1309 1310 hash_code = crc >> 26; 1311 return (hash_code); 1312 } 1313 1314 void 1315 cs_reset(void *arg) 1316 { 1317 struct cs_softc *sc = arg; 1318 1319 /* Mark the interface as down */ 1320 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1321 1322 /* Reset the chip */ 1323 cs_reset_chip(sc); 1324 } 1325 1326 int 1327 cs_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1328 { 1329 struct cs_softc *sc = ifp->if_softc; 1330 struct ifreq *ifr = (struct ifreq *) data; 1331 int state; 1332 int result; 1333 1334 state = splnet(); 1335 1336 result = 0; /* only set if something goes wrong */ 1337 1338 switch (cmd) { 1339 case SIOCGIFMEDIA: 1340 case SIOCSIFMEDIA: 1341 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1342 break; 1343 1344 default: 1345 result = ether_ioctl(ifp, cmd, data); 1346 if (result == ENETRESET) { 1347 if (ifp->if_flags & IFF_RUNNING) { 1348 /* 1349 * Multicast list has changed. Set the 1350 * hardware filter accordingly. 1351 */ 1352 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1353 } 1354 result = 0; 1355 } 1356 break; 1357 } 1358 1359 splx(state); 1360 1361 return result; 1362 } 1363 1364 int 1365 cs_mediachange(struct ifnet *ifp) 1366 { 1367 1368 /* 1369 * Current media is already set up. Just reset the interface 1370 * to let the new value take hold. 1371 */ 1372 cs_init(ifp); 1373 return (0); 1374 } 1375 1376 void 1377 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1378 { 1379 struct cs_softc *sc = ifp->if_softc; 1380 1381 /* 1382 * The currently selected media is always the active media. 1383 */ 1384 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1385 1386 if (ifp->if_flags & IFF_UP) { 1387 /* Interface up, status is valid. */ 1388 ifmr->ifm_status = IFM_AVALID | 1389 (sc->sc_carrier ? IFM_ACTIVE : 0); 1390 } 1391 else ifmr->ifm_status = 0; 1392 } 1393 1394 int 1395 cs_intr(void *arg) 1396 { 1397 struct cs_softc *sc = arg; 1398 u_int16_t Event; 1399 #if NRND > 0 1400 u_int16_t rndEvent; 1401 #endif 1402 1403 /*printf("cs_intr %p\n", sc);*/ 1404 /* Ignore any interrupts that happen while the chip is being reset */ 1405 if (sc->sc_resetting) { 1406 printf("%s: cs_intr: reset in progress\n", 1407 sc->sc_dev.dv_xname); 1408 return 1; 1409 } 1410 1411 /* Read an event from the Interrupt Status Queue */ 1412 if (sc->sc_memorymode) 1413 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1414 else 1415 Event = CS_READ_PORT(sc, PORT_ISQ); 1416 1417 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1418 return 0; /* not ours */ 1419 1420 #if NRND > 0 1421 rndEvent = Event; 1422 #endif 1423 1424 /* Process all the events in the Interrupt Status Queue */ 1425 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1426 /* Dispatch to an event handler based on the register number */ 1427 switch (Event & REG_NUM_MASK) { 1428 case REG_NUM_RX_EVENT: 1429 cs_receive_event(sc, Event); 1430 break; 1431 case REG_NUM_TX_EVENT: 1432 cs_transmit_event(sc, Event); 1433 break; 1434 case REG_NUM_BUF_EVENT: 1435 cs_buffer_event(sc, Event); 1436 break; 1437 case REG_NUM_TX_COL: 1438 case REG_NUM_RX_MISS: 1439 cs_counter_event(sc, Event); 1440 break; 1441 default: 1442 printf("%s: unknown interrupt event 0x%x\n", 1443 sc->sc_dev.dv_xname, Event); 1444 break; 1445 } 1446 1447 /* Read another event from the Interrupt Status Queue */ 1448 if (sc->sc_memorymode) 1449 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1450 else 1451 Event = CS_READ_PORT(sc, PORT_ISQ); 1452 } 1453 1454 /* have handled the interrupt */ 1455 #if NRND > 0 1456 rnd_add_uint32(&sc->rnd_source, rndEvent); 1457 #endif 1458 return 1; 1459 } 1460 1461 void 1462 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent) 1463 { 1464 struct ifnet *ifp; 1465 u_int16_t errorCount; 1466 1467 ifp = &sc->sc_ethercom.ec_if; 1468 1469 switch (cntEvent & REG_NUM_MASK) { 1470 case REG_NUM_TX_COL: 1471 /* 1472 * the count should be read before an overflow occurs. 1473 */ 1474 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1475 /* 1476 * the tramsit event routine always checks the number of 1477 * collisions for any packet so we don't increment any 1478 * counters here, as they should already have been 1479 * considered. 1480 */ 1481 break; 1482 case REG_NUM_RX_MISS: 1483 /* 1484 * the count should be read before an overflow occurs. 1485 */ 1486 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1487 /* 1488 * Increment the input error count, the first 6bits are the 1489 * register id. 1490 */ 1491 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1492 break; 1493 default: 1494 /* do nothing */ 1495 break; 1496 } 1497 } 1498 1499 void 1500 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent) 1501 { 1502 1503 /* 1504 * multiple events can be in the buffer event register at one time so 1505 * a standard switch statement will not suffice, here every event 1506 * must be checked. 1507 */ 1508 1509 /* 1510 * if 128 bits have been rxed by the time we get here, the dest event 1511 * will be cleared and 128 event will be set. 1512 */ 1513 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1514 cs_process_rx_early(sc); 1515 } 1516 1517 if (bufEvent & BUF_EVENT_RX_DMA) { 1518 /* process the receive data */ 1519 if (sc->sc_dma_process_rx) 1520 (*sc->sc_dma_process_rx)(sc); 1521 else 1522 /* should panic? */ 1523 printf("%s: unexpected DMA event\n", sc->sc_dev.dv_xname); 1524 } 1525 1526 if (bufEvent & BUF_EVENT_TX_UNDR) { 1527 #if 0 1528 /* 1529 * This can happen occasionally, and it's not worth worrying 1530 * about. 1531 */ 1532 printf("%s: transmit underrun (%d -> %d)\n", 1533 sc->sc_dev.dv_xname, sc->sc_xe_ent, 1534 cs_xmit_early_table[sc->sc_xe_ent].worse); 1535 #endif 1536 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1537 sc->sc_xe_togo = 1538 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1539 1540 /* had an underrun, transmit is finished */ 1541 sc->sc_txbusy = FALSE; 1542 } 1543 1544 if (bufEvent & BUF_EVENT_SW_INT) { 1545 printf("%s: software initiated interrupt\n", 1546 sc->sc_dev.dv_xname); 1547 } 1548 } 1549 1550 void 1551 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent) 1552 { 1553 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1554 1555 /* If there were any errors transmitting this frame */ 1556 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1557 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1558 /* Increment the output error count */ 1559 ifp->if_oerrors++; 1560 1561 /* Note carrier loss. */ 1562 if (txEvent & TX_EVENT_LOSS_CRS) 1563 sc->sc_carrier = 0; 1564 1565 /* If debugging is enabled then log error messages */ 1566 if (ifp->if_flags & IFF_DEBUG) { 1567 if (txEvent & TX_EVENT_LOSS_CRS) { 1568 printf("%s: lost carrier\n", 1569 sc->sc_dev.dv_xname); 1570 } 1571 if (txEvent & TX_EVENT_SQE_ERR) { 1572 printf("%s: SQE error\n", 1573 sc->sc_dev.dv_xname); 1574 } 1575 if (txEvent & TX_EVENT_OUT_WIN) { 1576 printf("%s: out-of-window collision\n", 1577 sc->sc_dev.dv_xname); 1578 } 1579 if (txEvent & TX_EVENT_JABBER) { 1580 printf("%s: jabber\n", sc->sc_dev.dv_xname); 1581 } 1582 if (txEvent & TX_EVENT_16_COLL) { 1583 printf("%s: 16 collisions\n", 1584 sc->sc_dev.dv_xname); 1585 } 1586 } 1587 } 1588 else { 1589 /* Transmission successful, carrier is up. */ 1590 sc->sc_carrier = 1; 1591 #ifdef SHARK 1592 ledNetActive(); 1593 #endif 1594 } 1595 1596 /* Add the number of collisions for this frame */ 1597 if (txEvent & TX_EVENT_16_COLL) { 1598 ifp->if_collisions += 16; 1599 } else { 1600 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1601 } 1602 1603 ifp->if_opackets++; 1604 1605 /* Transmission is no longer in progress */ 1606 sc->sc_txbusy = FALSE; 1607 1608 /* If there is more to transmit */ 1609 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1610 /* Start the next transmission */ 1611 cs_start_output(ifp); 1612 } 1613 } 1614 1615 void 1616 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent) 1617 { 1618 1619 if (rxEvent & RX_EVENT_RUNT) 1620 printf("%s: runt\n", sc->sc_dev.dv_xname); 1621 1622 if (rxEvent & RX_EVENT_X_DATA) 1623 printf("%s: extra data\n", sc->sc_dev.dv_xname); 1624 1625 if (rxEvent & RX_EVENT_CRC_ERR) { 1626 if (rxEvent & RX_EVENT_DRIBBLE) 1627 printf("%s: alignment error\n", sc->sc_dev.dv_xname); 1628 else 1629 printf("%s: CRC error\n", sc->sc_dev.dv_xname); 1630 } else { 1631 if (rxEvent & RX_EVENT_DRIBBLE) 1632 printf("%s: dribble bits\n", sc->sc_dev.dv_xname); 1633 } 1634 } 1635 1636 void 1637 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent) 1638 { 1639 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1640 1641 /* If the frame was not received OK */ 1642 if (!(rxEvent & RX_EVENT_RX_OK)) { 1643 /* Increment the input error count */ 1644 ifp->if_ierrors++; 1645 1646 /* 1647 * If debugging is enabled then log error messages. 1648 */ 1649 if (ifp->if_flags & IFF_DEBUG) { 1650 if (rxEvent != REG_NUM_RX_EVENT) { 1651 cs_print_rx_errors(sc, rxEvent); 1652 1653 /* 1654 * Must read the length of all received 1655 * frames 1656 */ 1657 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1658 1659 /* Skip the received frame */ 1660 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1661 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1662 RX_CFG_SKIP); 1663 } else { 1664 printf("%s: implied skip\n", 1665 sc->sc_dev.dv_xname); 1666 } 1667 } 1668 } else { 1669 /* 1670 * process the received frame and pass it up to the upper 1671 * layers. 1672 */ 1673 cs_process_receive(sc); 1674 } 1675 } 1676 1677 void 1678 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1679 { 1680 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1681 1682 ifp->if_ipackets++; 1683 1684 #if NBPFILTER > 0 1685 /* 1686 * Check if there's a BPF listener on this interface. 1687 * If so, hand off the raw packet to BPF. 1688 */ 1689 if (ifp->if_bpf) 1690 bpf_mtap(ifp->if_bpf, m); 1691 #endif 1692 1693 /* Pass the packet up. */ 1694 (*ifp->if_input)(ifp, m); 1695 } 1696 1697 void 1698 cs_process_receive(struct cs_softc *sc) 1699 { 1700 struct ifnet *ifp; 1701 struct mbuf *m; 1702 int totlen; 1703 u_int16_t *pBuff, *pBuffLimit; 1704 int pad; 1705 unsigned int frameOffset = 0; /* XXX: gcc */ 1706 1707 #ifdef SHARK 1708 ledNetActive(); 1709 #endif 1710 1711 ifp = &sc->sc_ethercom.ec_if; 1712 1713 /* Received a packet; carrier is up. */ 1714 sc->sc_carrier = 1; 1715 1716 if (sc->sc_memorymode) { 1717 /* Initialize the frame offset */ 1718 frameOffset = PKTPG_RX_LENGTH; 1719 1720 /* Get the length of the received frame */ 1721 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1722 frameOffset += 2; 1723 } 1724 else { 1725 /* drop status */ 1726 CS_READ_PORT(sc, PORT_RXTX_DATA); 1727 1728 /* Get the length of the received frame */ 1729 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1730 } 1731 1732 if (totlen > ETHER_MAX_LEN) { 1733 printf("%s: invalid packet length %d\n", 1734 sc->sc_dev.dv_xname, totlen); 1735 1736 /* skip the received frame */ 1737 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1738 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1739 return; 1740 } 1741 1742 MGETHDR(m, M_DONTWAIT, MT_DATA); 1743 if (m == 0) { 1744 printf("%s: cs_process_receive: unable to allocate mbuf\n", 1745 sc->sc_dev.dv_xname); 1746 ifp->if_ierrors++; 1747 /* 1748 * couldn't allocate an mbuf so things are not good, may as 1749 * well drop the packet I think. 1750 * 1751 * have already read the length so we should be right to skip 1752 * the packet. 1753 */ 1754 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1755 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1756 return; 1757 } 1758 m->m_pkthdr.rcvif = ifp; 1759 m->m_pkthdr.len = totlen; 1760 1761 /* number of bytes to align ip header on word boundary for ipintr */ 1762 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1763 1764 /* 1765 * alloc mbuf cluster if we need. 1766 * we need 1 byte spare because following 1767 * packet read loop can overrun. 1768 */ 1769 if (totlen + pad + 1 > MHLEN) { 1770 MCLGET(m, M_DONTWAIT); 1771 if ((m->m_flags & M_EXT) == 0) { 1772 /* couldn't allocate an mbuf cluster */ 1773 printf("%s: cs_process_receive: unable to allocate a cluster\n", 1774 sc->sc_dev.dv_xname); 1775 m_freem(m); 1776 1777 /* skip the received frame */ 1778 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1779 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1780 return; 1781 } 1782 } 1783 1784 /* align ip header on word boundary for ipintr */ 1785 m->m_data += pad; 1786 1787 m->m_len = totlen; 1788 pBuff = mtod(m, u_int16_t *); 1789 1790 /* now read the data from the chip */ 1791 if (sc->sc_memorymode) { 1792 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1793 while (pBuff < pBuffLimit) { 1794 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1795 frameOffset += 2; 1796 } 1797 } 1798 else { 1799 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1); 1800 } 1801 1802 cs_ether_input(sc, m); 1803 } 1804 1805 void 1806 cs_process_rx_early(struct cs_softc *sc) 1807 { 1808 struct ifnet *ifp; 1809 struct mbuf *m; 1810 u_int16_t frameCount, oldFrameCount; 1811 u_int16_t rxEvent; 1812 u_int16_t *pBuff; 1813 int pad; 1814 unsigned int frameOffset; 1815 1816 1817 ifp = &sc->sc_ethercom.ec_if; 1818 1819 /* Initialize the frame offset */ 1820 frameOffset = PKTPG_RX_FRAME; 1821 frameCount = 0; 1822 1823 MGETHDR(m, M_DONTWAIT, MT_DATA); 1824 if (m == 0) { 1825 printf("%s: cs_process_rx_early: unable to allocate mbuf\n", 1826 sc->sc_dev.dv_xname); 1827 ifp->if_ierrors++; 1828 /* 1829 * couldn't allocate an mbuf so things are not good, may as 1830 * well drop the packet I think. 1831 * 1832 * have already read the length so we should be right to skip 1833 * the packet. 1834 */ 1835 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1836 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1837 return; 1838 } 1839 m->m_pkthdr.rcvif = ifp; 1840 /* 1841 * save processing by always using a mbuf cluster, guaranteed to fit 1842 * packet 1843 */ 1844 MCLGET(m, M_DONTWAIT); 1845 if ((m->m_flags & M_EXT) == 0) { 1846 /* couldn't allocate an mbuf cluster */ 1847 printf("%s: cs_process_rx_early: unable to allocate a cluster\n", 1848 sc->sc_dev.dv_xname); 1849 m_freem(m); 1850 /* skip the frame */ 1851 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1852 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1853 return; 1854 } 1855 1856 /* align ip header on word boundary for ipintr */ 1857 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1858 m->m_data += pad; 1859 1860 /* set up the buffer pointer to point to the data area */ 1861 pBuff = mtod(m, u_int16_t *); 1862 1863 /* 1864 * now read the frame byte counter until we have finished reading the 1865 * frame 1866 */ 1867 oldFrameCount = 0; 1868 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1869 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1870 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1871 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1872 frameOffset += 2; 1873 } 1874 1875 /* read the new count from the chip */ 1876 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1877 } 1878 1879 /* update the mbuf counts */ 1880 m->m_len = oldFrameCount; 1881 m->m_pkthdr.len = oldFrameCount; 1882 1883 /* now check the Rx Event register */ 1884 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1885 1886 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1887 /* 1888 * do an implied skip, it seems to be more reliable than a 1889 * forced skip. 1890 */ 1891 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1892 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1893 1894 /* 1895 * now read the RX_EVENT register to perform an implied skip. 1896 */ 1897 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1898 1899 cs_ether_input(sc, m); 1900 } else { 1901 m_freem(m); 1902 ifp->if_ierrors++; 1903 } 1904 } 1905 1906 void 1907 cs_start_output(struct ifnet *ifp) 1908 { 1909 struct cs_softc *sc; 1910 struct mbuf *pMbuf; 1911 struct mbuf *pMbufChain; 1912 u_int16_t BusStatus; 1913 u_int16_t Length; 1914 int txLoop = 0; 1915 int dropout = 0; 1916 1917 sc = ifp->if_softc; 1918 1919 /* check that the interface is up and running */ 1920 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1921 return; 1922 } 1923 1924 /* Don't interrupt a transmission in progress */ 1925 if (sc->sc_txbusy) { 1926 return; 1927 } 1928 1929 /* this loop will only run through once if transmission is successful */ 1930 /* 1931 * While there are packets to transmit and a transmit is not in 1932 * progress 1933 */ 1934 while (sc->sc_txbusy == 0 && dropout == 0) { 1935 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1936 if (pMbufChain == NULL) 1937 break; 1938 1939 #if NBPFILTER > 0 1940 /* 1941 * If BPF is listening on this interface, let it see the packet 1942 * before we commit it to the wire. 1943 */ 1944 if (ifp->if_bpf) 1945 bpf_mtap(ifp->if_bpf, pMbufChain); 1946 #endif 1947 1948 /* Find the total length of the data to transmit */ 1949 Length = 0; 1950 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1951 Length += pMbuf->m_len; 1952 1953 do { 1954 /* 1955 * Request that the transmit be started after all 1956 * data has been copied 1957 * 1958 * In IO mode must write to the IO port not the packet 1959 * page address 1960 * 1961 * If this is changed to start transmission after a 1962 * small amount of data has been copied you tend to 1963 * get packet missed errors i think because the ISA 1964 * bus is too slow. Or possibly the copy routine is 1965 * not streamlined enough. 1966 */ 1967 if (sc->sc_memorymode) { 1968 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1969 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1970 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1971 } 1972 else { 1973 CS_WRITE_PORT(sc, PORT_TX_CMD, 1974 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1975 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1976 } 1977 1978 /* 1979 * Adjust early-transmit machinery. 1980 */ 1981 if (--sc->sc_xe_togo == 0) { 1982 sc->sc_xe_ent = 1983 cs_xmit_early_table[sc->sc_xe_ent].better; 1984 sc->sc_xe_togo = 1985 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1986 } 1987 /* 1988 * Read the BusStatus register which indicates 1989 * success of the request 1990 */ 1991 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1992 1993 /* 1994 * If there was an error in the transmit bid free the 1995 * mbuf and go on. This is presuming that mbuf is 1996 * corrupt. 1997 */ 1998 if (BusStatus & BUS_ST_TX_BID_ERR) { 1999 printf("%s: transmit bid error (too big)", 2000 sc->sc_dev.dv_xname); 2001 2002 /* Discard the bad mbuf chain */ 2003 m_freem(pMbufChain); 2004 sc->sc_ethercom.ec_if.if_oerrors++; 2005 2006 /* Loop up to transmit the next chain */ 2007 txLoop = 0; 2008 } else { 2009 if (BusStatus & BUS_ST_RDY4TXNOW) { 2010 /* 2011 * The chip is ready for transmission 2012 * now 2013 */ 2014 /* 2015 * Copy the frame to the chip to 2016 * start transmission 2017 */ 2018 cs_copy_tx_frame(sc, pMbufChain); 2019 2020 /* Free the mbuf chain */ 2021 m_freem(pMbufChain); 2022 2023 /* Transmission is now in progress */ 2024 sc->sc_txbusy = TRUE; 2025 txLoop = 0; 2026 } else { 2027 /* 2028 * if we get here we want to try 2029 * again with the same mbuf, until 2030 * the chip lets us transmit. 2031 */ 2032 txLoop++; 2033 if (txLoop > CS_OUTPUT_LOOP_MAX) { 2034 /* Free the mbuf chain */ 2035 m_freem(pMbufChain); 2036 /* 2037 * Transmission is not in 2038 * progress 2039 */ 2040 sc->sc_txbusy = FALSE; 2041 /* 2042 * Increment the output error 2043 * count 2044 */ 2045 ifp->if_oerrors++; 2046 /* 2047 * exit the routine and drop 2048 * the packet. 2049 */ 2050 txLoop = 0; 2051 dropout = 1; 2052 } 2053 } 2054 } 2055 } while (txLoop); 2056 } 2057 } 2058 2059 void 2060 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 2061 { 2062 struct mbuf *m; 2063 int len, leftover, frameoff; 2064 u_int16_t dbuf; 2065 u_int8_t *p; 2066 #ifdef DIAGNOSTIC 2067 u_int8_t *lim; 2068 #endif 2069 2070 /* Initialize frame pointer and data port address */ 2071 frameoff = PKTPG_TX_FRAME; 2072 2073 /* start out with no leftover data */ 2074 leftover = 0; 2075 dbuf = 0; 2076 2077 /* Process the chain of mbufs */ 2078 for (m = m0; m != NULL; m = m->m_next) { 2079 /* 2080 * Process all of the data in a single mbuf. 2081 */ 2082 p = mtod(m, u_int8_t *); 2083 len = m->m_len; 2084 #ifdef DIAGNOSTIC 2085 lim = p + len; 2086 #endif 2087 2088 while (len > 0) { 2089 if (leftover) { 2090 /* 2091 * Data left over (from mbuf or realignment). 2092 * Buffer the next byte, and write it and 2093 * the leftover data out. 2094 */ 2095 dbuf |= *p++ << 8; 2096 len--; 2097 if (sc->sc_memorymode) { 2098 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2099 frameoff += 2; 2100 } 2101 else { 2102 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2103 } 2104 leftover = 0; 2105 } else if ((long) p & 1) { 2106 /* 2107 * Misaligned data. Buffer the next byte. 2108 */ 2109 dbuf = *p++; 2110 len--; 2111 leftover = 1; 2112 } else { 2113 /* 2114 * Aligned data. This is the case we like. 2115 * 2116 * Write-region out as much as we can, then 2117 * buffer the remaining byte (if any). 2118 */ 2119 leftover = len & 1; 2120 len &= ~1; 2121 if (sc->sc_memorymode) { 2122 MEM_WRITE_REGION_2(sc, frameoff, 2123 (u_int16_t *) p, len >> 1); 2124 frameoff += len; 2125 } 2126 else { 2127 IO_WRITE_MULTI_2(sc, 2128 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 2129 } 2130 p += len; 2131 2132 if (leftover) 2133 dbuf = *p++; 2134 len = 0; 2135 } 2136 } 2137 if (len < 0) 2138 panic("cs_copy_tx_frame: negative len"); 2139 #ifdef DIAGNOSTIC 2140 if (p != lim) 2141 panic("cs_copy_tx_frame: p != lim"); 2142 #endif 2143 } 2144 if (leftover) { 2145 if (sc->sc_memorymode) { 2146 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2147 } 2148 else { 2149 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2150 } 2151 } 2152 } 2153 2154 static int 2155 cs_enable(struct cs_softc *sc) 2156 { 2157 2158 if (CS_IS_ENABLED(sc) == 0) { 2159 if (sc->sc_enable != NULL) { 2160 int error; 2161 2162 error = (*sc->sc_enable)(sc); 2163 if (error) 2164 return (error); 2165 } 2166 sc->sc_cfgflags |= CFGFLG_ENABLED; 2167 } 2168 2169 return (0); 2170 } 2171 2172 static void 2173 cs_disable(struct cs_softc *sc) 2174 { 2175 2176 if (CS_IS_ENABLED(sc)) { 2177 if (sc->sc_disable != NULL) 2178 (*sc->sc_disable)(sc); 2179 2180 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2181 } 2182 } 2183 2184 static void 2185 cs_stop(struct ifnet *ifp, int disable) 2186 { 2187 struct cs_softc *sc = ifp->if_softc; 2188 2189 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2190 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2191 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2192 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2193 2194 if (disable) { 2195 cs_disable(sc); 2196 } 2197 2198 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2199 } 2200 2201 int 2202 cs_activate(struct device *self, enum devact act) 2203 { 2204 struct cs_softc *sc = (void *)self; 2205 int s, error = 0; 2206 2207 s = splnet(); 2208 switch (act) { 2209 case DVACT_ACTIVATE: 2210 error = EOPNOTSUPP; 2211 break; 2212 2213 case DVACT_DEACTIVATE: 2214 if_deactivate(&sc->sc_ethercom.ec_if); 2215 break; 2216 } 2217 splx(s); 2218 2219 return error; 2220 } 2221 2222 static void 2223 cs_power(int why, void *arg) 2224 { 2225 struct cs_softc *sc = arg; 2226 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2227 int s; 2228 2229 s = splnet(); 2230 switch (why) { 2231 case PWR_STANDBY: 2232 case PWR_SUSPEND: 2233 cs_stop(ifp, 0); 2234 break; 2235 case PWR_RESUME: 2236 if (ifp->if_flags & IFF_UP) { 2237 cs_init(ifp); 2238 } 2239 break; 2240 case PWR_SOFTSUSPEND: 2241 case PWR_SOFTSTANDBY: 2242 case PWR_SOFTRESUME: 2243 break; 2244 } 2245 splx(s); 2246 }
Cache object: 0266b05196d7268b7609d9a67b42dd22
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