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sys/dev/ic/cs89x0.c
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1 /* $NetBSD: cs89x0.c,v 1.23 2008/04/08 12:07:25 cegger Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher Gilbert 5 * All rights reserved. 6 * 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. The name of the company nor the name of the author may be used to 13 * endorse or promote products derived from this software without specific 14 * prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright 1997 31 * Digital Equipment Corporation. All rights reserved. 32 * 33 * This software is furnished under license and may be used and 34 * copied only in accordance with the following terms and conditions. 35 * Subject to these conditions, you may download, copy, install, 36 * use, modify and distribute this software in source and/or binary 37 * form. No title or ownership is transferred hereby. 38 * 39 * 1) Any source code used, modified or distributed must reproduce 40 * and retain this copyright notice and list of conditions as 41 * they appear in the source file. 42 * 43 * 2) No right is granted to use any trade name, trademark, or logo of 44 * Digital Equipment Corporation. Neither the "Digital Equipment 45 * Corporation" name nor any trademark or logo of Digital Equipment 46 * Corporation may be used to endorse or promote products derived 47 * from this software without the prior written permission of 48 * Digital Equipment Corporation. 49 * 50 * 3) This software is provided "AS-IS" and any express or implied 51 * warranties, including but not limited to, any implied warranties 52 * of merchantability, fitness for a particular purpose, or 53 * non-infringement are disclaimed. In no event shall DIGITAL be 54 * liable for any damages whatsoever, and in particular, DIGITAL 55 * shall not be liable for special, indirect, consequential, or 56 * incidental damages or damages for lost profits, loss of 57 * revenue or loss of use, whether such damages arise in contract, 58 * negligence, tort, under statute, in equity, at law or otherwise, 59 * even if advised of the possibility of such damage. 60 */ 61 62 /* 63 **++ 64 ** FACILITY 65 ** 66 ** Device Driver for the Crystal CS8900 ISA Ethernet Controller. 67 ** 68 ** ABSTRACT 69 ** 70 ** This module provides standard ethernet access for INET protocols 71 ** only. 72 ** 73 ** AUTHORS 74 ** 75 ** Peter Dettori SEA - Software Engineering. 76 ** 77 ** CREATION DATE: 78 ** 79 ** 13-Feb-1997. 80 ** 81 ** MODIFICATION HISTORY (Digital): 82 ** 83 ** Revision 1.27 1998/01/20 17:59:40 cgd 84 ** update for moved headers 85 ** 86 ** Revision 1.26 1998/01/12 19:29:36 cgd 87 ** use arm32/isa versions of isadma code. 88 ** 89 ** Revision 1.25 1997/12/12 01:35:27 cgd 90 ** convert to use new arp code (from Brini) 91 ** 92 ** Revision 1.24 1997/12/10 22:31:56 cgd 93 ** trim some fat (get rid of ability to explicitly supply enet addr, since 94 ** it was never used and added a bunch of code which really doesn't belong in 95 ** an enet driver), and clean up slightly. 96 ** 97 ** Revision 1.23 1997/10/06 16:42:12 cgd 98 ** copyright notices 99 ** 100 ** Revision 1.22 1997/06/20 19:38:01 chaiken 101 ** fixes some smartcard problems 102 ** 103 ** Revision 1.21 1997/06/10 02:56:20 grohn 104 ** Added call to ledNetActive 105 ** 106 ** Revision 1.20 1997/06/05 00:47:06 dettori 107 ** Changed cs_process_rx_dma to reset and re-initialise the 108 ** ethernet chip when DMA gets out of sync, or mbufs 109 ** can't be allocated. 110 ** 111 ** Revision 1.19 1997/06/03 03:09:58 dettori 112 ** Turn off sc_txbusy flag when a transmit underrun 113 ** occurs. 114 ** 115 ** Revision 1.18 1997/06/02 00:04:35 dettori 116 ** redefined the transmit table to get around the nfs_timer bug while we are 117 ** looking into it further. 118 ** 119 ** Also changed interrupts from EDGE to LEVEL. 120 ** 121 ** Revision 1.17 1997/05/27 23:31:01 dettori 122 ** Pulled out changes to DMAMODE defines. 123 ** 124 ** Revision 1.16 1997/05/23 04:25:16 cgd 125 ** reformat log so it fits in 80cols 126 ** 127 ** Revision 1.15 1997/05/23 04:22:18 cgd 128 ** remove the existing copyright notice (which Peter Dettori indicated 129 ** was incorrect, copied from an existing NetBSD file only so that the 130 ** file would have a copyright notice on it, and which he'd intended to 131 ** replace). Replace it with a Digital copyright notice, cloned from 132 ** ess.c. It's not really correct either (it indicates that the source 133 ** is Digital confidential!), but is better than nothing and more 134 ** correct than what was there before. 135 ** 136 ** Revision 1.14 1997/05/23 04:12:50 cgd 137 ** use an adaptive transmit start algorithm: start by telling the chip 138 ** to start transmitting after 381 bytes have been fed to it. if that 139 ** gets transmit underruns, ramp down to 1021 bytes then "whole 140 ** packet." If successful at a given level for a while, try the next 141 ** more agressive level. This code doesn't ever try to start 142 ** transmitting after 5 bytes have been sent to the NIC, because 143 ** that underruns rather regularly. The back-off and ramp-up mechanism 144 ** could probably be tuned a little bit, but this works well enough to 145 ** support > 1MB/s transmit rates on a clear ethernet (which is about 146 ** 20-25% better than the driver had previously been getting). 147 ** 148 ** Revision 1.13 1997/05/22 21:06:54 cgd 149 ** redo cs_copy_tx_frame() from scratch. It had a fatal flaw: it was blindly 150 ** casting from u_int8_t * to u_int16_t * without worrying about alignment 151 ** issues. This would cause bogus data to be spit out for mbufs with 152 ** misaligned data. For instance, it caused the following bits to appear 153 ** on the wire: 154 ** ... etBND 1S2C .SHA(K) R ... 155 ** 11112222333344445555 156 ** which should have appeared as: 157 ** ... NetBSD 1.2C (SHARK) ... 158 ** 11112222333344445555 159 ** Note the apparent 'rotate' of the bytes in the word, which was due to 160 ** incorrect unaligned accesses. This data corruption was the cause of 161 ** incoming telnet/rlogin hangs. 162 ** 163 ** Revision 1.12 1997/05/22 01:55:32 cgd 164 ** reformat log so it fits in 80cols 165 ** 166 ** Revision 1.11 1997/05/22 01:50:27 cgd 167 ** * enable input packet address checking in the BPF+IFF_PROMISCUOUS case, 168 ** so packets aimed at other hosts don't get sent to ether_input(). 169 ** * Add a static const char *rcsid initialized with an RCS Id tag, so that 170 ** you can easily tell (`strings`) what version of the driver is in your 171 ** kernel binary. 172 ** * get rid of ether_cmp(). It was inconsistently used, not necessarily 173 ** safe, and not really a performance win anyway. (It was only used when 174 ** setting up the multicast logical address filter, which is an 175 ** infrequent event. It could have been used in the IFF_PROMISCUOUS 176 ** address check above, but the benefit of it vs. memcmp would be 177 ** inconsequential, there.) Use memcmp() instead. 178 ** * restructure csStartOuput to avoid the following bugs in the case where 179 ** txWait was being set: 180 ** * it would accidentally drop the outgoing packet if told to wait 181 ** but the outgoing packet queue was empty. 182 ** * it would bpf_mtap() the outgoing packet multiple times (once for 183 ** each time it was told to wait), and would also recalculate 184 ** the length of the outgoing packet each time it was told to 185 ** wait. 186 ** While there, rename txWait to txLoop, since with the new structure of 187 ** the code, the latter name makes more sense. 188 ** 189 ** Revision 1.10 1997/05/19 02:03:20 cgd 190 ** Set RX_CTL in cs_set_ladr_filt(), rather than cs_initChip(). cs_initChip() 191 ** is the only caller of cs_set_ladr_filt(), and always calls it, so this 192 ** ends up being logically the same. In cs_set_ladr_filt(), if IFF_PROMISC 193 ** is set, enable promiscuous mode (and set IFF_ALLMULTI), otherwise behave 194 ** as before. 195 ** 196 ** Revision 1.9 1997/05/19 01:45:37 cgd 197 ** create a new function, cs_ether_input(), which does received-packet 198 ** BPF and ether_input processing. This code used to be in three places, 199 ** and centralizing it will make adding IFF_PROMISC support much easier. 200 ** Also, in cs_copy_tx_frame(), put it some (currently disabled) code to 201 ** do copies with bus_space_write_region_2(). It's more correct, and 202 ** potentially more efficient. That function needs to be gutted (to 203 ** deal properly with alignment issues, which it currently does wrong), 204 ** however, and the change doesn't gain much, so there's no point in 205 ** enabling it now. 206 ** 207 ** Revision 1.8 1997/05/19 01:17:10 cgd 208 ** fix a comment re: the setting of the TxConfig register. Clean up 209 ** interface counter maintenance (make it use standard idiom). 210 ** 211 **-- 212 */ 213 214 #include <sys/cdefs.h> 215 __KERNEL_RCSID(0, "$NetBSD: cs89x0.c,v 1.23 2008/04/08 12:07:25 cegger Exp $"); 216 217 #include "opt_inet.h" 218 219 #include <sys/param.h> 220 #include <sys/systm.h> 221 #include <sys/mbuf.h> 222 #include <sys/syslog.h> 223 #include <sys/socket.h> 224 #include <sys/device.h> 225 #include <sys/malloc.h> 226 #include <sys/ioctl.h> 227 #include <sys/errno.h> 228 229 #include "rnd.h" 230 #if NRND > 0 231 #include <sys/rnd.h> 232 #endif 233 234 #include <net/if.h> 235 #include <net/if_ether.h> 236 #include <net/if_media.h> 237 #ifdef INET 238 #include <netinet/in.h> 239 #include <netinet/if_inarp.h> 240 #endif 241 242 #include "bpfilter.h" 243 #if NBPFILTER > 0 244 #include <net/bpf.h> 245 #include <net/bpfdesc.h> 246 #endif 247 248 #include <uvm/uvm_extern.h> 249 250 #include <sys/bus.h> 251 #include <sys/intr.h> 252 253 #include <dev/ic/cs89x0reg.h> 254 #include <dev/ic/cs89x0var.h> 255 256 #ifdef SHARK 257 #include <shark/shark/sequoia.h> 258 #endif 259 260 /* 261 * MACRO DEFINITIONS 262 */ 263 #define CS_OUTPUT_LOOP_MAX 100 /* max times round notorious tx loop */ 264 265 /* 266 * FUNCTION PROTOTYPES 267 */ 268 void cs_get_default_media(struct cs_softc *); 269 int cs_get_params(struct cs_softc *); 270 int cs_get_enaddr(struct cs_softc *); 271 int cs_reset_chip(struct cs_softc *); 272 void cs_reset(void *); 273 int cs_ioctl(struct ifnet *, u_long, void *); 274 void cs_initChip(struct cs_softc *); 275 void cs_buffer_event(struct cs_softc *, u_int16_t); 276 void cs_transmit_event(struct cs_softc *, u_int16_t); 277 void cs_receive_event(struct cs_softc *, u_int16_t); 278 void cs_process_receive(struct cs_softc *); 279 void cs_process_rx_early(struct cs_softc *); 280 void cs_start_output(struct ifnet *); 281 void cs_copy_tx_frame(struct cs_softc *, struct mbuf *); 282 void cs_set_ladr_filt(struct cs_softc *, struct ethercom *); 283 u_int16_t cs_hash_index(char *); 284 void cs_counter_event(struct cs_softc *, u_int16_t); 285 286 int cs_mediachange(struct ifnet *); 287 void cs_mediastatus(struct ifnet *, struct ifmediareq *); 288 289 static int cs_enable(struct cs_softc *); 290 static void cs_disable(struct cs_softc *); 291 static void cs_stop(struct ifnet *, int); 292 static void cs_power(int, void *); 293 static int cs_scan_eeprom(struct cs_softc *); 294 static int cs_read_pktpg_from_eeprom(struct cs_softc *, int, u_int16_t *); 295 296 297 /* 298 * GLOBAL DECLARATIONS 299 */ 300 301 /* 302 * Xmit-early table. 303 * 304 * To get better performance, we tell the chip to start packet 305 * transmission before the whole packet is copied to the chip. 306 * However, this can fail under load. When it fails, we back off 307 * to a safer setting for a little while. 308 * 309 * txcmd is the value of txcmd used to indicate when to start transmission. 310 * better is the next 'better' state in the table. 311 * better_count is the number of output packets before transition to the 312 * better state. 313 * worse is the next 'worse' state in the table. 314 * 315 * Transition to the next worse state happens automatically when a 316 * transmittion underrun occurs. 317 */ 318 struct cs_xmit_early { 319 u_int16_t txcmd; 320 int better; 321 int better_count; 322 int worse; 323 } cs_xmit_early_table[3] = { 324 { TX_CMD_START_381, 0, INT_MAX, 1, }, 325 { TX_CMD_START_1021, 0, 50000, 2, }, 326 { TX_CMD_START_ALL, 1, 5000, 2, }, 327 }; 328 329 int cs_default_media[] = { 330 IFM_ETHER|IFM_10_2, 331 IFM_ETHER|IFM_10_5, 332 IFM_ETHER|IFM_10_T, 333 IFM_ETHER|IFM_10_T|IFM_FDX, 334 }; 335 int cs_default_nmedia = sizeof(cs_default_media) / sizeof(cs_default_media[0]); 336 337 int 338 cs_attach(struct cs_softc *sc, u_int8_t *enaddr, int *media, 339 int nmedia, int defmedia) 340 { 341 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 342 const char *chipname, *medname; 343 u_int16_t reg; 344 int i; 345 346 /* Start out in IO mode */ 347 sc->sc_memorymode = FALSE; 348 349 /* make sure we're right */ 350 for (i = 0; i < 10000; i++) { 351 reg = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 352 if (reg == EISA_NUM_CRYSTAL) { 353 break; 354 } 355 } 356 if (i == 10000) { 357 aprint_error_dev(&sc->sc_dev, "wrong id(0x%x)\n", reg); 358 return 1; /* XXX should panic? */ 359 } 360 361 reg = CS_READ_PACKET_PAGE(sc, PKTPG_PRODUCT_ID); 362 sc->sc_prodid = reg & PROD_ID_MASK; 363 sc->sc_prodrev = (reg & PROD_REV_MASK) >> 8; 364 365 switch (sc->sc_prodid) { 366 case PROD_ID_CS8900: 367 chipname = "CS8900"; 368 break; 369 case PROD_ID_CS8920: 370 chipname = "CS8920"; 371 break; 372 case PROD_ID_CS8920M: 373 chipname = "CS8920M"; 374 break; 375 default: 376 panic("cs_attach: impossible"); 377 } 378 379 /* 380 * the first thing to do is check that the mbuf cluster size is 381 * greater than the MTU for an ethernet frame. The code depends on 382 * this and to port this to a OS where this was not the case would 383 * not be straightforward. 384 * 385 * we need 1 byte spare because our 386 * packet read loop can overrun. 387 * and we may need pad bytes to align ip header. 388 */ 389 if (MCLBYTES < ETHER_MAX_LEN + 1 + 390 ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header)) { 391 printf("%s: MCLBYTES too small for Ethernet frame\n", 392 device_xname(&sc->sc_dev)); 393 return 1; 394 } 395 396 /* Start out not transmitting */ 397 sc->sc_txbusy = FALSE; 398 399 /* Set up early transmit threshhold */ 400 sc->sc_xe_ent = 0; 401 sc->sc_xe_togo = cs_xmit_early_table[sc->sc_xe_ent].better_count; 402 403 /* Initialize ifnet structure. */ 404 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 405 ifp->if_softc = sc; 406 ifp->if_start = cs_start_output; 407 ifp->if_init = cs_init; 408 ifp->if_ioctl = cs_ioctl; 409 ifp->if_stop = cs_stop; 410 ifp->if_watchdog = NULL; /* no watchdog at this stage */ 411 ifp->if_flags = IFF_SIMPLEX | IFF_NOTRAILERS | 412 IFF_BROADCAST | IFF_MULTICAST; 413 IFQ_SET_READY(&ifp->if_snd); 414 415 /* Initialize ifmedia structures. */ 416 ifmedia_init(&sc->sc_media, 0, cs_mediachange, cs_mediastatus); 417 418 if (media != NULL) { 419 for (i = 0; i < nmedia; i++) 420 ifmedia_add(&sc->sc_media, media[i], 0, NULL); 421 ifmedia_set(&sc->sc_media, defmedia); 422 } else { 423 for (i = 0; i < cs_default_nmedia; i++) 424 ifmedia_add(&sc->sc_media, cs_default_media[i], 425 0, NULL); 426 cs_get_default_media(sc); 427 } 428 429 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 430 if (cs_scan_eeprom(sc) == CS_ERROR) { 431 /* failed to scan the eeprom, pretend there isn't an eeprom */ 432 aprint_error_dev(&sc->sc_dev, "unable to scan EEPROM\n"); 433 sc->sc_cfgflags |= CFGFLG_NOT_EEPROM; 434 } 435 } 436 437 if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 438 /* Get parameters from the EEPROM */ 439 if (cs_get_params(sc) == CS_ERROR) { 440 aprint_error_dev(&sc->sc_dev, "unable to get settings from EEPROM\n"); 441 return 1; 442 } 443 } 444 445 if (enaddr != NULL) 446 memcpy(sc->sc_enaddr, enaddr, sizeof(sc->sc_enaddr)); 447 else if ((sc->sc_cfgflags & CFGFLG_NOT_EEPROM) == 0) { 448 /* Get and store the Ethernet address */ 449 if (cs_get_enaddr(sc) == CS_ERROR) { 450 aprint_error_dev(&sc->sc_dev, "unable to read Ethernet address\n"); 451 return 1; 452 } 453 } else { 454 #if 1 455 int j; 456 uint v; 457 458 for (j = 0; j < 6; j += 2) { 459 v = CS_READ_PACKET_PAGE(sc, PKTPG_IND_ADDR + j); 460 sc->sc_enaddr[j + 0] = v; 461 sc->sc_enaddr[j + 1] = v >> 8; 462 } 463 #else 464 printf("%s: no Ethernet address!\n", device_xname(&sc->sc_dev)); 465 return 1; 466 #endif 467 } 468 469 switch (IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media)) { 470 case IFM_10_2: 471 medname = "BNC"; 472 break; 473 case IFM_10_5: 474 medname = "AUI"; 475 break; 476 case IFM_10_T: 477 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 478 medname = "UTP <full-duplex>"; 479 else 480 medname = "UTP"; 481 break; 482 default: 483 panic("cs_attach: impossible"); 484 } 485 printf("%s: %s rev. %c, address %s, media %s\n", device_xname(&sc->sc_dev), 486 chipname, sc->sc_prodrev + 'A', ether_sprintf(sc->sc_enaddr), 487 medname); 488 489 if (sc->sc_dma_attach) 490 (*sc->sc_dma_attach)(sc); 491 492 sc->sc_sh = shutdownhook_establish(cs_reset, sc); 493 if (sc->sc_sh == NULL) { 494 aprint_error_dev(&sc->sc_dev, "unable to establish shutdownhook\n"); 495 cs_detach(sc); 496 return 1; 497 } 498 499 /* Attach the interface. */ 500 if_attach(ifp); 501 ether_ifattach(ifp, sc->sc_enaddr); 502 503 #if NRND > 0 504 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 505 RND_TYPE_NET, 0); 506 #endif 507 sc->sc_cfgflags |= CFGFLG_ATTACHED; 508 509 /* Reset the chip */ 510 if (cs_reset_chip(sc) == CS_ERROR) { 511 aprint_error_dev(&sc->sc_dev, "reset failed\n"); 512 cs_detach(sc); 513 return 1; 514 } 515 516 sc->sc_powerhook = powerhook_establish(device_xname(&sc->sc_dev), 517 cs_power, sc); 518 if (sc->sc_powerhook == 0) 519 aprint_error_dev(&sc->sc_dev, "warning: powerhook_establish failed\n"); 520 521 return 0; 522 } 523 524 int 525 cs_detach(struct cs_softc *sc) 526 { 527 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 528 529 if (sc->sc_powerhook) { 530 powerhook_disestablish(sc->sc_powerhook); 531 sc->sc_powerhook = 0; 532 } 533 534 if (sc->sc_cfgflags & CFGFLG_ATTACHED) { 535 #if NRND > 0 536 rnd_detach_source(&sc->rnd_source); 537 #endif 538 ether_ifdetach(ifp); 539 if_detach(ifp); 540 sc->sc_cfgflags &= ~CFGFLG_ATTACHED; 541 } 542 543 if (sc->sc_sh != NULL) 544 shutdownhook_disestablish(sc->sc_sh); 545 546 #if 0 547 /* 548 * XXX not necessary 549 */ 550 if (sc->sc_cfgflags & CFGFLG_DMA_MODE) { 551 isa_dmamem_unmap(sc->sc_ic, sc->sc_drq, sc->sc_dmabase, sc->sc_dmasize); 552 isa_dmamem_free(sc->sc_ic, sc->sc_drq, sc->sc_dmaaddr, sc->sc_dmasize); 553 isa_dmamap_destroy(sc->sc_ic, sc->sc_drq); 554 sc->sc_cfgflags &= ~CFGFLG_DMA_MODE; 555 } 556 #endif 557 558 return 0; 559 } 560 561 void 562 cs_get_default_media(struct cs_softc *sc) 563 { 564 u_int16_t adp_cfg, xmit_ctl; 565 566 if (cs_verify_eeprom(sc) == CS_ERROR) { 567 aprint_error_dev(&sc->sc_dev, "cs_get_default_media: EEPROM missing or bad\n"); 568 goto fakeit; 569 } 570 571 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adp_cfg) == CS_ERROR) { 572 aprint_error_dev(&sc->sc_dev, "unable to read adapter config from EEPROM\n"); 573 goto fakeit; 574 } 575 576 if (cs_read_eeprom(sc, EEPROM_XMIT_CTL, &xmit_ctl) == CS_ERROR) { 577 aprint_error_dev(&sc->sc_dev, "unable to read transmit control from EEPROM\n"); 578 goto fakeit; 579 } 580 581 switch (adp_cfg & ADPTR_CFG_MEDIA) { 582 case ADPTR_CFG_AUI: 583 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_5); 584 break; 585 case ADPTR_CFG_10BASE2: 586 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_2); 587 break; 588 case ADPTR_CFG_10BASET: 589 default: 590 if (xmit_ctl & XMIT_CTL_FDX) 591 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T|IFM_FDX); 592 else 593 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 594 break; 595 } 596 return; 597 598 fakeit: 599 aprint_error_dev(&sc->sc_dev, "WARNING: default media setting may be inaccurate\n"); 600 /* XXX Arbitrary... */ 601 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_10_T); 602 } 603 604 /* 605 * cs_scan_eeprom 606 * 607 * Attempt to take a complete copy of the eeprom into main memory. 608 * this will allow faster parsing of the eeprom data. 609 * 610 * Only tested against a 8920M's eeprom, but the data sheet for the 611 * 8920A indicates that is uses the same layout. 612 */ 613 int 614 cs_scan_eeprom(struct cs_softc *sc) 615 { 616 u_int16_t result; 617 int i; 618 int eeprom_size; 619 u_int8_t checksum = 0; 620 621 if (cs_verify_eeprom(sc) == CS_ERROR) { 622 aprint_error_dev(&sc->sc_dev, "cs_scan_params: EEPROM missing or bad\n"); 623 return (CS_ERROR); 624 } 625 626 /* 627 * read the 0th word from the eeprom, it will tell us the length 628 * and if the eeprom is valid 629 */ 630 cs_read_eeprom(sc, 0, &result); 631 632 /* check the eeprom signature */ 633 if ((result & 0xE000) != 0xA000) { 634 /* empty eeprom */ 635 return (CS_ERROR); 636 } 637 638 /* 639 * take the eeprom size (note the read value doesn't include the header 640 * word) 641 */ 642 eeprom_size = (result & 0xff) + 2; 643 644 sc->eeprom_data = malloc(eeprom_size, M_DEVBUF, M_WAITOK); 645 if (sc->eeprom_data == NULL) { 646 /* no memory, treat this as if there's no eeprom */ 647 return (CS_ERROR); 648 } 649 650 sc->eeprom_size = eeprom_size; 651 652 /* read the eeprom into the buffer, also calculate the checksum */ 653 for (i = 0; i < (eeprom_size >> 1); i++) { 654 cs_read_eeprom(sc, i, &(sc->eeprom_data[i])); 655 checksum += (sc->eeprom_data[i] & 0xff00) >> 8; 656 checksum += (sc->eeprom_data[i] & 0x00ff); 657 } 658 659 /* 660 * validate checksum calculation, the sum of all the bytes should be 0, 661 * as the high byte of the last word is the 2's complement of the 662 * sum to that point. 663 */ 664 if (checksum != 0) { 665 aprint_error_dev(&sc->sc_dev, "eeprom checksum failure\n"); 666 return (CS_ERROR); 667 } 668 669 return (CS_OK); 670 } 671 672 static int 673 cs_read_pktpg_from_eeprom(struct cs_softc *sc, int pktpg, u_int16_t *pValue) 674 { 675 int x, maxword; 676 677 /* Check that we have eeprom data */ 678 if ((sc->eeprom_data == NULL) || (sc->eeprom_size < 2)) 679 return (CS_ERROR); 680 681 /* 682 * We only want to read the data words, the last word contains the 683 * checksum 684 */ 685 maxword = (sc->eeprom_size - 2) >> 1; 686 687 /* start 1 word in, as the first word is the length and signature */ 688 x = 1; 689 690 while ( x < (maxword)) { 691 u_int16_t header; 692 int group_size; 693 int offset; 694 int offset_max; 695 696 /* read in the group header word */ 697 header = sc->eeprom_data[x]; 698 x++; /* skip group header */ 699 700 /* 701 * size of group in words is in the top 4 bits, note that it 702 * is one less than the number of words 703 */ 704 group_size = header & 0xF000; 705 706 /* 707 * CS8900 Data sheet says this should be 0x01ff, 708 * but my cs8920 eeprom has higher offsets, 709 * perhaps the 8920 allows higher offsets, otherwise 710 * it's writing to places that it shouldn't 711 */ 712 /* work out the offsets this group covers */ 713 offset = header & 0x0FFF; 714 offset_max = offset + (group_size << 1); 715 716 /* check if the pkgpg we're after is in this group */ 717 if ((offset <= pktpg) && (pktpg <= offset_max)) { 718 /* the pkgpg value we want is in here */ 719 int eeprom_location; 720 721 eeprom_location = ((pktpg - offset) >> 1) ; 722 723 *pValue = sc->eeprom_data[x + eeprom_location]; 724 return (CS_OK); 725 } else { 726 /* skip this group (+ 1 for first entry) */ 727 x += group_size + 1; 728 } 729 } 730 731 /* 732 * if we've fallen out here then we don't have a value in the EEPROM 733 * for this pktpg so return an error 734 */ 735 return (CS_ERROR); 736 } 737 738 int 739 cs_get_params(struct cs_softc *sc) 740 { 741 u_int16_t isaConfig; 742 u_int16_t adapterConfig; 743 744 if (cs_verify_eeprom(sc) == CS_ERROR) { 745 aprint_error_dev(&sc->sc_dev, "cs_get_params: EEPROM missing or bad\n"); 746 return (CS_ERROR); 747 } 748 749 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 750 /* Get ISA configuration from the EEPROM */ 751 if (cs_read_pktpg_from_eeprom(sc, PKTPG_BUS_CTL, &isaConfig) 752 == CS_ERROR) { 753 /* eeprom doesn't have this value, use data sheet default */ 754 isaConfig = 0x0017; 755 } 756 757 /* Get adapter configuration from the EEPROM */ 758 if (cs_read_pktpg_from_eeprom(sc, PKTPG_SELF_CTL, &adapterConfig) 759 == CS_ERROR) { 760 /* eeprom doesn't have this value, use data sheet default */ 761 adapterConfig = 0x0015; 762 } 763 764 /* Copy the USE_SA flag */ 765 if (isaConfig & BUS_CTL_USE_SA) 766 sc->sc_cfgflags |= CFGFLG_USE_SA; 767 768 /* Copy the IO Channel Ready flag */ 769 if (isaConfig & BUS_CTL_IOCHRDY) 770 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 771 772 /* Copy the DC/DC Polarity flag */ 773 if (adapterConfig & SELF_CTL_HCB1) 774 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 775 } else { 776 /* Get ISA configuration from the EEPROM */ 777 if (cs_read_eeprom(sc, EEPROM_ISA_CFG, &isaConfig) == CS_ERROR) 778 goto eeprom_bad; 779 780 /* Get adapter configuration from the EEPROM */ 781 if (cs_read_eeprom(sc, EEPROM_ADPTR_CFG, &adapterConfig) == CS_ERROR) 782 goto eeprom_bad; 783 784 /* Copy the USE_SA flag */ 785 if (isaConfig & ISA_CFG_USE_SA) 786 sc->sc_cfgflags |= CFGFLG_USE_SA; 787 788 /* Copy the IO Channel Ready flag */ 789 if (isaConfig & ISA_CFG_IOCHRDY) 790 sc->sc_cfgflags |= CFGFLG_IOCHRDY; 791 792 /* Copy the DC/DC Polarity flag */ 793 if (adapterConfig & ADPTR_CFG_DCDC_POL) 794 sc->sc_cfgflags |= CFGFLG_DCDC_POL; 795 } 796 797 return (CS_OK); 798 eeprom_bad: 799 aprint_error_dev(&sc->sc_dev, "cs_get_params: unable to read from EEPROM\n"); 800 return (CS_ERROR); 801 } 802 803 int 804 cs_get_enaddr(struct cs_softc *sc) 805 { 806 u_int16_t *myea; 807 808 if (cs_verify_eeprom(sc) == CS_ERROR) { 809 aprint_error_dev(&sc->sc_dev, "cs_get_enaddr: EEPROM missing or bad\n"); 810 return (CS_ERROR); 811 } 812 813 myea = (u_int16_t *)sc->sc_enaddr; 814 815 /* Get Ethernet address from the EEPROM */ 816 /* XXX this will likely lose on a big-endian machine. -- cgd */ 817 if (sc->sc_cfgflags & CFGFLG_PARSE_EEPROM) { 818 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR, &myea[0]) 819 == CS_ERROR) 820 goto eeprom_bad; 821 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 2, &myea[1]) 822 == CS_ERROR) 823 goto eeprom_bad; 824 if (cs_read_pktpg_from_eeprom(sc, PKTPG_IND_ADDR + 4, &myea[2]) 825 == CS_ERROR) 826 goto eeprom_bad; 827 } else { 828 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_H, &myea[0]) == CS_ERROR) 829 goto eeprom_bad; 830 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_M, &myea[1]) == CS_ERROR) 831 goto eeprom_bad; 832 if (cs_read_eeprom(sc, EEPROM_IND_ADDR_L, &myea[2]) == CS_ERROR) 833 goto eeprom_bad; 834 } 835 836 return (CS_OK); 837 838 eeprom_bad: 839 aprint_error_dev(&sc->sc_dev, "cs_get_enaddr: unable to read from EEPROM\n"); 840 return (CS_ERROR); 841 } 842 843 int 844 cs_reset_chip(struct cs_softc *sc) 845 { 846 int intState; 847 int x; 848 849 /* Disable interrupts at the CPU so reset command is atomic */ 850 intState = splnet(); 851 852 /* 853 * We are now resetting the chip 854 * 855 * A spurious interrupt is generated by the chip when it is reset. This 856 * variable informs the interrupt handler to ignore this interrupt. 857 */ 858 sc->sc_resetting = TRUE; 859 860 /* Issue a reset command to the chip */ 861 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, SELF_CTL_RESET); 862 863 /* Re-enable interrupts at the CPU */ 864 splx(intState); 865 866 /* The chip is always in IO mode after a reset */ 867 sc->sc_memorymode = FALSE; 868 869 /* If transmission was in progress, it is not now */ 870 sc->sc_txbusy = FALSE; 871 872 /* 873 * there was a delay(125); here, but it seems uneccesary 125 usec is 874 * 1/8000 of a second, not 1/8 of a second. the data sheet advises 875 * 1/10 of a second here, but the SI_BUSY and INIT_DONE loops below 876 * should be sufficient. 877 */ 878 879 /* Transition SBHE to switch chip from 8-bit to 16-bit */ 880 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 881 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 882 IO_READ_1(sc, PORT_PKTPG_PTR + 0); 883 IO_READ_1(sc, PORT_PKTPG_PTR + 1); 884 885 /* Wait until the EEPROM is not busy */ 886 for (x = 0; x < MAXLOOP; x++) { 887 if (!(CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_SI_BUSY)) 888 break; 889 } 890 891 if (x == MAXLOOP) 892 return CS_ERROR; 893 894 /* Wait until initialization is done */ 895 for (x = 0; x < MAXLOOP; x++) { 896 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_INIT_DONE) 897 break; 898 } 899 900 if (x == MAXLOOP) 901 return CS_ERROR; 902 903 /* Reset is no longer in progress */ 904 sc->sc_resetting = FALSE; 905 906 return CS_OK; 907 } 908 909 int 910 cs_verify_eeprom(struct cs_softc *sc) 911 { 912 u_int16_t self_status; 913 914 /* Verify that the EEPROM is present and OK */ 915 self_status = CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST); 916 if (((self_status & SELF_ST_EEP_PRES) && 917 (self_status & SELF_ST_EEP_OK)) == 0) 918 return (CS_ERROR); 919 920 return (CS_OK); 921 } 922 923 int 924 cs_read_eeprom(struct cs_softc *sc, int offset, u_int16_t *pValue) 925 { 926 int x; 927 928 /* Ensure that the EEPROM is not busy */ 929 for (x = 0; x < MAXLOOP; x++) { 930 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 931 SELF_ST_SI_BUSY)) 932 break; 933 } 934 935 if (x == MAXLOOP) 936 return (CS_ERROR); 937 938 /* Issue the command to read the offset within the EEPROM */ 939 CS_WRITE_PACKET_PAGE_IO(sc, PKTPG_EEPROM_CMD, 940 offset | EEPROM_CMD_READ); 941 942 /* Wait until the command is completed */ 943 for (x = 0; x < MAXLOOP; x++) { 944 if (!(CS_READ_PACKET_PAGE_IO(sc, PKTPG_SELF_ST) & 945 SELF_ST_SI_BUSY)) 946 break; 947 } 948 949 if (x == MAXLOOP) 950 return (CS_ERROR); 951 952 /* Get the EEPROM data from the EEPROM Data register */ 953 *pValue = CS_READ_PACKET_PAGE_IO(sc, PKTPG_EEPROM_DATA); 954 955 return (CS_OK); 956 } 957 958 void 959 cs_initChip(struct cs_softc *sc) 960 { 961 u_int16_t busCtl; 962 u_int16_t selfCtl; 963 u_int16_t v; 964 u_int16_t isaId; 965 int i; 966 int media = IFM_SUBTYPE(sc->sc_media.ifm_cur->ifm_media); 967 968 /* Disable reception and transmission of frames */ 969 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 970 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) & 971 ~LINE_CTL_RX_ON & ~LINE_CTL_TX_ON); 972 973 /* Disable interrupt at the chip */ 974 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 975 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) & ~BUS_CTL_INT_ENBL); 976 977 /* If IOCHRDY is enabled then clear the bit in the busCtl register */ 978 busCtl = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL); 979 if (sc->sc_cfgflags & CFGFLG_IOCHRDY) { 980 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 981 busCtl & ~BUS_CTL_IOCHRDY); 982 } else { 983 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 984 busCtl | BUS_CTL_IOCHRDY); 985 } 986 987 /* Set the Line Control register to match the media type */ 988 if (media == IFM_10_T) 989 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_10BASET); 990 else 991 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, LINE_CTL_AUI_ONLY); 992 993 /* 994 * Set the BSTATUS/HC1 pin to be used as HC1. HC1 is used to 995 * enable the DC/DC converter 996 */ 997 selfCtl = SELF_CTL_HC1E; 998 999 /* If the media type is 10Base2 */ 1000 if (media == IFM_10_2) { 1001 /* 1002 * Enable the DC/DC converter if it has a low enable. 1003 */ 1004 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) == 0) 1005 /* 1006 * Set the HCB1 bit, which causes the HC1 pin to go 1007 * low. 1008 */ 1009 selfCtl |= SELF_CTL_HCB1; 1010 } else { /* Media type is 10BaseT or AUI */ 1011 /* 1012 * Disable the DC/DC converter if it has a high enable. 1013 */ 1014 if ((sc->sc_cfgflags & CFGFLG_DCDC_POL) != 0) { 1015 /* 1016 * Set the HCB1 bit, which causes the HC1 pin to go 1017 * low. 1018 */ 1019 selfCtl |= SELF_CTL_HCB1; 1020 } 1021 } 1022 CS_WRITE_PACKET_PAGE(sc, PKTPG_SELF_CTL, selfCtl); 1023 1024 /* enable normal link pulse */ 1025 if (sc->sc_prodid == PROD_ID_CS8920 || sc->sc_prodid == PROD_ID_CS8920M) 1026 CS_WRITE_PACKET_PAGE(sc, PKTPG_AUTONEG_CTL, AUTOCTL_NLP_ENABLE); 1027 1028 /* Enable full-duplex, if appropriate */ 1029 if (sc->sc_media.ifm_cur->ifm_media & IFM_FDX) 1030 CS_WRITE_PACKET_PAGE(sc, PKTPG_TEST_CTL, TEST_CTL_FDX); 1031 1032 /* RX_CTL set in cs_set_ladr_filt(), below */ 1033 1034 /* enable all transmission interrupts */ 1035 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, TX_CFG_ALL_IE); 1036 1037 /* Accept all receive interrupts */ 1038 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, RX_CFG_ALL_IE); 1039 1040 /* 1041 * Configure Operational Modes 1042 * 1043 * I have turned off the BUF_CFG_RX_MISS_IE, to speed things up, this is 1044 * a better way to do it because the card has a counter which can be 1045 * read to update the RX_MISS counter. This saves many interrupts. 1046 * 1047 * I have turned on the tx and rx overflow interrupts to counter using 1048 * the receive miss interrupt. This is a better estimate of errors 1049 * and requires lower system overhead. 1050 */ 1051 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, BUF_CFG_TX_UNDR_IE | 1052 BUF_CFG_RX_DMA_IE); 1053 1054 if (sc->sc_dma_chipinit) 1055 (*sc->sc_dma_chipinit)(sc); 1056 1057 /* If memory mode is enabled */ 1058 if (sc->sc_cfgflags & CFGFLG_MEM_MODE) { 1059 /* If external logic is present for address decoding */ 1060 if (CS_READ_PACKET_PAGE(sc, PKTPG_SELF_ST) & SELF_ST_EL_PRES) { 1061 /* 1062 * Program the external logic to decode address bits 1063 * SA20-SA23 1064 */ 1065 CS_WRITE_PACKET_PAGE(sc, PKTPG_EEPROM_CMD, 1066 ((sc->sc_pktpgaddr & 0xffffff) >> 20) | 1067 EEPROM_CMD_ELSEL); 1068 } 1069 1070 /* 1071 * Write the packet page base physical address to the memory 1072 * base register. 1073 */ 1074 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 0, 1075 sc->sc_pktpgaddr & 0xFFFF); 1076 CS_WRITE_PACKET_PAGE(sc, PKTPG_MEM_BASE + 2, 1077 sc->sc_pktpgaddr >> 16); 1078 busCtl = BUS_CTL_MEM_MODE; 1079 1080 /* tell the chip to read the addresses off the SA pins */ 1081 if (sc->sc_cfgflags & CFGFLG_USE_SA) { 1082 busCtl |= BUS_CTL_USE_SA; 1083 } 1084 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1085 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | busCtl); 1086 1087 /* We are in memory mode now! */ 1088 sc->sc_memorymode = TRUE; 1089 1090 /* 1091 * wait here (10ms) for the chip to swap over. this is the 1092 * maximum time that this could take. 1093 */ 1094 delay(10000); 1095 1096 /* Verify that we can read from the chip */ 1097 isaId = CS_READ_PACKET_PAGE(sc, PKTPG_EISA_NUM); 1098 1099 /* 1100 * As a last minute sanity check before actually using mapped 1101 * memory we verify that we can read the isa number from the 1102 * chip in memory mode. 1103 */ 1104 if (isaId != EISA_NUM_CRYSTAL) { 1105 aprint_error_dev(&sc->sc_dev, "failed to enable memory mode\n"); 1106 sc->sc_memorymode = FALSE; 1107 } else { 1108 /* 1109 * we are in memory mode so if we aren't using DMA, 1110 * then program the chip to interrupt early. 1111 */ 1112 if ((sc->sc_cfgflags & CFGFLG_DMA_MODE) == 0) { 1113 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 1114 BUF_CFG_RX_DEST_IE | 1115 BUF_CFG_RX_MISS_OVER_IE | 1116 BUF_CFG_TX_COL_OVER_IE); 1117 } 1118 } 1119 1120 } 1121 1122 /* Put Ethernet address into the Individual Address register */ 1123 for (i = 0; i < 6; i += 2) { 1124 v = sc->sc_enaddr[i + 0] | (sc->sc_enaddr[i + 1]) << 8; 1125 CS_WRITE_PACKET_PAGE(sc, PKTPG_IND_ADDR + i, v); 1126 } 1127 1128 if (sc->sc_irq != -1) { 1129 /* Set the interrupt level in the chip */ 1130 if (sc->sc_prodid == PROD_ID_CS8900) { 1131 if (sc->sc_irq == 5) { 1132 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, 3); 1133 } else { 1134 CS_WRITE_PACKET_PAGE(sc, PKTPG_INT_NUM, (sc->sc_irq) - 10); 1135 } 1136 } 1137 else { /* CS8920 */ 1138 CS_WRITE_PACKET_PAGE(sc, PKTPG_8920_INT_NUM, sc->sc_irq); 1139 } 1140 } 1141 1142 /* write the multicast mask to the address filter register */ 1143 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1144 1145 /* Enable reception and transmission of frames */ 1146 CS_WRITE_PACKET_PAGE(sc, PKTPG_LINE_CTL, 1147 CS_READ_PACKET_PAGE(sc, PKTPG_LINE_CTL) | 1148 LINE_CTL_RX_ON | LINE_CTL_TX_ON); 1149 1150 /* Enable interrupt at the chip */ 1151 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 1152 CS_READ_PACKET_PAGE(sc, PKTPG_BUS_CTL) | BUS_CTL_INT_ENBL); 1153 } 1154 1155 int 1156 cs_init(struct ifnet *ifp) 1157 { 1158 int intState; 1159 int error = CS_OK; 1160 struct cs_softc *sc = ifp->if_softc; 1161 1162 if (cs_enable(sc)) 1163 goto out; 1164 1165 cs_stop(ifp, 0); 1166 1167 intState = splnet(); 1168 1169 #if 0 1170 /* Mark the interface as down */ 1171 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_UP | IFF_RUNNING); 1172 #endif 1173 1174 #ifdef CS_DEBUG 1175 /* Enable debugging */ 1176 sc->sc_ethercom.ec_if.if_flags |= IFF_DEBUG; 1177 #endif 1178 1179 /* Reset the chip */ 1180 if ((error = cs_reset_chip(sc)) == CS_OK) { 1181 /* Initialize the chip */ 1182 cs_initChip(sc); 1183 1184 /* Mark the interface as running */ 1185 sc->sc_ethercom.ec_if.if_flags |= IFF_RUNNING; 1186 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE; 1187 sc->sc_ethercom.ec_if.if_timer = 0; 1188 1189 /* Assume we have carrier until we are told otherwise. */ 1190 sc->sc_carrier = 1; 1191 } else { 1192 aprint_error_dev(&sc->sc_dev, "unable to reset chip\n"); 1193 } 1194 1195 splx(intState); 1196 out: 1197 if (error == CS_OK) 1198 return 0; 1199 return EIO; 1200 } 1201 1202 void 1203 cs_set_ladr_filt(struct cs_softc *sc, struct ethercom *ec) 1204 { 1205 struct ifnet *ifp = &ec->ec_if; 1206 struct ether_multi *enm; 1207 struct ether_multistep step; 1208 u_int16_t af[4]; 1209 u_int16_t port, mask, index; 1210 1211 /* 1212 * Set up multicast address filter by passing all multicast addresses 1213 * through a crc generator, and then using the high order 6 bits as an 1214 * index into the 64 bit logical address filter. The high order bit 1215 * selects the word, while the rest of the bits select the bit within 1216 * the word. 1217 */ 1218 if (ifp->if_flags & IFF_PROMISC) { 1219 /* accept all valid frames. */ 1220 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1221 RX_CTL_PROMISC_A | RX_CTL_RX_OK_A | 1222 RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1223 ifp->if_flags |= IFF_ALLMULTI; 1224 return; 1225 } 1226 1227 /* 1228 * accept frames if a. crc valid, b. individual address match c. 1229 * broadcast address,and d. multicast addresses matched in the hash 1230 * filter 1231 */ 1232 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CTL, 1233 RX_CTL_RX_OK_A | RX_CTL_IND_A | RX_CTL_BCAST_A | RX_CTL_MCAST_A); 1234 1235 1236 /* 1237 * start off with all multicast flag clear, set it if we need to 1238 * later, otherwise we will leave it. 1239 */ 1240 ifp->if_flags &= ~IFF_ALLMULTI; 1241 af[0] = af[1] = af[2] = af[3] = 0x0000; 1242 1243 /* 1244 * Loop through all the multicast addresses unless we get a range of 1245 * addresses, in which case we will just accept all packets. 1246 * Justification for this is given in the next comment. 1247 */ 1248 ETHER_FIRST_MULTI(step, ec, enm); 1249 while (enm != NULL) { 1250 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1251 sizeof enm->enm_addrlo)) { 1252 /* 1253 * We must listen to a range of multicast addresses. 1254 * For now, just accept all multicasts, rather than 1255 * trying to set only those filter bits needed to match 1256 * the range. (At this time, the only use of address 1257 * ranges is for IP multicast routing, for which the 1258 * range is big enough to require all bits set.) 1259 */ 1260 ifp->if_flags |= IFF_ALLMULTI; 1261 af[0] = af[1] = af[2] = af[3] = 0xffff; 1262 break; 1263 } else { 1264 /* 1265 * we have got an individual address so just set that 1266 * bit. 1267 */ 1268 index = cs_hash_index(enm->enm_addrlo); 1269 1270 /* Set the bit the Logical address filter. */ 1271 port = (u_int16_t) (index >> 4); 1272 mask = (u_int16_t) (1 << (index & 0xf)); 1273 af[port] |= mask; 1274 1275 ETHER_NEXT_MULTI(step, enm); 1276 } 1277 } 1278 1279 /* now program the chip with the addresses */ 1280 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 0, af[0]); 1281 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 2, af[1]); 1282 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 4, af[2]); 1283 CS_WRITE_PACKET_PAGE(sc, PKTPG_LOG_ADDR + 6, af[3]); 1284 return; 1285 } 1286 1287 u_int16_t 1288 cs_hash_index(char *addr) 1289 { 1290 uint32_t crc; 1291 uint16_t hash_code; 1292 1293 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 1294 1295 hash_code = crc >> 26; 1296 return (hash_code); 1297 } 1298 1299 void 1300 cs_reset(void *arg) 1301 { 1302 struct cs_softc *sc = arg; 1303 1304 /* Mark the interface as down */ 1305 sc->sc_ethercom.ec_if.if_flags &= ~IFF_RUNNING; 1306 1307 /* Reset the chip */ 1308 cs_reset_chip(sc); 1309 } 1310 1311 int 1312 cs_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1313 { 1314 struct cs_softc *sc = ifp->if_softc; 1315 struct ifreq *ifr = (struct ifreq *) data; 1316 int state; 1317 int result; 1318 1319 state = splnet(); 1320 1321 result = 0; /* only set if something goes wrong */ 1322 1323 switch (cmd) { 1324 case SIOCGIFMEDIA: 1325 case SIOCSIFMEDIA: 1326 result = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); 1327 break; 1328 1329 default: 1330 result = ether_ioctl(ifp, cmd, data); 1331 if (result == ENETRESET) { 1332 if (ifp->if_flags & IFF_RUNNING) { 1333 /* 1334 * Multicast list has changed. Set the 1335 * hardware filter accordingly. 1336 */ 1337 cs_set_ladr_filt(sc, &sc->sc_ethercom); 1338 } 1339 result = 0; 1340 } 1341 break; 1342 } 1343 1344 splx(state); 1345 1346 return result; 1347 } 1348 1349 int 1350 cs_mediachange(struct ifnet *ifp) 1351 { 1352 1353 /* 1354 * Current media is already set up. Just reset the interface 1355 * to let the new value take hold. 1356 */ 1357 cs_init(ifp); 1358 return (0); 1359 } 1360 1361 void 1362 cs_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1363 { 1364 struct cs_softc *sc = ifp->if_softc; 1365 1366 /* 1367 * The currently selected media is always the active media. 1368 */ 1369 ifmr->ifm_active = sc->sc_media.ifm_cur->ifm_media; 1370 1371 if (ifp->if_flags & IFF_UP) { 1372 /* Interface up, status is valid. */ 1373 ifmr->ifm_status = IFM_AVALID | 1374 (sc->sc_carrier ? IFM_ACTIVE : 0); 1375 } 1376 else ifmr->ifm_status = 0; 1377 } 1378 1379 int 1380 cs_intr(void *arg) 1381 { 1382 struct cs_softc *sc = arg; 1383 u_int16_t Event; 1384 #if NRND > 0 1385 u_int16_t rndEvent; 1386 #endif 1387 1388 /*printf("cs_intr %p\n", sc);*/ 1389 /* Ignore any interrupts that happen while the chip is being reset */ 1390 if (sc->sc_resetting) { 1391 printf("%s: cs_intr: reset in progress\n", 1392 device_xname(&sc->sc_dev)); 1393 return 1; 1394 } 1395 1396 /* Read an event from the Interrupt Status Queue */ 1397 if (sc->sc_memorymode) 1398 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1399 else 1400 Event = CS_READ_PORT(sc, PORT_ISQ); 1401 1402 if ((Event & REG_NUM_MASK) == 0 || Event == 0xffff) 1403 return 0; /* not ours */ 1404 1405 #if NRND > 0 1406 rndEvent = Event; 1407 #endif 1408 1409 /* Process all the events in the Interrupt Status Queue */ 1410 while ((Event & REG_NUM_MASK) != 0 && Event != 0xffff) { 1411 /* Dispatch to an event handler based on the register number */ 1412 switch (Event & REG_NUM_MASK) { 1413 case REG_NUM_RX_EVENT: 1414 cs_receive_event(sc, Event); 1415 break; 1416 case REG_NUM_TX_EVENT: 1417 cs_transmit_event(sc, Event); 1418 break; 1419 case REG_NUM_BUF_EVENT: 1420 cs_buffer_event(sc, Event); 1421 break; 1422 case REG_NUM_TX_COL: 1423 case REG_NUM_RX_MISS: 1424 cs_counter_event(sc, Event); 1425 break; 1426 default: 1427 printf("%s: unknown interrupt event 0x%x\n", 1428 device_xname(&sc->sc_dev), Event); 1429 break; 1430 } 1431 1432 /* Read another event from the Interrupt Status Queue */ 1433 if (sc->sc_memorymode) 1434 Event = CS_READ_PACKET_PAGE(sc, PKTPG_ISQ); 1435 else 1436 Event = CS_READ_PORT(sc, PORT_ISQ); 1437 } 1438 1439 /* have handled the interrupt */ 1440 #if NRND > 0 1441 rnd_add_uint32(&sc->rnd_source, rndEvent); 1442 #endif 1443 return 1; 1444 } 1445 1446 void 1447 cs_counter_event(struct cs_softc *sc, u_int16_t cntEvent) 1448 { 1449 struct ifnet *ifp; 1450 u_int16_t errorCount; 1451 1452 ifp = &sc->sc_ethercom.ec_if; 1453 1454 switch (cntEvent & REG_NUM_MASK) { 1455 case REG_NUM_TX_COL: 1456 /* 1457 * the count should be read before an overflow occurs. 1458 */ 1459 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_TX_COL); 1460 /* 1461 * the tramsit event routine always checks the number of 1462 * collisions for any packet so we don't increment any 1463 * counters here, as they should already have been 1464 * considered. 1465 */ 1466 break; 1467 case REG_NUM_RX_MISS: 1468 /* 1469 * the count should be read before an overflow occurs. 1470 */ 1471 errorCount = CS_READ_PACKET_PAGE(sc, PKTPG_RX_MISS); 1472 /* 1473 * Increment the input error count, the first 6bits are the 1474 * register id. 1475 */ 1476 ifp->if_ierrors += ((errorCount & 0xffC0) >> 6); 1477 break; 1478 default: 1479 /* do nothing */ 1480 break; 1481 } 1482 } 1483 1484 void 1485 cs_buffer_event(struct cs_softc *sc, u_int16_t bufEvent) 1486 { 1487 1488 /* 1489 * multiple events can be in the buffer event register at one time so 1490 * a standard switch statement will not suffice, here every event 1491 * must be checked. 1492 */ 1493 1494 /* 1495 * if 128 bits have been rxed by the time we get here, the dest event 1496 * will be cleared and 128 event will be set. 1497 */ 1498 if ((bufEvent & (BUF_EVENT_RX_DEST | BUF_EVENT_RX_128)) != 0) { 1499 cs_process_rx_early(sc); 1500 } 1501 1502 if (bufEvent & BUF_EVENT_RX_DMA) { 1503 /* process the receive data */ 1504 if (sc->sc_dma_process_rx) 1505 (*sc->sc_dma_process_rx)(sc); 1506 else 1507 /* should panic? */ 1508 aprint_error_dev(&sc->sc_dev, "unexpected DMA event\n"); 1509 } 1510 1511 if (bufEvent & BUF_EVENT_TX_UNDR) { 1512 #if 0 1513 /* 1514 * This can happen occasionally, and it's not worth worrying 1515 * about. 1516 */ 1517 printf("%s: transmit underrun (%d -> %d)\n", 1518 device_xname(&sc->sc_dev), sc->sc_xe_ent, 1519 cs_xmit_early_table[sc->sc_xe_ent].worse); 1520 #endif 1521 sc->sc_xe_ent = cs_xmit_early_table[sc->sc_xe_ent].worse; 1522 sc->sc_xe_togo = 1523 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1524 1525 /* had an underrun, transmit is finished */ 1526 sc->sc_txbusy = FALSE; 1527 } 1528 1529 if (bufEvent & BUF_EVENT_SW_INT) { 1530 printf("%s: software initiated interrupt\n", 1531 device_xname(&sc->sc_dev)); 1532 } 1533 } 1534 1535 void 1536 cs_transmit_event(struct cs_softc *sc, u_int16_t txEvent) 1537 { 1538 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1539 1540 /* If there were any errors transmitting this frame */ 1541 if (txEvent & (TX_EVENT_LOSS_CRS | TX_EVENT_SQE_ERR | TX_EVENT_OUT_WIN | 1542 TX_EVENT_JABBER | TX_EVENT_16_COLL)) { 1543 /* Increment the output error count */ 1544 ifp->if_oerrors++; 1545 1546 /* Note carrier loss. */ 1547 if (txEvent & TX_EVENT_LOSS_CRS) 1548 sc->sc_carrier = 0; 1549 1550 /* If debugging is enabled then log error messages */ 1551 if (ifp->if_flags & IFF_DEBUG) { 1552 if (txEvent & TX_EVENT_LOSS_CRS) { 1553 aprint_error_dev(&sc->sc_dev, "lost carrier\n"); 1554 } 1555 if (txEvent & TX_EVENT_SQE_ERR) { 1556 aprint_error_dev(&sc->sc_dev, "SQE error\n"); 1557 } 1558 if (txEvent & TX_EVENT_OUT_WIN) { 1559 aprint_error_dev(&sc->sc_dev, "out-of-window collision\n"); 1560 } 1561 if (txEvent & TX_EVENT_JABBER) { 1562 aprint_error_dev(&sc->sc_dev, "jabber\n"); 1563 } 1564 if (txEvent & TX_EVENT_16_COLL) { 1565 aprint_error_dev(&sc->sc_dev, "16 collisions\n"); 1566 } 1567 } 1568 } 1569 else { 1570 /* Transmission successful, carrier is up. */ 1571 sc->sc_carrier = 1; 1572 #ifdef SHARK 1573 ledNetActive(); 1574 #endif 1575 } 1576 1577 /* Add the number of collisions for this frame */ 1578 if (txEvent & TX_EVENT_16_COLL) { 1579 ifp->if_collisions += 16; 1580 } else { 1581 ifp->if_collisions += ((txEvent & TX_EVENT_COLL_MASK) >> 11); 1582 } 1583 1584 ifp->if_opackets++; 1585 1586 /* Transmission is no longer in progress */ 1587 sc->sc_txbusy = FALSE; 1588 1589 /* If there is more to transmit */ 1590 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) { 1591 /* Start the next transmission */ 1592 cs_start_output(ifp); 1593 } 1594 } 1595 1596 void 1597 cs_print_rx_errors(struct cs_softc *sc, u_int16_t rxEvent) 1598 { 1599 1600 if (rxEvent & RX_EVENT_RUNT) 1601 aprint_error_dev(&sc->sc_dev, "runt\n"); 1602 1603 if (rxEvent & RX_EVENT_X_DATA) 1604 aprint_error_dev(&sc->sc_dev, "extra data\n"); 1605 1606 if (rxEvent & RX_EVENT_CRC_ERR) { 1607 if (rxEvent & RX_EVENT_DRIBBLE) 1608 aprint_error_dev(&sc->sc_dev, "alignment error\n"); 1609 else 1610 aprint_error_dev(&sc->sc_dev, "CRC error\n"); 1611 } else { 1612 if (rxEvent & RX_EVENT_DRIBBLE) 1613 aprint_error_dev(&sc->sc_dev, "dribble bits\n"); 1614 } 1615 } 1616 1617 void 1618 cs_receive_event(struct cs_softc *sc, u_int16_t rxEvent) 1619 { 1620 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1621 1622 /* If the frame was not received OK */ 1623 if (!(rxEvent & RX_EVENT_RX_OK)) { 1624 /* Increment the input error count */ 1625 ifp->if_ierrors++; 1626 1627 /* 1628 * If debugging is enabled then log error messages. 1629 */ 1630 if (ifp->if_flags & IFF_DEBUG) { 1631 if (rxEvent != REG_NUM_RX_EVENT) { 1632 cs_print_rx_errors(sc, rxEvent); 1633 1634 /* 1635 * Must read the length of all received 1636 * frames 1637 */ 1638 CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1639 1640 /* Skip the received frame */ 1641 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1642 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | 1643 RX_CFG_SKIP); 1644 } else { 1645 aprint_error_dev(&sc->sc_dev, "implied skip\n"); 1646 } 1647 } 1648 } else { 1649 /* 1650 * process the received frame and pass it up to the upper 1651 * layers. 1652 */ 1653 cs_process_receive(sc); 1654 } 1655 } 1656 1657 void 1658 cs_ether_input(struct cs_softc *sc, struct mbuf *m) 1659 { 1660 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1661 1662 ifp->if_ipackets++; 1663 1664 #if NBPFILTER > 0 1665 /* 1666 * Check if there's a BPF listener on this interface. 1667 * If so, hand off the raw packet to BPF. 1668 */ 1669 if (ifp->if_bpf) 1670 bpf_mtap(ifp->if_bpf, m); 1671 #endif 1672 1673 /* Pass the packet up. */ 1674 (*ifp->if_input)(ifp, m); 1675 } 1676 1677 void 1678 cs_process_receive(struct cs_softc *sc) 1679 { 1680 struct ifnet *ifp; 1681 struct mbuf *m; 1682 int totlen; 1683 u_int16_t *pBuff, *pBuffLimit; 1684 int pad; 1685 unsigned int frameOffset = 0; /* XXX: gcc */ 1686 1687 #ifdef SHARK 1688 ledNetActive(); 1689 #endif 1690 1691 ifp = &sc->sc_ethercom.ec_if; 1692 1693 /* Received a packet; carrier is up. */ 1694 sc->sc_carrier = 1; 1695 1696 if (sc->sc_memorymode) { 1697 /* Initialize the frame offset */ 1698 frameOffset = PKTPG_RX_LENGTH; 1699 1700 /* Get the length of the received frame */ 1701 totlen = CS_READ_PACKET_PAGE(sc, frameOffset); 1702 frameOffset += 2; 1703 } 1704 else { 1705 /* drop status */ 1706 CS_READ_PORT(sc, PORT_RXTX_DATA); 1707 1708 /* Get the length of the received frame */ 1709 totlen = CS_READ_PORT(sc, PORT_RXTX_DATA); 1710 } 1711 1712 if (totlen > ETHER_MAX_LEN) { 1713 aprint_error_dev(&sc->sc_dev, "invalid packet length %d\n", 1714 totlen); 1715 1716 /* skip the received frame */ 1717 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1718 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1719 return; 1720 } 1721 1722 MGETHDR(m, M_DONTWAIT, MT_DATA); 1723 if (m == 0) { 1724 aprint_error_dev(&sc->sc_dev, "cs_process_receive: unable to allocate mbuf\n"); 1725 ifp->if_ierrors++; 1726 /* 1727 * couldn't allocate an mbuf so things are not good, may as 1728 * well drop the packet I think. 1729 * 1730 * have already read the length so we should be right to skip 1731 * the packet. 1732 */ 1733 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1734 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1735 return; 1736 } 1737 m->m_pkthdr.rcvif = ifp; 1738 m->m_pkthdr.len = totlen; 1739 1740 /* number of bytes to align ip header on word boundary for ipintr */ 1741 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1742 1743 /* 1744 * alloc mbuf cluster if we need. 1745 * we need 1 byte spare because following 1746 * packet read loop can overrun. 1747 */ 1748 if (totlen + pad + 1 > MHLEN) { 1749 MCLGET(m, M_DONTWAIT); 1750 if ((m->m_flags & M_EXT) == 0) { 1751 /* couldn't allocate an mbuf cluster */ 1752 aprint_error_dev(&sc->sc_dev, "cs_process_receive: unable to allocate a cluster\n"); 1753 m_freem(m); 1754 1755 /* skip the received frame */ 1756 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1757 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1758 return; 1759 } 1760 } 1761 1762 /* align ip header on word boundary for ipintr */ 1763 m->m_data += pad; 1764 1765 m->m_len = totlen; 1766 pBuff = mtod(m, u_int16_t *); 1767 1768 /* now read the data from the chip */ 1769 if (sc->sc_memorymode) { 1770 pBuffLimit = pBuff + (totlen + 1) / 2; /* don't want to go over */ 1771 while (pBuff < pBuffLimit) { 1772 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1773 frameOffset += 2; 1774 } 1775 } 1776 else { 1777 IO_READ_MULTI_2(sc, PORT_RXTX_DATA, pBuff, (totlen + 1)>>1); 1778 } 1779 1780 cs_ether_input(sc, m); 1781 } 1782 1783 void 1784 cs_process_rx_early(struct cs_softc *sc) 1785 { 1786 struct ifnet *ifp; 1787 struct mbuf *m; 1788 u_int16_t frameCount, oldFrameCount; 1789 u_int16_t rxEvent; 1790 u_int16_t *pBuff; 1791 int pad; 1792 unsigned int frameOffset; 1793 1794 1795 ifp = &sc->sc_ethercom.ec_if; 1796 1797 /* Initialize the frame offset */ 1798 frameOffset = PKTPG_RX_FRAME; 1799 frameCount = 0; 1800 1801 MGETHDR(m, M_DONTWAIT, MT_DATA); 1802 if (m == 0) { 1803 aprint_error_dev(&sc->sc_dev, "cs_process_rx_early: unable to allocate mbuf\n"); 1804 ifp->if_ierrors++; 1805 /* 1806 * couldn't allocate an mbuf so things are not good, may as 1807 * well drop the packet I think. 1808 * 1809 * have already read the length so we should be right to skip 1810 * the packet. 1811 */ 1812 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1813 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1814 return; 1815 } 1816 m->m_pkthdr.rcvif = ifp; 1817 /* 1818 * save processing by always using a mbuf cluster, guaranteed to fit 1819 * packet 1820 */ 1821 MCLGET(m, M_DONTWAIT); 1822 if ((m->m_flags & M_EXT) == 0) { 1823 /* couldn't allocate an mbuf cluster */ 1824 aprint_error_dev(&sc->sc_dev, "cs_process_rx_early: unable to allocate a cluster\n"); 1825 m_freem(m); 1826 /* skip the frame */ 1827 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 1828 CS_READ_PACKET_PAGE(sc, PKTPG_RX_CFG) | RX_CFG_SKIP); 1829 return; 1830 } 1831 1832 /* align ip header on word boundary for ipintr */ 1833 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header); 1834 m->m_data += pad; 1835 1836 /* set up the buffer pointer to point to the data area */ 1837 pBuff = mtod(m, u_int16_t *); 1838 1839 /* 1840 * now read the frame byte counter until we have finished reading the 1841 * frame 1842 */ 1843 oldFrameCount = 0; 1844 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1845 while ((frameCount != 0) && (frameCount < MCLBYTES)) { 1846 for (; oldFrameCount < frameCount; oldFrameCount += 2) { 1847 *pBuff++ = CS_READ_PACKET_PAGE(sc, frameOffset); 1848 frameOffset += 2; 1849 } 1850 1851 /* read the new count from the chip */ 1852 frameCount = CS_READ_PACKET_PAGE(sc, PKTPG_FRAME_BYTE_COUNT); 1853 } 1854 1855 /* update the mbuf counts */ 1856 m->m_len = oldFrameCount; 1857 m->m_pkthdr.len = oldFrameCount; 1858 1859 /* now check the Rx Event register */ 1860 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1861 1862 if ((rxEvent & RX_EVENT_RX_OK) != 0) { 1863 /* 1864 * do an implied skip, it seems to be more reliable than a 1865 * forced skip. 1866 */ 1867 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_STATUS); 1868 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_LENGTH); 1869 1870 /* 1871 * now read the RX_EVENT register to perform an implied skip. 1872 */ 1873 rxEvent = CS_READ_PACKET_PAGE(sc, PKTPG_RX_EVENT); 1874 1875 cs_ether_input(sc, m); 1876 } else { 1877 m_freem(m); 1878 ifp->if_ierrors++; 1879 } 1880 } 1881 1882 void 1883 cs_start_output(struct ifnet *ifp) 1884 { 1885 struct cs_softc *sc; 1886 struct mbuf *pMbuf; 1887 struct mbuf *pMbufChain; 1888 u_int16_t BusStatus; 1889 u_int16_t Length; 1890 int txLoop = 0; 1891 int dropout = 0; 1892 1893 sc = ifp->if_softc; 1894 1895 /* check that the interface is up and running */ 1896 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1897 return; 1898 } 1899 1900 /* Don't interrupt a transmission in progress */ 1901 if (sc->sc_txbusy) { 1902 return; 1903 } 1904 1905 /* this loop will only run through once if transmission is successful */ 1906 /* 1907 * While there are packets to transmit and a transmit is not in 1908 * progress 1909 */ 1910 while (sc->sc_txbusy == 0 && dropout == 0) { 1911 IFQ_DEQUEUE(&ifp->if_snd, pMbufChain); 1912 if (pMbufChain == NULL) 1913 break; 1914 1915 #if NBPFILTER > 0 1916 /* 1917 * If BPF is listening on this interface, let it see the packet 1918 * before we commit it to the wire. 1919 */ 1920 if (ifp->if_bpf) 1921 bpf_mtap(ifp->if_bpf, pMbufChain); 1922 #endif 1923 1924 /* Find the total length of the data to transmit */ 1925 Length = 0; 1926 for (pMbuf = pMbufChain; pMbuf != NULL; pMbuf = pMbuf->m_next) 1927 Length += pMbuf->m_len; 1928 1929 do { 1930 /* 1931 * Request that the transmit be started after all 1932 * data has been copied 1933 * 1934 * In IO mode must write to the IO port not the packet 1935 * page address 1936 * 1937 * If this is changed to start transmission after a 1938 * small amount of data has been copied you tend to 1939 * get packet missed errors i think because the ISA 1940 * bus is too slow. Or possibly the copy routine is 1941 * not streamlined enough. 1942 */ 1943 if (sc->sc_memorymode) { 1944 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CMD, 1945 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1946 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_LENGTH, Length); 1947 } 1948 else { 1949 CS_WRITE_PORT(sc, PORT_TX_CMD, 1950 cs_xmit_early_table[sc->sc_xe_ent].txcmd); 1951 CS_WRITE_PORT(sc, PORT_TX_LENGTH, Length); 1952 } 1953 1954 /* 1955 * Adjust early-transmit machinery. 1956 */ 1957 if (--sc->sc_xe_togo == 0) { 1958 sc->sc_xe_ent = 1959 cs_xmit_early_table[sc->sc_xe_ent].better; 1960 sc->sc_xe_togo = 1961 cs_xmit_early_table[sc->sc_xe_ent].better_count; 1962 } 1963 /* 1964 * Read the BusStatus register which indicates 1965 * success of the request 1966 */ 1967 BusStatus = CS_READ_PACKET_PAGE(sc, PKTPG_BUS_ST); 1968 1969 /* 1970 * If there was an error in the transmit bid free the 1971 * mbuf and go on. This is presuming that mbuf is 1972 * corrupt. 1973 */ 1974 if (BusStatus & BUS_ST_TX_BID_ERR) { 1975 aprint_error_dev(&sc->sc_dev, "transmit bid error (too big)"); 1976 1977 /* Discard the bad mbuf chain */ 1978 m_freem(pMbufChain); 1979 sc->sc_ethercom.ec_if.if_oerrors++; 1980 1981 /* Loop up to transmit the next chain */ 1982 txLoop = 0; 1983 } else { 1984 if (BusStatus & BUS_ST_RDY4TXNOW) { 1985 /* 1986 * The chip is ready for transmission 1987 * now 1988 */ 1989 /* 1990 * Copy the frame to the chip to 1991 * start transmission 1992 */ 1993 cs_copy_tx_frame(sc, pMbufChain); 1994 1995 /* Free the mbuf chain */ 1996 m_freem(pMbufChain); 1997 1998 /* Transmission is now in progress */ 1999 sc->sc_txbusy = TRUE; 2000 txLoop = 0; 2001 } else { 2002 /* 2003 * if we get here we want to try 2004 * again with the same mbuf, until 2005 * the chip lets us transmit. 2006 */ 2007 txLoop++; 2008 if (txLoop > CS_OUTPUT_LOOP_MAX) { 2009 /* Free the mbuf chain */ 2010 m_freem(pMbufChain); 2011 /* 2012 * Transmission is not in 2013 * progress 2014 */ 2015 sc->sc_txbusy = FALSE; 2016 /* 2017 * Increment the output error 2018 * count 2019 */ 2020 ifp->if_oerrors++; 2021 /* 2022 * exit the routine and drop 2023 * the packet. 2024 */ 2025 txLoop = 0; 2026 dropout = 1; 2027 } 2028 } 2029 } 2030 } while (txLoop); 2031 } 2032 } 2033 2034 void 2035 cs_copy_tx_frame(struct cs_softc *sc, struct mbuf *m0) 2036 { 2037 struct mbuf *m; 2038 int len, leftover, frameoff; 2039 u_int16_t dbuf; 2040 u_int8_t *p; 2041 #ifdef DIAGNOSTIC 2042 u_int8_t *lim; 2043 #endif 2044 2045 /* Initialize frame pointer and data port address */ 2046 frameoff = PKTPG_TX_FRAME; 2047 2048 /* start out with no leftover data */ 2049 leftover = 0; 2050 dbuf = 0; 2051 2052 /* Process the chain of mbufs */ 2053 for (m = m0; m != NULL; m = m->m_next) { 2054 /* 2055 * Process all of the data in a single mbuf. 2056 */ 2057 p = mtod(m, u_int8_t *); 2058 len = m->m_len; 2059 #ifdef DIAGNOSTIC 2060 lim = p + len; 2061 #endif 2062 2063 while (len > 0) { 2064 if (leftover) { 2065 /* 2066 * Data left over (from mbuf or realignment). 2067 * Buffer the next byte, and write it and 2068 * the leftover data out. 2069 */ 2070 dbuf |= *p++ << 8; 2071 len--; 2072 if (sc->sc_memorymode) { 2073 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2074 frameoff += 2; 2075 } 2076 else { 2077 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2078 } 2079 leftover = 0; 2080 } else if ((long) p & 1) { 2081 /* 2082 * Misaligned data. Buffer the next byte. 2083 */ 2084 dbuf = *p++; 2085 len--; 2086 leftover = 1; 2087 } else { 2088 /* 2089 * Aligned data. This is the case we like. 2090 * 2091 * Write-region out as much as we can, then 2092 * buffer the remaining byte (if any). 2093 */ 2094 leftover = len & 1; 2095 len &= ~1; 2096 if (sc->sc_memorymode) { 2097 MEM_WRITE_REGION_2(sc, frameoff, 2098 (u_int16_t *) p, len >> 1); 2099 frameoff += len; 2100 } 2101 else { 2102 IO_WRITE_MULTI_2(sc, 2103 PORT_RXTX_DATA, (u_int16_t *)p, len >> 1); 2104 } 2105 p += len; 2106 2107 if (leftover) 2108 dbuf = *p++; 2109 len = 0; 2110 } 2111 } 2112 if (len < 0) 2113 panic("cs_copy_tx_frame: negative len"); 2114 #ifdef DIAGNOSTIC 2115 if (p != lim) 2116 panic("cs_copy_tx_frame: p != lim"); 2117 #endif 2118 } 2119 if (leftover) { 2120 if (sc->sc_memorymode) { 2121 CS_WRITE_PACKET_PAGE(sc, frameoff, dbuf); 2122 } 2123 else { 2124 CS_WRITE_PORT(sc, PORT_RXTX_DATA, dbuf); 2125 } 2126 } 2127 } 2128 2129 static int 2130 cs_enable(struct cs_softc *sc) 2131 { 2132 2133 if (CS_IS_ENABLED(sc) == 0) { 2134 if (sc->sc_enable != NULL) { 2135 int error; 2136 2137 error = (*sc->sc_enable)(sc); 2138 if (error) 2139 return (error); 2140 } 2141 sc->sc_cfgflags |= CFGFLG_ENABLED; 2142 } 2143 2144 return (0); 2145 } 2146 2147 static void 2148 cs_disable(struct cs_softc *sc) 2149 { 2150 2151 if (CS_IS_ENABLED(sc)) { 2152 if (sc->sc_disable != NULL) 2153 (*sc->sc_disable)(sc); 2154 2155 sc->sc_cfgflags &= ~CFGFLG_ENABLED; 2156 } 2157 } 2158 2159 static void 2160 cs_stop(struct ifnet *ifp, int disable) 2161 { 2162 struct cs_softc *sc = ifp->if_softc; 2163 2164 CS_WRITE_PACKET_PAGE(sc, PKTPG_RX_CFG, 0); 2165 CS_WRITE_PACKET_PAGE(sc, PKTPG_TX_CFG, 0); 2166 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUF_CFG, 0); 2167 CS_WRITE_PACKET_PAGE(sc, PKTPG_BUS_CTL, 0); 2168 2169 if (disable) { 2170 cs_disable(sc); 2171 } 2172 2173 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2174 } 2175 2176 int 2177 cs_activate(struct device *self, enum devact act) 2178 { 2179 struct cs_softc *sc = (void *)self; 2180 int s, error = 0; 2181 2182 s = splnet(); 2183 switch (act) { 2184 case DVACT_ACTIVATE: 2185 error = EOPNOTSUPP; 2186 break; 2187 2188 case DVACT_DEACTIVATE: 2189 if_deactivate(&sc->sc_ethercom.ec_if); 2190 break; 2191 } 2192 splx(s); 2193 2194 return error; 2195 } 2196 2197 static void 2198 cs_power(int why, void *arg) 2199 { 2200 struct cs_softc *sc = arg; 2201 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 2202 int s; 2203 2204 s = splnet(); 2205 switch (why) { 2206 case PWR_STANDBY: 2207 case PWR_SUSPEND: 2208 cs_stop(ifp, 0); 2209 break; 2210 case PWR_RESUME: 2211 if (ifp->if_flags & IFF_UP) { 2212 cs_init(ifp); 2213 } 2214 break; 2215 case PWR_SOFTSUSPEND: 2216 case PWR_SOFTSTANDBY: 2217 case PWR_SOFTRESUME: 2218 break; 2219 } 2220 splx(s); 2221 }
Cache object: 201d0de692379851f7e1ab68f83f9e7e
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