The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/dptreg.h

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    1 /*      $OpenBSD: dptreg.h,v 1.3 2001/07/26 03:55:54 mickey Exp $       */
    2 /*      $NetBSD: dptreg.h,v 1.4 1999/10/19 20:16:48 ad Exp $    */
    3 
    4 /*
    5  * Copyright (c) 1999 Andy Doran <ad@NetBSD.org>
    6  * All rights reserved.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  */
   30 
   31 #ifndef _IC_DPTREG_H_
   32 #define _IC_DPTREG_H_ 1
   33 
   34 /* Hardware limits */
   35 #define DPT_MAX_TARGETS         16
   36 #define DPT_MAX_LUNS            8
   37 #define DPT_MAX_CHANNELS        3
   38 
   39 /* Software parameters */
   40 #define DPT_MAX_XFER            ((DPT_SG_SIZE - 1) << PGSHIFT)
   41 #define DPT_MAX_CCBS            256
   42 #define DPT_SG_SIZE             64
   43 #define DPT_ABORT_TIMEOUT       2000    /* milliseconds */
   44 #define DPT_MORE_TIMEOUT        1000    /* microseconds */
   45 
   46 #ifdef _KERNEL
   47 
   48 #if BYTE_ORDER == LITTLE_ENDIAN
   49 #define SWAP32(x)       bswap32((x))
   50 #define SWAP16(x)       bswap16((x))
   51 #define RSWAP32(x)      (x)
   52 #define RSWAP16(x)      (x)
   53 #else
   54 #define SWAP32(x)       (x)
   55 #define SWAP16(x)       (x)
   56 #define RSWAP32(x)      bswap32((x))
   57 #define RSWAP16(x)      bswap16((x))
   58 #endif
   59 
   60 #ifdef __OpenBSD__
   61 #define bswap16 swap16
   62 #define bswap32 swap32
   63 #endif
   64 
   65 #define dpt_inb(x, o)   \
   66     bus_space_read_1((x)->sc_iot, (x)->sc_ioh, (o))
   67 
   68 #define dpt_inw(x, o)   \
   69     RSWAP16(bus_space_read_2((x)->sc_iot, (x)->sc_ioh, (o)))
   70 
   71 #define dpt_inl(x, o)   \
   72     RSWAP32(bus_space_read_4((x)->sc_iot, (x)->sc_ioh, (o)))
   73 
   74 #define dpt_outb(x, o, d) \
   75     bus_space_write_1((x)->sc_iot, (x)->sc_ioh, (o), (d))
   76 
   77 #define dpt_outw(x, o, d) \
   78     bus_space_write_2((x)->sc_iot, (x)->sc_ioh, (o), RSWAP16(d))
   79 
   80 #define dpt_outl(x, o, d) \
   81     bus_space_write_4((x)->sc_iot, (x)->sc_ioh, (o), RSWAP32(d))
   82 
   83 #endif  /* _KERNEL */
   84  
   85 /*
   86  * HBA registers
   87  */
   88 #define HA_BASE                 0x10
   89 #define HA_DATA                 (HA_BASE + 0)
   90 #define HA_ERROR                (HA_BASE + 1)
   91 #define HA_DMA_BASE             (HA_BASE + 2)
   92 #define HA_ICMD_CODE2           (HA_BASE + 4)
   93 #define HA_ICMD_CODE1           (HA_BASE + 5)
   94 #define HA_ICMD                 (HA_BASE + 6)
   95 
   96 /* EATA commands. There are many more the we don't define or use. */
   97 #define HA_COMMAND              (HA_BASE + 7)
   98 #define   CP_PIO_GETCFG         0xf0    /* Read configuration data, PIO */
   99 #define   CP_PIO_CMD            0xf2    /* Execute command, PIO */
  100 #define   CP_DMA_GETCFG         0xfd    /* Read configuration data, DMA */
  101 #define   CP_DMA_CMD            0xff    /* Execute command, DMA */
  102 #define   CP_PIO_TRUNCATE       0xf4    /* Truncate transfer command, PIO */
  103 #define   CP_RESET              0xf9    /* Reset controller and SCSI bus */
  104 #define   CP_REBOOT             0x06    /* Reboot controller (last resort) */
  105 #define   CP_IMMEDIATE          0xfa    /* EATA immediate command */
  106 #define     CPI_GEN_ABORT       0x00    /* Generic abort */
  107 #define     CPI_SPEC_RESET      0x01    /* Specific reset */
  108 #define     CPI_BUS_RESET       0x02    /* Bus reset */
  109 #define     CPI_SPEC_ABORT      0x03    /* Specific abort */
  110 #define     CPI_QUIET_INTR      0x04    /* ?? */
  111 #define     CPI_ROM_DL_EN       0x05    /* ?? */
  112 #define     CPI_COLD_BOOT       0x06    /* Cold boot HBA */
  113 #define     CPI_FORCE_IO        0x07    /* ?? */
  114 #define     CPI_BUS_OFFLINE     0x08    /* Set SCSI bus offline */
  115 #define     CPI_RESET_MSKD_BUS  0x09    /* Reset masked bus */
  116 #define     CPI_POWEROFF_WARN   0x0a    /* Power about to fail */
  117 
  118 #define HA_STATUS               (HA_BASE + 7)
  119 #define   HA_ST_ERROR           0x01
  120 #define   HA_ST_MORE            0x02
  121 #define   HA_ST_CORRECTD        0x04
  122 #define   HA_ST_DRQ             0x08
  123 #define   HA_ST_SEEK_COMPLETE   0x10
  124 #define   HA_ST_WRT_FLT         0x20
  125 #define   HA_ST_READY           0x40
  126 #define   HA_ST_BUSY            0x80
  127 #define   HA_ST_DATA_RDY        (HA_ST_SEEK_COMPLETE|HA_ST_READY|HA_ST_DRQ)
  128 
  129 #define HA_AUX_STATUS           (HA_BASE + 8)
  130 #define   HA_AUX_BUSY           0x01
  131 #define   HA_AUX_INTR           0x02
  132 
  133 /*
  134  * Structure of an EATA command packet.
  135  */
  136 struct eata_cp {
  137         u_int8_t        cp_scsireset    :1;     /* cause a bus reset */
  138         u_int8_t        cp_hbainit      :1;     /* cause HBA to reinitialize */
  139         u_int8_t        cp_autosense    :1;     /* auto request sense on err */
  140         u_int8_t        cp_scatter      :1;     /* doing SG I/O */
  141         u_int8_t        cp_quick        :1;     /* return no status packet */
  142         u_int8_t        cp_interpret    :1;     /* HBA interprets SCSI CDB */
  143         u_int8_t        cp_dataout      :1;     /* data out phase */
  144         u_int8_t        cp_datain       :1;     /* data in phase */
  145         u_int8_t        cp_senselen;            /* request sense length */
  146         u_int8_t        cp_unused0[3];          /* unused */
  147         u_int8_t        cp_tophys       :1;     /* send to RAID component */
  148         u_int8_t        cp_unused1      :7;     /* unused */
  149         u_int8_t        cp_physunit     :1;     /* phys unit on mirrored pair */
  150         u_int8_t        cp_noat         :1;     /* no address translation */
  151         u_int8_t        cp_nocache      :1;     /* no HBA caching */
  152         u_int8_t        cp_unused2      :5;     /* unused */
  153         u_int8_t        cp_id           :5;     /* SCSI device id of target */
  154         u_int8_t        cp_channel      :3;     /* SCSI channel id */
  155         u_int8_t        cp_lun          :3;     /* SCSI LUN id */
  156         u_int8_t        cp_unused3      :2;     /* unused */
  157         u_int8_t        cp_luntar       :1;     /* CP is for target ROUTINE */
  158         u_int8_t        cp_dispri       :1;     /* give disconnect privilege */
  159         u_int8_t        cp_identify     :1;     /* always true */
  160         u_int8_t        cp_msg[3];              /* message bytes 0-3 */
  161 
  162         /* Partial SCSI CDB ref */
  163         u_int8_t        cp_scsi_cmd;
  164         u_int8_t        cp_extent       :1;
  165         u_int8_t        cp_bytchk       :1;
  166         u_int8_t        cp_reladr       :1;
  167         u_int8_t        cp_cmplst       :1;
  168         u_int8_t        cp_fmtdata      :1;
  169         u_int8_t        cp_cdblun       :3;
  170         u_int8_t        cp_page;
  171         u_int8_t        cp_unused4;
  172         u_int8_t        cp_len;
  173         u_int8_t        cp_link         :1;
  174         u_int8_t        cp_flag         :1;
  175         u_int8_t        cp_unused5      :4;
  176         u_int8_t        cp_vendor       :2;
  177         u_int8_t        cp_cdbmore[6];
  178 
  179         u_int32_t       cp_datalen;     /* length in bytes of data/SG list */
  180         u_int32_t       cp_ccbid;       /* ID of software CCB */
  181         u_int32_t       cp_dataaddr;    /* address of data/SG list */
  182         u_int32_t       cp_stataddr;    /* addr for status packet */
  183         u_int32_t       cp_senseaddr;   /* addr of req. sense (err only) */
  184 };
  185 
  186 /*
  187  * EATA status packet as returned by controller upon command completion. It 
  188  * contains status, message info and a handle on the initiating CCB. 
  189  */
  190 struct eata_sp {
  191         u_int8_t        sp_hba_status;          /* host adapter status */
  192         u_int8_t        sp_scsi_status;         /* SCSI bus status */
  193         u_int8_t        sp_reserved[2];         /* reserved */
  194         u_int32_t       sp_inv_residue;         /* bytes not transferred */
  195         u_int32_t       sp_ccbid;               /* ID of software CCB */
  196         u_int8_t        sp_id_message;
  197         u_int8_t        sp_que_message;
  198         u_int8_t        sp_tag_message;
  199         u_int8_t        sp_messages[9];
  200 };
  201 
  202 /* 
  203  * HBA status as returned by status packet. Bit 7 signals end of command. 
  204  */
  205 #define HA_NO_ERROR             0x00    /* No error on command */
  206 #define HA_ERROR_SEL_TO         0x01    /* Device selection timeout */
  207 #define HA_ERROR_CMD_TO         0x02    /* Device command timeout */
  208 #define HA_ERROR_RESET          0x03    /* SCSI bus was reset */
  209 #define HA_INIT_POWERUP         0x04    /* Initial controller power up */
  210 #define HA_UNX_BUSPHASE         0x05    /* Unexpected bus phase */
  211 #define HA_UNX_BUS_FREE         0x06    /* Unexpected bus free */
  212 #define HA_BUS_PARITY           0x07    /* SCSI bus parity error */
  213 #define HA_SCSI_HUNG            0x08    /* SCSI bus hung */
  214 #define HA_UNX_MSGRJCT          0x09    /* Unexpected message reject */
  215 #define HA_RESET_STUCK          0x0A    /* SCSI bus reset stuck */
  216 #define HA_RSENSE_FAIL          0x0B    /* Auto-request sense failed */
  217 #define HA_PARITY               0x0C    /* HBA memory parity error */
  218 #define HA_ABORT_NA             0x0D    /* CP aborted - not on bus */
  219 #define HA_ABORTED              0x0E    /* CP aborted - was on bus */
  220 #define HA_RESET_NA             0x0F    /* CP reset - not on bus */
  221 #define HA_RESET                0x10    /* CP reset - was on bus */
  222 #define HA_ECC                  0x11    /* HBA memory ECC error */
  223 #define HA_PCI_PARITY           0x12    /* PCI parity error */
  224 #define HA_PCI_MASTER           0x13    /* PCI master abort */
  225 #define HA_PCI_TARGET           0x14    /* PCI target abort */
  226 #define HA_PCI_SIGNAL_TARGET    0x15    /* PCI signalled target abort */
  227 #define HA_ABORT                0x20    /* Software abort (too many retries) */
  228 
  229 /*
  230  * Scatter-gather list element.
  231  */
  232 struct eata_sg {
  233         u_int32_t       sg_addr;
  234         u_int32_t       sg_len;
  235 };
  236 
  237 /*
  238  * EATA configuration data as returned by HBA. XXX this is bogus, some fields
  239  * don't *seem* to be filled on my SmartCache III. Also, it doesn't sync up 
  240  * with the structure FreeBSD uses. [ad]
  241  */
  242 struct eata_cfg {
  243         u_int8_t  ec_devtype;
  244         u_int8_t  ec_pagecode;
  245         u_int8_t  ec_reserved0;
  246         u_int8_t  ec_cfglen;            /* Length in bytes after this field */
  247         u_int8_t  ec_eatasig[4];        /* EATA signature  */
  248         u_int8_t  ec_eataversion;       /* EATA version number */
  249         u_int8_t  ec_overlapcmds : 1;   /* Overlapped cmds supported */
  250         u_int8_t  ec_targetmode : 1;    /* Target mode supported */
  251         u_int8_t  ec_trunnotrec : 1;    /* Truncate cmd not supported */
  252         u_int8_t  ec_moresupported:1;   /* More cmd supported */
  253         u_int8_t  ec_dmasupported : 1;  /* DMA mode supported */
  254         u_int8_t  ec_dmanumvalid : 1;   /* DMA channel field is valid */
  255         u_int8_t  ec_atadev : 1;        /* This is an ATA device */
  256         u_int8_t  ec_hbavalid : 1;      /* HBA field is valid */
  257         u_int8_t  ec_padlength[2];      /* Pad bytes for PIO cmds */
  258         u_int8_t  ec_hba[4];            /* Host adapter SCSI IDs */
  259         u_int8_t  ec_cplen[4];          /* Command packet length */
  260         u_int8_t  ec_splen[4];          /* Status packet length */
  261         u_int8_t  ec_queuedepth[2];     /* Controller queue depth */
  262         u_int8_t  ec_reserved1[2];
  263         u_int8_t  ec_sglen[2];          /* Maximum scatter gather list size */
  264         u_int8_t  ec_irqnum : 4;        /* IRQ number */
  265         u_int8_t  ec_irqtrigger : 1;    /* IRQ trigger: 0 = edge, 1 = level */
  266         u_int8_t  ec_secondary : 1;     /* Controller not at address 0x170 */
  267         u_int8_t  ec_dmanum : 2;        /* DMA channel index for ISA */
  268         u_int8_t  ec_irq;               /* IRQ address */
  269         u_int8_t  ec_iodisable : 1;     /* ISA I/O address disabled */
  270         u_int8_t  ec_forceaddr : 1;     /* PCI forced to an EISA/ISA addr */
  271         u_int8_t  ec_sg64k : 1;         /* 64K of SG space */
  272         u_int8_t  ec_sgunaligned : 1;   /* Can do unaligned SG, otherwise 4 */
  273         u_int8_t  ec_reserved2 : 4;     /* Reserved */
  274         u_int8_t  ec_maxtarget : 5;     /* Maximun SCSI target ID supported */
  275         u_int8_t  ec_maxchannel : 3;    /* Maximun channel number supported */
  276         u_int8_t  ec_maxlun;            /* Maximum LUN supported */
  277         u_int8_t  ec_reserved3 : 3;     /* Reserved field */
  278         u_int8_t  ec_autoterm : 1;      /* Support auto term (low byte) */
  279         u_int8_t  ec_pcim1 : 1;         /* PCI M1 chipset */
  280         u_int8_t  ec_bogusraidid : 1;   /* Raid ID may be questionable  */
  281         u_int8_t  ec_pci : 1;           /* PCI adapter */
  282         u_int8_t  ec_eisa : 1;          /* EISA adapter */
  283         u_int8_t  ec_raidnum;           /* RAID host adapter humber */
  284 };
  285 
  286 /*
  287  * How SCSI inquiry data breaks down for EATA boards.
  288  */
  289 struct eata_inquiry_data {
  290         u_int8_t        ei_device;
  291         u_int8_t        ei_dev_qual2;
  292         u_int8_t        ei_version;
  293         u_int8_t        ei_response_format;
  294         u_int8_t        ei_additional_length;
  295         u_int8_t        ei_unused[2];
  296         u_int8_t        ei_flags;       
  297         char            ei_vendor[8];   /* Vendor, e.g: DPT, NEC */
  298         char            ei_model[7];    /* Model number */
  299         char            ei_suffix[9];   /* Model number suffix */
  300         char            ei_fw[3];       /* Firmware */
  301         char            ei_fwrev[1];    /* Firmware revision */
  302         u_int8_t        ei_extra[8];
  303 };
  304 
  305 #endif  /* !defined _IC_DPTREG_H_ */

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