FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/elinkxl.c
1 /* $NetBSD: elinkxl.c,v 1.72.2.1 2004/07/02 18:32:55 he Exp $ */
2
3 /*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Frank van der Linden.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: elinkxl.c,v 1.72.2.1 2004/07/02 18:32:55 he Exp $");
41
42 #include "bpfilter.h"
43 #include "rnd.h"
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/callout.h>
48 #include <sys/kernel.h>
49 #include <sys/mbuf.h>
50 #include <sys/socket.h>
51 #include <sys/ioctl.h>
52 #include <sys/errno.h>
53 #include <sys/syslog.h>
54 #include <sys/select.h>
55 #include <sys/device.h>
56 #if NRND > 0
57 #include <sys/rnd.h>
58 #endif
59
60 #include <uvm/uvm_extern.h>
61
62 #include <net/if.h>
63 #include <net/if_dl.h>
64 #include <net/if_ether.h>
65 #include <net/if_media.h>
66
67 #if NBPFILTER > 0
68 #include <net/bpf.h>
69 #include <net/bpfdesc.h>
70 #endif
71
72 #include <machine/cpu.h>
73 #include <machine/bus.h>
74 #include <machine/intr.h>
75 #include <machine/endian.h>
76
77 #include <dev/mii/miivar.h>
78 #include <dev/mii/mii.h>
79 #include <dev/mii/mii_bitbang.h>
80
81 #include <dev/ic/elink3reg.h>
82 /* #include <dev/ic/elink3var.h> */
83 #include <dev/ic/elinkxlreg.h>
84 #include <dev/ic/elinkxlvar.h>
85
86 #ifdef DEBUG
87 int exdebug = 0;
88 #endif
89
90 /* ifmedia callbacks */
91 int ex_media_chg __P((struct ifnet *ifp));
92 void ex_media_stat __P((struct ifnet *ifp, struct ifmediareq *req));
93
94 void ex_probe_media __P((struct ex_softc *));
95 void ex_set_filter __P((struct ex_softc *));
96 void ex_set_media __P((struct ex_softc *));
97 void ex_set_xcvr __P((struct ex_softc *, u_int16_t));
98 struct mbuf *ex_get __P((struct ex_softc *, int));
99 u_int16_t ex_read_eeprom __P((struct ex_softc *, int));
100 int ex_init __P((struct ifnet *));
101 void ex_read __P((struct ex_softc *));
102 void ex_reset __P((struct ex_softc *));
103 void ex_set_mc __P((struct ex_softc *));
104 void ex_getstats __P((struct ex_softc *));
105 void ex_printstats __P((struct ex_softc *));
106 void ex_tick __P((void *));
107
108 void ex_power __P((int, void *));
109
110 static int ex_eeprom_busy __P((struct ex_softc *));
111 static int ex_add_rxbuf __P((struct ex_softc *, struct ex_rxdesc *));
112 static void ex_init_txdescs __P((struct ex_softc *));
113
114 static void ex_shutdown __P((void *));
115 static void ex_start __P((struct ifnet *));
116 static void ex_txstat __P((struct ex_softc *));
117
118 int ex_mii_readreg __P((struct device *, int, int));
119 void ex_mii_writereg __P((struct device *, int, int, int));
120 void ex_mii_statchg __P((struct device *));
121
122 void ex_probemedia __P((struct ex_softc *));
123
124 /*
125 * Structure to map media-present bits in boards to ifmedia codes and
126 * printable media names. Used for table-driven ifmedia initialization.
127 */
128 struct ex_media {
129 int exm_mpbit; /* media present bit */
130 const char *exm_name; /* name of medium */
131 int exm_ifmedia; /* ifmedia word for medium */
132 int exm_epmedia; /* ELINKMEDIA_* constant */
133 };
134
135 /*
136 * Media table for 3c90x chips. Note that chips with MII have no
137 * `native' media.
138 */
139 struct ex_media ex_native_media[] = {
140 { ELINK_PCI_10BASE_T, "10baseT", IFM_ETHER|IFM_10_T,
141 ELINKMEDIA_10BASE_T },
142 { ELINK_PCI_10BASE_T, "10baseT-FDX", IFM_ETHER|IFM_10_T|IFM_FDX,
143 ELINKMEDIA_10BASE_T },
144 { ELINK_PCI_AUI, "10base5", IFM_ETHER|IFM_10_5,
145 ELINKMEDIA_AUI },
146 { ELINK_PCI_BNC, "10base2", IFM_ETHER|IFM_10_2,
147 ELINKMEDIA_10BASE_2 },
148 { ELINK_PCI_100BASE_TX, "100baseTX", IFM_ETHER|IFM_100_TX,
149 ELINKMEDIA_100BASE_TX },
150 { ELINK_PCI_100BASE_TX, "100baseTX-FDX",IFM_ETHER|IFM_100_TX|IFM_FDX,
151 ELINKMEDIA_100BASE_TX },
152 { ELINK_PCI_100BASE_FX, "100baseFX", IFM_ETHER|IFM_100_FX,
153 ELINKMEDIA_100BASE_FX },
154 { ELINK_PCI_100BASE_MII,"manual", IFM_ETHER|IFM_MANUAL,
155 ELINKMEDIA_MII },
156 { ELINK_PCI_100BASE_T4, "100baseT4", IFM_ETHER|IFM_100_T4,
157 ELINKMEDIA_100BASE_T4 },
158 { 0, NULL, 0,
159 0 },
160 };
161
162 /*
163 * MII bit-bang glue.
164 */
165 u_int32_t ex_mii_bitbang_read __P((struct device *));
166 void ex_mii_bitbang_write __P((struct device *, u_int32_t));
167
168 const struct mii_bitbang_ops ex_mii_bitbang_ops = {
169 ex_mii_bitbang_read,
170 ex_mii_bitbang_write,
171 {
172 ELINK_PHY_DATA, /* MII_BIT_MDO */
173 ELINK_PHY_DATA, /* MII_BIT_MDI */
174 ELINK_PHY_CLK, /* MII_BIT_MDC */
175 ELINK_PHY_DIR, /* MII_BIT_DIR_HOST_PHY */
176 0, /* MII_BIT_DIR_PHY_HOST */
177 }
178 };
179
180 /*
181 * Back-end attach and configure.
182 */
183 void
184 ex_config(sc)
185 struct ex_softc *sc;
186 {
187 struct ifnet *ifp;
188 u_int16_t val;
189 u_int8_t macaddr[ETHER_ADDR_LEN] = {0};
190 bus_space_tag_t iot = sc->sc_iot;
191 bus_space_handle_t ioh = sc->sc_ioh;
192 int i, error, attach_stage;
193
194 callout_init(&sc->ex_mii_callout);
195
196 ex_reset(sc);
197
198 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR0);
199 macaddr[0] = val >> 8;
200 macaddr[1] = val & 0xff;
201 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR1);
202 macaddr[2] = val >> 8;
203 macaddr[3] = val & 0xff;
204 val = ex_read_eeprom(sc, EEPROM_OEM_ADDR2);
205 macaddr[4] = val >> 8;
206 macaddr[5] = val & 0xff;
207
208 aprint_normal("%s: MAC address %s\n", sc->sc_dev.dv_xname,
209 ether_sprintf(macaddr));
210
211 if (sc->ex_conf & (EX_CONF_INV_LED_POLARITY|EX_CONF_PHY_POWER)) {
212 GO_WINDOW(2);
213 val = bus_space_read_2(iot, ioh, ELINK_W2_RESET_OPTIONS);
214 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY)
215 val |= ELINK_RESET_OPT_LEDPOLAR;
216 if (sc->ex_conf & EX_CONF_PHY_POWER)
217 val |= ELINK_RESET_OPT_PHYPOWER;
218 bus_space_write_2(iot, ioh, ELINK_W2_RESET_OPTIONS, val);
219 }
220 if (sc->ex_conf & EX_CONF_NO_XCVR_PWR) {
221 GO_WINDOW(0);
222 bus_space_write_2(iot, ioh, ELINK_W0_MFG_ID,
223 EX_XCVR_PWR_MAGICBITS);
224 }
225
226 attach_stage = 0;
227
228 /*
229 * Allocate the upload descriptors, and create and load the DMA
230 * map for them.
231 */
232 if ((error = bus_dmamem_alloc(sc->sc_dmat,
233 EX_NUPD * sizeof (struct ex_upd), PAGE_SIZE, 0, &sc->sc_useg, 1,
234 &sc->sc_urseg, BUS_DMA_NOWAIT)) != 0) {
235 aprint_error(
236 "%s: can't allocate upload descriptors, error = %d\n",
237 sc->sc_dev.dv_xname, error);
238 goto fail;
239 }
240
241 attach_stage = 1;
242
243 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg,
244 EX_NUPD * sizeof (struct ex_upd), (caddr_t *)&sc->sc_upd,
245 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
246 aprint_error("%s: can't map upload descriptors, error = %d\n",
247 sc->sc_dev.dv_xname, error);
248 goto fail;
249 }
250
251 attach_stage = 2;
252
253 if ((error = bus_dmamap_create(sc->sc_dmat,
254 EX_NUPD * sizeof (struct ex_upd), 1,
255 EX_NUPD * sizeof (struct ex_upd), 0, BUS_DMA_NOWAIT,
256 &sc->sc_upd_dmamap)) != 0) {
257 aprint_error(
258 "%s: can't create upload desc. DMA map, error = %d\n",
259 sc->sc_dev.dv_xname, error);
260 goto fail;
261 }
262
263 attach_stage = 3;
264
265 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_upd_dmamap,
266 sc->sc_upd, EX_NUPD * sizeof (struct ex_upd), NULL,
267 BUS_DMA_NOWAIT)) != 0) {
268 aprint_error(
269 "%s: can't load upload desc. DMA map, error = %d\n",
270 sc->sc_dev.dv_xname, error);
271 goto fail;
272 }
273
274 attach_stage = 4;
275
276 /*
277 * Allocate the download descriptors, and create and load the DMA
278 * map for them.
279 */
280 if ((error = bus_dmamem_alloc(sc->sc_dmat,
281 EX_NDPD * sizeof (struct ex_dpd), PAGE_SIZE, 0, &sc->sc_dseg, 1,
282 &sc->sc_drseg, BUS_DMA_NOWAIT)) != 0) {
283 aprint_error(
284 "%s: can't allocate download descriptors, error = %d\n",
285 sc->sc_dev.dv_xname, error);
286 goto fail;
287 }
288
289 attach_stage = 5;
290
291 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg,
292 EX_NDPD * sizeof (struct ex_dpd), (caddr_t *)&sc->sc_dpd,
293 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
294 aprint_error("%s: can't map download descriptors, error = %d\n",
295 sc->sc_dev.dv_xname, error);
296 goto fail;
297 }
298 memset(sc->sc_dpd, 0, EX_NDPD * sizeof (struct ex_dpd));
299
300 attach_stage = 6;
301
302 if ((error = bus_dmamap_create(sc->sc_dmat,
303 EX_NDPD * sizeof (struct ex_dpd), 1,
304 EX_NDPD * sizeof (struct ex_dpd), 0, BUS_DMA_NOWAIT,
305 &sc->sc_dpd_dmamap)) != 0) {
306 aprint_error(
307 "%s: can't create download desc. DMA map, error = %d\n",
308 sc->sc_dev.dv_xname, error);
309 goto fail;
310 }
311
312 attach_stage = 7;
313
314 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dpd_dmamap,
315 sc->sc_dpd, EX_NDPD * sizeof (struct ex_dpd), NULL,
316 BUS_DMA_NOWAIT)) != 0) {
317 aprint_error(
318 "%s: can't load download desc. DMA map, error = %d\n",
319 sc->sc_dev.dv_xname, error);
320 goto fail;
321 }
322
323 attach_stage = 8;
324
325
326 /*
327 * Create the transmit buffer DMA maps.
328 */
329 for (i = 0; i < EX_NDPD; i++) {
330 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
331 EX_NTFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
332 &sc->sc_tx_dmamaps[i])) != 0) {
333 aprint_error(
334 "%s: can't create tx DMA map %d, error = %d\n",
335 sc->sc_dev.dv_xname, i, error);
336 goto fail;
337 }
338 }
339
340 attach_stage = 9;
341
342 /*
343 * Create the receive buffer DMA maps.
344 */
345 for (i = 0; i < EX_NUPD; i++) {
346 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
347 EX_NRFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
348 &sc->sc_rx_dmamaps[i])) != 0) {
349 aprint_error(
350 "%s: can't create rx DMA map %d, error = %d\n",
351 sc->sc_dev.dv_xname, i, error);
352 goto fail;
353 }
354 }
355
356 attach_stage = 10;
357
358 /*
359 * Create ring of upload descriptors, only once. The DMA engine
360 * will loop over this when receiving packets, stalling if it
361 * hits an UPD with a finished receive.
362 */
363 for (i = 0; i < EX_NUPD; i++) {
364 sc->sc_rxdescs[i].rx_dmamap = sc->sc_rx_dmamaps[i];
365 sc->sc_rxdescs[i].rx_upd = &sc->sc_upd[i];
366 sc->sc_upd[i].upd_frags[0].fr_len =
367 htole32((MCLBYTES - 2) | EX_FR_LAST);
368 if (ex_add_rxbuf(sc, &sc->sc_rxdescs[i]) != 0) {
369 aprint_error("%s: can't allocate or map rx buffers\n",
370 sc->sc_dev.dv_xname);
371 goto fail;
372 }
373 }
374
375 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap, 0,
376 EX_NUPD * sizeof (struct ex_upd),
377 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
378
379 ex_init_txdescs(sc);
380
381 attach_stage = 11;
382
383
384 GO_WINDOW(3);
385 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS);
386 if (val & ELINK_MEDIACAP_MII)
387 sc->ex_conf |= EX_CONF_MII;
388
389 ifp = &sc->sc_ethercom.ec_if;
390
391 /*
392 * Initialize our media structures and MII info. We'll
393 * probe the MII if we discover that we have one.
394 */
395 sc->ex_mii.mii_ifp = ifp;
396 sc->ex_mii.mii_readreg = ex_mii_readreg;
397 sc->ex_mii.mii_writereg = ex_mii_writereg;
398 sc->ex_mii.mii_statchg = ex_mii_statchg;
399 ifmedia_init(&sc->ex_mii.mii_media, IFM_IMASK, ex_media_chg,
400 ex_media_stat);
401
402 if (sc->ex_conf & EX_CONF_MII) {
403 /*
404 * Find PHY, extract media information from it.
405 * First, select the right transceiver.
406 */
407 ex_set_xcvr(sc, val);
408
409 mii_attach(&sc->sc_dev, &sc->ex_mii, 0xffffffff,
410 MII_PHY_ANY, MII_OFFSET_ANY, 0);
411 if (LIST_FIRST(&sc->ex_mii.mii_phys) == NULL) {
412 ifmedia_add(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE,
413 0, NULL);
414 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_NONE);
415 } else {
416 ifmedia_set(&sc->ex_mii.mii_media, IFM_ETHER|IFM_AUTO);
417 }
418 } else
419 ex_probemedia(sc);
420
421 strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
422 ifp->if_softc = sc;
423 ifp->if_start = ex_start;
424 ifp->if_ioctl = ex_ioctl;
425 ifp->if_watchdog = ex_watchdog;
426 ifp->if_init = ex_init;
427 ifp->if_stop = ex_stop;
428 ifp->if_flags =
429 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
430 IFQ_SET_READY(&ifp->if_snd);
431
432 /*
433 * We can support 802.1Q VLAN-sized frames.
434 */
435 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
436
437 /*
438 * The 3c90xB has hardware IPv4/TCPv4/UDPv4 checksum support.
439 */
440 if (sc->ex_conf & EX_CONF_90XB)
441 sc->sc_ethercom.ec_if.if_capabilities |= IFCAP_CSUM_IPv4 |
442 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4;
443
444 if_attach(ifp);
445 ether_ifattach(ifp, macaddr);
446
447 GO_WINDOW(1);
448
449 sc->tx_start_thresh = 20;
450 sc->tx_succ_ok = 0;
451
452 /* TODO: set queues to 0 */
453
454 #if NRND > 0
455 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname,
456 RND_TYPE_NET, 0);
457 #endif
458
459 /* Establish callback to reset card when we reboot. */
460 sc->sc_sdhook = shutdownhook_establish(ex_shutdown, sc);
461 if (sc->sc_sdhook == NULL)
462 aprint_error("%s: WARNING: unable to establish shutdown hook\n",
463 sc->sc_dev.dv_xname);
464
465 /* Add a suspend hook to make sure we come back up after a resume. */
466 sc->sc_powerhook = powerhook_establish(ex_power, sc);
467 if (sc->sc_powerhook == NULL)
468 aprint_error("%s: WARNING: unable to establish power hook\n",
469 sc->sc_dev.dv_xname);
470
471 /* The attach is successful. */
472 sc->ex_flags |= EX_FLAGS_ATTACHED;
473 return;
474
475 fail:
476 /*
477 * Free any resources we've allocated during the failed attach
478 * attempt. Do this in reverse order and fall though.
479 */
480 switch (attach_stage) {
481 case 11:
482 {
483 struct ex_rxdesc *rxd;
484
485 for (i = 0; i < EX_NUPD; i++) {
486 rxd = &sc->sc_rxdescs[i];
487 if (rxd->rx_mbhead != NULL) {
488 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
489 m_freem(rxd->rx_mbhead);
490 }
491 }
492 }
493 /* FALLTHROUGH */
494
495 case 10:
496 for (i = 0; i < EX_NUPD; i++)
497 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]);
498 /* FALLTHROUGH */
499
500 case 9:
501 for (i = 0; i < EX_NDPD; i++)
502 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]);
503 /* FALLTHROUGH */
504 case 8:
505 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap);
506 /* FALLTHROUGH */
507
508 case 7:
509 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap);
510 /* FALLTHROUGH */
511
512 case 6:
513 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd,
514 EX_NDPD * sizeof (struct ex_dpd));
515 /* FALLTHROUGH */
516
517 case 5:
518 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg);
519 break;
520
521 case 4:
522 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap);
523 /* FALLTHROUGH */
524
525 case 3:
526 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap);
527 /* FALLTHROUGH */
528
529 case 2:
530 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd,
531 EX_NUPD * sizeof (struct ex_upd));
532 /* FALLTHROUGH */
533
534 case 1:
535 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg);
536 break;
537 }
538
539 }
540
541 /*
542 * Find the media present on non-MII chips.
543 */
544 void
545 ex_probemedia(sc)
546 struct ex_softc *sc;
547 {
548 bus_space_tag_t iot = sc->sc_iot;
549 bus_space_handle_t ioh = sc->sc_ioh;
550 struct ifmedia *ifm = &sc->ex_mii.mii_media;
551 struct ex_media *exm;
552 u_int16_t config1, reset_options, default_media;
553 int defmedia = 0;
554 const char *sep = "", *defmedianame = NULL;
555
556 GO_WINDOW(3);
557 config1 = bus_space_read_2(iot, ioh, ELINK_W3_INTERNAL_CONFIG + 2);
558 reset_options = bus_space_read_1(iot, ioh, ELINK_W3_RESET_OPTIONS);
559 GO_WINDOW(0);
560
561 default_media = (config1 & CONFIG_MEDIAMASK) >> CONFIG_MEDIAMASK_SHIFT;
562
563 aprint_normal("%s: ", sc->sc_dev.dv_xname);
564
565 /* Sanity check that there are any media! */
566 if ((reset_options & ELINK_PCI_MEDIAMASK) == 0) {
567 aprint_error("no media present!\n");
568 ifmedia_add(ifm, IFM_ETHER|IFM_NONE, 0, NULL);
569 ifmedia_set(ifm, IFM_ETHER|IFM_NONE);
570 return;
571 }
572
573 #define PRINT(str) aprint_normal("%s%s", sep, str); sep = ", "
574
575 for (exm = ex_native_media; exm->exm_name != NULL; exm++) {
576 if (reset_options & exm->exm_mpbit) {
577 /*
578 * Default media is a little complicated. We
579 * support full-duplex which uses the same
580 * reset options bit.
581 *
582 * XXX Check EEPROM for default to FDX?
583 */
584 if (exm->exm_epmedia == default_media) {
585 if ((exm->exm_ifmedia & IFM_FDX) == 0) {
586 defmedia = exm->exm_ifmedia;
587 defmedianame = exm->exm_name;
588 }
589 } else if (defmedia == 0) {
590 defmedia = exm->exm_ifmedia;
591 defmedianame = exm->exm_name;
592 }
593 ifmedia_add(ifm, exm->exm_ifmedia, exm->exm_epmedia,
594 NULL);
595 PRINT(exm->exm_name);
596 }
597 }
598
599 #undef PRINT
600
601 #ifdef DIAGNOSTIC
602 if (defmedia == 0)
603 panic("ex_probemedia: impossible");
604 #endif
605
606 aprint_normal(", default %s\n", defmedianame);
607 ifmedia_set(ifm, defmedia);
608 }
609
610 /*
611 * Bring device up.
612 */
613 int
614 ex_init(ifp)
615 struct ifnet *ifp;
616 {
617 struct ex_softc *sc = ifp->if_softc;
618 bus_space_tag_t iot = sc->sc_iot;
619 bus_space_handle_t ioh = sc->sc_ioh;
620 int i;
621 int error = 0;
622
623 if ((error = ex_enable(sc)) != 0)
624 goto out;
625
626 ex_waitcmd(sc);
627 ex_stop(ifp, 0);
628
629 /*
630 * Set the station address and clear the station mask. The latter
631 * is needed for 90x cards, 0 is the default for 90xB cards.
632 */
633 GO_WINDOW(2);
634 for (i = 0; i < ETHER_ADDR_LEN; i++) {
635 bus_space_write_1(iot, ioh, ELINK_W2_ADDR_0 + i,
636 LLADDR(ifp->if_sadl)[i]);
637 bus_space_write_1(iot, ioh, ELINK_W2_RECVMASK_0 + i, 0);
638 }
639
640 GO_WINDOW(3);
641
642 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_RESET);
643 ex_waitcmd(sc);
644 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_RESET);
645 ex_waitcmd(sc);
646
647 /*
648 * Disable reclaim threshold for 90xB, set free threshold to
649 * 6 * 256 = 1536 for 90x.
650 */
651 if (sc->ex_conf & EX_CONF_90XB)
652 bus_space_write_2(iot, ioh, ELINK_COMMAND,
653 ELINK_TXRECLTHRESH | 255);
654 else
655 bus_space_write_1(iot, ioh, ELINK_TXFREETHRESH, 6);
656
657 bus_space_write_2(iot, ioh, ELINK_COMMAND,
658 SET_RX_EARLY_THRESH | ELINK_THRESH_DISABLE);
659
660 bus_space_write_4(iot, ioh, ELINK_DMACTRL,
661 bus_space_read_4(iot, ioh, ELINK_DMACTRL) | ELINK_DMAC_UPRXEAREN);
662
663 bus_space_write_2(iot, ioh, ELINK_COMMAND,
664 SET_RD_0_MASK | XL_WATCHED_INTERRUPTS);
665 bus_space_write_2(iot, ioh, ELINK_COMMAND,
666 SET_INTR_MASK | XL_WATCHED_INTERRUPTS);
667
668 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | 0xff);
669 if (sc->intr_ack)
670 (* sc->intr_ack)(sc);
671 ex_set_media(sc);
672 ex_set_mc(sc);
673
674
675 bus_space_write_2(iot, ioh, ELINK_COMMAND, STATS_ENABLE);
676 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE);
677 bus_space_write_4(iot, ioh, ELINK_UPLISTPTR, sc->sc_upddma);
678 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_ENABLE);
679 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_UPUNSTALL);
680
681 if (sc->ex_conf & (EX_CONF_PHY_POWER | EX_CONF_INV_LED_POLARITY)) {
682 u_int16_t cbcard_config;
683
684 GO_WINDOW(2);
685 cbcard_config = bus_space_read_2(sc->sc_iot, sc->sc_ioh, 0x0c);
686 if (sc->ex_conf & EX_CONF_PHY_POWER) {
687 cbcard_config |= 0x4000; /* turn on PHY power */
688 }
689 if (sc->ex_conf & EX_CONF_INV_LED_POLARITY) {
690 cbcard_config |= 0x0010; /* invert LED polarity */
691 }
692 bus_space_write_2(sc->sc_iot, sc->sc_ioh, 0x0c, cbcard_config);
693
694 GO_WINDOW(3);
695 }
696
697 ifp->if_flags |= IFF_RUNNING;
698 ifp->if_flags &= ~IFF_OACTIVE;
699 ex_start(ifp);
700
701 GO_WINDOW(1);
702
703 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc);
704
705 out:
706 if (error) {
707 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
708 ifp->if_timer = 0;
709 printf("%s: interface not running\n", sc->sc_dev.dv_xname);
710 }
711 return (error);
712 }
713
714 #define MCHASHSIZE 256
715 #define ex_mchash(addr) (ether_crc32_be((addr), ETHER_ADDR_LEN) & \
716 (MCHASHSIZE - 1))
717
718 /*
719 * Set multicast receive filter. Also take care of promiscuous mode
720 * here (XXX).
721 */
722 void
723 ex_set_mc(sc)
724 struct ex_softc *sc;
725 {
726 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
727 struct ethercom *ec = &sc->sc_ethercom;
728 struct ether_multi *enm;
729 struct ether_multistep estep;
730 int i;
731 u_int16_t mask = FIL_INDIVIDUAL | FIL_BRDCST;
732
733 if (ifp->if_flags & IFF_PROMISC) {
734 mask |= FIL_PROMISC;
735 goto allmulti;
736 }
737
738 ETHER_FIRST_MULTI(estep, ec, enm);
739 if (enm == NULL)
740 goto nomulti;
741
742 if ((sc->ex_conf & EX_CONF_90XB) == 0)
743 /* No multicast hash filtering. */
744 goto allmulti;
745
746 for (i = 0; i < MCHASHSIZE; i++)
747 bus_space_write_2(sc->sc_iot, sc->sc_ioh,
748 ELINK_COMMAND, ELINK_CLEARHASHFILBIT | i);
749
750 do {
751 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
752 ETHER_ADDR_LEN) != 0)
753 goto allmulti;
754
755 i = ex_mchash(enm->enm_addrlo);
756 bus_space_write_2(sc->sc_iot, sc->sc_ioh,
757 ELINK_COMMAND, ELINK_SETHASHFILBIT | i);
758 ETHER_NEXT_MULTI(estep, enm);
759 } while (enm != NULL);
760 mask |= FIL_MULTIHASH;
761
762 nomulti:
763 ifp->if_flags &= ~IFF_ALLMULTI;
764 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND,
765 SET_RX_FILTER | mask);
766 return;
767
768 allmulti:
769 ifp->if_flags |= IFF_ALLMULTI;
770 mask |= FIL_MULTICAST;
771 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND,
772 SET_RX_FILTER | mask);
773 }
774
775
776 static void
777 ex_txstat(sc)
778 struct ex_softc *sc;
779 {
780 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
781 bus_space_tag_t iot = sc->sc_iot;
782 bus_space_handle_t ioh = sc->sc_ioh;
783 int i;
784
785 /*
786 * We need to read+write TX_STATUS until we get a 0 status
787 * in order to turn off the interrupt flag.
788 */
789 while ((i = bus_space_read_1(iot, ioh, ELINK_TXSTATUS)) & TXS_COMPLETE) {
790 bus_space_write_1(iot, ioh, ELINK_TXSTATUS, 0x0);
791
792 if (i & TXS_JABBER) {
793 ++sc->sc_ethercom.ec_if.if_oerrors;
794 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG)
795 printf("%s: jabber (%x)\n",
796 sc->sc_dev.dv_xname, i);
797 ex_init(ifp);
798 /* TODO: be more subtle here */
799 } else if (i & TXS_UNDERRUN) {
800 ++sc->sc_ethercom.ec_if.if_oerrors;
801 if (sc->sc_ethercom.ec_if.if_flags & IFF_DEBUG)
802 printf("%s: fifo underrun (%x) @%d\n",
803 sc->sc_dev.dv_xname, i,
804 sc->tx_start_thresh);
805 if (sc->tx_succ_ok < 100)
806 sc->tx_start_thresh = min(ETHER_MAX_LEN,
807 sc->tx_start_thresh + 20);
808 sc->tx_succ_ok = 0;
809 ex_init(ifp);
810 /* TODO: be more subtle here */
811 } else if (i & TXS_MAX_COLLISION) {
812 ++sc->sc_ethercom.ec_if.if_collisions;
813 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_ENABLE);
814 sc->sc_ethercom.ec_if.if_flags &= ~IFF_OACTIVE;
815 } else
816 sc->tx_succ_ok = (sc->tx_succ_ok+1) & 127;
817 }
818 }
819
820 int
821 ex_media_chg(ifp)
822 struct ifnet *ifp;
823 {
824
825 if (ifp->if_flags & IFF_UP)
826 ex_init(ifp);
827 return 0;
828 }
829
830 void
831 ex_set_xcvr(sc, media)
832 struct ex_softc *sc;
833 const u_int16_t media;
834 {
835 bus_space_tag_t iot = sc->sc_iot;
836 bus_space_handle_t ioh = sc->sc_ioh;
837 u_int32_t icfg;
838
839 /*
840 * We're already in Window 3
841 */
842 icfg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG);
843 icfg &= ~(CONFIG_XCVR_SEL << 16);
844 if (media & (ELINK_MEDIACAP_MII | ELINK_MEDIACAP_100BASET4))
845 icfg |= ELINKMEDIA_MII << (CONFIG_XCVR_SEL_SHIFT + 16);
846 if (media & ELINK_MEDIACAP_100BASETX)
847 icfg |= ELINKMEDIA_AUTO << (CONFIG_XCVR_SEL_SHIFT + 16);
848 if (media & ELINK_MEDIACAP_100BASEFX)
849 icfg |= ELINKMEDIA_100BASE_FX
850 << (CONFIG_XCVR_SEL_SHIFT + 16);
851 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, icfg);
852 }
853
854 void
855 ex_set_media(sc)
856 struct ex_softc *sc;
857 {
858 bus_space_tag_t iot = sc->sc_iot;
859 bus_space_handle_t ioh = sc->sc_ioh;
860 u_int32_t configreg;
861
862 if (((sc->ex_conf & EX_CONF_MII) &&
863 (sc->ex_mii.mii_media_active & IFM_FDX))
864 || (!(sc->ex_conf & EX_CONF_MII) &&
865 (sc->ex_mii.mii_media.ifm_media & IFM_FDX))) {
866 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL,
867 MAC_CONTROL_FDX);
868 } else {
869 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, 0);
870 }
871
872 /*
873 * If the device has MII, select it, and then tell the
874 * PHY which media to use.
875 */
876 if (sc->ex_conf & EX_CONF_MII) {
877 u_int16_t val;
878
879 GO_WINDOW(3);
880 val = bus_space_read_2(iot, ioh, ELINK_W3_RESET_OPTIONS);
881 ex_set_xcvr(sc, val);
882 mii_mediachg(&sc->ex_mii);
883 return;
884 }
885
886 GO_WINDOW(4);
887 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE, 0);
888 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER);
889 delay(800);
890
891 /*
892 * Now turn on the selected media/transceiver.
893 */
894 switch (IFM_SUBTYPE(sc->ex_mii.mii_media.ifm_cur->ifm_media)) {
895 case IFM_10_T:
896 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE,
897 JABBER_GUARD_ENABLE|LINKBEAT_ENABLE);
898 break;
899
900 case IFM_10_2:
901 bus_space_write_2(iot, ioh, ELINK_COMMAND, START_TRANSCEIVER);
902 DELAY(800);
903 break;
904
905 case IFM_100_TX:
906 case IFM_100_FX:
907 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE,
908 LINKBEAT_ENABLE);
909 DELAY(800);
910 break;
911
912 case IFM_10_5:
913 bus_space_write_2(iot, ioh, ELINK_W4_MEDIA_TYPE,
914 SQE_ENABLE);
915 DELAY(800);
916 break;
917
918 case IFM_MANUAL:
919 break;
920
921 case IFM_NONE:
922 return;
923
924 default:
925 panic("ex_set_media: impossible");
926 }
927
928 GO_WINDOW(3);
929 configreg = bus_space_read_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG);
930
931 configreg &= ~(CONFIG_MEDIAMASK << 16);
932 configreg |= (sc->ex_mii.mii_media.ifm_cur->ifm_data <<
933 (CONFIG_MEDIAMASK_SHIFT + 16));
934
935 bus_space_write_4(iot, ioh, ELINK_W3_INTERNAL_CONFIG, configreg);
936 }
937
938 /*
939 * Get currently-selected media from card.
940 * (if_media callback, may be called before interface is brought up).
941 */
942 void
943 ex_media_stat(ifp, req)
944 struct ifnet *ifp;
945 struct ifmediareq *req;
946 {
947 struct ex_softc *sc = ifp->if_softc;
948 u_int16_t help;
949
950 if ((ifp->if_flags & (IFF_UP|IFF_RUNNING)) == (IFF_UP|IFF_RUNNING)) {
951 if (sc->ex_conf & EX_CONF_MII) {
952 mii_pollstat(&sc->ex_mii);
953 req->ifm_status = sc->ex_mii.mii_media_status;
954 req->ifm_active = sc->ex_mii.mii_media_active;
955 } else {
956 GO_WINDOW(4);
957 req->ifm_status = IFM_AVALID;
958 req->ifm_active =
959 sc->ex_mii.mii_media.ifm_cur->ifm_media;
960 help = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
961 ELINK_W4_MEDIA_TYPE);
962 if (help & LINKBEAT_DETECT)
963 req->ifm_status |= IFM_ACTIVE;
964 GO_WINDOW(1);
965 }
966 }
967 }
968
969
970
971 /*
972 * Start outputting on the interface.
973 */
974 static void
975 ex_start(ifp)
976 struct ifnet *ifp;
977 {
978 struct ex_softc *sc = ifp->if_softc;
979 bus_space_tag_t iot = sc->sc_iot;
980 bus_space_handle_t ioh = sc->sc_ioh;
981 volatile struct ex_fraghdr *fr = NULL;
982 volatile struct ex_dpd *dpd = NULL, *prevdpd = NULL;
983 struct ex_txdesc *txp;
984 struct mbuf *mb_head;
985 bus_dmamap_t dmamap;
986 int offset, totlen, segment, error;
987 u_int32_t csum_flags;
988
989 if (sc->tx_head || sc->tx_free == NULL)
990 return;
991
992 txp = NULL;
993
994 /*
995 * We're finished if there is nothing more to add to the list or if
996 * we're all filled up with buffers to transmit.
997 */
998 while (sc->tx_free != NULL) {
999 /*
1000 * Grab a packet to transmit.
1001 */
1002 IFQ_DEQUEUE(&ifp->if_snd, mb_head);
1003 if (mb_head == NULL)
1004 break;
1005
1006 /*
1007 * Get pointer to next available tx desc.
1008 */
1009 txp = sc->tx_free;
1010 dmamap = txp->tx_dmamap;
1011
1012 /*
1013 * Go through each of the mbufs in the chain and initialize
1014 * the transmit buffer descriptors with the physical address
1015 * and size of the mbuf.
1016 */
1017 reload:
1018 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
1019 mb_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1020 switch (error) {
1021 case 0:
1022 /* Success. */
1023 break;
1024
1025 case EFBIG:
1026 {
1027 struct mbuf *mn;
1028
1029 /*
1030 * We ran out of segments. We have to recopy this
1031 * mbuf chain first. Bail out if we can't get the
1032 * new buffers.
1033 */
1034 printf("%s: too many segments, ", sc->sc_dev.dv_xname);
1035
1036 MGETHDR(mn, M_DONTWAIT, MT_DATA);
1037 if (mn == NULL) {
1038 m_freem(mb_head);
1039 printf("aborting\n");
1040 goto out;
1041 }
1042 if (mb_head->m_pkthdr.len > MHLEN) {
1043 MCLGET(mn, M_DONTWAIT);
1044 if ((mn->m_flags & M_EXT) == 0) {
1045 m_freem(mn);
1046 m_freem(mb_head);
1047 printf("aborting\n");
1048 goto out;
1049 }
1050 }
1051 m_copydata(mb_head, 0, mb_head->m_pkthdr.len,
1052 mtod(mn, caddr_t));
1053 mn->m_pkthdr.len = mn->m_len = mb_head->m_pkthdr.len;
1054 m_freem(mb_head);
1055 mb_head = mn;
1056 printf("retrying\n");
1057 goto reload;
1058 }
1059
1060 default:
1061 /*
1062 * Some other problem; report it.
1063 */
1064 printf("%s: can't load mbuf chain, error = %d\n",
1065 sc->sc_dev.dv_xname, error);
1066 m_freem(mb_head);
1067 goto out;
1068 }
1069
1070 /*
1071 * remove our tx desc from freelist.
1072 */
1073 sc->tx_free = txp->tx_next;
1074 txp->tx_next = NULL;
1075
1076 fr = &txp->tx_dpd->dpd_frags[0];
1077 totlen = 0;
1078 for (segment = 0; segment < dmamap->dm_nsegs; segment++, fr++) {
1079 fr->fr_addr = htole32(dmamap->dm_segs[segment].ds_addr);
1080 fr->fr_len = htole32(dmamap->dm_segs[segment].ds_len);
1081 totlen += dmamap->dm_segs[segment].ds_len;
1082 }
1083 fr--;
1084 fr->fr_len |= htole32(EX_FR_LAST);
1085 txp->tx_mbhead = mb_head;
1086
1087 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
1088 BUS_DMASYNC_PREWRITE);
1089
1090 dpd = txp->tx_dpd;
1091 dpd->dpd_nextptr = 0;
1092 dpd->dpd_fsh = htole32(totlen);
1093
1094 /* Byte-swap constants so compiler can optimize. */
1095
1096 if (sc->ex_conf & EX_CONF_90XB) {
1097 csum_flags = 0;
1098
1099 if (mb_head->m_pkthdr.csum_flags & M_CSUM_IPv4)
1100 csum_flags |= htole32(EX_DPD_IPCKSUM);
1101
1102 if (mb_head->m_pkthdr.csum_flags & M_CSUM_TCPv4)
1103 csum_flags |= htole32(EX_DPD_TCPCKSUM);
1104 else if (mb_head->m_pkthdr.csum_flags & M_CSUM_UDPv4)
1105 csum_flags |= htole32(EX_DPD_UDPCKSUM);
1106
1107 dpd->dpd_fsh |= csum_flags;
1108 } else {
1109 KDASSERT((mb_head->m_pkthdr.csum_flags &
1110 (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) == 0);
1111 }
1112
1113 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1114 ((caddr_t)dpd - (caddr_t)sc->sc_dpd),
1115 sizeof (struct ex_dpd),
1116 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1117
1118 /*
1119 * No need to stall the download engine, we know it's
1120 * not busy right now.
1121 *
1122 * Fix up pointers in both the "soft" tx and the physical
1123 * tx list.
1124 */
1125 if (sc->tx_head != NULL) {
1126 prevdpd = sc->tx_tail->tx_dpd;
1127 offset = ((caddr_t)prevdpd - (caddr_t)sc->sc_dpd);
1128 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1129 offset, sizeof (struct ex_dpd),
1130 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1131 prevdpd->dpd_nextptr = htole32(DPD_DMADDR(sc, txp));
1132 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1133 offset, sizeof (struct ex_dpd),
1134 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1135 sc->tx_tail->tx_next = txp;
1136 sc->tx_tail = txp;
1137 } else {
1138 sc->tx_tail = sc->tx_head = txp;
1139 }
1140
1141 #if NBPFILTER > 0
1142 /*
1143 * Pass packet to bpf if there is a listener.
1144 */
1145 if (ifp->if_bpf)
1146 bpf_mtap(ifp->if_bpf, mb_head);
1147 #endif
1148 }
1149 out:
1150 if (sc->tx_head) {
1151 sc->tx_tail->tx_dpd->dpd_fsh |= htole32(EX_DPD_DNIND);
1152 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1153 ((caddr_t)sc->tx_tail->tx_dpd - (caddr_t)sc->sc_dpd),
1154 sizeof (struct ex_dpd),
1155 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1156 ifp->if_flags |= IFF_OACTIVE;
1157 bus_space_write_2(iot, ioh, ELINK_COMMAND, ELINK_DNUNSTALL);
1158 bus_space_write_4(iot, ioh, ELINK_DNLISTPTR,
1159 DPD_DMADDR(sc, sc->tx_head));
1160
1161 /* trigger watchdog */
1162 ifp->if_timer = 5;
1163 }
1164 }
1165
1166
1167 int
1168 ex_intr(arg)
1169 void *arg;
1170 {
1171 struct ex_softc *sc = arg;
1172 bus_space_tag_t iot = sc->sc_iot;
1173 bus_space_handle_t ioh = sc->sc_ioh;
1174 u_int16_t stat;
1175 int ret = 0;
1176 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1177
1178 if ((ifp->if_flags & IFF_RUNNING) == 0 ||
1179 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0)
1180 return (0);
1181
1182 for (;;) {
1183 stat = bus_space_read_2(iot, ioh, ELINK_STATUS);
1184
1185 if ((stat & XL_WATCHED_INTERRUPTS) == 0) {
1186 if ((stat & INTR_LATCH) == 0) {
1187 #if 0
1188 printf("%s: intr latch cleared\n",
1189 sc->sc_dev.dv_xname);
1190 #endif
1191 break;
1192 }
1193 }
1194
1195 ret = 1;
1196
1197 /*
1198 * Acknowledge interrupts.
1199 */
1200 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR |
1201 (stat & (XL_WATCHED_INTERRUPTS | INTR_LATCH)));
1202 if (sc->intr_ack)
1203 (*sc->intr_ack)(sc);
1204
1205 if (stat & HOST_ERROR) {
1206 printf("%s: adapter failure (%x)\n",
1207 sc->sc_dev.dv_xname, stat);
1208 ex_reset(sc);
1209 ex_init(ifp);
1210 return 1;
1211 }
1212 if (stat & TX_COMPLETE) {
1213 ex_txstat(sc);
1214 }
1215 if (stat & UPD_STATS) {
1216 ex_getstats(sc);
1217 }
1218 if (stat & DN_COMPLETE) {
1219 struct ex_txdesc *txp, *ptxp = NULL;
1220 bus_dmamap_t txmap;
1221
1222 /* reset watchdog timer, was set in ex_start() */
1223 ifp->if_timer = 0;
1224
1225 for (txp = sc->tx_head; txp != NULL;
1226 txp = txp->tx_next) {
1227 bus_dmamap_sync(sc->sc_dmat,
1228 sc->sc_dpd_dmamap,
1229 (caddr_t)txp->tx_dpd - (caddr_t)sc->sc_dpd,
1230 sizeof (struct ex_dpd),
1231 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1232 if (txp->tx_mbhead != NULL) {
1233 txmap = txp->tx_dmamap;
1234 bus_dmamap_sync(sc->sc_dmat, txmap,
1235 0, txmap->dm_mapsize,
1236 BUS_DMASYNC_POSTWRITE);
1237 bus_dmamap_unload(sc->sc_dmat, txmap);
1238 m_freem(txp->tx_mbhead);
1239 txp->tx_mbhead = NULL;
1240 }
1241 ptxp = txp;
1242 }
1243
1244 /*
1245 * Move finished tx buffers back to the tx free list.
1246 */
1247 if (sc->tx_free) {
1248 sc->tx_ftail->tx_next = sc->tx_head;
1249 sc->tx_ftail = ptxp;
1250 } else
1251 sc->tx_ftail = sc->tx_free = sc->tx_head;
1252
1253 sc->tx_head = sc->tx_tail = NULL;
1254 ifp->if_flags &= ~IFF_OACTIVE;
1255 }
1256
1257 if (stat & UP_COMPLETE) {
1258 struct ex_rxdesc *rxd;
1259 struct mbuf *m;
1260 struct ex_upd *upd;
1261 bus_dmamap_t rxmap;
1262 u_int32_t pktstat;
1263
1264 rcvloop:
1265 rxd = sc->rx_head;
1266 rxmap = rxd->rx_dmamap;
1267 m = rxd->rx_mbhead;
1268 upd = rxd->rx_upd;
1269
1270 bus_dmamap_sync(sc->sc_dmat, rxmap, 0,
1271 rxmap->dm_mapsize,
1272 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1273 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap,
1274 ((caddr_t)upd - (caddr_t)sc->sc_upd),
1275 sizeof (struct ex_upd),
1276 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1277 pktstat = le32toh(upd->upd_pktstatus);
1278
1279 if (pktstat & EX_UPD_COMPLETE) {
1280 /*
1281 * Remove first packet from the chain.
1282 */
1283 sc->rx_head = rxd->rx_next;
1284 rxd->rx_next = NULL;
1285
1286 /*
1287 * Add a new buffer to the receive chain.
1288 * If this fails, the old buffer is recycled
1289 * instead.
1290 */
1291 if (ex_add_rxbuf(sc, rxd) == 0) {
1292 u_int16_t total_len;
1293
1294 if (pktstat &
1295 ((sc->sc_ethercom.ec_capenable &
1296 ETHERCAP_VLAN_MTU) ?
1297 EX_UPD_ERR_VLAN : EX_UPD_ERR)) {
1298 ifp->if_ierrors++;
1299 m_freem(m);
1300 goto rcvloop;
1301 }
1302
1303 total_len = pktstat & EX_UPD_PKTLENMASK;
1304 if (total_len <
1305 sizeof(struct ether_header)) {
1306 m_freem(m);
1307 goto rcvloop;
1308 }
1309 m->m_pkthdr.rcvif = ifp;
1310 m->m_pkthdr.len = m->m_len = total_len;
1311 #if NBPFILTER > 0
1312 if (ifp->if_bpf)
1313 bpf_mtap(ifp->if_bpf, m);
1314 #endif
1315 /*
1316 * Set the incoming checksum information for the packet.
1317 */
1318 if ((sc->ex_conf & EX_CONF_90XB) != 0 &&
1319 (pktstat & EX_UPD_IPCHECKED) != 0) {
1320 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1321 if (pktstat & EX_UPD_IPCKSUMERR)
1322 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD;
1323 if (pktstat & EX_UPD_TCPCHECKED) {
1324 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1325 if (pktstat & EX_UPD_TCPCKSUMERR)
1326 m->m_pkthdr.csum_flags |=
1327 M_CSUM_TCP_UDP_BAD;
1328 } else if (pktstat & EX_UPD_UDPCHECKED) {
1329 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1330 if (pktstat & EX_UPD_UDPCKSUMERR)
1331 m->m_pkthdr.csum_flags |=
1332 M_CSUM_TCP_UDP_BAD;
1333 }
1334 }
1335 (*ifp->if_input)(ifp, m);
1336 }
1337 goto rcvloop;
1338 }
1339 /*
1340 * Just in case we filled up all UPDs and the DMA engine
1341 * stalled. We could be more subtle about this.
1342 */
1343 if (bus_space_read_4(iot, ioh, ELINK_UPLISTPTR) == 0) {
1344 printf("%s: uplistptr was 0\n",
1345 sc->sc_dev.dv_xname);
1346 ex_init(ifp);
1347 } else if (bus_space_read_4(iot, ioh, ELINK_UPPKTSTATUS)
1348 & 0x2000) {
1349 printf("%s: receive stalled\n",
1350 sc->sc_dev.dv_xname);
1351 bus_space_write_2(iot, ioh, ELINK_COMMAND,
1352 ELINK_UPUNSTALL);
1353 }
1354 }
1355
1356 #if NRND > 0
1357 if (stat)
1358 rnd_add_uint32(&sc->rnd_source, stat);
1359 #endif
1360 }
1361
1362 /* no more interrupts */
1363 if (ret && IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1364 ex_start(ifp);
1365 return ret;
1366 }
1367
1368 int
1369 ex_ioctl(ifp, cmd, data)
1370 struct ifnet *ifp;
1371 u_long cmd;
1372 caddr_t data;
1373 {
1374 struct ex_softc *sc = ifp->if_softc;
1375 struct ifreq *ifr = (struct ifreq *)data;
1376 int s, error;
1377
1378 s = splnet();
1379
1380 switch (cmd) {
1381 case SIOCSIFMEDIA:
1382 case SIOCGIFMEDIA:
1383 error = ifmedia_ioctl(ifp, ifr, &sc->ex_mii.mii_media, cmd);
1384 break;
1385
1386 default:
1387 error = ether_ioctl(ifp, cmd, data);
1388 if (error == ENETRESET) {
1389 if (sc->enabled) {
1390 /*
1391 * Multicast list has changed; set the hardware filter
1392 * accordingly.
1393 */
1394 ex_set_mc(sc);
1395 }
1396 error = 0;
1397 }
1398 break;
1399 }
1400
1401 splx(s);
1402 return (error);
1403 }
1404
1405 void
1406 ex_getstats(sc)
1407 struct ex_softc *sc;
1408 {
1409 bus_space_handle_t ioh = sc->sc_ioh;
1410 bus_space_tag_t iot = sc->sc_iot;
1411 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1412 u_int8_t upperok;
1413
1414 GO_WINDOW(6);
1415 upperok = bus_space_read_1(iot, ioh, UPPER_FRAMES_OK);
1416 ifp->if_ipackets += bus_space_read_1(iot, ioh, RX_FRAMES_OK);
1417 ifp->if_ipackets += (upperok & 0x03) << 8;
1418 ifp->if_opackets += bus_space_read_1(iot, ioh, TX_FRAMES_OK);
1419 ifp->if_opackets += (upperok & 0x30) << 4;
1420 ifp->if_ierrors += bus_space_read_1(iot, ioh, RX_OVERRUNS);
1421 ifp->if_collisions += bus_space_read_1(iot, ioh, TX_COLLISIONS);
1422 /*
1423 * There seems to be no way to get the exact number of collisions,
1424 * this is the number that occurred at the very least.
1425 */
1426 ifp->if_collisions += 2 * bus_space_read_1(iot, ioh,
1427 TX_AFTER_X_COLLISIONS);
1428 /*
1429 * Interface byte counts are counted by ether_input() and
1430 * ether_output(), so don't accumulate them here. Just
1431 * read the NIC counters so they don't generate overflow interrupts.
1432 * Upper byte counters are latched from reading the totals, so
1433 * they don't need to be read if we don't need their values.
1434 */
1435 bus_space_read_2(iot, ioh, RX_TOTAL_OK);
1436 bus_space_read_2(iot, ioh, TX_TOTAL_OK);
1437
1438 /*
1439 * Clear the following to avoid stats overflow interrupts
1440 */
1441 bus_space_read_1(iot, ioh, TX_DEFERRALS);
1442 bus_space_read_1(iot, ioh, TX_AFTER_1_COLLISION);
1443 bus_space_read_1(iot, ioh, TX_NO_SQE);
1444 bus_space_read_1(iot, ioh, TX_CD_LOST);
1445 GO_WINDOW(4);
1446 bus_space_read_1(iot, ioh, ELINK_W4_BADSSD);
1447 GO_WINDOW(1);
1448 }
1449
1450 void
1451 ex_printstats(sc)
1452 struct ex_softc *sc;
1453 {
1454 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1455
1456 ex_getstats(sc);
1457 printf("in %llu out %llu ierror %llu oerror %llu ibytes %llu obytes "
1458 "%llu\n", (unsigned long long)ifp->if_ipackets,
1459 (unsigned long long)ifp->if_opackets,
1460 (unsigned long long)ifp->if_ierrors,
1461 (unsigned long long)ifp->if_oerrors,
1462 (unsigned long long)ifp->if_ibytes,
1463 (unsigned long long)ifp->if_obytes);
1464 }
1465
1466 void
1467 ex_tick(arg)
1468 void *arg;
1469 {
1470 struct ex_softc *sc = arg;
1471 int s;
1472
1473 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0)
1474 return;
1475
1476 s = splnet();
1477
1478 if (sc->ex_conf & EX_CONF_MII)
1479 mii_tick(&sc->ex_mii);
1480
1481 if (!(bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, ELINK_STATUS)
1482 & COMMAND_IN_PROGRESS))
1483 ex_getstats(sc);
1484
1485 splx(s);
1486
1487 callout_reset(&sc->ex_mii_callout, hz, ex_tick, sc);
1488 }
1489
1490 void
1491 ex_reset(sc)
1492 struct ex_softc *sc;
1493 {
1494 u_int16_t val = GLOBAL_RESET;
1495
1496 if (sc->ex_conf & EX_CONF_RESETHACK)
1497 val |= 0x10;
1498 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_COMMAND, val);
1499 /*
1500 * XXX apparently the command in progress bit can't be trusted
1501 * during a reset, so we just always wait this long. Fortunately
1502 * we normally only reset the chip during autoconfig.
1503 */
1504 delay(100000);
1505 ex_waitcmd(sc);
1506 }
1507
1508 void
1509 ex_watchdog(ifp)
1510 struct ifnet *ifp;
1511 {
1512 struct ex_softc *sc = ifp->if_softc;
1513
1514 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
1515 ++sc->sc_ethercom.ec_if.if_oerrors;
1516
1517 ex_reset(sc);
1518 ex_init(ifp);
1519 }
1520
1521 void
1522 ex_stop(ifp, disable)
1523 struct ifnet *ifp;
1524 int disable;
1525 {
1526 struct ex_softc *sc = ifp->if_softc;
1527 bus_space_tag_t iot = sc->sc_iot;
1528 bus_space_handle_t ioh = sc->sc_ioh;
1529 struct ex_txdesc *tx;
1530 struct ex_rxdesc *rx;
1531 int i;
1532
1533 bus_space_write_2(iot, ioh, ELINK_COMMAND, RX_DISABLE);
1534 bus_space_write_2(iot, ioh, ELINK_COMMAND, TX_DISABLE);
1535 bus_space_write_2(iot, ioh, ELINK_COMMAND, STOP_TRANSCEIVER);
1536
1537 for (tx = sc->tx_head ; tx != NULL; tx = tx->tx_next) {
1538 if (tx->tx_mbhead == NULL)
1539 continue;
1540 m_freem(tx->tx_mbhead);
1541 tx->tx_mbhead = NULL;
1542 bus_dmamap_unload(sc->sc_dmat, tx->tx_dmamap);
1543 tx->tx_dpd->dpd_fsh = tx->tx_dpd->dpd_nextptr = 0;
1544 bus_dmamap_sync(sc->sc_dmat, sc->sc_dpd_dmamap,
1545 ((caddr_t)tx->tx_dpd - (caddr_t)sc->sc_dpd),
1546 sizeof (struct ex_dpd),
1547 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1548 }
1549 sc->tx_tail = sc->tx_head = NULL;
1550 ex_init_txdescs(sc);
1551
1552 sc->rx_tail = sc->rx_head = 0;
1553 for (i = 0; i < EX_NUPD; i++) {
1554 rx = &sc->sc_rxdescs[i];
1555 if (rx->rx_mbhead != NULL) {
1556 bus_dmamap_unload(sc->sc_dmat, rx->rx_dmamap);
1557 m_freem(rx->rx_mbhead);
1558 rx->rx_mbhead = NULL;
1559 }
1560 ex_add_rxbuf(sc, rx);
1561 }
1562
1563 bus_space_write_2(iot, ioh, ELINK_COMMAND, ACK_INTR | INTR_LATCH);
1564
1565 callout_stop(&sc->ex_mii_callout);
1566 if (sc->ex_conf & EX_CONF_MII)
1567 mii_down(&sc->ex_mii);
1568
1569 if (disable)
1570 ex_disable(sc);
1571
1572 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1573 ifp->if_timer = 0;
1574 }
1575
1576 static void
1577 ex_init_txdescs(sc)
1578 struct ex_softc *sc;
1579 {
1580 int i;
1581
1582 for (i = 0; i < EX_NDPD; i++) {
1583 sc->sc_txdescs[i].tx_dmamap = sc->sc_tx_dmamaps[i];
1584 sc->sc_txdescs[i].tx_dpd = &sc->sc_dpd[i];
1585 if (i < EX_NDPD - 1)
1586 sc->sc_txdescs[i].tx_next = &sc->sc_txdescs[i + 1];
1587 else
1588 sc->sc_txdescs[i].tx_next = NULL;
1589 }
1590 sc->tx_free = &sc->sc_txdescs[0];
1591 sc->tx_ftail = &sc->sc_txdescs[EX_NDPD-1];
1592 }
1593
1594
1595 int
1596 ex_activate(self, act)
1597 struct device *self;
1598 enum devact act;
1599 {
1600 struct ex_softc *sc = (void *) self;
1601 int s, error = 0;
1602
1603 s = splnet();
1604 switch (act) {
1605 case DVACT_ACTIVATE:
1606 error = EOPNOTSUPP;
1607 break;
1608
1609 case DVACT_DEACTIVATE:
1610 if (sc->ex_conf & EX_CONF_MII)
1611 mii_activate(&sc->ex_mii, act, MII_PHY_ANY,
1612 MII_OFFSET_ANY);
1613 if_deactivate(&sc->sc_ethercom.ec_if);
1614 break;
1615 }
1616 splx(s);
1617
1618 return (error);
1619 }
1620
1621 int
1622 ex_detach(sc)
1623 struct ex_softc *sc;
1624 {
1625 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1626 struct ex_rxdesc *rxd;
1627 int i;
1628
1629 /* Succeed now if there's no work to do. */
1630 if ((sc->ex_flags & EX_FLAGS_ATTACHED) == 0)
1631 return (0);
1632
1633 /* Unhook our tick handler. */
1634 callout_stop(&sc->ex_mii_callout);
1635
1636 if (sc->ex_conf & EX_CONF_MII) {
1637 /* Detach all PHYs */
1638 mii_detach(&sc->ex_mii, MII_PHY_ANY, MII_OFFSET_ANY);
1639 }
1640
1641 /* Delete all remaining media. */
1642 ifmedia_delete_instance(&sc->ex_mii.mii_media, IFM_INST_ANY);
1643
1644 #if NRND > 0
1645 rnd_detach_source(&sc->rnd_source);
1646 #endif
1647 ether_ifdetach(ifp);
1648 if_detach(ifp);
1649
1650 for (i = 0; i < EX_NUPD; i++) {
1651 rxd = &sc->sc_rxdescs[i];
1652 if (rxd->rx_mbhead != NULL) {
1653 bus_dmamap_unload(sc->sc_dmat, rxd->rx_dmamap);
1654 m_freem(rxd->rx_mbhead);
1655 rxd->rx_mbhead = NULL;
1656 }
1657 }
1658 for (i = 0; i < EX_NUPD; i++)
1659 bus_dmamap_destroy(sc->sc_dmat, sc->sc_rx_dmamaps[i]);
1660 for (i = 0; i < EX_NDPD; i++)
1661 bus_dmamap_destroy(sc->sc_dmat, sc->sc_tx_dmamaps[i]);
1662 bus_dmamap_unload(sc->sc_dmat, sc->sc_dpd_dmamap);
1663 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dpd_dmamap);
1664 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_dpd,
1665 EX_NDPD * sizeof (struct ex_dpd));
1666 bus_dmamem_free(sc->sc_dmat, &sc->sc_dseg, sc->sc_drseg);
1667 bus_dmamap_unload(sc->sc_dmat, sc->sc_upd_dmamap);
1668 bus_dmamap_destroy(sc->sc_dmat, sc->sc_upd_dmamap);
1669 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_upd,
1670 EX_NUPD * sizeof (struct ex_upd));
1671 bus_dmamem_free(sc->sc_dmat, &sc->sc_useg, sc->sc_urseg);
1672
1673 shutdownhook_disestablish(sc->sc_sdhook);
1674 powerhook_disestablish(sc->sc_powerhook);
1675
1676 return (0);
1677 }
1678
1679 /*
1680 * Before reboots, reset card completely.
1681 */
1682 static void
1683 ex_shutdown(arg)
1684 void *arg;
1685 {
1686 struct ex_softc *sc = arg;
1687
1688 ex_stop(&sc->sc_ethercom.ec_if, 1);
1689 /*
1690 * Make sure the interface is powered up when we reboot,
1691 * otherwise firmware on some systems gets really confused.
1692 */
1693 (void) ex_enable(sc);
1694 }
1695
1696 /*
1697 * Read EEPROM data.
1698 * XXX what to do if EEPROM doesn't unbusy?
1699 */
1700 u_int16_t
1701 ex_read_eeprom(sc, offset)
1702 struct ex_softc *sc;
1703 int offset;
1704 {
1705 bus_space_tag_t iot = sc->sc_iot;
1706 bus_space_handle_t ioh = sc->sc_ioh;
1707 u_int16_t data = 0, cmd = READ_EEPROM;
1708 int off;
1709
1710 off = sc->ex_conf & EX_CONF_EEPROM_OFF ? 0x30 : 0;
1711 cmd = sc->ex_conf & EX_CONF_EEPROM_8BIT ? READ_EEPROM8 : READ_EEPROM;
1712
1713 GO_WINDOW(0);
1714 if (ex_eeprom_busy(sc))
1715 goto out;
1716 bus_space_write_2(iot, ioh, ELINK_W0_EEPROM_COMMAND,
1717 cmd | (off + (offset & 0x3f)));
1718 if (ex_eeprom_busy(sc))
1719 goto out;
1720 data = bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_DATA);
1721 out:
1722 return data;
1723 }
1724
1725 static int
1726 ex_eeprom_busy(sc)
1727 struct ex_softc *sc;
1728 {
1729 bus_space_tag_t iot = sc->sc_iot;
1730 bus_space_handle_t ioh = sc->sc_ioh;
1731 int i = 100;
1732
1733 while (i--) {
1734 if (!(bus_space_read_2(iot, ioh, ELINK_W0_EEPROM_COMMAND) &
1735 EEPROM_BUSY))
1736 return 0;
1737 delay(100);
1738 }
1739 printf("\n%s: eeprom stays busy.\n", sc->sc_dev.dv_xname);
1740 return (1);
1741 }
1742
1743 /*
1744 * Create a new rx buffer and add it to the 'soft' rx list.
1745 */
1746 static int
1747 ex_add_rxbuf(sc, rxd)
1748 struct ex_softc *sc;
1749 struct ex_rxdesc *rxd;
1750 {
1751 struct mbuf *m, *oldm;
1752 bus_dmamap_t rxmap;
1753 int error, rval = 0;
1754
1755 oldm = rxd->rx_mbhead;
1756 rxmap = rxd->rx_dmamap;
1757
1758 MGETHDR(m, M_DONTWAIT, MT_DATA);
1759 if (m != NULL) {
1760 MCLGET(m, M_DONTWAIT);
1761 if ((m->m_flags & M_EXT) == 0) {
1762 m_freem(m);
1763 if (oldm == NULL)
1764 return 1;
1765 m = oldm;
1766 m->m_data = m->m_ext.ext_buf;
1767 rval = 1;
1768 }
1769 } else {
1770 if (oldm == NULL)
1771 return 1;
1772 m = oldm;
1773 m->m_data = m->m_ext.ext_buf;
1774 rval = 1;
1775 }
1776
1777 /*
1778 * Setup the DMA map for this receive buffer.
1779 */
1780 if (m != oldm) {
1781 if (oldm != NULL)
1782 bus_dmamap_unload(sc->sc_dmat, rxmap);
1783 error = bus_dmamap_load(sc->sc_dmat, rxmap,
1784 m->m_ext.ext_buf, MCLBYTES, NULL,
1785 BUS_DMA_READ|BUS_DMA_NOWAIT);
1786 if (error) {
1787 printf("%s: can't load rx buffer, error = %d\n",
1788 sc->sc_dev.dv_xname, error);
1789 panic("ex_add_rxbuf"); /* XXX */
1790 }
1791 }
1792
1793 /*
1794 * Align for data after 14 byte header.
1795 */
1796 m->m_data += 2;
1797
1798 rxd->rx_mbhead = m;
1799 rxd->rx_upd->upd_pktstatus = htole32(MCLBYTES - 2);
1800 rxd->rx_upd->upd_frags[0].fr_addr =
1801 htole32(rxmap->dm_segs[0].ds_addr + 2);
1802 rxd->rx_upd->upd_nextptr = 0;
1803
1804 /*
1805 * Attach it to the end of the list.
1806 */
1807 if (sc->rx_head != NULL) {
1808 sc->rx_tail->rx_next = rxd;
1809 sc->rx_tail->rx_upd->upd_nextptr = htole32(sc->sc_upddma +
1810 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd));
1811 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap,
1812 (caddr_t)sc->rx_tail->rx_upd - (caddr_t)sc->sc_upd,
1813 sizeof (struct ex_upd),
1814 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1815 } else {
1816 sc->rx_head = rxd;
1817 }
1818 sc->rx_tail = rxd;
1819
1820 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, rxmap->dm_mapsize,
1821 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1822 bus_dmamap_sync(sc->sc_dmat, sc->sc_upd_dmamap,
1823 ((caddr_t)rxd->rx_upd - (caddr_t)sc->sc_upd),
1824 sizeof (struct ex_upd), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1825 return (rval);
1826 }
1827
1828 u_int32_t
1829 ex_mii_bitbang_read(self)
1830 struct device *self;
1831 {
1832 struct ex_softc *sc = (void *) self;
1833
1834 /* We're already in Window 4. */
1835 return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT));
1836 }
1837
1838 void
1839 ex_mii_bitbang_write(self, val)
1840 struct device *self;
1841 u_int32_t val;
1842 {
1843 struct ex_softc *sc = (void *) self;
1844
1845 /* We're already in Window 4. */
1846 bus_space_write_2(sc->sc_iot, sc->sc_ioh, ELINK_W4_PHYSMGMT, val);
1847 }
1848
1849 int
1850 ex_mii_readreg(v, phy, reg)
1851 struct device *v;
1852 int phy, reg;
1853 {
1854 struct ex_softc *sc = (struct ex_softc *)v;
1855 int val;
1856
1857 if ((sc->ex_conf & EX_CONF_INTPHY) && phy != ELINK_INTPHY_ID)
1858 return 0;
1859
1860 GO_WINDOW(4);
1861
1862 val = mii_bitbang_readreg(v, &ex_mii_bitbang_ops, phy, reg);
1863
1864 GO_WINDOW(1);
1865
1866 return (val);
1867 }
1868
1869 void
1870 ex_mii_writereg(v, phy, reg, data)
1871 struct device *v;
1872 int phy;
1873 int reg;
1874 int data;
1875 {
1876 struct ex_softc *sc = (struct ex_softc *)v;
1877
1878 GO_WINDOW(4);
1879
1880 mii_bitbang_writereg(v, &ex_mii_bitbang_ops, phy, reg, data);
1881
1882 GO_WINDOW(1);
1883 }
1884
1885 void
1886 ex_mii_statchg(v)
1887 struct device *v;
1888 {
1889 struct ex_softc *sc = (struct ex_softc *)v;
1890 bus_space_tag_t iot = sc->sc_iot;
1891 bus_space_handle_t ioh = sc->sc_ioh;
1892 int mctl;
1893
1894 GO_WINDOW(3);
1895 mctl = bus_space_read_2(iot, ioh, ELINK_W3_MAC_CONTROL);
1896 if (sc->ex_mii.mii_media_active & IFM_FDX)
1897 mctl |= MAC_CONTROL_FDX;
1898 else
1899 mctl &= ~MAC_CONTROL_FDX;
1900 bus_space_write_2(iot, ioh, ELINK_W3_MAC_CONTROL, mctl);
1901 GO_WINDOW(1); /* back to operating window */
1902 }
1903
1904 int
1905 ex_enable(sc)
1906 struct ex_softc *sc;
1907 {
1908 if (sc->enabled == 0 && sc->enable != NULL) {
1909 if ((*sc->enable)(sc) != 0) {
1910 printf("%s: de/vice enable failed\n",
1911 sc->sc_dev.dv_xname);
1912 return (EIO);
1913 }
1914 sc->enabled = 1;
1915 }
1916 return (0);
1917 }
1918
1919 void
1920 ex_disable(sc)
1921 struct ex_softc *sc;
1922 {
1923 if (sc->enabled == 1 && sc->disable != NULL) {
1924 (*sc->disable)(sc);
1925 sc->enabled = 0;
1926 }
1927 }
1928
1929 void
1930 ex_power(why, arg)
1931 int why;
1932 void *arg;
1933 {
1934 struct ex_softc *sc = (void *)arg;
1935 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1936 int s;
1937
1938 s = splnet();
1939 switch (why) {
1940 case PWR_SUSPEND:
1941 case PWR_STANDBY:
1942 ex_stop(ifp, 0);
1943 if (sc->power != NULL)
1944 (*sc->power)(sc, why);
1945 break;
1946 case PWR_RESUME:
1947 if (ifp->if_flags & IFF_UP) {
1948 if (sc->power != NULL)
1949 (*sc->power)(sc, why);
1950 ex_init(ifp);
1951 }
1952 break;
1953 case PWR_SOFTSUSPEND:
1954 case PWR_SOFTSTANDBY:
1955 case PWR_SOFTRESUME:
1956 break;
1957 }
1958 splx(s);
1959 }
Cache object: 41e3d752bac9d563f69a6dcc3ba1fa40
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